Peter Drescher
mbed library with additional peripherals for ST F401 board
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mbed official
This mbed LIB has additional peripherals for ST F401 board
- UART2 : PA_3 rx, PA_2 tx
- UART3 : PC_7 rx, PC_6 tx
- I2C2 : PB_3 SDA, PB_10 SCL
- I2C3 : PB_4 SDA, PA_8 SCL
Revision 15:4892fe388435, committed 2013-08-07
- Comitter:
- bogdanm
- Date:
- Wed Aug 07 16:43:59 2013 +0300
- Parent:
- 14:096882eb0961
- Child:
- 16:7da2369b400c
- Commit message:
- Added LPC4088 target and interrupt chaining code
Changed in this revision
--- a/api/CAN.h Mon Aug 05 14:54:27 2013 +0000
+++ b/api/CAN.h Wed Aug 07 16:43:59 2013 +0300
@@ -1,196 +1,229 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_H
-#define MBED_CAN_H
-
-#include "platform.h"
-
-#if DEVICE_CAN
-
-#include "can_api.h"
-#include "can_helper.h"
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-/** CANMessage class
- */
-class CANMessage : public CAN_Message {
-
-public:
- /** Creates empty CAN message.
- */
- CANMessage() {
- len = 8;
- type = CANData;
- format = CANStandard;
- id = 0;
- memset(data, 0, 8);
- }
-
- /** Creates CAN message with specific content.
- */
- CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
- len = _len & 0xF;
- type = _type;
- format = _format;
- id = _id;
- memcpy(data, _data, _len);
- }
-
- /** Creates CAN remote message.
- */
- CANMessage(int _id, CANFormat _format = CANStandard) {
- len = 0;
- type = CANRemote;
- format = _format;
- id = _id;
- memset(data, 0, 8);
- }
-};
-
-/** A can bus client, used for communicating with can devices
- */
-class CAN {
-
-public:
- /** Creates an CAN interface connected to specific pins.
- *
- * @param rd read from transmitter
- * @param td transmit to transmitter
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * Ticker ticker;
- * DigitalOut led1(LED1);
- * DigitalOut led2(LED2);
- * CAN can1(p9, p10);
- * CAN can2(p30, p29);
- *
- * char counter = 0;
- *
- * void send() {
- * if(can1.write(CANMessage(1337, &counter, 1))) {
- * printf("Message sent: %d\n", counter);
- * counter++;
- * }
- * led1 = !led1;
- * }
- *
- * int main() {
- * ticker.attach(&send, 1);
- * CANMessage msg;
- * while(1) {
- * if(can2.read(msg)) {
- * printf("Message received: %d\n\n", msg.data[0]);
- * led2 = !led2;
- * }
- * wait(0.2);
- * }
- * }
- * @endcode
- */
- CAN(PinName rd, PinName td);
- virtual ~CAN();
-
- /** Set the frequency of the CAN interface
- *
- * @param hz The bus frequency in hertz
- *
- * @returns
- * 1 if successful,
- * 0 otherwise
- */
- int frequency(int hz);
-
- /** Write a CANMessage to the bus.
- *
- * @param msg The CANMessage to write.
- *
- * @returns
- * 0 if write failed,
- * 1 if write was successful
- */
- int write(CANMessage msg);
-
- /** Read a CANMessage from the bus.
- *
- * @param msg A CANMessage to read to.
- *
- * @returns
- * 0 if no message arrived,
- * 1 if message arrived
- */
- int read(CANMessage &msg);
-
- /** Reset CAN interface.
- *
- * To use after error overflow.
- */
- void reset();
-
- /** Puts or removes the CAN interface into silent monitoring mode
- *
- * @param silent boolean indicating whether to go into silent mode or not
- */
- void monitor(bool silent);
-
- /** Returns number of read errors to detect read overflow errors.
- */
- unsigned char rderror();
-
- /** Returns number of write errors to detect write overflow errors.
- */
- unsigned char tderror();
-
- /** Attach a function to call whenever a CAN frame received interrupt is
- * generated.
- *
- * @param fptr A pointer to a void function, or 0 to set as none
- */
- void attach(void (*fptr)(void));
-
- /** Attach a member function to call whenever a CAN frame received interrupt
- * is generated.
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- */
- template<typename T>
- void attach(T* tptr, void (T::*mptr)(void)) {
- if((mptr != NULL) && (tptr != NULL)) {
- _rxirq.attach(tptr, mptr);
- setup_interrupt();
- } else {
- remove_interrupt();
- }
- }
-
-private:
- can_t _can;
- FunctionPointer _rxirq;
-
- void setup_interrupt(void);
- void remove_interrupt(void);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif // MBED_CAN_H
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_H
+#define MBED_CAN_H
+
+#include "platform.h"
+
+#if DEVICE_CAN
+
+#include "can_api.h"
+#include "can_helper.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** CANMessage class
+ */
+class CANMessage : public CAN_Message {
+
+public:
+ /** Creates empty CAN message.
+ */
+ CANMessage() {
+ len = 8;
+ type = CANData;
+ format = CANStandard;
+ id = 0;
+ memset(data, 0, 8);
+ }
+
+ /** Creates CAN message with specific content.
+ */
+ CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
+ len = _len & 0xF;
+ type = _type;
+ format = _format;
+ id = _id;
+ memcpy(data, _data, _len);
+ }
+
+ /** Creates CAN remote message.
+ */
+ CANMessage(int _id, CANFormat _format = CANStandard) {
+ len = 0;
+ type = CANRemote;
+ format = _format;
+ id = _id;
+ memset(data, 0, 8);
+ }
+};
+
+/** A can bus client, used for communicating with can devices
+ */
+class CAN {
+
+public:
+ /** Creates an CAN interface connected to specific pins.
+ *
+ * @param rd read from transmitter
+ * @param td transmit to transmitter
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * Ticker ticker;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ * CAN can1(p9, p10);
+ * CAN can2(p30, p29);
+ *
+ * char counter = 0;
+ *
+ * void send() {
+ * if(can1.write(CANMessage(1337, &counter, 1))) {
+ * printf("Message sent: %d\n", counter);
+ * counter++;
+ * }
+ * led1 = !led1;
+ * }
+ *
+ * int main() {
+ * ticker.attach(&send, 1);
+ * CANMessage msg;
+ * while(1) {
+ * if(can2.read(msg)) {
+ * printf("Message received: %d\n\n", msg.data[0]);
+ * led2 = !led2;
+ * }
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ */
+ CAN(PinName rd, PinName td);
+ virtual ~CAN();
+
+ /** Set the frequency of the CAN interface
+ *
+ * @param hz The bus frequency in hertz
+ *
+ * @returns
+ * 1 if successful,
+ * 0 otherwise
+ */
+ int frequency(int hz);
+
+ /** Write a CANMessage to the bus.
+ *
+ * @param msg The CANMessage to write.
+ *
+ * @returns
+ * 0 if write failed,
+ * 1 if write was successful
+ */
+ int write(CANMessage msg);
+
+ /** Read a CANMessage from the bus.
+ *
+ * @param msg A CANMessage to read to.
+ *
+ * @returns
+ * 0 if no message arrived,
+ * 1 if message arrived
+ */
+ int read(CANMessage &msg);
+
+ /** Reset CAN interface.
+ *
+ * To use after error overflow.
+ */
+ void reset();
+
+ /** Puts or removes the CAN interface into silent monitoring mode
+ *
+ * @param silent boolean indicating whether to go into silent mode or not
+ */
+ void monitor(bool silent);
+
+ enum Mode {
+ Reset = 0,
+ Normal,
+ Silent,
+ LocalTest,
+ GlobalTest,
+ SilentTest
+ };
+
+ /** Change CAN operation to the specified mode
+ *
+ * @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
+ *
+ * @returns
+ * 0 if mode change failed or unsupported,
+ * 1 if mode change was successful
+ */
+ int mode(Mode mode);
+
+ /** Returns number of read errors to detect read overflow errors.
+ */
+ unsigned char rderror();
+
+ /** Returns number of write errors to detect write overflow errors.
+ */
+ unsigned char tderror();
+
+ enum IrqType {
+ RxIrq = 0,
+ TxIrq,
+ EwIrq,
+ DoIrq,
+ WuIrq,
+ EpIrq,
+ AlIrq,
+ BeIrq,
+ IdIrq
+ };
+
+ /** Attach a function to call whenever a CAN frame received interrupt is
+ * generated.
+ *
+ * @param fptr A pointer to a void function, or 0 to set as none
+ * @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
+ */
+ void attach(void (*fptr)(void), IrqType type=RxIrq);
+
+ /** Attach a member function to call whenever a CAN frame received interrupt
+ * is generated.
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
+ */
+ template<typename T>
+ void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ _irq[type].attach(tptr, mptr);
+ can_irq_set(&_can, (CanIrqType)type, 1);
+ }
+ else {
+ can_irq_set(&_can, (CanIrqType)type, 0);
+ }
+ }
+
+ static void _irq_handler(uint32_t id, CanIrqType type);
+
+protected:
+ can_t _can;
+ FunctionPointer _irq[9];
+};
+
+} // namespace mbed
+
+#endif
+
+#endif // MBED_CAN_H
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/api/CallChain.h Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,176 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CALLCHAIN_H
+#define MBED_CALLCHAIN_H
+
+#include "FunctionPointer.h"
+#include <string.h>
+
+namespace mbed {
+
+/** Group one or more functions in an instance of a CallChain, then call them in
+ * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
+ * but can be used for other purposes.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * CallChain chain;
+ *
+ * void first(void) {
+ * printf("'first' function.\n");
+ * }
+ *
+ * void second(void) {
+ * printf("'second' function.\n");
+ * }
+ *
+ * class Test {
+ * public:
+ * void f(void) {
+ * printf("A::f (class member).\n");
+ * }
+ * };
+ *
+ * int main() {
+ * Test test;
+ *
+ * chain.add(second);
+ * chain.add_front(first);
+ * chain.add(&test, &Test::f);
+ * chain.call();
+ * }
+ * @endcode
+ */
+
+typedef FunctionPointer* pFunctionPointer_t;
+
+class CallChain {
+public:
+ /** Create an empty chain
+ *
+ * @param size (optional) Initial size of the chain
+ */
+ CallChain(int size = 4);
+ virtual ~CallChain();
+
+ /** Add a function at the end of the chain
+ *
+ * @param function A pointer to a void function
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add(void (*function)(void));
+
+ /** Add a function at the end of the chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add(T *tptr, void (T::*mptr)(void)) {
+ return common_add(new FunctionPointer(tptr, mptr));
+ }
+
+ /** Add a function at the beginning of the chain
+ *
+ * @param function A pointer to a void function
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add_front(void (*function)(void));
+
+ /** Add a function at the beginning of the chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_front(T *tptr, void (T::*mptr)(void)) {
+ return common_add_front(new FunctionPointer(tptr, mptr));
+ }
+
+ /** Get the number of functions in the chain
+ */
+ int size() const;
+
+ /** Get a function object from the chain
+ *
+ * @param i function object index
+ *
+ * @returns
+ * The function object at position 'i' in the chain
+ */
+ pFunctionPointer_t get(int i) const;
+
+ /** Look for a function object in the call chain
+ *
+ * @param f the function object to search
+ *
+ * @returns
+ * The index of the function object if found, -1 otherwise.
+ */
+ int find(pFunctionPointer_t f) const;
+
+ /** Clear the call chain (remove all functions in the chain).
+ */
+ void clear();
+
+ /** Remove a function object from the chain
+ *
+ * @arg f the function object to remove
+ *
+ * @returns
+ * true if the function object was found and removed, false otherwise.
+ */
+ bool remove(pFunctionPointer_t f);
+
+ /** Call all the functions in the chain in sequence
+ */
+ void call();
+
+#ifdef MBED_OPERATORS
+ void operator ()(void) {
+ call();
+ }
+ pFunctionPointer_t operator [](int i) const {
+ return get(i);
+ }
+#endif
+
+private:
+ void _check_size();
+ pFunctionPointer_t common_add(pFunctionPointer_t pf);
+ pFunctionPointer_t common_add_front(pFunctionPointer_t pf);
+
+ pFunctionPointer_t* _chain;
+ int _size;
+ int _elements;
+};
+
+} // namespace mbed
+
+#endif
+
--- a/api/FunctionPointer.h Mon Aug 05 14:54:27 2013 +0000
+++ b/api/FunctionPointer.h Wed Aug 07 16:43:59 2013 +0300
@@ -20,6 +20,8 @@
namespace mbed {
+typedef void (*pvoidf_t)(void);
+
/** A class for storing and calling a pointer to a static or member void function
*/
class FunctionPointer {
@@ -64,6 +66,14 @@
*/
void call();
+ pvoidf_t get_function() const {
+ return (pvoidf_t)_function;
+ }
+
+#ifdef MBED_OPERATORS
+ void operator ()(void);
+#endif
+
private:
template<typename T>
static void membercaller(void *object, char *member) {
--- a/api/InterruptIn.h Mon Aug 05 14:54:27 2013 +0000
+++ b/api/InterruptIn.h Wed Aug 07 16:43:59 2013 +0300
@@ -24,6 +24,7 @@
#include "gpio_irq_api.h"
#include "FunctionPointer.h"
+#include "CallChain.h"
namespace mbed {
@@ -72,37 +73,167 @@
/** Attach a function to call when a rising edge occurs on the input
*
* @param fptr A pointer to a void function, or 0 to set as none
+ *
+ * @returns
+ * The function object created for 'fptr'
*/
- void rise(void (*fptr)(void));
+ pFunctionPointer_t rise(void (*fptr)(void));
+
+ /** Add a function to be called when a rising edge occurs at the end of the call chain
+ *
+ * @param fptr the function to add
+ *
+ * @returns
+ * The function object created for 'fptr'
+ */
+ pFunctionPointer_t rise_add(void (*fptr)(void)) {
+ return rise_add_common(fptr);
+ }
+
+ /** Add a function to be called when a rising edge occurs at the beginning of the call chain
+ *
+ * @param fptr the function to add
+ *
+ * @returns
+ * The function object created for 'fptr'
+ */
+ pFunctionPointer_t rise_add_front(void (*fptr)(void)) {
+ return rise_add_common(fptr, true);
+ }
/** Attach a member function to call when a rising edge occurs on the input
*
* @param tptr pointer to the object to call the member function on
* @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t rise(T* tptr, void (T::*mptr)(void)) {
+ _rise.clear();
+ pFunctionPointer_t pf = _rise.add(tptr, mptr);
+ gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+ return pf;
+ }
+
+ /** Add a function to be called when a rising edge occurs at the end of the call chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
*/
template<typename T>
- void rise(T* tptr, void (T::*mptr)(void)) {
- _rise.attach(tptr, mptr);
- gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+ pFunctionPointer_t rise_add(T* tptr, void (T::*mptr)(void)) {
+ return rise_add_common(tptr, mptr);
}
+ /** Add a function to be called when a rising edge occurs at the beginning of the call chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t rise_add_front(T* tptr, void (T::*mptr)(void)) {
+ return rise_add_common(tptr, mptr, true);
+ }
+
+ /** Remove a function from the list of functions to be called when a rising edge occurs
+ *
+ * @param pf the function object to remove
+ *
+ * @returns
+ * true if the function was found and removed, false otherwise
+ */
+ bool rise_remove(pFunctionPointer_t pf);
+
/** Attach a function to call when a falling edge occurs on the input
*
* @param fptr A pointer to a void function, or 0 to set as none
+ *
+ * @returns
+ * The function object created for 'fptr'
*/
- void fall(void (*fptr)(void));
+ pFunctionPointer_t fall(void (*fptr)(void));
+
+ /** Add a function to be called when a falling edge occurs at the end of the call chain
+ *
+ * @param fptr the function to add
+ *
+ * @returns
+ * The function object created for 'fptr'
+ */
+ pFunctionPointer_t fall_add(void (*fptr)(void)) {
+ return fall_add_common(fptr);
+ }
+
+ /** Add a function to be called when a falling edge occurs at the beginning of the call chain
+ *
+ * @param fptr the function to add
+ *
+ * @returns
+ * The function object created for 'fptr'
+ */
+ pFunctionPointer_t fall_add_front(void (*fptr)(void)) {
+ return fall_add_common(fptr, true);
+ }
/** Attach a member function to call when a falling edge occurs on the input
*
* @param tptr pointer to the object to call the member function on
* @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t fall(T* tptr, void (T::*mptr)(void)) {
+ _fall.clear();
+ pFunctionPointer_t pf = _fall.add(tptr, mptr);
+ gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+ return pf;
+ }
+
+ /** Add a function to be called when a falling edge occurs at the end of the call chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
*/
template<typename T>
- void fall(T* tptr, void (T::*mptr)(void)) {
- _fall.attach(tptr, mptr);
- gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+ pFunctionPointer_t fall_add(T* tptr, void (T::*mptr)(void)) {
+ return fall_add_common(tptr, mptr);
}
+ /** Add a function to be called when a falling edge occurs at the beginning of the call chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t fall_add_front(T* tptr, void (T::*mptr)(void)) {
+ return fall_add_common(tptr, mptr, true);
+ }
+
+ /** Remove a function from the list of functions to be called when a falling edge occurs
+ *
+ * @param pf the function object to remove
+ *
+ * @returns
+ * true if the function was found and removed, false otherwise
+ */
+ bool fall_remove(pFunctionPointer_t pf);
+
/** Set the input pin mode
*
* @param mode PullUp, PullDown, PullNone
@@ -112,11 +243,27 @@
static void _irq_handler(uint32_t id, gpio_irq_event event);
protected:
+ pFunctionPointer_t rise_add_common(void (*fptr)(void), bool front=false);
+ pFunctionPointer_t fall_add_common(void (*fptr)(void), bool front=false);
+
+ template<typename T>
+ pFunctionPointer_t rise_add_common(T* tptr, void (T::*mptr)(void), bool front=false) {
+ pFunctionPointer_t pf = front ? _rise.add_front(tptr, mptr) : _rise.add(tptr, mptr);
+ gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+ return pf;
+ }
+ template<typename T>
+ pFunctionPointer_t fall_add_common(T* tptr, void (T::*mptr)(void), bool front=false) {
+ pFunctionPointer_t pf = front ? _fall.add_front(tptr, mptr) : _fall.add(tptr, mptr);
+ gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+ return pf;
+ }
+
gpio_t gpio;
gpio_irq_t gpio_irq;
- FunctionPointer _rise;
- FunctionPointer _fall;
+ CallChain _rise;
+ CallChain _fall;
};
} // namespace mbed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/api/InterruptManager.h Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,143 @@
+#ifndef MBED_INTERRUPTMANAGER_H
+#define MBED_INTERRUPTMANAGER_H
+
+#include "cmsis.h"
+#include "CallChain.h"
+#include <string.h>
+
+namespace mbed {
+
+/** Use this singleton if you need to chain interrupt handlers.
+ *
+ * Example (for LPC1768):
+ * @code
+ * #include "InterruptManager.h"
+ * #include "mbed.h"
+ *
+ * Ticker flipper;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * void flip(void) {
+ * led1 = !led1;
+ * }
+ *
+ * void handler(void) {
+ * led2 = !led1;
+ * }
+ *
+ * int main() {
+ * led1 = led2 = 0;
+ * flipper.attach(&flip, 1.0);
+ * InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
+ * }
+ * @endcode
+ */
+class InterruptManager {
+public:
+ /** Return the only instance of this class
+ */
+ static InterruptManager* get();
+
+ /** Destroy the current instance of the interrupt manager
+ */
+ static void destroy();
+
+ /** Add a handler for an interrupt at the end of the handler list
+ *
+ * @param function the handler to add
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
+ return add_common(function, irq);
+ }
+
+ /** Add a handler for an interrupt at the beginning of the handler list
+ *
+ * @param function the handler to add
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
+ return add_common(function, irq, true);
+ }
+
+ /** Add a handler for an interrupt at the end of the handler list
+ *
+ * @param tptr pointer to the object that has the handler function
+ * @param mptr pointer to the actual handler function
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+ return add_common(tptr, mptr, irq);
+ }
+
+ /** Add a handler for an interrupt at the beginning of the handler list
+ *
+ * @param tptr pointer to the object that has the handler function
+ * @param mptr pointer to the actual handler function
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+ return add_common(tptr, mptr, irq, true);
+ }
+
+ /** Remove a handler from an interrupt
+ *
+ * @param handler the function object for the handler to remove
+ * @param irq the interrupt number
+ *
+ * @returns
+ * true if the handler was found and removed, false otherwise
+ */
+ bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
+
+private:
+ InterruptManager();
+ ~InterruptManager();
+
+ // We declare the copy contructor and the assignment operator, but we don't
+ // implement them. This way, if someone tries to copy/assign our instance,
+ // he will get an error at compile time.
+ InterruptManager(const InterruptManager&);
+ InterruptManager& operator =(const InterruptManager&);
+
+ template<typename T>
+ pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {
+ int irq_pos = get_irq_index(irq);
+ bool change = must_replace_vector(irq);
+
+ pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
+ if (change)
+ NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+ return pf;
+ }
+
+ pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);
+ bool must_replace_vector(IRQn_Type irq);
+ int get_irq_index(IRQn_Type irq);
+ void irq_helper();
+ void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);
+ static void static_irq_helper();
+
+ CallChain* _chains[NVIC_NUM_VECTORS];
+ static InterruptManager* _instance;
+};
+
+} // namespace mbed
+
+#endif
+
--- a/api/Serial.h Mon Aug 05 14:54:27 2013 +0000
+++ b/api/Serial.h Wed Aug 07 16:43:59 2013 +0300
@@ -23,6 +23,7 @@
#include "Stream.h"
#include "FunctionPointer.h"
#include "serial_api.h"
+#include "CallChain.h"
namespace mbed {
@@ -82,7 +83,7 @@
* @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None)
* @param stop The number of stop bits (1 or 2; default = 1)
*/
- void format(int bits = 8, Parity parity=Serial::None, int stop_bits=1);
+ void format(int bits=8, Parity parity=Serial::None, int stop_bits=1);
/** Determine if there is a character available to read
*
@@ -104,23 +105,95 @@
*
* @param fptr A pointer to a void function, or 0 to set as none
* @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ *
+ * @returns
+ * The function object created for 'fptr'
*/
- void attach(void (*fptr)(void), IrqType type=RxIrq);
+ pFunctionPointer_t attach(void (*fptr)(void), IrqType type=RxIrq);
+
+ /** Add a function to be called when a serial interrupt is generated at the end of the call chain
+ *
+ * @param fptr the function to add
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ *
+ * @returns
+ * The function object created for 'fptr'
+ */
+ pFunctionPointer_t add_handler(void (*fptr)(void), IrqType type=RxIrq) {
+ return add_handler_helper(fptr, type);
+ }
+
+ /** Add a function to be called when a serial interrupt is generated at the beginning of the call chain
+ *
+ * @param fptr the function to add
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ *
+ * @returns
+ * The function object created for 'fptr'
+ */
+ pFunctionPointer_t add_handler_front(void (*fptr)(void), IrqType type=RxIrq) {
+ return add_handler_helper(fptr, type, true);
+ }
/** Attach a member function to call whenever a serial interrupt is generated
*
* @param tptr pointer to the object to call the member function on
* @param mptr pointer to the member function to be called
* @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ *
+ * @param
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ _irq[type].clear();
+ pFunctionPointer_t pf = _irq[type].add(tptr, mptr);
+ serial_irq_set(&_serial, (SerialIrq)type, 1);
+ return pf;
+ }
+ else
+ return NULL;
+ }
+
+ /** Add a function to be called when a serial interrupt is generated at the end of the call chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ *
+ * @returns
+ * The function object created for 'fptr'
*/
template<typename T>
- void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
- if((mptr != NULL) && (tptr != NULL)) {
- _irq[type].attach(tptr, mptr);
- serial_irq_set(&_serial, (SerialIrq)type, 1);
- }
+ pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+ return add_handler_helper(tptr, mptr, type);
}
+ /** Add a function to be called when a serial interrupt is generated at the beginning of the call chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ *
+ * @returns
+ * The function object created for 'fptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+ return add_handler_helper(tptr, mptr, type, true);
+ }
+
+ /** Remove a function from the list of functions to be called when a serial interrupt is generated
+ *
+ * @param pf the function object to remove
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ *
+ * @returns
+ * true if the function was found and removed, false otherwise
+ */
+ bool remove_handler(pFunctionPointer_t pf, IrqType type=RxIrq);
+
/** Generate a break condition on the serial line
*/
void send_break();
@@ -130,9 +203,21 @@
protected:
virtual int _getc();
virtual int _putc(int c);
+ pFunctionPointer_t add_handler_helper(void (*function)(void), IrqType type, bool front=false);
+
+ template<typename T>
+ pFunctionPointer_t add_handler_helper(T* tptr, void (T::*mptr)(void), IrqType type, bool front=false) {
+ if ((mptr != NULL) && (tptr != NULL)) {
+ pFunctionPointer_t pf = front ? _irq[type].add_front(tptr, mptr) : _irq[type].add(tptr, mptr);
+ serial_irq_set(&_serial, (SerialIrq)type, 1);
+ return pf;
+ }
+ else
+ return NULL;
+ }
serial_t _serial;
- FunctionPointer _irq[2];
+ CallChain _irq[2];
int _baud;
};
--- a/api/Ticker.h Mon Aug 05 14:54:27 2013 +0000
+++ b/api/Ticker.h Wed Aug 07 16:43:59 2013 +0300
@@ -18,6 +18,7 @@
#include "TimerEvent.h"
#include "FunctionPointer.h"
+#include "CallChain.h"
namespace mbed {
@@ -62,9 +63,34 @@
*
* @param fptr pointer to the function to be called
* @param t the time between calls in seconds
+ *
+ * @returns
+ * The function object created for 'fptr'
*/
- void attach(void (*fptr)(void), float t) {
- attach_us(fptr, t * 1000000.0f);
+ pFunctionPointer_t attach(void (*fptr)(void), float t) {
+ return attach_us(fptr, t * 1000000.0f);
+ }
+
+ /** Add a function to be called by the Ticker at the end of the call chain
+ *
+ * @param fptr the function to add
+ *
+ * @returns
+ * The function object created for 'fptr'
+ */
+ pFunctionPointer_t add_function(void (*fptr)(void)) {
+ return add_function_helper(fptr);
+ }
+
+ /** Add a function to be called by the Ticker at the beginning of the call chain
+ *
+ * @param fptr the function to add
+ *
+ * @returns
+ * The function object created for 'fptr'
+ */
+ pFunctionPointer_t add_function_front(void (*fptr)(void)) {
+ return add_function_helper(fptr, true);
}
/** Attach a member function to be called by the Ticker, specifiying the interval in seconds
@@ -72,20 +98,53 @@
* @param tptr pointer to the object to call the member function on
* @param mptr pointer to the member function to be called
* @param t the time between calls in seconds
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
*/
template<typename T>
- void attach(T* tptr, void (T::*mptr)(void), float t) {
- attach_us(tptr, mptr, t * 1000000.0f);
+ pFunctionPointer_t attach(T* tptr, void (T::*mptr)(void), float t) {
+ return attach_us(tptr, mptr, t * 1000000.0f);
+ }
+
+ /** Add a function to be called by the Ticker at the end of the call chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_function(T* tptr, void (T::*mptr)(void)) {
+ return add_function_helper(tptr, mptr);
+ }
+
+ /** Add a function to be called by the Ticker at the beginning of the call chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_function_front(T* tptr, void (T::*mptr)(void)) {
+ return add_function_helper(tptr, mptr, true);
}
/** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
*
* @param fptr pointer to the function to be called
* @param t the time between calls in micro-seconds
+ *
+ * @returns
+ * The function object created for 'fptr'
*/
- void attach_us(void (*fptr)(void), unsigned int t) {
- _function.attach(fptr);
+ pFunctionPointer_t attach_us(void (*fptr)(void), unsigned int t) {
+ pFunctionPointer_t pf = _chain.add(fptr);
setup(t);
+ return pf;
}
/** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
@@ -93,23 +152,49 @@
* @param tptr pointer to the object to call the member function on
* @param mptr pointer to the member function to be called
* @param t the time between calls in micro-seconds
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
*/
template<typename T>
- void attach_us(T* tptr, void (T::*mptr)(void), unsigned int t) {
- _function.attach(tptr, mptr);
+ pFunctionPointer_t attach_us(T* tptr, void (T::*mptr)(void), unsigned int t) {
+ pFunctionPointer_t pf = _chain.add(mptr, tptr);
setup(t);
+ return pf;
}
/** Detach the function
*/
void detach();
+ /** Remove a function from the Ticker's call chain
+ *
+ * @param pf the function object to remove
+ *
+ * @returns
+ * true if the function was found and removed, false otherwise
+ */
+ bool remove_function(pFunctionPointer_t pf) {
+ bool res = _chain.remove(pf);
+ if (res && _chain.size() == 0)
+ detach();
+ return res;
+ }
+
protected:
void setup(unsigned int t);
+ pFunctionPointer_t add_function_helper(void (*fptr)(void), bool front=false);
virtual void handler();
+ template<typename T>
+ pFunctionPointer_t add_function_helper(T* tptr, void (T::*mptr)(void), bool front=false) {
+ if (_chain.size() == 0)
+ return NULL;
+ return front ? _chain.add_front(tptr, mptr) : _chain.add(tptr, mptr);
+ }
+
unsigned int _delay;
- FunctionPointer _function;
+ CallChain _chain;
};
} // namespace mbed
--- a/common/CAN.cpp Mon Aug 05 14:54:27 2013 +0000
+++ b/common/CAN.cpp Wed Aug 07 16:43:59 2013 +0300
@@ -23,10 +23,12 @@
CAN::CAN(PinName rd, PinName td) {
can_init(&_can, rd, td);
+ can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
}
CAN::~CAN() {
can_free(&_can);
+ can_irq_free(&_can);
}
int CAN::frequency(int f) {
@@ -57,62 +59,23 @@
can_monitor(&_can, (silent) ? 1 : 0);
}
-static FunctionPointer* can_obj[2] = { NULL };
-
-// Have to check that the CAN block is active before reading the Interrupt
-// Control Register, or the mbed hangs
-void can_irq(void) {
- uint32_t icr;
-
- if(LPC_SC->PCONP & (1 << 13)) {
- icr = LPC_CAN1->ICR;
+int CAN::mode(Mode mode) {
+ return can_mode(&_can, (CanMode)mode);
+}
- if(icr && (can_obj[0] != NULL)) {
- can_obj[0]->call();
- }
- }
-
- if(LPC_SC->PCONP & (1 << 14)) {
- icr = LPC_CAN2->ICR;
- if(icr && (can_obj[1] != NULL)) {
- can_obj[1]->call();
+ void CAN::attach(void (*fptr)(void), IrqType type) {
+ if (fptr) {
+ _irq[(CanIrqType)type].attach(fptr);
+ can_irq_set(&_can, (CanIrqType)type, 1);
+ } else {
+ can_irq_set(&_can, (CanIrqType)type, 0);
}
}
-}
-
-void CAN::setup_interrupt(void) {
- switch ((int)_can.dev) {
- case CAN_1: can_obj[0] = &_rxirq; break;
- case CAN_2: can_obj[1] = &_rxirq; break;
+ void CAN::_irq_handler(uint32_t id, CanIrqType type) {
+ CAN *handler = (CAN*)id;
+ handler->_irq[type].call();
}
- _can.dev->MOD |= 1;
- _can.dev->IER |= 1;
- _can.dev->MOD &= ~1;
- NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq);
- NVIC_EnableIRQ(CAN_IRQn);
-}
-
-void CAN::remove_interrupt(void) {
- switch ((int)_can.dev) {
- case CAN_1: can_obj[0] = NULL; break;
- case CAN_2: can_obj[1] = NULL; break;
- }
-
- _can.dev->IER &= ~(1);
- if ((can_obj[0] == NULL) && (can_obj[1] == NULL)) {
- NVIC_DisableIRQ(CAN_IRQn);
- }
-}
-
-void CAN::attach(void (*fptr)(void)) {
- if (fptr != NULL) {
- _rxirq.attach(fptr);
- setup_interrupt();
- } else {
- remove_interrupt();
- }
-}
} // namespace mbed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/common/CallChain.cpp Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,98 @@
+#include "CallChain.h"
+#include "cmsis.h"
+
+namespace mbed {
+
+CallChain::CallChain(int size) : _size(size), _elements(0) {
+ _chain = new pFunctionPointer_t[size]();
+}
+
+CallChain::~CallChain() {
+ clear();
+ delete _chain;
+}
+
+pFunctionPointer_t CallChain::add(void (*function)(void)) {
+ return common_add(new FunctionPointer(function));
+}
+
+pFunctionPointer_t CallChain::add_front(void (*function)(void)) {
+ return common_add_front(new FunctionPointer(function));
+}
+
+int CallChain::size() const {
+ return _elements;
+}
+
+pFunctionPointer_t CallChain::get(int i) const {
+ if (i < 0 || i >= _elements)
+ return NULL;
+ return _chain[i];
+}
+
+int CallChain::find(pFunctionPointer_t f) const {
+ for (int i = 0; i < _elements; i++)
+ if (f == _chain[i])
+ return i;
+ return -1;
+}
+
+void CallChain::clear() {
+ __disable_irq();
+ for(int i = 0; i < _elements; i ++) {
+ delete _chain[i];
+ _chain[i] = NULL;
+ }
+ _elements = 0;
+ __enable_irq();
+}
+
+bool CallChain::remove(pFunctionPointer_t f) {
+ int i;
+
+ if ((i = find(f)) == -1)
+ return false;
+ __disable_irq();
+ if (i != _elements - 1)
+ memmove(_chain + i, _chain + i + 1, (_elements - i - 1) * sizeof(pFunctionPointer_t));
+ delete f;
+ _elements --;
+ __enable_irq();
+ return true;
+}
+
+void CallChain::call() {
+ for(int i = 0; i < _elements; i++)
+ _chain[i]->call();
+}
+
+void CallChain::_check_size() {
+ if (_elements < _size)
+ return;
+ __disable_irq();
+ _size = (_size < 4) ? 4 : _size + 4;
+ pFunctionPointer_t* new_chain = new pFunctionPointer_t[_size]();
+ memcpy(new_chain, _chain, _elements * sizeof(pFunctionPointer_t));
+ delete _chain;
+ _chain = new_chain;
+ __enable_irq();
+}
+
+pFunctionPointer_t CallChain::common_add(pFunctionPointer_t pf) {
+ _check_size();
+ _chain[_elements] = pf;
+ _elements ++;
+ return pf;
+}
+
+pFunctionPointer_t CallChain::common_add_front(pFunctionPointer_t pf) {
+ _check_size();
+ __disable_irq();
+ memmove(_chain + 1, _chain, _elements * sizeof(pFunctionPointer_t));
+ _chain[0] = pf;
+ _elements ++;
+ __enable_irq();
+ return pf;
+}
+
+} // namespace mbed
--- a/common/FunctionPointer.cpp Mon Aug 05 14:54:27 2013 +0000
+++ b/common/FunctionPointer.cpp Wed Aug 07 16:43:59 2013 +0300
@@ -34,4 +34,10 @@
}
}
+#ifdef MBED_OPERATORS
+void FunctionPointer::operator ()(void) {
+ call();
+}
+#endif
+
} // namespace mbed
--- a/common/InterruptIn.cpp Mon Aug 05 14:54:27 2013 +0000
+++ b/common/InterruptIn.cpp Wed Aug 07 16:43:59 2013 +0300
@@ -36,22 +36,58 @@
gpio_mode(&gpio, pull);
}
-void InterruptIn::rise(void (*fptr)(void)) {
+pFunctionPointer_t InterruptIn::rise(void (*fptr)(void)) {
+ pFunctionPointer_t pf = NULL;
+ _rise.clear();
if (fptr) {
- _rise.attach(fptr);
+ pf = _rise.add(fptr);
gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
} else {
gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
}
+ return pf;
+}
+
+pFunctionPointer_t InterruptIn::rise_add_common(void (*fptr)(void), bool front) {
+ if (NULL == fptr)
+ return NULL;
+ pFunctionPointer_t pf = front ? _rise.add_front(fptr) : _rise.add(fptr);
+ gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+ return pf;
}
-void InterruptIn::fall(void (*fptr)(void)) {
+bool InterruptIn::rise_remove(pFunctionPointer_t pf) {
+ bool res = _rise.remove(pf);
+ if (res && _rise.size() == 0)
+ gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
+ return res;
+}
+
+pFunctionPointer_t InterruptIn::fall(void (*fptr)(void)) {
+ pFunctionPointer_t pf = NULL;
+ _fall.clear();
if (fptr) {
- _fall.attach(fptr);
+ pf = _fall.add(fptr);
gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
} else {
gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
}
+ return pf;
+}
+
+pFunctionPointer_t InterruptIn::fall_add_common(void (*fptr)(void), bool front) {
+ if (NULL == fptr)
+ return NULL;
+ pFunctionPointer_t pf = front ? _fall.add_front(fptr) : _fall.add(fptr);
+ gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+ return pf;
+}
+
+bool InterruptIn::fall_remove(pFunctionPointer_t pf) {
+ bool res = _fall.remove(pf);
+ if (res && _fall.size() == 0)
+ gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
+ return res;
}
void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/common/InterruptManager.cpp Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,89 @@
+#include "InterruptManager.h"
+#include <string.h>
+
+#define CHAIN_INITIAL_SIZE 4
+
+namespace mbed {
+
+typedef void (*pvoidf)(void);
+
+InterruptManager* InterruptManager::_instance = NULL;
+
+InterruptManager* InterruptManager::get() {
+ if (NULL == _instance)
+ _instance = new InterruptManager();
+ return _instance;
+}
+
+InterruptManager::InterruptManager() {
+ memset(_chains, 0, NVIC_NUM_VECTORS * sizeof(CallChain*));
+}
+
+void InterruptManager::destroy() {
+ // Not a good idea to call this unless NO interrupt at all
+ // is under the control of the handler; otherwise, a system crash
+ // is very likely to occur
+ if (NULL != _instance) {
+ delete _instance;
+ _instance = NULL;
+ }
+}
+
+InterruptManager::~InterruptManager() {
+ for(int i = 0; i < NVIC_NUM_VECTORS; i++)
+ if (NULL != _chains[i])
+ delete _chains[i];
+}
+
+bool InterruptManager::must_replace_vector(IRQn_Type irq) {
+ int irq_pos = get_irq_index(irq);
+
+ if (NULL == _chains[irq_pos]) {
+ _chains[irq_pos] = new CallChain(CHAIN_INITIAL_SIZE);
+ _chains[irq_pos]->add((pvoidf)NVIC_GetVector(irq));
+ return true;
+ }
+ return false;
+}
+
+pFunctionPointer_t InterruptManager::add_common(void (*function)(void), IRQn_Type irq, bool front) {
+ int irq_pos = get_irq_index(irq);
+ bool change = must_replace_vector(irq);
+
+ pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(function) : _chains[irq_pos]->add(function);
+ if (change)
+ NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+ return pf;
+}
+
+bool InterruptManager::remove_handler(pFunctionPointer_t handler, IRQn_Type irq) {
+ int irq_pos = get_irq_index(irq);
+
+ if (NULL == _chains[irq_pos])
+ return false;
+ if (!_chains[irq_pos]->remove(handler))
+ return false;
+ // If there's a single function left in the chain, swith the interrupt vector
+ // to call that function directly. This way we save both time and space.
+ if (_chains[irq_pos]->size() == 1 && NULL != _chains[irq_pos]->get(0)->get_function()) {
+ NVIC_SetVector(irq, (uint32_t)_chains[irq_pos]->get(0)->get_function());
+ delete _chains[irq_pos];
+ _chains[irq_pos] = NULL;
+ }
+ return true;
+}
+
+void InterruptManager::irq_helper() {
+ _chains[__get_IPSR()]->call();
+}
+
+int InterruptManager::get_irq_index(IRQn_Type irq) {
+ return (int)irq + NVIC_USER_IRQ_OFFSET;
+}
+
+void InterruptManager::static_irq_helper() {
+ InterruptManager::get()->irq_helper();
+}
+
+} // namespace mbed
+
--- a/common/Serial.cpp Mon Aug 05 14:54:27 2013 +0000
+++ b/common/Serial.cpp Wed Aug 07 16:43:59 2013 +0300
@@ -44,15 +44,32 @@
return serial_writable(&_serial);
}
-void Serial::attach(void (*fptr)(void), IrqType type) {
+pFunctionPointer_t Serial::attach(void (*fptr)(void), IrqType type) {
+ pFunctionPointer_t pf = NULL;
+ _irq[type].clear();
if (fptr) {
- _irq[type].attach(fptr);
+ pf = _irq[type].add(fptr);
serial_irq_set(&_serial, (SerialIrq)type, 1);
} else {
serial_irq_set(&_serial, (SerialIrq)type, 0);
}
+ return pf;
}
+pFunctionPointer_t Serial::add_handler_helper(void (*fptr)(void), IrqType type, bool front) {
+ if (NULL == fptr)
+ return NULL;
+ pFunctionPointer_t pf = front ? _irq[type].add_front(fptr) : _irq[type].add(fptr);
+ serial_irq_set(&_serial, (SerialIrq)type, 1);
+ return pf;
+}
+
+bool Serial::remove_handler(pFunctionPointer_t pf, IrqType type) {
+ bool res = _irq[type].remove(pf);
+ if (res && _irq[type].size() == 0)
+ serial_irq_set(&_serial, (SerialIrq)type, 0);
+ return res;
+}
void Serial::_irq_handler(uint32_t id, SerialIrq irq_type) {
Serial *handler = (Serial*)id;
--- a/common/Ticker.cpp Mon Aug 05 14:54:27 2013 +0000
+++ b/common/Ticker.cpp Wed Aug 07 16:43:59 2013 +0300
@@ -22,7 +22,7 @@
void Ticker::detach() {
remove();
- _function.attach(0);
+ _chain.clear();
}
void Ticker::setup(unsigned int t) {
@@ -33,7 +33,13 @@
void Ticker::handler() {
insert(event.timestamp + _delay);
- _function.call();
+ _chain.call();
+}
+
+pFunctionPointer_t Ticker::add_function_helper(void (*fptr)(void), bool front) {
+ if (_chain.size() == 0)
+ return NULL;
+ return front ? _chain.add_front(fptr) : _chain.add(fptr);
}
} // namespace mbed
--- a/common/Timeout.cpp Mon Aug 05 14:54:27 2013 +0000
+++ b/common/Timeout.cpp Wed Aug 07 16:43:59 2013 +0300
@@ -18,7 +18,7 @@
namespace mbed {
void Timeout::handler() {
- _function.call();
+ _chain.call();
}
} // namespace mbed
--- a/hal/can_api.h Mon Aug 05 14:54:27 2013 +0000
+++ b/hal/can_api.h Wed Aug 07 16:43:59 2013 +0300
@@ -28,13 +28,43 @@
extern "C" {
#endif
+typedef enum {
+ IRQ_RX,
+ IRQ_TX,
+ IRQ_ERROR,
+ IRQ_OVERRUN,
+ IRQ_WAKEUP,
+ IRQ_PASSIVE,
+ IRQ_ARB,
+ IRQ_BUS,
+ IRQ_READY
+} CanIrqType;
+
+
+typedef enum {
+ MODE_RESET,
+ MODE_NORMAL,
+ MODE_SILENT,
+ MODE_TEST_GLOBAL,
+ MODE_TEST_LOCAL,
+ MODE_TEST_SILENT
+} CanMode;
+
+typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
+
typedef struct can_s can_t;
void can_init (can_t *obj, PinName rd, PinName td);
void can_free (can_t *obj);
int can_frequency(can_t *obj, int hz);
+
+void can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id);
+void can_irq_free (can_t *obj);
+void can_irq_set (can_t *obj, CanIrqType irq, uint32_t enable);
+
int can_write (can_t *obj, CAN_Message, int cc);
int can_read (can_t *obj, CAN_Message *msg);
+int can_mode (can_t *obj, CanMode mode);
void can_reset (can_t *obj);
unsigned char can_rderror (can_t *obj);
unsigned char can_tderror (can_t *obj);
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/MKL25Z4.ld Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,163 @@
+/*
+ * KL25Z ARM GCC linker script file
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFFF0C0, LENGTH = 16K - 0xC0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ *(.text.Reset_Handler)
+ *(.text.System_Init)
+ . = ALIGN(4);
+ } > VECTORS
+
+ .flash_protect :
+ {
+ KEEP(*(.kinetis_flash_config_field))
+ . = ALIGN(4);
+ } > FLASH_PROTECTION
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/startup_MKL25Z4.s Wed Aug 07 16:43:59 2013 +0300 @@ -0,0 +1,236 @@ +/* KL25Z startup ARM GCC + * Purpose: startup file for Cortex-M0 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.2 + * Date: 15 Nov 2011 + * + * Copyright (c) 2011, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv6-m + +/* Memory Model + The HEAP starts at the end of the DATA section and grows upward. + + The STACK starts at the end of the RAM and grows downward. + + The HEAP and stack STACK are only checked at compile time: + (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE + + This is just a check for the bare minimum for the Heap+Stack area before + aborting compilation, it is not the run time limit: + Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 + */ + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x80 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x80 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vector_table,"a",%progbits + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */ + .long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */ + .long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */ + .long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */ + .long Default_Handler /* Reserved interrupt 20 */ + .long FTFA_IRQHandler /* FTFA interrupt */ + .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */ + .long LLW_IRQHandler /* Low Leakage Wakeup */ + .long I2C0_IRQHandler /* I2C0 interrupt */ + .long I2C1_IRQHandler /* I2C0 interrupt 25 */ + .long SPI0_IRQHandler /* SPI0 interrupt */ + .long SPI1_IRQHandler /* SPI1 interrupt */ + .long UART0_IRQHandler /* UART0 status/error interrupt */ + .long UART1_IRQHandler /* UART1 status/error interrupt */ + .long UART2_IRQHandler /* UART2 status/error interrupt */ + .long ADC0_IRQHandler /* ADC0 interrupt */ + .long CMP0_IRQHandler /* CMP0 interrupt */ + .long TPM0_IRQHandler /* TPM0 fault, overflow and channels interrupt */ + .long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt */ + .long TPM2_IRQHandler /* TPM2 fault, overflow and channels interrupt */ + .long RTC_IRQHandler /* RTC interrupt */ + .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */ + .long PIT_IRQHandler /* PIT timer interrupt */ + .long Default_Handler /* Reserved interrupt 39 */ + .long USB0_IRQHandler /* USB0 interrupt */ + .long DAC0_IRQHandler /* DAC interrupt */ + .long TSI0_IRQHandler /* TSI0 interrupt */ + .long MCG_IRQHandler /* MCG interrupt */ + .long LPTimer_IRQHandler /* LPTimer interrupt */ + .long Default_Handler /* Reserved interrupt 45 */ + .long PORTA_IRQHandler /* Port A interrupt */ + .long PORTD_IRQHandler /* Port D interrupt */ + + .size __isr_vector, . - __isr_vector + + .section .text.Reset_Handler + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .flash_to_ram_loop_end + + movs r4, 0 +.flash_to_ram_loop: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .flash_to_ram_loop +.flash_to_ram_loop_end: + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler SVC_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + def_default_handler DMA0_IRQHandler + def_default_handler DMA1_IRQHandler + def_default_handler DMA2_IRQHandler + def_default_handler DMA3_IRQHandler + def_default_handler FTFA_IRQHandler + def_default_handler LVD_LVW_IRQHandler + def_default_handler LLW_IRQHandler + def_default_handler I2C0_IRQHandler + def_default_handler I2C1_IRQHandler + def_default_handler SPI0_IRQHandler + def_default_handler SPI1_IRQHandler + def_default_handler UART0_IRQHandler + def_default_handler UART1_IRQHandler + def_default_handler UART2_IRQHandler + def_default_handler ADC0_IRQHandler + def_default_handler CMP0_IRQHandler + def_default_handler TPM0_IRQHandler + def_default_handler TPM1_IRQHandler + def_default_handler TPM2_IRQHandler + def_default_handler RTC_IRQHandler + def_default_handler RTC_Seconds_IRQHandler + def_default_handler PIT_IRQHandler + def_default_handler USB0_IRQHandler + def_default_handler DAC0_IRQHandler + def_default_handler TSI0_IRQHandler + def_default_handler MCG_IRQHandler + def_default_handler LPTimer_IRQHandler + def_default_handler PORTA_IRQHandler + def_default_handler PORTD_IRQHandler + + .weak DEF_IRQHandler + .set DEF_IRQHandler, Default_Handler + +/* Flash protection region, placed at 0x400 */ + .text + .thumb + .align 2 + .section .kinetis_flash_config_field,"a",%progbits +kinetis_flash_config: + .long 0xffffffff + .long 0xffffffff + .long 0xffffffff + .long 0xfffffffe + + .end
--- a/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/cmsis_nvic.c Mon Aug 05 14:54:27 2013 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/cmsis_nvic.c Wed Aug 07 16:43:59 2013 +0300 @@ -5,7 +5,6 @@ */ #include "cmsis_nvic.h" -#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals #define NVIC_RAM_VECTOR_ADDRESS (0x1FFFF000) // Vectors positioned at start of RAM #define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
--- a/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/cmsis_nvic.h Mon Aug 05 14:54:27 2013 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/cmsis_nvic.h Wed Aug 07 16:43:59 2013 +0300 @@ -7,6 +7,9 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H +#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals +#define NVIC_USER_IRQ_OFFSET 16 + #include "cmsis.h" #ifdef __cplusplus
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.c Mon Aug 05 14:54:27 2013 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.c Wed Aug 07 16:43:59 2013 +0300
@@ -27,7 +27,6 @@
* Option 2 is the one to go for, as RAM is the most valuable resource
*/
-#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.h Mon Aug 05 14:54:27 2013 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.h Wed Aug 07 16:43:59 2013 +0300
@@ -9,6 +9,9 @@
#include "cmsis.h"
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
#ifdef __cplusplus
extern "C" {
#endif
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.c Mon Aug 05 14:54:27 2013 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.c Wed Aug 07 16:43:59 2013 +0300 @@ -5,7 +5,6 @@ */ #include "cmsis_nvic.h" -#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals #define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM #define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.h Mon Aug 05 14:54:27 2013 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.h Wed Aug 07 16:43:59 2013 +0300
@@ -9,6 +9,9 @@
#include "cmsis.h"
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
#ifdef __cplusplus
extern "C" {
#endif
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis_nvic.c Mon Aug 05 14:54:27 2013 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis_nvic.c Wed Aug 07 16:43:59 2013 +0300
@@ -5,7 +5,6 @@
*/
#include "cmsis_nvic.h"
-#define NVIC_NUM_VECTORS (16 + 33) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
@@ -22,11 +21,11 @@
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
- vectors[IRQn + 16] = vector;
+ vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
- return vectors[IRQn + 16];
+ return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
}
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis_nvic.h Mon Aug 05 14:54:27 2013 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis_nvic.h Wed Aug 07 16:43:59 2013 +0300
@@ -9,6 +9,9 @@
#include "cmsis.h"
+#define NVIC_NUM_VECTORS (16 + 33)
+#define NVIC_USER_IRQ_OFFSET 16
+
#ifdef __cplusplus
extern "C" {
#endif
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis_nvic.h Mon Aug 05 14:54:27 2013 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis_nvic.h Wed Aug 07 16:43:59 2013 +0300 @@ -7,6 +7,9 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H +#define NVIC_NUM_VECTORS 32 +#define NVIC_USER_IRQ_OFFSET 0 + #include "cmsis.h" #ifdef __cplusplus
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.h Mon Aug 05 14:54:27 2013 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.h Wed Aug 07 16:43:59 2013 +0300
@@ -8,6 +8,8 @@
#ifndef __ARM7_CORE_H__
#define __ARM7_CORE_H__
+#include "vector_defns.h"
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -255,6 +257,15 @@
NVIC->IntEnClr = 1 << (uint32_t)IRQn;
}
+static __INLINE uint32_t __get_IPSR(void)
+{
+ unsigned i;
+
+ for(i = 0; i < 32; i ++)
+ if(NVIC->Address == NVIC->VectAddr[i])
+ return i;
+ return 1; // 1 is an invalid entry in the interrupt table on LPC2368
+}
#ifdef __cplusplus
}
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/vector_defns.h Mon Aug 05 14:54:27 2013 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/vector_defns.h Wed Aug 07 16:43:59 2013 +0300 @@ -37,8 +37,10 @@ // VIC register addresses #define VIC_Base 0xfffff000 #define VICAddress_Offset 0xf00 +#define VICVectAddr0_Offset 0x100 #define VICVectAddr2_Offset 0x108 #define VICVectAddr3_Offset 0x10c +#define VICVectAddr31_Offset 0x17c #define VICIntEnClr_Offset 0x014 #define VICIntEnClr (*(volatile unsigned long *)(VIC_Base + 0x014)) #define VICVectAddr2 (*(volatile unsigned long *)(VIC_Base + 0x108))
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC408X/LPC407x_8x_177x_8x.h Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,1521 @@
+/****************************************************************************************************//**
+* $Id$ LPC407x_8x_177x_8x.h 2012-04-25
+*//**
+ * @file LPC407x_8x_177x_8x.h
+ *
+ * @brief CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for
+ * NXP LPC407x_8x_177x_8x.
+ * @version V0.7
+ * @date 20. June 2012
+ * @author NXP MCU SW Application Team
+*
+* Copyright(C) 2012, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+#ifndef __LPC407x_8x_177x_8x_H__
+#define __LPC407x_8x_177x_8x_H__
+
+#define CORE_M4
+
+// ##################
+// Code Red - excluded extern "C" as unrequired
+// ##################
+#if 0
+#ifdef __cplusplus
+extern "C" {
+#endif
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+ TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
+ TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
+ TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
+ TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
+ UART0_IRQn = 5, /*!< UART0 Interrupt */
+ UART1_IRQn = 6, /*!< UART1 Interrupt */
+ UART2_IRQn = 7, /*!< UART2 Interrupt */
+ UART3_IRQn = 8, /*!< UART3 Interrupt */
+ PWM1_IRQn = 9, /*!< PWM1 Interrupt */
+ I2C0_IRQn = 10, /*!< I2C0 Interrupt */
+ I2C1_IRQn = 11, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 12, /*!< I2C2 Interrupt */
+ Reserved0_IRQn = 13, /*!< Reserved */
+ SSP0_IRQn = 14, /*!< SSP0 Interrupt */
+ SSP1_IRQn = 15, /*!< SSP1 Interrupt */
+ PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
+ RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
+ EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
+ EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
+ EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
+ EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
+ ADC_IRQn = 22, /*!< A/D Converter Interrupt */
+ BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
+ USB_IRQn = 24, /*!< USB Interrupt */
+ CAN_IRQn = 25, /*!< CAN Interrupt */
+ DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
+ I2S_IRQn = 27, /*!< I2S Interrupt */
+ ENET_IRQn = 28, /*!< Ethernet Interrupt */
+ MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */
+ MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
+ QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
+ PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
+ USBActivity_IRQn = 33, /*!< USB Activity interrupt */
+ CANActivity_IRQn = 34, /*!< CAN Activity interrupt */
+ UART4_IRQn = 35, /*!< UART4 Interrupt */
+ SSP2_IRQn = 36, /*!< SSP2 Interrupt */
+ LCD_IRQn = 37, /*!< LCD Interrupt */
+ GPIO_IRQn = 38, /*!< GPIO Interrupt */
+ PWM0_IRQn = 39, /*!< 39 PWM0 */
+ EEPROM_IRQn = 40, /*!< 40 EEPROM */
+ CMP0_IRQn = 41, /*!< 41 CMP0 */
+ CMP1_IRQn = 42 /*!< 42 CMP1 */
+} IRQn_Type;
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+#ifdef CORE_M4
+/* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */
+#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+
+
+#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
+#else
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
+
+#endif
+
+#include "system_LPC407x_8x_177x_8x.h" /*!< LPC408x_7x System */
+
+
+
+
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+typedef struct /* Common Registers */
+{
+ __I uint32_t IntStat;
+ __I uint32_t IntTCStat;
+ __O uint32_t IntTCClear;
+ __I uint32_t IntErrStat;
+ __O uint32_t IntErrClr;
+ __I uint32_t RawIntTCStat;
+ __I uint32_t RawIntErrStat;
+ __I uint32_t EnbldChns;
+ __IO uint32_t SoftBReq;
+ __IO uint32_t SoftSReq;
+ __IO uint32_t SoftLBReq;
+ __IO uint32_t SoftLSReq;
+ __IO uint32_t Config;
+ __IO uint32_t Sync;
+} LPC_GPDMA_TypeDef;
+
+typedef struct /* Channel Registers */
+{
+ __IO uint32_t CSrcAddr;
+ __IO uint32_t CDestAddr;
+ __IO uint32_t CLLI;
+ __IO uint32_t CControl;
+ __IO uint32_t CConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- System Control (SC) ------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */
+ __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */
+ __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */
+ __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */
+ uint32_t RESERVED1[4];
+ __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */
+ __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */
+ __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */
+ __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */
+ uint32_t RESERVED2[4];
+ __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
+ __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
+ __IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control for Peripherals Register */
+ uint32_t RESERVED3[13];
+ __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */
+ __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */
+ __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */
+ __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
+ __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
+ __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
+ uint32_t RESERVED4[10];
+ __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
+ uint32_t RESERVED5[1];
+ __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
+ __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
+ uint32_t RESERVED6[12];
+ __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
+ uint32_t RESERVED7[7];
+ __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
+ __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */
+ __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */
+ uint32_t RESERVED8;
+ __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */
+ __IO uint32_t SPIFICLKSEL;
+ __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */
+ uint32_t RESERVED10[1];
+ __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
+ __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
+ __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
+ __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */
+ __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */
+ uint32_t RESERVED11[2];
+ __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */
+ __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
+ } LPC_SC_TypeDef;
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+typedef struct
+{
+ __IO uint32_t MAC1; /* MAC Registers */
+ __IO uint32_t MAC2;
+ __IO uint32_t IPGT;
+ __IO uint32_t IPGR;
+ __IO uint32_t CLRT;
+ __IO uint32_t MAXF;
+ __IO uint32_t SUPP;
+ __IO uint32_t TEST;
+ __IO uint32_t MCFG;
+ __IO uint32_t MCMD;
+ __IO uint32_t MADR;
+ __O uint32_t MWTD;
+ __I uint32_t MRDD;
+ __I uint32_t MIND;
+ uint32_t RESERVED0[2];
+ __IO uint32_t SA0;
+ __IO uint32_t SA1;
+ __IO uint32_t SA2;
+ uint32_t RESERVED1[45];
+ __IO uint32_t Command; /* Control Registers */
+ __I uint32_t Status;
+ __IO uint32_t RxDescriptor;
+ __IO uint32_t RxStatus;
+ __IO uint32_t RxDescriptorNumber;
+ __I uint32_t RxProduceIndex;
+ __IO uint32_t RxConsumeIndex;
+ __IO uint32_t TxDescriptor;
+ __IO uint32_t TxStatus;
+ __IO uint32_t TxDescriptorNumber;
+ __IO uint32_t TxProduceIndex;
+ __I uint32_t TxConsumeIndex;
+ uint32_t RESERVED2[10];
+ __I uint32_t TSV0;
+ __I uint32_t TSV1;
+ __I uint32_t RSV;
+ uint32_t RESERVED3[3];
+ __IO uint32_t FlowControlCounter;
+ __I uint32_t FlowControlStatus;
+ uint32_t RESERVED4[34];
+ __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
+ __I uint32_t RxFilterWoLStatus;
+ __O uint32_t RxFilterWoLClear;
+ uint32_t RESERVED5;
+ __IO uint32_t HashFilterL;
+ __IO uint32_t HashFilterH;
+ uint32_t RESERVED6[882];
+ __I uint32_t IntStatus; /* Module Control Registers */
+ __IO uint32_t IntEnable;
+ __O uint32_t IntClear;
+ __O uint32_t IntSet;
+ uint32_t RESERVED7;
+ __IO uint32_t PowerDown;
+ uint32_t RESERVED8;
+ __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+/*------------- LCD controller (LCD) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t TIMH; /* LCD Registers */
+ __IO uint32_t TIMV;
+ __IO uint32_t POL;
+ __IO uint32_t LE;
+ __IO uint32_t UPBASE;
+ __IO uint32_t LPBASE;
+ __IO uint32_t CTRL;
+ __IO uint32_t INTMSK;
+ __I uint32_t INTRAW;
+ __I uint32_t INTSTAT;
+ __O uint32_t INTCLR;
+ __I uint32_t UPCURR;
+ __I uint32_t LPCURR;
+ uint32_t RESERVED0[115];
+ __IO uint32_t PAL[128];
+ uint32_t RESERVED1[256];
+ __IO uint32_t CRSR_IMG[256];
+ __IO uint32_t CRSR_CTRL;
+ __IO uint32_t CRSR_CFG;
+ __IO uint32_t CRSR_PAL0;
+ __IO uint32_t CRSR_PAL1;
+ __IO uint32_t CRSR_XY;
+ __IO uint32_t CRSR_CLIP;
+ uint32_t RESERVED2[2];
+ __IO uint32_t CRSR_INTMSK;
+ __O uint32_t CRSR_INTCLR;
+ __I uint32_t CRSR_INTRAW;
+ __I uint32_t CRSR_INTSTAT;
+} LPC_LCD_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+typedef struct
+{
+ __I uint32_t Revision; /* USB Host Registers */
+ __IO uint32_t Control;
+ __IO uint32_t CommandStatus;
+ __IO uint32_t InterruptStatus;
+ __IO uint32_t InterruptEnable;
+ __IO uint32_t InterruptDisable;
+ __IO uint32_t HCCA;
+ __I uint32_t PeriodCurrentED;
+ __IO uint32_t ControlHeadED;
+ __IO uint32_t ControlCurrentED;
+ __IO uint32_t BulkHeadED;
+ __IO uint32_t BulkCurrentED;
+ __I uint32_t DoneHead;
+ __IO uint32_t FmInterval;
+ __I uint32_t FmRemaining;
+ __I uint32_t FmNumber;
+ __IO uint32_t PeriodicStart;
+ __IO uint32_t LSTreshold;
+ __IO uint32_t RhDescriptorA;
+ __IO uint32_t RhDescriptorB;
+ __IO uint32_t RhStatus;
+ __IO uint32_t RhPortStatus1;
+ __IO uint32_t RhPortStatus2;
+ uint32_t RESERVED0[40];
+ __I uint32_t Module_ID;
+
+ __I uint32_t IntSt; /* USB On-The-Go Registers */
+ __IO uint32_t IntEn;
+ __O uint32_t IntSet;
+ __O uint32_t IntClr;
+ __IO uint32_t StCtrl;
+ __IO uint32_t Tmr;
+ uint32_t RESERVED1[58];
+
+ __I uint32_t DevIntSt; /* USB Device Interrupt Registers */
+ __IO uint32_t DevIntEn;
+ __O uint32_t DevIntClr;
+ __O uint32_t DevIntSet;
+
+ __O uint32_t CmdCode; /* USB Device SIE Command Registers */
+ __I uint32_t CmdData;
+
+ __I uint32_t RxData; /* USB Device Transfer Registers */
+ __O uint32_t TxData;
+ __I uint32_t RxPLen;
+ __O uint32_t TxPLen;
+ __IO uint32_t Ctrl;
+ __O uint32_t DevIntPri;
+
+ __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
+ __IO uint32_t EpIntEn;
+ __O uint32_t EpIntClr;
+ __O uint32_t EpIntSet;
+ __O uint32_t EpIntPri;
+
+ __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
+ __O uint32_t EpInd;
+ __IO uint32_t MaxPSize;
+
+ __I uint32_t DMARSt; /* USB Device DMA Registers */
+ __O uint32_t DMARClr;
+ __O uint32_t DMARSet;
+ uint32_t RESERVED2[9];
+ __IO uint32_t UDCAH;
+ __I uint32_t EpDMASt;
+ __O uint32_t EpDMAEn;
+ __O uint32_t EpDMADis;
+ __I uint32_t DMAIntSt;
+ __IO uint32_t DMAIntEn;
+ uint32_t RESERVED3[2];
+ __I uint32_t EoTIntSt;
+ __O uint32_t EoTIntClr;
+ __O uint32_t EoTIntSet;
+ __I uint32_t NDDRIntSt;
+ __O uint32_t NDDRIntClr;
+ __O uint32_t NDDRIntSet;
+ __I uint32_t SysErrIntSt;
+ __O uint32_t SysErrIntClr;
+ __O uint32_t SysErrIntSet;
+ uint32_t RESERVED4[15];
+
+ union {
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */
+ __O uint32_t I2C_TX;
+ };
+ __IO uint32_t I2C_STS;
+ __IO uint32_t I2C_CTL;
+ __IO uint32_t I2C_CLKHI;
+ __O uint32_t I2C_CLKLO;
+ uint32_t RESERVED5[824];
+
+ union {
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
+ __IO uint32_t OTGClkCtrl;
+ };
+ union {
+ __I uint32_t USBClkSt;
+ __I uint32_t OTGClkSt;
+ };
+} LPC_USB_TypeDef;
+
+/*------------- CRC Engine (CRC) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t MODE;
+ __IO uint32_t SEED;
+ union {
+ __I uint32_t SUM;
+ struct {
+ __O uint32_t DATA;
+ } WR_DATA_DWORD;
+
+ struct {
+ __O uint16_t DATA;
+ uint16_t RESERVED;
+ }WR_DATA_WORD;
+
+ struct {
+ __O uint8_t DATA;
+ uint8_t RESERVED[3];
+ }WR_DATA_BYTE;
+ };
+} LPC_CRC_TypeDef;
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+typedef struct
+{
+ __IO uint32_t DIR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t MASK;
+ __IO uint32_t PIN;
+ __IO uint32_t SET;
+ __O uint32_t CLR;
+} LPC_GPIO_TypeDef;
+
+typedef struct
+{
+ __I uint32_t IntStatus;
+ __I uint32_t IO0IntStatR;
+ __I uint32_t IO0IntStatF;
+ __O uint32_t IO0IntClr;
+ __IO uint32_t IO0IntEnR;
+ __IO uint32_t IO0IntEnF;
+ uint32_t RESERVED0[3];
+ __I uint32_t IO2IntStatR;
+ __I uint32_t IO2IntStatF;
+ __O uint32_t IO2IntClr;
+ __IO uint32_t IO2IntEnR;
+ __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- External Memory Controller (EMC) -----------------------------*/
+typedef struct
+{
+ __IO uint32_t Control;
+ __I uint32_t Status;
+ __IO uint32_t Config;
+ uint32_t RESERVED0[5];
+ __IO uint32_t DynamicControl;
+ __IO uint32_t DynamicRefresh;
+ __IO uint32_t DynamicReadConfig;
+ uint32_t RESERVED1[1];
+ __IO uint32_t DynamicRP;
+ __IO uint32_t DynamicRAS;
+ __IO uint32_t DynamicSREX;
+ __IO uint32_t DynamicAPR;
+ __IO uint32_t DynamicDAL;
+ __IO uint32_t DynamicWR;
+ __IO uint32_t DynamicRC;
+ __IO uint32_t DynamicRFC;
+ __IO uint32_t DynamicXSR;
+ __IO uint32_t DynamicRRD;
+ __IO uint32_t DynamicMRD;
+ uint32_t RESERVED2[9];
+ __IO uint32_t StaticExtendedWait;
+ uint32_t RESERVED3[31];
+ __IO uint32_t DynamicConfig0;
+ __IO uint32_t DynamicRasCas0;
+ uint32_t RESERVED4[6];
+ __IO uint32_t DynamicConfig1;
+ __IO uint32_t DynamicRasCas1;
+ uint32_t RESERVED5[6];
+ __IO uint32_t DynamicConfig2;
+ __IO uint32_t DynamicRasCas2;
+ uint32_t RESERVED6[6];
+ __IO uint32_t DynamicConfig3;
+ __IO uint32_t DynamicRasCas3;
+ uint32_t RESERVED7[38];
+ __IO uint32_t StaticConfig0;
+ __IO uint32_t StaticWaitWen0;
+ __IO uint32_t StaticWaitOen0;
+ __IO uint32_t StaticWaitRd0;
+ __IO uint32_t StaticWaitPage0;
+ __IO uint32_t StaticWaitWr0;
+ __IO uint32_t StaticWaitTurn0;
+ uint32_t RESERVED8[1];
+ __IO uint32_t StaticConfig1;
+ __IO uint32_t StaticWaitWen1;
+ __IO uint32_t StaticWaitOen1;
+ __IO uint32_t StaticWaitRd1;
+ __IO uint32_t StaticWaitPage1;
+ __IO uint32_t StaticWaitWr1;
+ __IO uint32_t StaticWaitTurn1;
+ uint32_t RESERVED9[1];
+ __IO uint32_t StaticConfig2;
+ __IO uint32_t StaticWaitWen2;
+ __IO uint32_t StaticWaitOen2;
+ __IO uint32_t StaticWaitRd2;
+ __IO uint32_t StaticWaitPage2;
+ __IO uint32_t StaticWaitWr2;
+ __IO uint32_t StaticWaitTurn2;
+ uint32_t RESERVED10[1];
+ __IO uint32_t StaticConfig3;
+ __IO uint32_t StaticWaitWen3;
+ __IO uint32_t StaticWaitOen3;
+ __IO uint32_t StaticWaitRd3;
+ __IO uint32_t StaticWaitPage3;
+ __IO uint32_t StaticWaitWr3;
+ __IO uint32_t StaticWaitTurn3;
+} LPC_EMC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t MOD;
+ uint8_t RESERVED0[3];
+ __IO uint32_t TC;
+ __O uint8_t FEED;
+ uint8_t RESERVED1[3];
+ __I uint32_t TV;
+ uint32_t RESERVED2;
+ __IO uint32_t WARNINT;
+ __IO uint32_t WINDOW;
+} LPC_WDT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
+ __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
+ __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
+ __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
+ __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
+ __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
+ __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
+ __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
+ __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
+ __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
+ __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
+ uint32_t RESERVED0[2];
+ __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
+ uint32_t RESERVED1[12];
+ __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
+} LPC_TIM_TypeDef;
+
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
+ __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
+ __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
+ __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
+ __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
+ __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
+ __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
+ __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
+ __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
+ __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
+ __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
+ __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */
+ __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */
+ uint32_t RESERVED0;
+ __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */
+ __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */
+ __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */
+ __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */
+ __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */
+ uint32_t RESERVED1[7];
+ __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
+/* There are three types of UARTs on the chip:
+(1) UART0,UART2, and UART3 are the standard UART.
+(2) UART1 is the standard with modem capability.
+(3) USART(UART4) is the sync/async UART with smart card capability.
+More details can be found on the Users Manual. */
+
+#if 0
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __I uint8_t FIFOLVL;
+} LPC_UART_TypeDef;
+#else
+typedef struct
+{
+ union
+ {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union
+ {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union
+ {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];//Reserved
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];//Reserved
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];//Reserved
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];//Reserved
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];//Reserved
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];//Reserved
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];//Reserved
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];//Reserved
+ __IO uint8_t RS485DLY;
+ uint8_t RESERVED11[3];//Reserved
+ __I uint8_t FIFOLVL;
+}LPC_UART_TypeDef;
+#endif
+
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t MCR;
+ uint8_t RESERVED2[3];
+ __I uint8_t LSR;
+ uint8_t RESERVED3[3];
+ __I uint8_t MSR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t SCR;
+ uint8_t RESERVED5[3];
+ __IO uint32_t ACR;
+ uint32_t RESERVED6;
+ __IO uint32_t FDR;
+ uint32_t RESERVED7;
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];
+ __IO uint8_t RS485DLY;
+ uint8_t RESERVED11[3];
+ __I uint8_t FIFOLVL;
+} LPC_UART1_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
+ __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
+ __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
+ };
+ union {
+ __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
+ __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
+ };
+ union {
+ __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
+ __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
+ };
+ __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
+ __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
+ __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
+ __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
+ __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
+ __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */
+ __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
+ __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */
+ __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */
+ __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */
+ uint32_t RESERVED0[2];
+ __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
+ uint32_t RESERVED1;
+ __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
+ __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
+ __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
+ __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
+ __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
+ __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */
+ uint32_t RESERVED2[989];
+ __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */
+ __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
+ __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
+ __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */
+ __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
+ __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
+ __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
+ uint32_t RESERVED3[3];
+ __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */
+} LPC_UART4_TypeDef;
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
+ __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
+ __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
+ __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
+ __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
+ __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
+ __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
+ __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
+ __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
+ __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
+ __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
+ __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
+ __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
+ __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
+ __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
+} LPC_I2C_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t ILR;
+ uint8_t RESERVED0[7];
+ __IO uint8_t CCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t CIIR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t AMR;
+ uint8_t RESERVED3[3];
+ __I uint32_t CTIME0;
+ __I uint32_t CTIME1;
+ __I uint32_t CTIME2;
+ __IO uint8_t SEC;
+ uint8_t RESERVED4[3];
+ __IO uint8_t MIN;
+ uint8_t RESERVED5[3];
+ __IO uint8_t HOUR;
+ uint8_t RESERVED6[3];
+ __IO uint8_t DOM;
+ uint8_t RESERVED7[3];
+ __IO uint8_t DOW;
+ uint8_t RESERVED8[3];
+ __IO uint16_t DOY;
+ uint16_t RESERVED9;
+ __IO uint8_t MONTH;
+ uint8_t RESERVED10[3];
+ __IO uint16_t YEAR;
+ uint16_t RESERVED11;
+ __IO uint32_t CALIBRATION;
+ __IO uint32_t GPREG0;
+ __IO uint32_t GPREG1;
+ __IO uint32_t GPREG2;
+ __IO uint32_t GPREG3;
+ __IO uint32_t GPREG4;
+ __IO uint8_t RTC_AUXEN;
+ uint8_t RESERVED12[3];
+ __IO uint8_t RTC_AUX;
+ uint8_t RESERVED13[3];
+ __IO uint8_t ALSEC;
+ uint8_t RESERVED14[3];
+ __IO uint8_t ALMIN;
+ uint8_t RESERVED15[3];
+ __IO uint8_t ALHOUR;
+ uint8_t RESERVED16[3];
+ __IO uint8_t ALDOM;
+ uint8_t RESERVED17[3];
+ __IO uint8_t ALDOW;
+ uint8_t RESERVED18[3];
+ __IO uint16_t ALDOY;
+ uint16_t RESERVED19;
+ __IO uint8_t ALMON;
+ uint8_t RESERVED20[3];
+ __IO uint16_t ALYEAR;
+ uint16_t RESERVED21;
+ __IO uint32_t ERSTATUS;
+ __IO uint32_t ERCONTROL;
+ __IO uint32_t ERCOUNTERS;
+ uint32_t RESERVED22;
+ __IO uint32_t ERFIRSTSTAMP0;
+ __IO uint32_t ERFIRSTSTAMP1;
+ __IO uint32_t ERFIRSTSTAMP2;
+ uint32_t RESERVED23;
+ __IO uint32_t ERLASTSTAMP0;
+ __IO uint32_t ERLASTSTAMP1;
+ __IO uint32_t ERLASTSTAMP2;
+} LPC_RTC_TypeDef;
+
+
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+typedef struct
+{
+ __IO uint32_t P0_0; /* 0x000 */
+ __IO uint32_t P0_1;
+ __IO uint32_t P0_2;
+ __IO uint32_t P0_3;
+ __IO uint32_t P0_4;
+ __IO uint32_t P0_5;
+ __IO uint32_t P0_6;
+ __IO uint32_t P0_7;
+
+ __IO uint32_t P0_8; /* 0x020 */
+ __IO uint32_t P0_9;
+ __IO uint32_t P0_10;
+ __IO uint32_t P0_11;
+ __IO uint32_t P0_12;
+ __IO uint32_t P0_13;
+ __IO uint32_t P0_14;
+ __IO uint32_t P0_15;
+
+ __IO uint32_t P0_16; /* 0x040 */
+ __IO uint32_t P0_17;
+ __IO uint32_t P0_18;
+ __IO uint32_t P0_19;
+ __IO uint32_t P0_20;
+ __IO uint32_t P0_21;
+ __IO uint32_t P0_22;
+ __IO uint32_t P0_23;
+
+ __IO uint32_t P0_24; /* 0x060 */
+ __IO uint32_t P0_25;
+ __IO uint32_t P0_26;
+ __IO uint32_t P0_27;
+ __IO uint32_t P0_28;
+ __IO uint32_t P0_29;
+ __IO uint32_t P0_30;
+ __IO uint32_t P0_31;
+
+ __IO uint32_t P1_0; /* 0x080 */
+ __IO uint32_t P1_1;
+ __IO uint32_t P1_2;
+ __IO uint32_t P1_3;
+ __IO uint32_t P1_4;
+ __IO uint32_t P1_5;
+ __IO uint32_t P1_6;
+ __IO uint32_t P1_7;
+
+ __IO uint32_t P1_8; /* 0x0A0 */
+ __IO uint32_t P1_9;
+ __IO uint32_t P1_10;
+ __IO uint32_t P1_11;
+ __IO uint32_t P1_12;
+ __IO uint32_t P1_13;
+ __IO uint32_t P1_14;
+ __IO uint32_t P1_15;
+
+ __IO uint32_t P1_16; /* 0x0C0 */
+ __IO uint32_t P1_17;
+ __IO uint32_t P1_18;
+ __IO uint32_t P1_19;
+ __IO uint32_t P1_20;
+ __IO uint32_t P1_21;
+ __IO uint32_t P1_22;
+ __IO uint32_t P1_23;
+
+ __IO uint32_t P1_24; /* 0x0E0 */
+ __IO uint32_t P1_25;
+ __IO uint32_t P1_26;
+ __IO uint32_t P1_27;
+ __IO uint32_t P1_28;
+ __IO uint32_t P1_29;
+ __IO uint32_t P1_30;
+ __IO uint32_t P1_31;
+
+ __IO uint32_t P2_0; /* 0x100 */
+ __IO uint32_t P2_1;
+ __IO uint32_t P2_2;
+ __IO uint32_t P2_3;
+ __IO uint32_t P2_4;
+ __IO uint32_t P2_5;
+ __IO uint32_t P2_6;
+ __IO uint32_t P2_7;
+
+ __IO uint32_t P2_8; /* 0x120 */
+ __IO uint32_t P2_9;
+ __IO uint32_t P2_10;
+ __IO uint32_t P2_11;
+ __IO uint32_t P2_12;
+ __IO uint32_t P2_13;
+ __IO uint32_t P2_14;
+ __IO uint32_t P2_15;
+
+ __IO uint32_t P2_16; /* 0x140 */
+ __IO uint32_t P2_17;
+ __IO uint32_t P2_18;
+ __IO uint32_t P2_19;
+ __IO uint32_t P2_20;
+ __IO uint32_t P2_21;
+ __IO uint32_t P2_22;
+ __IO uint32_t P2_23;
+
+ __IO uint32_t P2_24; /* 0x160 */
+ __IO uint32_t P2_25;
+ __IO uint32_t P2_26;
+ __IO uint32_t P2_27;
+ __IO uint32_t P2_28;
+ __IO uint32_t P2_29;
+ __IO uint32_t P2_30;
+ __IO uint32_t P2_31;
+
+ __IO uint32_t P3_0; /* 0x180 */
+ __IO uint32_t P3_1;
+ __IO uint32_t P3_2;
+ __IO uint32_t P3_3;
+ __IO uint32_t P3_4;
+ __IO uint32_t P3_5;
+ __IO uint32_t P3_6;
+ __IO uint32_t P3_7;
+
+ __IO uint32_t P3_8; /* 0x1A0 */
+ __IO uint32_t P3_9;
+ __IO uint32_t P3_10;
+ __IO uint32_t P3_11;
+ __IO uint32_t P3_12;
+ __IO uint32_t P3_13;
+ __IO uint32_t P3_14;
+ __IO uint32_t P3_15;
+
+ __IO uint32_t P3_16; /* 0x1C0 */
+ __IO uint32_t P3_17;
+ __IO uint32_t P3_18;
+ __IO uint32_t P3_19;
+ __IO uint32_t P3_20;
+ __IO uint32_t P3_21;
+ __IO uint32_t P3_22;
+ __IO uint32_t P3_23;
+
+ __IO uint32_t P3_24; /* 0x1E0 */
+ __IO uint32_t P3_25;
+ __IO uint32_t P3_26;
+ __IO uint32_t P3_27;
+ __IO uint32_t P3_28;
+ __IO uint32_t P3_29;
+ __IO uint32_t P3_30;
+ __IO uint32_t P3_31;
+
+ __IO uint32_t P4_0; /* 0x200 */
+ __IO uint32_t P4_1;
+ __IO uint32_t P4_2;
+ __IO uint32_t P4_3;
+ __IO uint32_t P4_4;
+ __IO uint32_t P4_5;
+ __IO uint32_t P4_6;
+ __IO uint32_t P4_7;
+
+ __IO uint32_t P4_8; /* 0x220 */
+ __IO uint32_t P4_9;
+ __IO uint32_t P4_10;
+ __IO uint32_t P4_11;
+ __IO uint32_t P4_12;
+ __IO uint32_t P4_13;
+ __IO uint32_t P4_14;
+ __IO uint32_t P4_15;
+
+ __IO uint32_t P4_16; /* 0x240 */
+ __IO uint32_t P4_17;
+ __IO uint32_t P4_18;
+ __IO uint32_t P4_19;
+ __IO uint32_t P4_20;
+ __IO uint32_t P4_21;
+ __IO uint32_t P4_22;
+ __IO uint32_t P4_23;
+
+ __IO uint32_t P4_24; /* 0x260 */
+ __IO uint32_t P4_25;
+ __IO uint32_t P4_26;
+ __IO uint32_t P4_27;
+ __IO uint32_t P4_28;
+ __IO uint32_t P4_29;
+ __IO uint32_t P4_30;
+ __IO uint32_t P4_31;
+
+ __IO uint32_t P5_0; /* 0x280 */
+ __IO uint32_t P5_1;
+ __IO uint32_t P5_2;
+ __IO uint32_t P5_3;
+ __IO uint32_t P5_4; /* 0x290 */
+} LPC_IOCON_TypeDef;
+
+
+
+
+
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+typedef struct
+{
+ __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
+ __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
+ __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
+ __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
+ __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
+ __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
+ __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
+ __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
+ __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
+ __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
+ __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
+ uint32_t RESERVED0;
+ __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
+ __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
+ __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
+ __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+typedef struct
+{
+ __IO uint32_t mask[512]; /* ID Masks */
+} LPC_CANAF_RAM_TypeDef;
+
+typedef struct /* Acceptance Filter Registers */
+{
+ ///Offset: 0x00000000 - Acceptance Filter Register
+ __IO uint32_t AFMR;
+
+ ///Offset: 0x00000004 - Standard Frame Individual Start Address Register
+ __IO uint32_t SFF_sa;
+
+ ///Offset: 0x00000008 - Standard Frame Group Start Address Register
+ __IO uint32_t SFF_GRP_sa;
+
+ ///Offset: 0x0000000C - Extended Frame Start Address Register
+ __IO uint32_t EFF_sa;
+
+ ///Offset: 0x00000010 - Extended Frame Group Start Address Register
+ __IO uint32_t EFF_GRP_sa;
+
+ ///Offset: 0x00000014 - End of AF Tables register
+ __IO uint32_t ENDofTable;
+
+ ///Offset: 0x00000018 - LUT Error Address register
+ __I uint32_t LUTerrAd;
+
+ ///Offset: 0x0000001C - LUT Error Register
+ __I uint32_t LUTerr;
+
+ ///Offset: 0x00000020 - CAN Central Transmit Status Register
+ __IO uint32_t FCANIE;
+
+ ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
+ __IO uint32_t FCANIC0;
+
+ ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
+ __IO uint32_t FCANIC1;
+} LPC_CANAF_TypeDef;
+
+typedef struct /* Central Registers */
+{
+ __I uint32_t TxSR;
+ __I uint32_t RxSR;
+ __I uint32_t MSR;
+} LPC_CANCR_TypeDef;
+
+typedef struct /* Controller Registers */
+{
+ ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
+ __IO uint32_t MOD;
+
+ ///Offset: 0x00000004 - Command bits that affect the state
+ __O uint32_t CMR;
+
+ ///Offset: 0x00000008 - Global Controller Status and Error Counters
+ __IO uint32_t GSR;
+
+ ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
+ __I uint32_t ICR;
+
+ ///Offset: 0x00000010 - Interrupt Enable Register
+ __IO uint32_t IER;
+
+ ///Offset: 0x00000014 - Bus Timing Register
+ __IO uint32_t BTR;
+
+ ///Offset: 0x00000018 - Error Warning Limit
+ __IO uint32_t EWL;
+
+ ///Offset: 0x0000001C - Status Register
+ __I uint32_t SR;
+
+ ///Offset: 0x00000020 - Receive frame status
+ __IO uint32_t RFS;
+
+ ///Offset: 0x00000024 - Received Identifier
+ __IO uint32_t RID;
+
+ ///Offset: 0x00000028 - Received data bytes 1-4
+ __IO uint32_t RDA;
+
+ ///Offset: 0x0000002C - Received data bytes 5-8
+ __IO uint32_t RDB;
+
+ ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
+ __IO uint32_t TFI1;
+
+ ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
+ __IO uint32_t TID1;
+
+ ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
+ __IO uint32_t TDA1;
+
+ ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
+ __IO uint32_t TDB1;
+
+ ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
+ __IO uint32_t TFI2;
+
+ ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
+ __IO uint32_t TID2;
+
+ ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
+ __IO uint32_t TDA2;
+
+ ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
+ __IO uint32_t TDB2;
+
+ ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
+ __IO uint32_t TFI3;
+
+ ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
+ __IO uint32_t TID3;
+
+ ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
+ __IO uint32_t TDA3;
+
+ ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
+ __IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CTRL;
+ __IO uint32_t CNTVAL;
+} LPC_DAC_TypeDef;
+
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t DAO;
+ __IO uint32_t DAI;
+ __O uint32_t TXFIFO;
+ __I uint32_t RXFIFO;
+ __I uint32_t STATE;
+ __IO uint32_t DMA1;
+ __IO uint32_t DMA2;
+ __IO uint32_t IRQ;
+ __IO uint32_t TXRATE;
+ __IO uint32_t RXRATE;
+ __IO uint32_t TXBITRATE;
+ __IO uint32_t RXBITRATE;
+ __IO uint32_t TXMODE;
+ __IO uint32_t RXMODE;
+} LPC_I2S_TypeDef;
+
+
+
+
+
+
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
+typedef struct
+{
+ __I uint32_t CON;
+ __O uint32_t CON_SET;
+ __O uint32_t CON_CLR;
+ __I uint32_t CAPCON;
+ __O uint32_t CAPCON_SET;
+ __O uint32_t CAPCON_CLR;
+ __IO uint32_t TC0;
+ __IO uint32_t TC1;
+ __IO uint32_t TC2;
+ __IO uint32_t LIM0;
+ __IO uint32_t LIM1;
+ __IO uint32_t LIM2;
+ __IO uint32_t MAT0;
+ __IO uint32_t MAT1;
+ __IO uint32_t MAT2;
+ __IO uint32_t DT;
+ __IO uint32_t CP;
+ __IO uint32_t CAP0;
+ __IO uint32_t CAP1;
+ __IO uint32_t CAP2;
+ __I uint32_t INTEN;
+ __O uint32_t INTEN_SET;
+ __O uint32_t INTEN_CLR;
+ __I uint32_t CNTCON;
+ __O uint32_t CNTCON_SET;
+ __O uint32_t CNTCON_CLR;
+ __I uint32_t INTF;
+ __O uint32_t INTF_SET;
+ __O uint32_t INTF_CLR;
+ __O uint32_t CAP_CLR;
+} LPC_MCPWM_TypeDef;
+
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
+typedef struct
+{
+ __O uint32_t CON;
+ __I uint32_t STAT;
+ __IO uint32_t CONF;
+ __I uint32_t POS;
+ __IO uint32_t MAXPOS;
+ __IO uint32_t CMPOS0;
+ __IO uint32_t CMPOS1;
+ __IO uint32_t CMPOS2;
+ __I uint32_t INXCNT;
+ __IO uint32_t INXCMP0;
+ __IO uint32_t LOAD;
+ __I uint32_t TIME;
+ __I uint32_t VEL;
+ __I uint32_t CAP;
+ __IO uint32_t VELCOMP;
+ __IO uint32_t FILTERPHA;
+ __IO uint32_t FILTERPHB;
+ __IO uint32_t FILTERINX;
+ __IO uint32_t WINDOW;
+ __IO uint32_t INXCMP1;
+ __IO uint32_t INXCMP2;
+ uint32_t RESERVED0[993];
+ __O uint32_t IEC;
+ __O uint32_t IES;
+ __I uint32_t INTSTAT;
+ __I uint32_t IE;
+ __O uint32_t CLR;
+ __O uint32_t SET;
+} LPC_QEI_TypeDef;
+
+/*------------- SD/MMC card Interface (MCI)-----------------------------------*/
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLOCK;
+ __IO uint32_t ARGUMENT;
+ __IO uint32_t COMMAND;
+ __I uint32_t RESP_CMD;
+ __I uint32_t RESP0;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __IO uint32_t DATATMR;
+ __IO uint32_t DATALEN;
+ __IO uint32_t DATACTRL;
+ __I uint32_t DATACNT;
+ __I uint32_t STATUS;
+ __O uint32_t CLEAR;
+ __IO uint32_t MASK0;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO[16];
+} LPC_MCI_TypeDef;
+
+
+
+
+
+
+
+
+
+
+/*------------- EEPROM Controller (EEPROM) -----------------------------------*/
+typedef struct
+{
+ __IO uint32_t CMD; /* 0x0080 */
+ __IO uint32_t ADDR;
+ __IO uint32_t WDATA;
+ __IO uint32_t RDATA;
+ __IO uint32_t WSTATE; /* 0x0090 */
+ __IO uint32_t CLKDIV;
+ __IO uint32_t PWRDWN; /* 0x0098 */
+ uint32_t RESERVED0[975];
+ __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */
+ __IO uint32_t INT_SET_ENABLE;
+ __IO uint32_t INT_STATUS; /* 0x0FE0 */
+ __IO uint32_t INT_ENABLE;
+ __IO uint32_t INT_CLR_STATUS;
+ __IO uint32_t INT_SET_STATUS;
+} LPC_EEPROM_TypeDef;
+
+
+/*------------- COMPARATOR ----------------------------------------------------*/
+
+typedef struct { /*!< (@ 0x40020000) COMPARATOR Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40020000) Comparator block control register */
+ __IO uint32_t CTRL0; /*!< (@ 0x40020004) Comparator 0 control register */
+ __IO uint32_t CTRL1; /*!< (@ 0x40020008) Comparator 1 control register */
+} LPC_COMPARATOR_Type;
+
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_PERI_RAM_BASE (0x20000000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_APB1_BASE (0x40080000UL)
+#define LPC_AHBRAM1_BASE (0x20004000UL)
+#define LPC_AHB_BASE (0x20080000UL)
+#define LPC_CM3_BASE (0xE0000000UL)
+
+/* APB0 peripherals */
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
+#define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000)
+#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
+#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
+#define LPC_COMPARATOR_BASE (LPC_APB0_BASE + 0x20000)
+#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
+#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
+#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000)
+#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
+#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
+#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
+#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
+
+/* APB1 peripherals */
+#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
+#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
+#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
+#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
+#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
+#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
+#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
+#define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000)
+#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
+#define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000)
+#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
+#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
+#define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000)
+#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
+
+/* AHB peripherals */
+#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100)
+#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120)
+#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140)
+#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160)
+#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180)
+#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0)
+#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0)
+#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0)
+#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000)
+#define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000)
+#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
+#define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000)
+#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000)
+#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020)
+#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040)
+#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060)
+#define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080)
+#define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0)
+#define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000)
+
+#define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080)
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
+#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
+#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
+#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
+#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
+#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
+#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
+#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
+#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
+#define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE )
+#define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE )
+#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
+#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
+#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
+#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
+#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
+#define LPC_COMPARATOR ((LPC_COMPARATOR_Type *) LPC_COMPARATOR_BASE)
+#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
+#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
+#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
+#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
+#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
+#define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE )
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
+#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
+#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
+#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
+#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
+#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
+#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
+#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
+#define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE )
+#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
+#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
+#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
+#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
+#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
+#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
+#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
+#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
+#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
+#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
+#define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE )
+#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
+#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
+#define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE )
+#define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE )
+#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
+#define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE )
+
+
+
+#endif // __LPC407x_8x_177x_8x_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/LPC407X_8X.sct Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,18 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00080000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00080000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x100000E8 0x0000FF18 { ; RW data
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x00008000 {
+ .ANY (AHBSRAM1)
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/startup_LPC407x_8x_177x_8x.s Wed Aug 07 16:43:59 2013 +0300 @@ -0,0 +1,254 @@ +;/***************************************************************************** +; * @file: startup_LPC407x_8x.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File +; * for the NXP LPC407x_8x Device Series +; * @version: V1.20 +; * @date: 16. January 2012 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M4 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + + + +__initial_sp EQU 0x10010000 ; Top of RAM from LPC4088 + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + ; DCD 0xEFFFF5D6 ; Reserved- vector sum + DCD 0xEFFFF39E ; Reserved- vector sum + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 16: Watchdog Timer + DCD TIMER0_IRQHandler ; 17: Timer0 + DCD TIMER1_IRQHandler ; 18: Timer1 + DCD TIMER2_IRQHandler ; 19: Timer2 + DCD TIMER3_IRQHandler ; 20: Timer3 + DCD UART0_IRQHandler ; 21: UART0 + DCD UART1_IRQHandler ; 22: UART1 + DCD UART2_IRQHandler ; 23: UART2 + DCD UART3_IRQHandler ; 24: UART3 + DCD PWM1_IRQHandler ; 25: PWM1 + DCD I2C0_IRQHandler ; 26: I2C0 + DCD I2C1_IRQHandler ; 27: I2C1 + DCD I2C2_IRQHandler ; 28: I2C2 + DCD 0 ; 29: reserved, not for SPIFI anymore + DCD SSP0_IRQHandler ; 30: SSP0 + DCD SSP1_IRQHandler ; 31: SSP1 + DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) + DCD RTC_IRQHandler ; 33: Real Time Clock + DCD EINT0_IRQHandler ; 34: External Interrupt 0 + DCD EINT1_IRQHandler ; 35: External Interrupt 1 + DCD EINT2_IRQHandler ; 36: External Interrupt 2 + DCD EINT3_IRQHandler ; 37: External Interrupt 3 + DCD ADC_IRQHandler ; 38: A/D Converter + DCD BOD_IRQHandler ; 39: Brown-Out Detect + DCD USB_IRQHandler ; 40: USB + DCD CAN_IRQHandler ; 41: CAN + DCD DMA_IRQHandler ; 42: General Purpose DMA + DCD I2S_IRQHandler ; 43: I2S + DCD ENET_IRQHandler ; 44: Ethernet + DCD MCI_IRQHandler ; 45: SD/MMC card I/F + DCD MCPWM_IRQHandler ; 46: Motor Control PWM + DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface + DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) + DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup + DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup + DCD UART4_IRQHandler ; 51: UART4 + DCD SSP2_IRQHandler ; 52: SSP2 + DCD LCD_IRQHandler ; 53: LCD + DCD GPIO_IRQHandler ; 54: GPIO + DCD PWM0_IRQHandler ; 55: PWM0 + DCD EEPROM_IRQHandler ; 56: EEPROM + + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + ;EXPORT SPIFI_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT PLL0_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT EINT2_IRQHandler [WEAK] + EXPORT EINT3_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT MCI_IRQHandler [WEAK] + EXPORT MCPWM_IRQHandler [WEAK] + EXPORT QEI_IRQHandler [WEAK] + EXPORT PLL1_IRQHandler [WEAK] + EXPORT USBActivity_IRQHandler [WEAK] + EXPORT CANActivity_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT SSP2_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPIO_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT EEPROM_IRQHandler [WEAK] + +WDT_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +PWM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +;SPIFI_IRQHandler ;not used +SSP0_IRQHandler +SSP1_IRQHandler +PLL0_IRQHandler +RTC_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +ADC_IRQHandler +BOD_IRQHandler +USB_IRQHandler +CAN_IRQHandler +DMA_IRQHandler +I2S_IRQHandler +ENET_IRQHandler +MCI_IRQHandler +MCPWM_IRQHandler +QEI_IRQHandler +PLL1_IRQHandler +USBActivity_IRQHandler +CANActivity_IRQHandler +UART4_IRQHandler +SSP2_IRQHandler +LCD_IRQHandler +GPIO_IRQHandler +PWM0_IRQHandler +EEPROM_IRQHandler + + B . + + ENDP + + + ALIGN + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys.cpp Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/LPC407x_8x.ld Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,180 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (C) Code Red Technologies Ltd, 2008-2013
+ * Generated linker script file for LPC4088
+ * Created from generic_c.ld (vLPCXpresso v5.1 (2 [Build 2065] [2013-02-20] ))
+ * By LPCXpresso v5.1.2 [Build 2065] [2013-02-20] on Wed Apr 17 14:50:07 CEST 2013
+ */
+
+
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
+ RamLoc64 (rwx) : ORIGIN = 0x100000E8, LENGTH = 0xFF18 /* 64k */
+ RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32k */
+
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash512 = 0x0 + 0x80000;
+ __top_RamLoc64 = 0x10000000 + 0x10000;
+ __top_RamPeriph32 = 0x20000000 + 0x8000;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ /* End C++ */
+ } > MFlash512
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ /* DATA section for RamPeriph32 */
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamPeriph32*)
+ . = ALIGN(4) ;
+ } > RamPeriph32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc64
+
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = .;
+ } > RamLoc64 AT>MFlash512
+
+ /* BSS section for RamPeriph32 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamPeriph32*)
+ . = ALIGN(4) ;
+ } > RamPeriph32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc64
+
+ /* NOINIT section for RamPeriph32 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamPeriph32*)
+ . = ALIGN(4) ;
+ } > RamPeriph32
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc64
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc64 - 0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/startup_lpc407x_8x.cpp Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,433 @@
+//*****************************************************************************
+// +--+
+// | ++----+
+// +-++ |
+// | |
+// +-+--+ |
+// | +--+--+
+// +----+ Copyright (c) 2012 Code Red Technologies Ltd.
+//
+// LPC407x_8x Microcontroller Startup code for use with Red Suite
+//
+// Version : 120624
+//
+// Software License Agreement
+//
+// The software is owned by Code Red Technologies and/or its suppliers, and is
+// protected under applicable copyright laws. All rights are reserved. Any
+// use in violation of the foregoing restrictions may subject the user to criminal
+// sanctions under applicable laws, as well as to civil liability for the breach
+// of the terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
+// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
+// CODE RED TECHNOLOGIES LTD.
+//
+//*****************************************************************************
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+ extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//#if defined (__USE_CMSIS)
+#include "LPC407x_8x_177x_8x.h"
+//#endif
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the default handlers. These are aliased.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions
+//
+//*****************************************************************************
+ void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//
+//*****************************************************************************
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EINT3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MCI_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART4_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+//
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+//*****************************************************************************
+//
+// External declaration for the pointer to the stack top from the Linker Script
+//
+//*****************************************************************************
+extern void _vStackTop(void);
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+//
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM3
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ MemManage_Handler, // The MPU fault handler
+ BusFault_Handler, // The bus fault handler
+ UsageFault_Handler, // The usage fault handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ DebugMon_Handler, // Debug monitor handler
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ // Chip Level - LPC17
+ WDT_IRQHandler, // 16, 0x40 - WDT
+ TIMER0_IRQHandler, // 17, 0x44 - TIMER0
+ TIMER1_IRQHandler, // 18, 0x48 - TIMER1
+ TIMER2_IRQHandler, // 19, 0x4c - TIMER2
+ TIMER3_IRQHandler, // 20, 0x50 - TIMER3
+ UART0_IRQHandler, // 21, 0x54 - UART0
+ UART1_IRQHandler, // 22, 0x58 - UART1
+ UART2_IRQHandler, // 23, 0x5c - UART2
+ UART3_IRQHandler, // 24, 0x60 - UART3
+ PWM1_IRQHandler, // 25, 0x64 - PWM1
+ I2C0_IRQHandler, // 26, 0x68 - I2C0
+ I2C1_IRQHandler, // 27, 0x6c - I2C1
+ I2C2_IRQHandler, // 28, 0x70 - I2C2
+ IntDefaultHandler, // 29, Not used
+ SSP0_IRQHandler, // 30, 0x78 - SSP0
+ SSP1_IRQHandler, // 31, 0x7c - SSP1
+ PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
+ RTC_IRQHandler, // 33, 0x84 - RTC
+ EINT0_IRQHandler, // 34, 0x88 - EINT0
+ EINT1_IRQHandler, // 35, 0x8c - EINT1
+ EINT2_IRQHandler, // 36, 0x90 - EINT2
+ EINT3_IRQHandler, // 37, 0x94 - EINT3
+ ADC_IRQHandler, // 38, 0x98 - ADC
+ BOD_IRQHandler, // 39, 0x9c - BOD
+ USB_IRQHandler, // 40, 0xA0 - USB
+ CAN_IRQHandler, // 41, 0xa4 - CAN
+ DMA_IRQHandler, // 42, 0xa8 - GP DMA
+ I2S_IRQHandler, // 43, 0xac - I2S
+ ENET_IRQHandler, // 44, 0xb0 - Ethernet
+ MCI_IRQHandler, // 45, 0xb4 - SD/MMC card I/F
+ MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
+ QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
+ PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
+ USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
+ CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
+ UART4_IRQHandler, // 51, 0xcc - UART4
+
+ SSP2_IRQHandler, // 52, 0xd0 - SSP2
+ LCD_IRQHandler, // 53, 0xd4 - LCD
+ GPIO_IRQHandler, // 54, 0xd8 - GPIO
+ PWM0_IRQHandler, // 55, 0xdc - PWM0
+ EEPROM_IRQHandler, // 56, 0xe0 - EEPROM
+
+};
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors")))
+void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void
+ResetISR(void) {
+
+ //
+ // Copy the data sections from flash to SRAM.
+ //
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Load base address of Global Section Table
+ SectionTableAddr = &__data_section_table;
+
+ // Copy the data sections from flash to SRAM.
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+ // At this point, SectionTableAddr = &__bss_section_table;
+ // Zero fill the bss segment
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)
+/*
+ * Code to enable the Cortex-M4 FPU only included
+ * if appropriate build options have been selected.
+ * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+ */
+ // Read CPACR (located at address 0xE000ED88)
+ // Set bits 20-23 to enable CP10 and CP11 coprocessors
+ // Write back the modified value to the CPACR
+ asm volatile ("LDR.W R0, =0xE000ED88\n\t"
+ "LDR R1, [R0]\n\t"
+ "ORR R1, R1, #(0xF << 20)\n\t"
+ "STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+
+ // Check to see if we are running the code from a non-zero
+ // address (eg RAM, external flash), in which case we need
+ // to modify the VTOR register to tell the CPU that the
+ // vector table is located at a non-0x0 address.
+
+ // Note that we do not use the CMSIS register access mechanism,
+ // as there is no guarantee that the project has been configured
+ // to use CMSIS.
+ unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+ if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
+ // CMSIS : SCB->VTOR = <address of vector table>
+ *pSCB_VTOR = (unsigned int)g_pfnVectors;
+ }
+
+//#ifdef __USE_CMSIS
+ SystemInit();
+//#endif
+
+#if defined (__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+ // Call the Redlib library, which in turn calls main()
+ __main() ;
+#else
+ main();
+#endif
+
+ //
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1) {
+ ;
+ }
+}
+
+//*****************************************************************************
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void NMI_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void HardFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void MemManage_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void BusFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void UsageFault_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void SVC_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void DebugMon_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void PendSV_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+__attribute__ ((section(".after_vectors")))
+void SysTick_Handler(void)
+{
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void IntDefaultHandler(void)
+{
+ while(1)
+ {
+ }
+}
+
+#include <stdlib.h>
+
+void *operator new(size_t size) {return malloc(size);}
+void *operator new[](size_t size){return malloc(size);}
+
+void operator delete(void *p) {free(p);}
+void operator delete[](void *p) {free(p);}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis.h Wed Aug 07 16:43:59 2013 +0300 @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC407x_8x specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "LPC407x_8x_177x_8x.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis_nvic.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - cmsis_nvic for LCP407x_8x
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis_nvic.h Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,26 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 41) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC408X/system_LPC407x_8x_177x_8x.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,571 @@
+/**********************************************************************
+* $Id$ system_LPC407x_8x_177x_8x.c 2012-01-16
+*//**
+* @file system_LPC407x_8x_177x_8x.c
+* @brief CMSIS Cortex-M3, M4 Device Peripheral Access Layer Source File
+* for the NXP LPC407x_8x_177x_8x Device Series
+*
+* ARM Limited (ARM) is supplying this software for use with
+* Cortex-M processor based microcontrollers. This file can be
+* freely distributed within development tools that are supporting
+* such ARM based processors.
+*
+* @version 1.2
+* @date 20. June. 2012
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2012, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+#include <stdint.h>
+#include "LPC407x_8x_177x_8x.h"
+#include "system_LPC407x_8x_177x_8x.h"
+
+#define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y))
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Controls and Status Register (SCS - address 0x400F C1A0)
+// <o1.0> EMC Shift Control Bit
+// <i> Controls how addresses are output on the EMC address pins for static memories
+// <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0)
+// <1=> Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1)
+//
+// <o1.1> EMC Reset Disable Bit
+// <i> If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition
+// <i> If 1, EMC is still retained its state through a warm reset
+// <0=> Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0)
+// <1=> Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1)
+//
+// <o1.2> EMC Burst Control
+// <i> Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects
+// <0=> Burst enabled (Bit 2 is 0)
+// <1=> Bust disbled (Bit 2 is 1)
+//
+// <o1.3> MCIPWR Active Level
+// <i> Selects the active level for the SD card interface signal SD_PWR
+// <0=> SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0)
+// <1=> SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1)
+//
+// <o1.4> Main Oscillator Range Select
+// <0=> In Range 1 MHz to 20 MHz (Bit 4 is 0)
+// <1=> In Range 15 MHz to 25 MHz (Bit 4 is 1)
+//
+// <o1.5> Main Oscillator enable
+// <i> 0 (zero) means disabled, 1 means enable
+//
+// <o1.6> Main Oscillator status (Read-Only)
+// </h>
+//
+// <h> Clock Source Select Register (CLKSRCSEL - address 0x400F C10C)
+// <o2.0> CLKSRC: Select the clock source for sysclk to PLL0 clock
+// <0=> Internal RC oscillator (Bit 0 is 0)
+// <1=> Main oscillator (Bit 0 is 1)
+// </h>
+//
+// <e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084)
+// <i> F_in is in the range of 1 MHz to 25 MHz
+// <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
+// <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
+//
+// <o4.0..4> MSEL: PLL Multiplier Value
+// <i> M Value
+// <1-32><#-1>
+//
+// <o4.5..6> PSEL: PLL Divider Value
+// <i> P Value
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// </e>
+//
+// <e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4)
+// <i> F_in is in the range of 1 MHz to 25 MHz
+// <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
+// <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
+//
+// <o6.0..4> MSEL: PLL Multiplier Value
+// <i> M Value
+// <1-32><#-1>
+//
+// <o6.5..6> PSEL: PLL Divider Value
+// <i> P Value
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// </e>
+//
+// <h> CPU Clock Selection Register (CCLKSEL - address 0x400F C104)
+// <o7.0..4> CCLKDIV: Select the value for divider of CPU clock (CCLK)
+// <i> 0: The divider is turned off. No clock will be provided to the CPU
+// <i> n: The input clock is divided by n to produce the CPU clock
+// <0-31>
+//
+// <o7.8> CCLKSEL: Select the input to the divider of CPU clock
+// <0=> sysclk clock is used
+// <1=> Main PLL0 clock is used
+// </h>
+//
+// <h> USB Clock Selection Register (USBCLKSEL - 0x400F C108)
+// <o8.0..4> USBDIV: USB clock (source PLL0) divider selection
+// <0=> Divider is off and no clock provides to USB subsystem
+// <4=> Divider value is 4 (The source clock is divided by 4)
+// <6=> Divider value is 6 (The source clock is divided by 6)
+//
+// <o8.8..9> USBSEL: Select the source for USB clock divider
+// <i> When CPU clock is selected, the USB can be accessed
+// <i> by software but cannot perform USB functions
+// <0=> sysclk clock (the clock input to PLL0)
+// <1=> The clock output from PLL0
+// <2=> The clock output from PLL1
+// </h>
+//
+// <h> EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100)
+// <o9.0> EMCDIV: Set the divider for EMC clock
+// <0=> Divider value is 1
+// <1=> Divider value is 2 (EMC clock is equal a half of input clock)
+// </h>
+//
+// <h> Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8)
+// <o10.0..4> PCLKDIV: APB Peripheral clock divider
+// <i> 0: The divider is turned off. No clock will be provided to APB peripherals
+// <i> n: The input clock is divided by n to produce the APB peripheral clock
+// <0-31>
+// </h>
+//
+// <h> SPIFI Clock Selection Register (SPIFICLKSEL - address 0x400F C1B4)
+// <o11.0..4> SPIFIDIV: Set the divider for SPIFI clock
+// <i> 0: The divider is turned off. No clock will be provided to the SPIFI
+// <i> n: The input clock is divided by n to produce the SPIFI clock
+// <0-31>
+//
+// <o11.8..9> SPIFISEL: Select the input clock for SPIFI clock divider
+// <0=> sysclk clock (the clock input to PLL0)
+// <1=> The clock output from PLL0
+// <2=> The clock output from PLL1
+// </h>
+//
+// <h> Power Control for Peripherals Register (PCONP - address 0x400F C1C8)
+// <o12.0> PCLCD: LCD controller power/clock enable (bit 0)
+// <o12.1> PCTIM0: Timer/Counter 0 power/clock enable (bit 1)
+// <o12.2> PCTIM1: Timer/Counter 1 power/clock enable (bit 2)
+// <o12.3> PCUART0: UART 0 power/clock enable (bit 3)
+// <o12.4> PCUART1: UART 1 power/clock enable (bit 4)
+// <o12.5> PCPWM0: PWM0 power/clock enable (bit 5)
+// <o12.6> PCPWM1: PWM1 power/clock enable (bit 6)
+// <o12.7> PCI2C0: I2C 0 interface power/clock enable (bit 7)
+// <o12.8> PCUART4: UART 4 power/clock enable (bit 8)
+// <o12.9> PCRTC: RTC and Event Recorder power/clock enable (bit 9)
+// <o12.10> PCSSP1: SSP 1 interface power/clock enable (bit 10)
+// <o12.11> PCEMC: External Memory Controller power/clock enable (bit 11)
+// <o12.12> PCADC: A/D converter power/clock enable (bit 12)
+// <o12.13> PCCAN1: CAN controller 1 power/clock enable (bit 13)
+// <o12.14> PCCAN2: CAN controller 2 power/clock enable (bit 14)
+// <o12.15> PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15)
+// <o12.17> PCMCPWM: Motor Control PWM power/clock enable (bit 17)
+// <o12.18> PCQEI: Quadrature encoder interface power/clock enable (bit 18)
+// <o12.19> PCI2C1: I2C 1 interface power/clock enable (bit 19)
+// <o12.20> PCSSP2: SSP 2 interface power/clock enable (bit 20)
+// <o12.21> PCSSP0: SSP 0 interface power/clock enable (bit 21)
+// <o12.22> PCTIM2: Timer 2 power/clock enable (bit 22)
+// <o12.23> PCTIM3: Timer 3 power/clock enable (bit 23)
+// <o12.24> PCUART2: UART 2 power/clock enable (bit 24)
+// <o12.25> PCUART3: UART 3 power/clock enable (bit 25)
+// <o12.26> PCI2C2: I2C 2 interface power/clock enable (bit 26)
+// <o12.27> PCI2S: I2S interface power/clock enable (bit 27)
+// <o12.28> PCSDC: SD Card interface power/clock enable (bit 28)
+// <o12.29> PCGPDMA: GPDMA function power/clock enable (bit 29)
+// <o12.30> PCENET: Ethernet block power/clock enable (bit 30)
+// <o12.31> PCUSB: USB interface power/clock enable (bit 31)
+// </h>
+//
+// <h> Clock Output Configuration Register (CLKOUTCFG)
+// <o13.0..3> CLKOUTSEL: Clock Source for CLKOUT Selection
+// <0=> CPU clock
+// <1=> Main Oscillator
+// <2=> Internal RC Oscillator
+// <3=> USB clock
+// <4=> RTC Oscillator
+// <5=> unused
+// <6=> Watchdog Oscillator
+//
+// <o13.4..7> CLKOUTDIV: Output Clock Divider
+// <1-16><#-1>
+//
+// <o13.8> CLKOUT_EN: CLKOUT enable
+// </h>
+//
+// </e>
+*/
+
+#define CLOCK_SETUP 1
+#define SCS_Val 0x00000020
+#define CLKSRCSEL_Val 0x00000001
+#define PLL0_SETUP 1
+#define PLL0CFG_Val 0x00000009
+#define PLL1_SETUP 1
+#define PLL1CFG_Val 0x00000023
+#define CCLKSEL_Val 0x00000101
+#define USBCLKSEL_Val 0x00000201
+#define EMCCLKSEL_Val 0x00000001
+#define PCLKSEL_Val 0x00000002
+#define SPIFICLKSEL_Val 0x00000002
+#define PCONP_Val 0x042887DE
+#define CLKOUTCFG_Val 0x00000100
+
+#ifdef CORE_M4
+#define LPC_CPACR 0xE000ED88
+
+#define SCB_MVFR0 0xE000EF40
+#define SCB_MVFR0_RESET 0x10110021
+
+#define SCB_MVFR1 0xE000EF44
+#define SCB_MVFR1_RESET 0x11000011
+#endif
+
+
+/*--------------------- Flash Accelerator Configuration ----------------------
+//
+// <e> Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000)
+// <o1.12..15> FLASHTIM: Flash Access Time
+// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
+// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
+// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
+// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
+// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
+// <5=> 6 CPU clocks (for any CPU clock)
+// </e>
+*/
+
+#define FLASH_SETUP 1
+#define FLASHCFG_Val 0x00005000
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SCS_Val), ~0x0000003F))
+ #error "SCS: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
+ #error "CLKSRCSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F))
+ #error "PLL0CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
+ #error "PLL1CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F))
+ #error "CCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
+ #error "USBCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
+ #error "EMCCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
+ #error "PCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
+ #error "PCONP: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
+ #error "CLKOUTCFG: Invalid values of reserved bits!"
+#endif
+
+/* Flash Accelerator Configuration -------------------------------------------*/
+#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
+ #warning "FLASHCFG: Invalid values of reserved bits!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+/* pll_out_clk = F_cco / (2 � P)
+ F_cco = pll_in_clk � M � 2 � P */
+#define __M ((PLL0CFG_Val & 0x1F) + 1)
+#define __PLL0_CLK(__F_IN) (__F_IN * __M)
+#define __CCLK_DIV (CCLKSEL_Val & 0x1F)
+#define __PCLK_DIV (PCLKSEL_Val & 0x1F)
+#define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1)
+
+/* Determine core clock frequency according to settings */
+#if (CLOCK_SETUP) /* Clock Setup */
+
+ #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
+ #error "Main Oscillator is selected as clock source but is not enabled!"
+ #endif
+
+ #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
+ #error "Main PLL is selected as clock source but is not enabled!"
+ #endif
+
+ #if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */
+ #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
+ #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
+ #define __PER_CLK (IRC_OSC/ __PCLK_DIV)
+ #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
+ #else /* sysclk = osc_clk */
+ #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
+ #define __PER_CLK (OSC_CLK/ __PCLK_DIV)
+ #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
+ #endif
+ #else /* cclk = pll_clk */
+ #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
+ #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
+ #define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
+ #define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
+ #else /* sysclk = osc_clk */
+ #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
+ #define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
+ #define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
+ #endif
+ #endif
+
+#else
+ #define __CORE_CLK (IRC_OSC)
+ #define __PER_CLK (IRC_OSC)
+ #define __EMC_CLK (__CORE_CLK)
+#endif
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */
+uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */
+uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will
+ be updated after call SystemCoreClockUpdate, should be 48MHz*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ /* Determine clock frequency according to clock register values */
+ if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */
+ if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
+ SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F));
+ PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F));
+ EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+ }
+ else { /* sysclk = osc_clk */
+ if ((LPC_SC->SCS & 0x40) == 0) {
+ SystemCoreClock = 0; /* this should never happen! */
+ PeripheralClock = 0;
+ EMCClock = 0;
+ }
+ else {
+ SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F));
+ PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F));
+ EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+ }
+ }
+ }
+ else { /* cclk = pll_clk */
+ if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */
+ SystemCoreClock = 0; /* this should never happen! */
+ PeripheralClock = 0;
+ EMCClock = 0;
+ }
+ else {
+ if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
+ uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
+ uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
+ uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
+ uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
+ SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div);
+ PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div);
+ EMCClock = SystemCoreClock / emc_div;
+ }
+ else { /* sysclk = osc_clk */
+ if ((LPC_SC->SCS & 0x40) == 0) {
+ SystemCoreClock = 0; /* this should never happen! */
+ PeripheralClock = 0;
+ EMCClock = 0;
+ }
+ else {
+ uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
+ uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
+ uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
+ uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
+ SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div);
+ PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div);
+ EMCClock = SystemCoreClock / emc_div;
+ }
+ }
+ }
+ }
+ /* ---update USBClock------------------*/
+ if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
+ {
+ switch (LPC_SC->USBCLKSEL & 0x1F)
+ {
+ case 0:
+ USBClock = 0; //no clock will be provided to the USB subsystem
+ break;
+ case 4:
+ case 6:
+ {
+ uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
+ uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F);
+ if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc
+ USBClock = OSC_CLK * mul / usb_div;
+ else //pll_clk_in = irc_clk
+ USBClock = IRC_OSC * mul / usb_div;
+ }
+ break;
+ default:
+ USBClock = 0; /* this should never happen! */
+ }
+ }
+ else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
+ {
+ if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc
+ USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
+ else //pll1_clk_in = irc_clk
+ USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
+ }
+ else
+ USBClock = 0; /* this should never happen! */
+}
+
+ /* Determine clock frequency according to clock register values */
+
+#ifdef CORE_M4
+
+void fpu_init(void)
+{
+ // from arm trm manual:
+// ; CPACR is located at address 0xE000ED88
+// LDR.W R0, =0xE000ED88
+// ; Read CPACR
+// LDR R1, [R0]
+// ; Set bits 20-23 to enable CP10 and CP11 coprocessors
+// ORR R1, R1, #(0xF << 20)
+// ; Write back the modified value to the CPACR
+// STR R1, [R0]
+
+
+ volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR;
+ volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0;
+ volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1;
+ volatile uint32_t Cpacr;
+ volatile uint32_t Mvfr0;
+ volatile uint32_t Mvfr1;
+ char vfpPresent = 0;
+
+ Mvfr0 = *regMvfr0;
+ Mvfr1 = *regMvfr1;
+
+ vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
+
+ if(vfpPresent)
+ {
+ Cpacr = *regCpacr;
+ Cpacr |= (0xF << 20);
+ *regCpacr = Cpacr; // enable CP10 and CP11 for full access
+ }
+
+}
+#endif
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+#ifndef __CODE_RED
+#ifdef CORE_M4
+fpu_init();
+#endif
+#endif
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ LPC_SC->SCS = SCS_Val;
+ if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
+ while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
+ }
+
+ LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/
+
+#if (PLL0_SETUP)
+ LPC_SC->PLL0CFG = PLL0CFG_Val;
+ LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */
+#endif
+
+#if (PLL1_SETUP)
+ LPC_SC->PLL1CFG = PLL1CFG_Val;
+ LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
+#endif
+
+ LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */
+ LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */
+ LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */
+ LPC_SC->SPIFICLKSEL = SPIFICLKSEL_Val; /* SPIFI Clock Selection */
+ LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */
+ LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
+ LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
+#endif
+
+ LPC_SC->PBOOST |= 0x03; /* Power Boost control */
+
+#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
+ LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A;
+#endif
+#ifndef __CODE_RED
+#ifdef __RAM_MODE__
+ SCB->VTOR = 0x10000000 & 0x3FFFFF80;
+#else
+ SCB->VTOR = 0x00000000 & 0x3FFFFF80;
+#endif
+#endif
+ SystemCoreClockUpdate();
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC408X/system_LPC407x_8x_177x_8x.h Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,89 @@
+/**********************************************************************
+* $Id$ system_LPC407x_8x_177x_8x.h 2011-06-02
+*//**
+* @file system_LPC407x_8x_177x_8x.h
+* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+* for the NXP LPC Device Series
+* @version 1.0
+* @date 02. June. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+#ifndef __SYSTEM_LPC407x_8x_177x_8x_H
+#define __SYSTEM_LPC407x_8x_177x_8x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */
+extern uint32_t EMCClock; /*!< EMC Clock */
+extern uint32_t USBClock; /*!< USB Frequency */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (12000000UL) /* Oscillator frequency */
+#define OSC_CLK ( XTAL) /* Main oscillator frequency */
+#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
+#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */
+#define WDT_OSC ( 500000UL) /* Internal WDT oscillator frequency */
+
+
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC407x_8x_177x_8x_H */
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.c Mon Aug 05 14:54:27 2013 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.c Wed Aug 07 16:43:59 2013 +0300 @@ -5,7 +5,6 @@ */ #include "cmsis_nvic.h" -#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals #define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM #define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.h Mon Aug 05 14:54:27 2013 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.h Wed Aug 07 16:43:59 2013 +0300 @@ -7,6 +7,9 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H +#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals +#define NVIC_USER_IRQ_OFFSET 16 + #include "cmsis.h" #ifdef __cplusplus
--- a/targets/hal/TARGET_Freescale/TARGET_KL25Z/i2c_api.c Mon Aug 05 14:54:27 2013 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/i2c_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -25,6 +25,9 @@
{PTE0, I2C_1, 6},
{PTB1, I2C_0, 2},
{PTB3, I2C_0, 2},
+ {PTC11, I2C_1, 2},
+ {PTC2, I2C_1, 2},
+ {PTA4, I2C_1, 2},
{NC , NC , 0}
};
@@ -34,6 +37,8 @@
{PTE1, I2C_1, 6},
{PTB0, I2C_0, 2},
{PTB2, I2C_0, 2},
+ {PTC10, I2C_1, 2},
+ {PTC1, I2C_1, 2},
{NC , NC, 0}
};
@@ -84,10 +89,18 @@
}
int i2c_start(i2c_t *obj) {
+ uint8_t temp;
+ volatile int i;
// if we are in the middle of a transaction
// activate the repeat_start flag
if (obj->i2c->S & I2C_S_BUSY_MASK) {
+ // KL25Z errata sheet: repeat start cannot be generated if the
+ // I2Cx_F[MULT] field is set to a non-zero value
+ temp = obj->i2c->F >> 6;
+ obj->i2c->F &= 0x3F;
obj->i2c->C1 |= 0x04;
+ for (i = 0; i < 100; i ++) __NOP();
+ obj->i2c->F |= temp << 6;
} else {
obj->i2c->C1 |= I2C_C1_MST_MASK;
obj->i2c->C1 |= I2C_C1_TX_MASK;
--- a/targets/hal/TARGET_Freescale/TARGET_KL25Z/serial_api.c Mon Aug 05 14:54:27 2013 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/serial_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -1,174 +1,182 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "serial_api.h"
-
-// math.h required for floating point operations for baud rate calculation
-#include <math.h>
-
-#include <string.h>
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-/******************************************************************************
- * INITIALIZATION
- ******************************************************************************/
-static const PinMap PinMap_UART_TX[] = {
- {PTC4, UART_1, 3},
- {PTA2, UART_0, 2},
- {PTD5, UART_2, 3},
- {PTD3, UART_2, 3},
- {NC , NC , 0}
-};
-
-static const PinMap PinMap_UART_RX[] = {
- {PTC3, UART_1, 3},
- {PTA1, UART_0, 2},
- {PTD4, UART_2, 3},
- {PTD2, UART_2, 3},
- {NC , NC , 0}
-};
-
-#define UART_NUM 3
-static uint32_t serial_irq_ids[UART_NUM] = {0};
-static uart_irq_handler irq_handler;
-
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
- // determine the UART to use
- UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
- UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
- UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
- if ((int)uart == NC) {
- error("Serial pinout mapping failed");
- }
-
- obj->uart = (UARTLP_Type *)uart;
- // enable clk
- switch (uart) {
- case UART_0: SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK | (1<<SIM_SOPT2_UART0SRC_SHIFT);
- SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; break;
- case UART_1: SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK; SIM->SCGC4 |= SIM_SCGC4_UART1_MASK; break;
- case UART_2: SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK; SIM->SCGC4 |= SIM_SCGC4_UART2_MASK; break;
- }
- // Disable UART before changing registers
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "serial_api.h"
+
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+
+#include <string.h>
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+static const PinMap PinMap_UART_TX[] = {
+ {PTC4, UART_1, 3},
+ {PTA2, UART_0, 2},
+ {PTD5, UART_2, 3},
+ {PTD3, UART_2, 3},
+ {PTD7, UART_0, 3},
+ {PTE20, UART_0, 4},
+ {PTE22, UART_2, 4},
+ {PTE0, UART_1, 3},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+ {PTC3, UART_1, 3},
+ {PTA1, UART_0, 2},
+ {PTD4, UART_2, 3},
+ {PTD2, UART_2, 3},
+ {PTD6, UART_0, 3},
+ {PTE23, UART_2, 4},
+ {PTE21, UART_0, 4},
+ {PTE1, UART_1, 3},
+ {NC , NC , 0}
+};
+
+#define UART_NUM 3
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+ // determine the UART to use
+ UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+ UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+ UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+ if ((int)uart == NC) {
+ error("Serial pinout mapping failed");
+ }
+
+ obj->uart = (UARTLP_Type *)uart;
+ // enable clk
+ switch (uart) {
+ case UART_0: SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK | (1<<SIM_SOPT2_UART0SRC_SHIFT);
+ SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; break;
+ case UART_1: SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK; SIM->SCGC4 |= SIM_SCGC4_UART1_MASK; break;
+ case UART_2: SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK; SIM->SCGC4 |= SIM_SCGC4_UART2_MASK; break;
+ }
+ // Disable UART before changing registers
obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
switch (uart) {
case UART_0: obj->index = 0; break;
case UART_1: obj->index = 1; break;
case UART_2: obj->index = 2; break;
- }
-
- // set default baud rate and format
- serial_baud (obj, 9600);
- serial_format(obj, 8, ParityNone, 1);
-
- // pinout the chosen uart
- pinmap_pinout(tx, PinMap_UART_TX);
- pinmap_pinout(rx, PinMap_UART_RX);
-
- // set rx/tx pins in PullUp mode
- pin_mode(tx, PullUp);
- pin_mode(rx, PullUp);
-
- obj->uart->C2 |= (UART_C2_RE_MASK | UART_C2_TE_MASK);
-
- if (uart == STDIO_UART) {
- stdio_uart_inited = 1;
- memcpy(&stdio_uart, obj, sizeof(serial_t));
- }
-}
-
-void serial_free(serial_t *obj) {
- serial_irq_ids[obj->index] = 0;
-}
-
-// serial_baud
-//
-// set the baud rate, taking in to account the current SystemFrequency
-//
-// The LPC2300 and LPC1700 have a divider and a fractional divider to control the
-// baud rate. The formula is:
-//
-// Baudrate = (1 / PCLK) * 16 * DL * (1 + DivAddVal / MulVal)
-// where:
-// 1 < MulVal <= 15
-// 0 <= DivAddVal < 14
-// DivAddVal < MulVal
-//
-void serial_baud(serial_t *obj, int baudrate) {
-
- // save C2 state
- uint8_t c2_state = (obj->uart->C2 & (UART_C2_RE_MASK | UART_C2_TE_MASK));
-
- // Disable UART before changing registers
- obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
-
- // [TODO] not hardcode this value
- uint32_t PCLK = (obj->uart == UART0) ? 48000000u : 24000000u;
-
- // First we check to see if the basic divide with no DivAddVal/MulVal
- // ratio gives us an integer result. If it does, we set DivAddVal = 0,
- // MulVal = 1. Otherwise, we search the valid ratio value range to find
- // the closest match. This could be more elegant, using search methods
- // and/or lookup tables, but the brute force method is not that much
- // slower, and is more maintainable.
- uint16_t DL = PCLK / (16 * baudrate);
-
- // set BDH and BDL
- obj->uart->BDH = (obj->uart->BDH & ~(0x1f)) | ((DL >> 8) & 0x1f);
- obj->uart->BDL = (obj->uart->BDL & ~(0xff)) | ((DL >> 0) & 0xff);
-
- // restore C2 state
- obj->uart->C2 |= c2_state;
-}
-
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+ }
+
+ // set default baud rate and format
+ serial_baud (obj, 9600);
+ serial_format(obj, 8, ParityNone, 1);
+
+ // pinout the chosen uart
+ pinmap_pinout(tx, PinMap_UART_TX);
+ pinmap_pinout(rx, PinMap_UART_RX);
+
+ // set rx/tx pins in PullUp mode
+ pin_mode(tx, PullUp);
+ pin_mode(rx, PullUp);
+
+ obj->uart->C2 |= (UART_C2_RE_MASK | UART_C2_TE_MASK);
+
+ if (uart == STDIO_UART) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj) {
+ serial_irq_ids[obj->index] = 0;
+}
+
+// serial_baud
+//
+// set the baud rate, taking in to account the current SystemFrequency
+//
+// The LPC2300 and LPC1700 have a divider and a fractional divider to control the
+// baud rate. The formula is:
+//
+// Baudrate = (1 / PCLK) * 16 * DL * (1 + DivAddVal / MulVal)
+// where:
+// 1 < MulVal <= 15
+// 0 <= DivAddVal < 14
+// DivAddVal < MulVal
+//
+void serial_baud(serial_t *obj, int baudrate) {
+
+ // save C2 state
+ uint8_t c2_state = (obj->uart->C2 & (UART_C2_RE_MASK | UART_C2_TE_MASK));
+
+ // Disable UART before changing registers
+ obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
+
+ // [TODO] not hardcode this value
+ uint32_t PCLK = (obj->uart == UART0) ? 48000000u : 24000000u;
+
+ // First we check to see if the basic divide with no DivAddVal/MulVal
+ // ratio gives us an integer result. If it does, we set DivAddVal = 0,
+ // MulVal = 1. Otherwise, we search the valid ratio value range to find
+ // the closest match. This could be more elegant, using search methods
+ // and/or lookup tables, but the brute force method is not that much
+ // slower, and is more maintainable.
+ uint16_t DL = PCLK / (16 * baudrate);
+
+ // set BDH and BDL
+ obj->uart->BDH = (obj->uart->BDH & ~(0x1f)) | ((DL >> 8) & 0x1f);
+ obj->uart->BDL = (obj->uart->BDL & ~(0xff)) | ((DL >> 0) & 0xff);
+
+ // restore C2 state
+ obj->uart->C2 |= c2_state;
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
uint8_t m10 = 0;
-
- // save C2 state
- uint8_t c2_state = (obj->uart->C2 & (UART_C2_RE_MASK | UART_C2_TE_MASK));
-
- // Disable UART before changing registers
- obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
-
- // 8 data bits = 0 ... 9 data bits = 1
- if ((data_bits < 8) || (data_bits > 9)) {
- error("Invalid number of bits (%d) in serial format, should be 8..9\r\n", data_bits);
+
+ // save C2 state
+ uint8_t c2_state = (obj->uart->C2 & (UART_C2_RE_MASK | UART_C2_TE_MASK));
+
+ // Disable UART before changing registers
+ obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
+
+ // 8 data bits = 0 ... 9 data bits = 1
+ if ((data_bits < 8) || (data_bits > 9)) {
+ error("Invalid number of bits (%d) in serial format, should be 8..9\r\n", data_bits);
}
- data_bits -= 8;
-
- uint8_t parity_enable, parity_select;
- switch (parity) {
- case ParityNone: parity_enable = 0; parity_select = 0; break;
- case ParityOdd : parity_enable = 1; parity_select = 1; data_bits++; break;
- case ParityEven: parity_enable = 1; parity_select = 0; data_bits++; break;
- default:
- error("Invalid serial parity setting\r\n");
- return;
- }
-
- // 1 stop bits = 0, 2 stop bits = 1
- if ((stop_bits != 1) && (stop_bits != 2)) {
- error("Invalid stop bits specified\r\n");
- }
+ data_bits -= 8;
+
+ uint8_t parity_enable, parity_select;
+ switch (parity) {
+ case ParityNone: parity_enable = 0; parity_select = 0; break;
+ case ParityOdd : parity_enable = 1; parity_select = 1; data_bits++; break;
+ case ParityEven: parity_enable = 1; parity_select = 0; data_bits++; break;
+ default:
+ error("Invalid serial parity setting\r\n");
+ return;
+ }
+
+ // 1 stop bits = 0, 2 stop bits = 1
+ if ((stop_bits != 1) && (stop_bits != 2)) {
+ error("Invalid stop bits specified\r\n");
+ }
stop_bits -= 1;
// 9 data bits + parity
@@ -179,11 +187,11 @@
}
data_bits = 0;
m10 = 1;
- }
-
- // data bits, parity and parity mode
- obj->uart->C1 = ((data_bits << 4)
- | (parity_enable << 1)
+ }
+
+ // data bits, parity and parity mode
+ obj->uart->C1 = ((data_bits << 4)
+ | (parity_enable << 1)
| (parity_select << 0));
// enable 10bit mode if needed
@@ -191,115 +199,115 @@
obj->uart->C4 &= ~UARTLP_C4_M10_MASK;
obj->uart->C4 |= (m10 << UARTLP_C4_M10_SHIFT);
}
-
- // stop bits
- obj->uart->BDH &= ~UART_BDH_SBNS_MASK;
- obj->uart->BDH |= (stop_bits << UART_BDH_SBNS_SHIFT);
-
- // restore C2 state
- obj->uart->C2 |= c2_state;
-}
-
-/******************************************************************************
- * INTERRUPTS HANDLING
- ******************************************************************************/
-static inline void uart_irq(uint8_t status, uint32_t index) {
- if (serial_irq_ids[index] != 0) {
- if (status & UART_S1_TDRE_MASK)
- irq_handler(serial_irq_ids[index], TxIrq);
-
- if (status & UART_S1_RDRF_MASK)
- irq_handler(serial_irq_ids[index], RxIrq);
- }
-}
-
-void uart0_irq() {
- uart_irq(UART0->S1, 0);
- if (UART0->S1 & UART_S1_OR_MASK)
- UART0->S1 |= UART_S1_OR_MASK;
-}
-void uart1_irq() {uart_irq(UART1->S1, 1);}
-void uart2_irq() {uart_irq(UART2->S1, 2);}
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
- irq_handler = handler;
- serial_irq_ids[obj->index] = id;
-}
-
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
- IRQn_Type irq_n = (IRQn_Type)0;
- uint32_t vector = 0;
- switch ((int)obj->uart) {
- case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
- case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
- case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
- }
-
- if (enable) {
- switch (irq) {
- case RxIrq: obj->uart->C2 |= (UART_C2_RIE_MASK); break;
- case TxIrq: obj->uart->C2 |= (UART_C2_TIE_MASK); break;
- }
- NVIC_SetVector(irq_n, vector);
- NVIC_EnableIRQ(irq_n);
-
- } else { // disable
- int all_disabled = 0;
- SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
- switch (irq) {
- case RxIrq: obj->uart->C2 &= ~(UART_C2_RIE_MASK); break;
- case TxIrq: obj->uart->C2 &= ~(UART_C2_TIE_MASK); break;
- }
- switch (other_irq) {
- case RxIrq: all_disabled = (obj->uart->C2 & (UART_C2_RIE_MASK)) == 0; break;
- case TxIrq: all_disabled = (obj->uart->C2 & (UART_C2_TIE_MASK)) == 0; break;
- }
- if (all_disabled)
- NVIC_DisableIRQ(irq_n);
- }
-}
-
-/******************************************************************************
- * READ/WRITE
- ******************************************************************************/
-int serial_getc(serial_t *obj) {
- while (!serial_readable(obj));
- return obj->uart->D;
-}
-
-void serial_putc(serial_t *obj, int c) {
- while (!serial_writable(obj));
- obj->uart->D = c;
-}
-
-int serial_readable(serial_t *obj) {
- // check overrun
- if (obj->uart->S1 & UART_S1_OR_MASK) {
- obj->uart->S1 |= UART_S1_OR_MASK;
- }
- return (obj->uart->S1 & UART_S1_RDRF_MASK);
-}
-
-int serial_writable(serial_t *obj) {
- // check overrun
- if (obj->uart->S1 & UART_S1_OR_MASK) {
- obj->uart->S1 |= UART_S1_OR_MASK;
- }
- return (obj->uart->S1 & UART_S1_TDRE_MASK);
-}
-
-void serial_clear(serial_t *obj) {
-}
-
-void serial_pinout_tx(PinName tx) {
- pinmap_pinout(tx, PinMap_UART_TX);
-}
-
-void serial_break_set(serial_t *obj) {
- obj->uart->C2 |= UART_C2_SBK_MASK;
-}
-
-void serial_break_clear(serial_t *obj) {
- obj->uart->C2 &= ~UART_C2_SBK_MASK;
-}
-
+
+ // stop bits
+ obj->uart->BDH &= ~UART_BDH_SBNS_MASK;
+ obj->uart->BDH |= (stop_bits << UART_BDH_SBNS_SHIFT);
+
+ // restore C2 state
+ obj->uart->C2 |= c2_state;
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint8_t status, uint32_t index) {
+ if (serial_irq_ids[index] != 0) {
+ if (status & UART_S1_TDRE_MASK)
+ irq_handler(serial_irq_ids[index], TxIrq);
+
+ if (status & UART_S1_RDRF_MASK)
+ irq_handler(serial_irq_ids[index], RxIrq);
+ }
+}
+
+void uart0_irq() {
+ uart_irq(UART0->S1, 0);
+ if (UART0->S1 & UART_S1_OR_MASK)
+ UART0->S1 |= UART_S1_OR_MASK;
+}
+void uart1_irq() {uart_irq(UART1->S1, 1);}
+void uart2_irq() {uart_irq(UART2->S1, 2);}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+ irq_handler = handler;
+ serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+ switch ((int)obj->uart) {
+ case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
+ case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
+ case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
+ }
+
+ if (enable) {
+ switch (irq) {
+ case RxIrq: obj->uart->C2 |= (UART_C2_RIE_MASK); break;
+ case TxIrq: obj->uart->C2 |= (UART_C2_TIE_MASK); break;
+ }
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+
+ } else { // disable
+ int all_disabled = 0;
+ SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+ switch (irq) {
+ case RxIrq: obj->uart->C2 &= ~(UART_C2_RIE_MASK); break;
+ case TxIrq: obj->uart->C2 &= ~(UART_C2_TIE_MASK); break;
+ }
+ switch (other_irq) {
+ case RxIrq: all_disabled = (obj->uart->C2 & (UART_C2_RIE_MASK)) == 0; break;
+ case TxIrq: all_disabled = (obj->uart->C2 & (UART_C2_TIE_MASK)) == 0; break;
+ }
+ if (all_disabled)
+ NVIC_DisableIRQ(irq_n);
+ }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+ while (!serial_readable(obj));
+ return obj->uart->D;
+}
+
+void serial_putc(serial_t *obj, int c) {
+ while (!serial_writable(obj));
+ obj->uart->D = c;
+}
+
+int serial_readable(serial_t *obj) {
+ // check overrun
+ if (obj->uart->S1 & UART_S1_OR_MASK) {
+ obj->uart->S1 |= UART_S1_OR_MASK;
+ }
+ return (obj->uart->S1 & UART_S1_RDRF_MASK);
+}
+
+int serial_writable(serial_t *obj) {
+ // check overrun
+ if (obj->uart->S1 & UART_S1_OR_MASK) {
+ obj->uart->S1 |= UART_S1_OR_MASK;
+ }
+ return (obj->uart->S1 & UART_S1_TDRE_MASK);
+}
+
+void serial_clear(serial_t *obj) {
+}
+
+void serial_pinout_tx(PinName tx) {
+ pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+ obj->uart->C2 |= UART_C2_SBK_MASK;
+}
+
+void serial_break_clear(serial_t *obj) {
+ obj->uart->C2 &= ~UART_C2_SBK_MASK;
+}
+
--- a/targets/hal/TARGET_Freescale/TARGET_KL25Z/spi_api.c Mon Aug 05 14:54:27 2013 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/spi_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -1,172 +1,172 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "spi_api.h"
-
-#include <math.h>
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_SPI_SCLK[] = {
- {PTA15, SPI_0, 2},
- {PTB11, SPI_1, 2},
- {PTC5, SPI_0, 2},
- {PTD1, SPI_0, 2},
- {PTD5, SPI_1, 2},
- {PTE2, SPI_1, 2},
- {NC , NC , 0}
-};
-
-static const PinMap PinMap_SPI_MOSI[] = {
- {PTA16, SPI_0, 2},
- {PTA17, SPI_0, 5},
- {PTB16, SPI_1, 2},
- {PTB17, SPI_1, 5},
- {PTC6, SPI_0, 2},
- {PTC7, SPI_0, 5},
- {PTD2, SPI_0, 2},
- {PTD3, SPI_0, 5},
- {PTD6, SPI_1, 2},
- {PTD7, SPI_1, 5},
- {PTE1, SPI_1, 2},
- {PTE3, SPI_1, 5},
- {NC , NC , 0}
-};
-
-static const PinMap PinMap_SPI_MISO[] = {
- {PTA16, SPI_0, 5},
- {PTA17, SPI_0, 2},
- {PTB16, SPI_1, 5},
- {PTB17, SPI_1, 2},
- {PTC6, SPI_0, 5},
- {PTC7, SPI_0, 2},
- {PTD2, SPI_0, 5},
- {PTD3, SPI_0, 2},
- {PTD6, SPI_1, 5},
- {PTD7, SPI_1, 2},
- {PTE1, SPI_1, 5},
- {PTE3, SPI_1, 2},
- {NC , NC , 0}
-};
-
-static const PinMap PinMap_SPI_SSEL[] = {
- {PTA14, SPI_0, 2},
- {PTB10, SPI_1, 2},
- {PTC4, SPI_0, 2},
- {PTD0, SPI_0, 2},
- {PTD4, SPI_1, 2},
- {PTE4, SPI_1, 2},
- {NC , NC , 0}
-};
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
- // determine the SPI to use
- SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
- SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
- SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
- SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
- SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
- SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
- obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
- if ((int)obj->spi == NC) {
- error("SPI pinout mapping failed");
- }
-
- // enable power and clocking
- switch ((int)obj->spi) {
- case SPI_0: SIM->SCGC5 |= 1 << 11; SIM->SCGC4 |= 1 << 22; break;
- case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break;
- }
-
- // set default format and frequency
- if (ssel == NC) {
- spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
- } else {
- spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
- }
- spi_frequency(obj, 1000000);
-
- // enable SPI
- obj->spi->C1 |= SPI_C1_SPE_MASK;
-
- // pin out the spi pins
- pinmap_pinout(mosi, PinMap_SPI_MOSI);
- pinmap_pinout(miso, PinMap_SPI_MISO);
- pinmap_pinout(sclk, PinMap_SPI_SCLK);
- if (ssel != NC) {
- pinmap_pinout(ssel, PinMap_SPI_SSEL);
- }
-}
-
-void spi_free(spi_t *obj) {
- // [TODO]
-}
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
- if (bits != 8) {
- error("Only 8bits SPI supported");
- }
-
- if ((mode < 0) || (mode > 3)) {
- error("SPI mode unsupported");
- }
-
- uint8_t polarity = (mode & 0x2) ? 1 : 0;
- uint8_t phase = (mode & 0x1) ? 1 : 0;
- uint8_t c1_data = ((!slave) << 4) | (polarity << 3) | (phase << 2);
-
- // clear MSTR, CPOL and CPHA bits
- obj->spi->C1 &= ~(0x7 << 2);
-
- // write new value
- obj->spi->C1 |= c1_data;
-}
-
-void spi_frequency(spi_t *obj, int hz) {
- uint32_t error = 0;
- uint32_t p_error = 0xffffffff;
- uint32_t ref = 0;
- uint8_t spr = 0;
- uint8_t ref_spr = 0;
- uint8_t ref_prescaler = 0;
-
- // bus clk
- uint32_t PCLK = 48000000u;
- uint8_t prescaler = 1;
- uint8_t divisor = 2;
-
- for (prescaler = 1; prescaler <= 8; prescaler++) {
- divisor = 2;
- for (spr = 0; spr <= 8; spr++, divisor *= 2) {
- ref = PCLK / (prescaler*divisor);
- if (ref > hz)
- continue;
- error = hz - ref;
- if (error < p_error) {
- ref_spr = spr;
- ref_prescaler = prescaler - 1;
- p_error = error;
- }
- }
- }
-
- // set SPPR and SPR
- obj->spi->BR = ((ref_prescaler & 0x7) << 4) | (ref_spr & 0xf);
-}
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "spi_api.h"
+
+#include <math.h>
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_SPI_SCLK[] = {
+ {PTA15, SPI_0, 2},
+ {PTB11, SPI_1, 2},
+ {PTC5, SPI_0, 2},
+ {PTD1, SPI_0, 2},
+ {PTD5, SPI_1, 2},
+ {PTE2, SPI_1, 2},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+ {PTA16, SPI_0, 2},
+ {PTA17, SPI_0, 5},
+ {PTB16, SPI_1, 2},
+ {PTB17, SPI_1, 5},
+ {PTC6, SPI_0, 2},
+ {PTC7, SPI_0, 5},
+ {PTD2, SPI_0, 2},
+ {PTD3, SPI_0, 5},
+ {PTD6, SPI_1, 2},
+ {PTD7, SPI_1, 5},
+ {PTE1, SPI_1, 2},
+ {PTE3, SPI_1, 5},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+ {PTA16, SPI_0, 5},
+ {PTA17, SPI_0, 2},
+ {PTB16, SPI_1, 5},
+ {PTB17, SPI_1, 2},
+ {PTC6, SPI_0, 5},
+ {PTC7, SPI_0, 2},
+ {PTD2, SPI_0, 5},
+ {PTD3, SPI_0, 2},
+ {PTD6, SPI_1, 5},
+ {PTD7, SPI_1, 2},
+ {PTE1, SPI_1, 5},
+ {PTE3, SPI_1, 2},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+ {PTA14, SPI_0, 2},
+ {PTB10, SPI_1, 2},
+ {PTC4, SPI_0, 2},
+ {PTD0, SPI_0, 2},
+ {PTD4, SPI_1, 2},
+ {PTE4, SPI_1, 2},
+ {NC , NC , 0}
+};
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+ // determine the SPI to use
+ SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+ SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+ SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+ SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+
+ obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
+ if ((int)obj->spi == NC) {
+ error("SPI pinout mapping failed");
+ }
+
+ // enable power and clocking
+ switch ((int)obj->spi) {
+ case SPI_0: SIM->SCGC5 |= 1 << 11; SIM->SCGC4 |= 1 << 22; break;
+ case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break;
+ }
+
+ // set default format and frequency
+ if (ssel == NC) {
+ spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
+ } else {
+ spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
+ }
+ spi_frequency(obj, 1000000);
+
+ // enable SPI
+ obj->spi->C1 |= SPI_C1_SPE_MASK;
+
+ // pin out the spi pins
+ pinmap_pinout(mosi, PinMap_SPI_MOSI);
+ pinmap_pinout(miso, PinMap_SPI_MISO);
+ pinmap_pinout(sclk, PinMap_SPI_SCLK);
+ if (ssel != NC) {
+ pinmap_pinout(ssel, PinMap_SPI_SSEL);
+ }
+}
+
+void spi_free(spi_t *obj) {
+ // [TODO]
+}
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+ if (bits != 8) {
+ error("Only 8bits SPI supported");
+ }
+
+ if ((mode < 0) || (mode > 3)) {
+ error("SPI mode unsupported");
+ }
+
+ uint8_t polarity = (mode & 0x2) ? 1 : 0;
+ uint8_t phase = (mode & 0x1) ? 1 : 0;
+ uint8_t c1_data = ((!slave) << 4) | (polarity << 3) | (phase << 2);
+
+ // clear MSTR, CPOL and CPHA bits
+ obj->spi->C1 &= ~(0x7 << 2);
+
+ // write new value
+ obj->spi->C1 |= c1_data;
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+ uint32_t error = 0;
+ uint32_t p_error = 0xffffffff;
+ uint32_t ref = 0;
+ uint8_t spr = 0;
+ uint8_t ref_spr = 0;
+ uint8_t ref_prescaler = 0;
+
+ // bus clk
+ uint32_t PCLK = 48000000u;
+ uint8_t prescaler = 1;
+ uint8_t divisor = 2;
+
+ for (prescaler = 1; prescaler <= 8; prescaler++) {
+ divisor = 2;
+ for (spr = 0; spr <= 8; spr++, divisor *= 2) {
+ ref = PCLK / (prescaler*divisor);
+ if (ref > hz)
+ continue;
+ error = hz - ref;
+ if (error < p_error) {
+ ref_spr = spr;
+ ref_prescaler = prescaler - 1;
+ p_error = error;
+ }
+ }
+ }
+
+ // set SPPR and SPR
+ obj->spi->BR = ((ref_prescaler & 0x7) << 4) | (ref_spr & 0xf);
+}
static inline int spi_writeable(spi_t * obj) {
return (obj->spi->S & SPI_S_SPTEF_MASK) ? 1 : 0;
@@ -174,16 +174,16 @@
static inline int spi_readable(spi_t * obj) {
return (obj->spi->S & SPI_S_SPRF_MASK) ? 1 : 0;
-}
-
-int spi_master_write(spi_t *obj, int value) {
- // wait tx buffer empty
- while(!spi_writeable(obj));
- obj->spi->D = (value & 0xff);
-
- // wait rx buffer full
- while (!spi_readable(obj));
- return obj->spi->D & 0xff;
+}
+
+int spi_master_write(spi_t *obj, int value) {
+ // wait tx buffer empty
+ while(!spi_writeable(obj));
+ obj->spi->D = (value & 0xff);
+
+ // wait rx buffer full
+ while (!spi_readable(obj));
+ return obj->spi->D & 0xff;
}
int spi_slave_receive(spi_t *obj) {
@@ -197,4 +197,4 @@
void spi_slave_write(spi_t *obj, int value) {
while (!spi_writeable(obj));
obj->spi->D = value;
-}
+}
--- a/targets/hal/TARGET_NXP/TARGET_LPC176X/can_api.c Mon Aug 05 14:54:27 2013 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/can_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -22,6 +22,8 @@
#include <math.h>
#include <string.h>
+#define CAN_NUM 2
+
/* Acceptance filter mode in AFMR register */
#define ACCF_OFF 0x01
#define ACCF_BYPASS 0x02
@@ -61,6 +63,9 @@
};
typedef struct CANMsg CANMsg;
+static uint32_t can_irq_ids[CAN_NUM] = {0};
+static can_irq_handler irq_handler;
+
static uint32_t can_disable(can_t *obj) {
uint32_t sm = obj->dev->MOD;
obj->dev->MOD |= 1;
@@ -73,6 +78,101 @@
}
}
+int can_mode(can_t *obj, CanMode mode)
+{
+ return 0; // not implemented
+}
+
+static inline void can_irq(uint32_t icr, uint32_t index) {
+ uint32_t i;
+
+ for(i = 0; i < 8; i++)
+ {
+ if((can_irq_ids[index] != 0) && (icr & (1 << i)))
+ {
+ switch (i) {
+ case 0: irq_handler(can_irq_ids[index], IRQ_RX); break;
+ case 1: irq_handler(can_irq_ids[index], IRQ_TX); break;
+ case 2: irq_handler(can_irq_ids[index], IRQ_ERROR); break;
+ case 3: irq_handler(can_irq_ids[index], IRQ_OVERRUN); break;
+ case 4: irq_handler(can_irq_ids[index], IRQ_WAKEUP); break;
+ case 5: irq_handler(can_irq_ids[index], IRQ_PASSIVE); break;
+ case 6: irq_handler(can_irq_ids[index], IRQ_ARB); break;
+ case 7: irq_handler(can_irq_ids[index], IRQ_BUS); break;
+ case 8: irq_handler(can_irq_ids[index], IRQ_READY); break;
+ }
+ }
+ }
+}
+
+// Have to check that the CAN block is active before reading the Interrupt
+// Control Register, or the mbed hangs
+void can_irq_n() {
+ uint32_t icr;
+
+ if(LPC_SC->PCONP & (1 << 13)) {
+ icr = LPC_CAN1->ICR & 0x1FF;
+ can_irq(icr, 0);
+ }
+
+ if(LPC_SC->PCONP & (1 << 14)) {
+ icr = LPC_CAN2->ICR & 0x1FF;
+ can_irq(icr, 1);
+ }
+}
+
+// Register CAN object's irq handler
+void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
+ irq_handler = handler;
+ can_irq_ids[obj->index] = id;
+}
+
+// Unregister CAN object's irq handler
+void can_irq_free(can_t *obj) {
+ obj->dev->IER &= ~(1);
+ can_irq_ids[obj->index] = 0;
+
+ if ((can_irq_ids[0] == 0) && (can_irq_ids[1] == 0)) {
+ NVIC_DisableIRQ(CAN_IRQn);
+ }
+}
+
+// Clear or set a irq
+void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
+ uint32_t ier;
+
+ switch (type) {
+ case IRQ_RX: ier = (1 << 0); break;
+ case IRQ_TX: ier = (1 << 1); break;
+ case IRQ_ERROR: ier = (1 << 2); break;
+ case IRQ_OVERRUN: ier = (1 << 3); break;
+ case IRQ_WAKEUP: ier = (1 << 4); break;
+ case IRQ_PASSIVE: ier = (1 << 5); break;
+ case IRQ_ARB: ier = (1 << 6); break;
+ case IRQ_BUS: ier = (1 << 7); break;
+ case IRQ_READY: ier = (1 << 8); break;
+ default: return;
+ }
+
+ obj->dev->MOD |= 1;
+ if(enable == 0) {
+ obj->dev->IER &= ~ier;
+ }
+ else {
+ obj->dev->IER |= ier;
+ }
+ obj->dev->MOD &= ~(1);
+
+ // Enable NVIC if at least 1 interrupt is active
+ if(LPC_CAN1->IER | LPC_CAN2->IER != 0) {
+ NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq_n);
+ NVIC_EnableIRQ(CAN_IRQn);
+ }
+ else {
+ NVIC_DisableIRQ(CAN_IRQn);
+ }
+}
+
static int can_pclk(can_t *obj) {
int value = 0;
switch ((int)obj->dev) {
@@ -166,7 +266,12 @@
pinmap_pinout(rd, PinMap_CAN_RD);
pinmap_pinout(td, PinMap_CAN_TD);
-
+
+ switch ((int)obj->dev) {
+ case CAN_1: obj->index = 0; break;
+ case CAN_2: obj->index = 1; break;
+ }
+
can_reset(obj);
obj->dev->IER = 0; // Disable Interrupts
can_frequency(obj, 100000);
--- a/targets/hal/TARGET_NXP/TARGET_LPC176X/objects.h Mon Aug 05 14:54:27 2013 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/objects.h Wed Aug 07 16:43:59 2013 +0300
@@ -1,78 +1,79 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- uint32_t port;
- uint32_t pin;
- uint32_t ch;
-};
-
-struct port_s {
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_out;
- __I uint32_t *reg_in;
- PortName port;
- uint32_t mask;
-};
-
-struct pwmout_s {
- __IO uint32_t *MR;
- PWMName pwm;
-};
-
-struct serial_s {
- LPC_UART_TypeDef *uart;
- int index;
-};
-
-struct analogin_s {
- ADCName adc;
-};
-
-struct dac_s {
- DACName dac;
-};
-
-struct can_s {
- LPC_CAN_TypeDef *dev;
-};
-
-struct i2c_s {
- LPC_I2C_TypeDef *i2c;
-};
-
-struct spi_s {
- LPC_SSP_TypeDef *spi;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t port;
+ uint32_t pin;
+ uint32_t ch;
+};
+
+struct port_s {
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_out;
+ __I uint32_t *reg_in;
+ PortName port;
+ uint32_t mask;
+};
+
+struct pwmout_s {
+ __IO uint32_t *MR;
+ PWMName pwm;
+};
+
+struct serial_s {
+ LPC_UART_TypeDef *uart;
+ int index;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct dac_s {
+ DACName dac;
+};
+
+struct can_s {
+ LPC_CAN_TypeDef *dev;
+ int index;
+};
+
+struct i2c_s {
+ LPC_I2C_TypeDef *i2c;
+};
+
+struct spi_s {
+ LPC_SSP_TypeDef *spi;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/PeripheralNames.h Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,88 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_UART0_BASE,
+ UART_1 = (int)LPC_UART1_BASE,
+ UART_2 = (int)LPC_UART2_BASE,
+ UART_3 = (int)LPC_UART3_BASE,
+ UART_4 = (int)LPC_UART4_BASE
+} UARTName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0
+} DACName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE,
+ SPI_2 = (int)LPC_SSP2_BASE
+} SPIName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C0_BASE,
+ I2C_1 = (int)LPC_I2C1_BASE,
+ I2C_2 = (int)LPC_I2C2_BASE
+} I2CName;
+
+typedef enum {
+ PWM0_1 = 1,
+ PWM0_2,
+ PWM0_3,
+ PWM0_4,
+ PWM0_5,
+ PWM0_6,
+ PWM1_1,
+ PWM1_2,
+ PWM1_3,
+ PWM1_4,
+ PWM1_5,
+ PWM1_6
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)LPC_CAN1_BASE,
+ CAN_2 = (int)LPC_CAN2_BASE
+} CANName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/PinNames.h Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,96 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 5
+
+typedef enum {
+ // LPC Pin Names
+ P0_0 = /*LPC_GPIO0_BASE*/0,
+ P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
+ P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
+ P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
+ P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
+ P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
+ P5_0, P5_1, P5_2, P5_3, P5_4,
+
+ // mbed DIP Pin Names
+ p5 = P0_9,
+ p6 = P0_8,
+ p7 = P0_7,
+ p8 = P0_6,
+ p9 = P0_0,
+ p10 = P0_1,
+ p11 = P0_18,
+ p12 = P0_17,
+ p13 = P0_15,
+ p14 = P0_16,
+ p15 = P0_23,
+ p16 = P0_24,
+ p17 = P0_25,
+ p18 = P0_26,
+ p19 = P1_30,
+ p20 = P1_31,
+ p21 = P2_5,
+ p22 = P2_4,
+ p23 = P2_3,
+ p24 = P2_2,
+ p25 = P2_1,
+ p26 = P2_0,
+ p27 = P0_11,
+ p28 = P0_10,
+ p29 = P0_5,
+ p30 = P0_4,
+
+ // Other mbed Pin Names
+ LED1 = P2_27,
+ LED2 = P2_26,
+ LED3 = P2_26,
+ LED4 = P2_26,
+
+ USBTX = P0_2,
+ USBRX = P0_3,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullUp = 0,
+ PullDown = 3,
+ PullNone = 2,
+ OpenDrain = 4
+} PinMode;
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/PortNames.h Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+ Port1 = 1,
+ Port2 = 2,
+ Port3 = 3,
+ Port4 = 4,
+ Port5 = 5
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/analogin_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,126 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "analogin_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#define ANALOGIN_MEDIAN_FILTER 1
+
+#define ADC_10BIT_RANGE 0x3FF
+#define ADC_12BIT_RANGE 0xFFF
+
+static inline int div_round_up(int x, int y) {
+ return (x + (y - 1)) / y;
+}
+
+static const PinMap PinMap_ADC[] = {
+ {P0_23, ADC0_0, 0x01},
+ {P0_24, ADC0_1, 0x01},
+ {P0_25, ADC0_2, 0x01},
+ {P0_26, ADC0_3, 0x01},
+ {P1_30, ADC0_4, 0x03},
+ {P1_31, ADC0_5, 0x03},
+ {P0_12, ADC0_6, 0x03},
+ {P0_13, ADC0_7, 0x03},
+ {NC , NC , 0 }
+};
+
+#define ADC_RANGE ADC_12BIT_RANGE
+
+void analogin_init(analogin_t *obj, PinName pin) {
+ obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+ if (obj->adc == (uint32_t)NC) {
+ error("ADC pin mapping failed");
+ }
+
+ // ensure power is turned on
+ LPC_SC->PCONP |= (1 << 12);
+
+ uint32_t PCLK = PeripheralClock;
+
+ // calculate minimum clock divider
+ // clkdiv = divider - 1
+ uint32_t MAX_ADC_CLK = 12400000;
+ uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
+
+ // Set the generic software-controlled ADC settings
+ LPC_ADC->CR = (0 << 0) // SEL: 0 = no channels selected
+ | (clkdiv << 8) // CLKDIV:
+ | (0 << 16) // BURST: 0 = software control
+ | (1 << 21) // PDN: 1 = operational
+ | (0 << 24) // START: 0 = no start
+ | (0 << 27); // EDGE: not applicable
+
+ // must enable analog mode (ADMODE = 0)
+ __IO uint32_t *reg = (__IO uint32_t*) (LPC_IOCON_BASE + 4 * pin);
+ *reg &= ~(1 << 7);
+
+ pinmap_pinout(pin, PinMap_ADC);
+}
+
+static inline uint32_t adc_read(analogin_t *obj) {
+ // Select the appropriate channel and start conversion
+ LPC_ADC->CR &= ~0xFF;
+ LPC_ADC->CR |= 1 << (int)obj->adc;
+ LPC_ADC->CR |= 1 << 24;
+
+ // Repeatedly get the sample data until DONE bit
+ unsigned int data;
+ do {
+ data = LPC_ADC->GDR;
+ } while ((data & ((unsigned int)1 << 31)) == 0);
+
+ // Stop conversion
+ LPC_ADC->CR &= ~(1 << 24);
+
+ return (data >> 4) & ADC_RANGE; // 12 bit
+}
+
+static inline void order(uint32_t *a, uint32_t *b) {
+ if (*a > *b) {
+ uint32_t t = *a;
+ *a = *b;
+ *b = t;
+ }
+}
+
+static inline uint32_t adc_read_u32(analogin_t *obj) {
+ uint32_t value;
+#if ANALOGIN_MEDIAN_FILTER
+ uint32_t v1 = adc_read(obj);
+ uint32_t v2 = adc_read(obj);
+ uint32_t v3 = adc_read(obj);
+ order(&v1, &v2);
+ order(&v2, &v3);
+ order(&v1, &v2);
+ value = v2;
+#else
+ value = adc_read(obj);
+#endif
+ return value;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+ uint32_t value = adc_read_u32(obj);
+
+ return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
+}
+
+float analogin_read(analogin_t *obj) {
+ uint32_t value = adc_read_u32(obj);
+ return (float)value * (1.0f / (float)ADC_RANGE);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/analogout_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "analogout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_DAC[] = {
+ {P0_26, DAC_0, 2},
+ {NC , NC , 0}
+};
+
+void analogout_init(dac_t *obj, PinName pin) {
+ obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
+ if (obj->dac == (uint32_t)NC) {
+ error("DAC pin mapping failed");
+ }
+
+ // DAC enable bit must be set
+ LPC_IOCON->P0_26 |= (1 << 16); // DACEN
+
+ // map out (must be done before accessing registers)
+ pinmap_pinout(pin, PinMap_DAC);
+
+ analogout_write_u16(obj, 0);
+}
+
+void analogout_free(dac_t *obj) {}
+
+static inline void dac_write(int value) {
+ value &= 0x3FF; // 10-bit
+
+ // Set the DAC output
+ LPC_DAC->CR = (0 << 16) // bias = 0
+ | (value << 6);
+}
+
+static inline int dac_read() {
+ return (LPC_DAC->CR >> 6) & 0x3FF;
+}
+
+void analogout_write(dac_t *obj, float value) {
+ if (value < 0.0f) {
+ dac_write(0);
+ } else if (value > 1.0f) {
+ dac_write(0x3FF);
+ } else {
+ dac_write(value * (float)0x3FF);
+ }
+}
+
+void analogout_write_u16(dac_t *obj, uint16_t value) {
+ dac_write(value >> 6); // 10-bit
+}
+
+float analogout_read(dac_t *obj) {
+ uint32_t value = dac_read();
+ return (float)value * (1.0f / (float)0x3FF);
+}
+
+uint16_t analogout_read_u16(dac_t *obj) {
+ uint32_t value = dac_read(); // 10-bit
+ return (value << 6) | ((value >> 4) & 0x003F);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/can_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,282 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+#include <string.h>
+
+#include "can_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+/* Acceptance filter mode in AFMR register */
+#define ACCF_OFF 0x01
+#define ACCF_BYPASS 0x02
+#define ACCF_ON 0x00
+#define ACCF_FULLCAN 0x04
+
+/* There are several bit timing calculators on the internet.
+http://www.port.de/engl/canprod/sv_req_form.html
+http://www.kvaser.com/can/index.htm
+*/
+
+static const PinMap PinMap_CAN_RD[] = {
+ {P0_0 , CAN_1, 1},
+ {P0_4 , CAN_2, 2},
+ {P0_21, CAN_1, 4},
+ {P2_7 , CAN_2, 1},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_CAN_TD[] = {
+ {P0_1 , CAN_1, 1},
+ {P0_5 , CAN_2, 2},
+ {P0_22, CAN_1, 4},
+ {P2_8 , CAN_2, 1},
+ {NC , NC , 0}
+};
+
+// Type definition to hold a CAN message
+struct CANMsg {
+ unsigned int reserved1 : 16;
+ unsigned int dlc : 4; // Bits 16..19: DLC - Data Length Counter
+ unsigned int reserved0 : 10;
+ unsigned int rtr : 1; // Bit 30: Set if this is a RTR message
+ unsigned int type : 1; // Bit 31: Set if this is a 29-bit ID message
+ unsigned int id; // CAN Message ID (11-bit or 29-bit)
+ unsigned char data[8]; // CAN Message Data Bytes 0-7
+};
+typedef struct CANMsg CANMsg;
+
+static uint32_t can_disable(can_t *obj) {
+ uint32_t sm = obj->dev->MOD;
+ obj->dev->MOD |= 1;
+ return sm;
+}
+
+static inline void can_enable(can_t *obj) {
+ if (obj->dev->MOD & 1) {
+ obj->dev->MOD &= ~(1);
+ }
+}
+
+// This table has the sampling points as close to 75% as possible. The first
+// value is TSEG1, the second TSEG2.
+static const int timing_pts[23][2] = {
+ {0x0, 0x0}, // 2, 50%
+ {0x1, 0x0}, // 3, 67%
+ {0x2, 0x0}, // 4, 75%
+ {0x3, 0x0}, // 5, 80%
+ {0x3, 0x1}, // 6, 67%
+ {0x4, 0x1}, // 7, 71%
+ {0x5, 0x1}, // 8, 75%
+ {0x6, 0x1}, // 9, 78%
+ {0x6, 0x2}, // 10, 70%
+ {0x7, 0x2}, // 11, 73%
+ {0x8, 0x2}, // 12, 75%
+ {0x9, 0x2}, // 13, 77%
+ {0x9, 0x3}, // 14, 71%
+ {0xA, 0x3}, // 15, 73%
+ {0xB, 0x3}, // 16, 75%
+ {0xC, 0x3}, // 17, 76%
+ {0xD, 0x3}, // 18, 78%
+ {0xD, 0x4}, // 19, 74%
+ {0xE, 0x4}, // 20, 75%
+ {0xF, 0x4}, // 21, 76%
+ {0xF, 0x5}, // 22, 73%
+ {0xF, 0x6}, // 23, 70%
+ {0xF, 0x7}, // 24, 67%
+};
+
+static unsigned int can_speed(unsigned int sclk, unsigned int pclk, unsigned int cclk, unsigned char psjw) {
+ uint32_t btr;
+ uint16_t brp = 0;
+ uint32_t calcbit;
+ uint32_t bitwidth;
+ int hit = 0;
+ int bits;
+
+ bitwidth = sclk / (pclk * cclk);
+
+ brp = bitwidth / 0x18;
+ while ((!hit) && (brp < bitwidth / 4)) {
+ brp++;
+ for (bits = 22; bits > 0; bits--) {
+ calcbit = (bits + 3) * (brp + 1);
+ if (calcbit == bitwidth) {
+ hit = 1;
+ break;
+ }
+ }
+ }
+
+ if (hit) {
+ btr = ((timing_pts[bits][1] << 20) & 0x00700000)
+ | ((timing_pts[bits][0] << 16) & 0x000F0000)
+ | ((psjw << 14) & 0x0000C000)
+ | ((brp << 0) & 0x000003FF);
+ } else {
+ btr = 0xFFFFFFFF;
+ }
+
+ return btr;
+}
+
+void can_init(can_t *obj, PinName rd, PinName td) {
+ CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
+ CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
+ obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
+ if ((int)obj->dev == NC) {
+ error("CAN pin mapping failed");
+ }
+
+ switch ((int)obj->dev) {
+ case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
+ case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
+ }
+
+ pinmap_pinout(rd, PinMap_CAN_RD);
+ pinmap_pinout(td, PinMap_CAN_TD);
+
+ can_reset(obj);
+ obj->dev->IER = 0; // Disable Interrupts
+ can_frequency(obj, 100000);
+
+ LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
+}
+
+void can_free(can_t *obj) {
+ switch ((int)obj->dev) {
+ case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break;
+ case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break;
+ }
+}
+
+int can_frequency(can_t *obj, int f) {
+ int pclk = PeripheralClock;
+ int btr = can_speed(SystemCoreClock, pclk, (unsigned int)f, 1);
+
+ if (btr > 0) {
+ uint32_t modmask = can_disable(obj);
+ obj->dev->BTR = btr;
+ obj->dev->MOD = modmask;
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc) {
+ unsigned int CANStatus;
+ CANMsg m;
+
+ can_enable(obj);
+
+ m.id = msg.id ;
+ m.dlc = msg.len & 0xF;
+ m.rtr = msg.type;
+ m.type = msg.format;
+ memcpy(m.data, msg.data, msg.len);
+ const unsigned int *buf = (const unsigned int *)&m;
+
+ CANStatus = obj->dev->SR;
+ if (CANStatus & 0x00000004) {
+ obj->dev->TFI1 = buf[0] & 0xC00F0000;
+ obj->dev->TID1 = buf[1];
+ obj->dev->TDA1 = buf[2];
+ obj->dev->TDB1 = buf[3];
+ if(cc) {
+ obj->dev->CMR = 0x30;
+ } else {
+ obj->dev->CMR = 0x21;
+ }
+ return 1;
+
+ } else if (CANStatus & 0x00000400) {
+ obj->dev->TFI2 = buf[0] & 0xC00F0000;
+ obj->dev->TID2 = buf[1];
+ obj->dev->TDA2 = buf[2];
+ obj->dev->TDB2 = buf[3];
+ if (cc) {
+ obj->dev->CMR = 0x50;
+ } else {
+ obj->dev->CMR = 0x41;
+ }
+ return 1;
+
+ } else if (CANStatus & 0x00040000) {
+ obj->dev->TFI3 = buf[0] & 0xC00F0000;
+ obj->dev->TID3 = buf[1];
+ obj->dev->TDA3 = buf[2];
+ obj->dev->TDB3 = buf[3];
+ if (cc) {
+ obj->dev->CMR = 0x90;
+ } else {
+ obj->dev->CMR = 0x81;
+ }
+ return 1;
+ }
+
+ return 0;
+}
+
+int can_read(can_t *obj, CAN_Message *msg) {
+ CANMsg x;
+ unsigned int *i = (unsigned int *)&x;
+
+ can_enable(obj);
+
+ if (obj->dev->GSR & 0x1) {
+ *i++ = obj->dev->RFS; // Frame
+ *i++ = obj->dev->RID; // ID
+ *i++ = obj->dev->RDA; // Data A
+ *i++ = obj->dev->RDB; // Data B
+ obj->dev->CMR = 0x04; // release receive buffer
+
+ msg->id = x.id;
+ msg->len = x.dlc;
+ msg->format = (x.type)? CANExtended : CANStandard;
+ msg->type = (x.rtr)? CANRemote: CANData;
+ memcpy(msg->data,x.data,x.dlc);
+ return 1;
+ }
+
+ return 0;
+}
+
+void can_reset(can_t *obj) {
+ can_disable(obj);
+ obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
+}
+
+unsigned char can_rderror(can_t *obj) {
+ return (obj->dev->GSR >> 16) & 0xFF;
+}
+
+unsigned char can_tderror(can_t *obj) {
+ return (obj->dev->GSR >> 24) & 0xFF;
+}
+
+void can_monitor(can_t *obj, int silent) {
+ uint32_t mod_mask = can_disable(obj);
+ if (silent) {
+ obj->dev->MOD |= (1 << 1);
+ } else {
+ obj->dev->MOD &= ~(1 << 1);
+ }
+ if (!(mod_mask & 1)) {
+ can_enable(obj);
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/device.h Wed Aug 07 16:43:59 2013 +0300 @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 1 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 // Need HW? +#define DEVICE_LOCALFILESYSTEM 0 // Need HW? +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 1 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/ethernet_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,964 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+
+#include "ethernet_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "toolchain.h"
+#include "error.h"
+
+#define NEW_LOGIC 0
+#define NEW_ETH_BUFFER 0
+
+#if NEW_ETH_BUFFER
+
+#define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets)
+#define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets)
+
+#define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size
+#define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length)
+
+#else
+
+// Memfree calculation:
+// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
+// (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
+#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
+#define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
+//#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
+
+//#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
+#define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */
+#define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */
+
+const int ethernet_MTU_SIZE = 0x300;
+
+#endif
+
+#define ETHERNET_ADDR_SIZE 6
+
+PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */
+ unsigned int Packet;
+ unsigned int Ctrl;
+};
+typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
+
+PACKED struct RX_STAT_TypeDef { /* RX Status struct */
+ unsigned int Info;
+ unsigned int HashCRC;
+};
+typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
+
+PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */
+ unsigned int Packet;
+ unsigned int Ctrl;
+};
+typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
+
+PACKED struct TX_STAT_TypeDef { /* TX Status struct */
+ unsigned int Info;
+};
+typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
+
+/* MAC Configuration Register 1 */
+#define MAC1_REC_EN 0x00000001 /* Receive Enable */
+#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
+#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
+#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
+#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
+#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
+#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
+#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
+#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
+#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
+#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
+
+/* MAC Configuration Register 2 */
+#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
+#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
+#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
+#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
+#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
+#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
+#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
+#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
+#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
+#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
+#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
+#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
+#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
+
+/* Back-to-Back Inter-Packet-Gap Register */
+#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
+#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
+
+/* Non Back-to-Back Inter-Packet-Gap Register */
+#define IPGR_DEF 0x00000012 /* Recommended value */
+
+/* Collision Window/Retry Register */
+#define CLRT_DEF 0x0000370F /* Default value */
+
+/* PHY Support Register */
+#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
+//#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
+#define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
+
+/* Test Register */
+#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
+#define TEST_TST_PAUSE 0x00000002 /* Test Pause */
+#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
+
+/* MII Management Configuration Register */
+#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
+#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
+#define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */
+#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
+
+/* MII Management Command Register */
+#define MCMD_READ 0x00000001 /* MII Read */
+#define MCMD_SCAN 0x00000002 /* MII Scan continuously */
+
+#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
+#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
+
+/* MII Management Address Register */
+#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
+#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
+
+/* MII Management Indicators Register */
+#define MIND_BUSY 0x00000001 /* MII is Busy */
+#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
+#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
+#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
+
+/* Command Register */
+#define CR_RX_EN 0x00000001 /* Enable Receive */
+#define CR_TX_EN 0x00000002 /* Enable Transmit */
+#define CR_REG_RES 0x00000008 /* Reset Host Registers */
+#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
+#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
+#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
+#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
+#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
+#define CR_RMII 0x00000200 /* Reduced MII Interface */
+#define CR_FULL_DUP 0x00000400 /* Full Duplex */
+
+/* Status Register */
+#define SR_RX_EN 0x00000001 /* Enable Receive */
+#define SR_TX_EN 0x00000002 /* Enable Transmit */
+
+/* Transmit Status Vector 0 Register */
+#define TSV0_CRC_ERR 0x00000001 /* CRC error */
+#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
+#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
+#define TSV0_DONE 0x00000008 /* Tramsmission Completed */
+#define TSV0_MCAST 0x00000010 /* Multicast Destination */
+#define TSV0_BCAST 0x00000020 /* Broadcast Destination */
+#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
+#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
+#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
+#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
+#define TSV0_GIANT 0x00000400 /* Giant Frame */
+#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
+#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
+#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
+#define TSV0_PAUSE 0x20000000 /* Pause Frame */
+#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
+#define TSV0_VLAN 0x80000000 /* VLAN Frame */
+
+/* Transmit Status Vector 1 Register */
+#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
+#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
+
+/* Receive Status Vector Register */
+#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
+#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
+#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
+#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
+#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
+#define RSV_CRC_ERR 0x00100000 /* CRC Error */
+#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
+#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
+#define RSV_REC_OK 0x00800000 /* Frame Received OK */
+#define RSV_MCAST 0x01000000 /* Multicast Frame */
+#define RSV_BCAST 0x02000000 /* Broadcast Frame */
+#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
+#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
+#define RSV_PAUSE 0x10000000 /* Pause Frame */
+#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
+#define RSV_VLAN 0x40000000 /* VLAN Frame */
+
+/* Flow Control Counter Register */
+#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
+#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
+
+/* Flow Control Status Register */
+#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
+
+/* Receive Filter Control Register */
+#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
+#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
+#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
+#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
+#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
+#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
+#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
+#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
+
+/* Receive Filter WoL Status/Clear Registers */
+#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
+#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
+#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
+#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
+#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
+#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
+#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
+#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
+
+/* Interrupt Status/Enable/Clear/Set Registers */
+#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
+#define INT_RX_ERR 0x00000002 /* Receive Error */
+#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
+#define INT_RX_DONE 0x00000008 /* Receive Done */
+#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
+#define INT_TX_ERR 0x00000020 /* Transmit Error */
+#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
+#define INT_TX_DONE 0x00000080 /* Transmit Done */
+#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
+#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
+
+/* Power Down Register */
+#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
+
+/* RX Descriptor Control Word */
+#define RCTRL_SIZE 0x000007FF /* Buffer size mask */
+#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
+
+/* RX Status Hash CRC Word */
+#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
+#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
+
+/* RX Status Information Word */
+#define RINFO_SIZE 0x000007FF /* Data size in bytes */
+#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
+#define RINFO_VLAN 0x00080000 /* VLAN Frame */
+#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
+#define RINFO_MCAST 0x00200000 /* Multicast Frame */
+#define RINFO_BCAST 0x00400000 /* Broadcast Frame */
+#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
+#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
+#define RINFO_LEN_ERR 0x02000000 /* Length Error */
+#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
+#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
+#define RINFO_OVERRUN 0x10000000 /* Receive overrun */
+#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
+#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
+#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
+
+//#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
+ RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+
+
+/* TX Descriptor Control Word */
+#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
+#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
+#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
+#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
+#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
+#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
+#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
+
+/* TX Status Information Word */
+#define TINFO_COL_CNT 0x01E00000 /* Collision Count */
+#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
+#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
+#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
+#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
+#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
+#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
+#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
+
+/* ENET Device Revision ID */
+#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
+
+/* DP83848C PHY Registers */
+#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
+#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
+#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
+#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
+#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
+#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
+#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
+#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
+
+/* PHY Extended Registers */
+#define PHY_REG_STS 0x10 /* Status Register */
+#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
+#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
+#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
+#define PHY_REG_RECR 0x15 /* Receive Error Counter */
+#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
+#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
+#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
+#define PHY_REG_PHYCR 0x19 /* PHY Control Register */
+#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
+#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
+#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
+
+#define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
+
+#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
+#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
+#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
+#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
+#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
+
+#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
+#define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */
+
+#define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */
+
+#define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */
+#define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */
+#define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */
+
+#define PHY_BMCR_RESET 0x8000 /* PHY Reset */
+
+#define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */
+
+#define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */
+#define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */
+
+
+static int phy_read(unsigned int PhyReg);
+static int phy_write(unsigned int PhyReg, unsigned short Data);
+
+static void txdscr_init(void);
+static void rxdscr_init(void);
+
+#if defined (__ICCARM__)
+# define AHBSRAM1
+#elif defined(TOOLCHAIN_GCC_CR)
+# define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
+#else
+# define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned))
+#endif
+
+AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
+AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
+AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
+AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
+AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
+AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
+
+
+#if NEW_LOGIC
+static int rx_consume_offset = -1;
+static int tx_produce_offset = -1;
+#else
+static int send_doff = 0;
+static int send_idx = -1;
+static int send_size = 0;
+
+static int receive_soff = 0;
+static int receive_idx = -1;
+#endif
+
+static uint32_t phy_id = 0;
+
+static inline int rinc(int idx, int mod) {
+ ++idx;
+ idx %= mod;
+ return idx;
+}
+
+//extern unsigned int SystemFrequency;
+static inline unsigned int clockselect() {
+ if(SystemCoreClock < 10000000) {
+ return 1;
+ } else if(SystemCoreClock < 15000000) {
+ return 2;
+ } else if(SystemCoreClock < 20000000) {
+ return 3;
+ } else if(SystemCoreClock < 25000000) {
+ return 4;
+ } else if(SystemCoreClock < 35000000) {
+ return 5;
+ } else if(SystemCoreClock < 50000000) {
+ return 6;
+ } else if(SystemCoreClock < 70000000) {
+ return 7;
+ } else if(SystemCoreClock < 80000000) {
+ return 8;
+ } else if(SystemCoreClock < 90000000) {
+ return 9;
+ } else if(SystemCoreClock < 100000000) {
+ return 10;
+ } else if(SystemCoreClock < 120000000) {
+ return 11;
+ } else if(SystemCoreClock < 130000000) {
+ return 12;
+ } else if(SystemCoreClock < 140000000) {
+ return 13;
+ } else if(SystemCoreClock < 150000000) {
+ return 15;
+ } else if(SystemCoreClock < 160000000) {
+ return 16;
+ } else {
+ return 0;
+ }
+}
+
+#ifndef min
+#define min(x, y) (((x)<(y))?(x):(y))
+#endif
+
+/*----------------------------------------------------------------------------
+ Ethernet Device initialize
+ *----------------------------------------------------------------------------*/
+int ethernet_init() {
+ int regv, tout;
+ char mac[ETHERNET_ADDR_SIZE];
+ unsigned int clock = clockselect();
+
+ LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */
+
+ LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */
+ LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */
+ LPC_IOCON->P1_1 &= ~0x07;
+ LPC_IOCON->P1_1 |= 0x01; /* ENET_TXD1 */
+ LPC_IOCON->P1_4 &= ~0x07;
+ LPC_IOCON->P1_4 |= 0x01; /* ENET_TXEN */
+ LPC_IOCON->P1_8 &= ~0x07;
+ LPC_IOCON->P1_8 |= 0x01; /* ENET_CRS */
+ LPC_IOCON->P1_9 &= ~0x07;
+ LPC_IOCON->P1_9 |= 0x01; /* ENET_RXD0 */
+ LPC_IOCON->P1_10 &= ~0x07;
+ LPC_IOCON->P1_10 |= 0x01; /* ENET_RXD1 */
+ LPC_IOCON->P1_14 &= ~0x07;
+ LPC_IOCON->P1_14 |= 0x01; /* ENET_RX_ER */
+ LPC_IOCON->P1_15 &= ~0x07;
+ LPC_IOCON->P1_15 |= 0x01; /* ENET_REF_CLK */
+ LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */
+ LPC_IOCON->P1_16 |= 0x01; /* ENET_MDC */
+ LPC_IOCON->P1_17 &= ~0x07;
+ LPC_IOCON->P1_17 |= 0x01; /* ENET_MDIO */
+
+ /* Reset all EMAC internal modules. */
+ LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
+ MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
+ LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
+
+ for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */
+
+ LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */
+ LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
+ LPC_EMAC->MAXF = ETH_MAX_FLEN;
+ LPC_EMAC->CLRT = CLRT_DEF;
+ LPC_EMAC->IPGR = IPGR_DEF;
+
+ LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */
+
+ LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */
+ LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */
+
+ for(tout = 100; tout; tout--) __NOP(); /* A short delay */
+
+ LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
+ LPC_EMAC->MCMD = 0;
+
+ LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */
+
+ for (tout = 100; tout; tout--) __NOP(); /* A short delay */
+
+ LPC_EMAC->SUPP = 0;
+
+ phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */
+ for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */
+ regv = phy_read(PHY_REG_BMCR);
+ if(regv < 0 || tout == 0) {
+ return -1; /* Error */
+ }
+ if(!(regv & PHY_BMCR_RESET)) {
+ break; /* Reset complete. */
+ }
+ }
+
+ phy_id = (phy_read(PHY_REG_IDR1) << 16);
+ phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
+
+ if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
+ error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
+ }
+
+ ethernet_set_link(-1, 0);
+
+ /* Set the Ethernet MAC Address registers */
+ ethernet_address(mac);
+ LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
+ LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
+ LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
+
+ txdscr_init(); /* initialize DMA TX Descriptor */
+ rxdscr_init(); /* initialize DMA RX Descriptor */
+
+ LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
+ /* Receive Broadcast, Perfect Match Packets */
+
+ LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */
+ LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */
+
+ LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */
+ LPC_EMAC->MAC1 |= MAC1_REC_EN;
+
+#if NEW_LOGIC
+ rx_consume_offset = -1;
+ tx_produce_offset = -1;
+#else
+ send_doff = 0;
+ send_idx = -1;
+ send_size = 0;
+
+ receive_soff = 0;
+ receive_idx = -1;
+#endif
+
+ return 0;
+}
+
+/*----------------------------------------------------------------------------
+ Ethernet Device Uninitialize
+ *----------------------------------------------------------------------------*/
+void ethernet_free() {
+ LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
+ LPC_EMAC->IntClear = 0xFFFF;
+
+ LPC_SC->PCONP &= ~0x40000000; /* Power down the EMAC controller. */
+
+ LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */
+ LPC_IOCON->P1_1 &= ~0x07;
+ LPC_IOCON->P1_4 &= ~0x07;
+ LPC_IOCON->P1_8 &= ~0x07;
+ LPC_IOCON->P1_9 &= ~0x07;
+ LPC_IOCON->P1_10 &= ~0x07;
+ LPC_IOCON->P1_14 &= ~0x07;
+ LPC_IOCON->P1_15 &= ~0x07;
+ LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */
+ LPC_IOCON->P1_17 &= ~0x07;
+}
+
+// if(TxProduceIndex == TxConsumeIndex) buffer array is empty
+// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
+// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
+// TxConsumeIndex - The buffer that will/is beign sent by hardware
+
+int ethernet_write(const char *data, int slen) {
+
+#if NEW_LOGIC
+
+ if(tx_produce_offset < 0) { // mark as active if not already
+ tx_produce_offset = 0;
+ }
+
+ int index = LPC_EMAC->TxProduceIndex;
+
+ int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
+ int requested = slen;
+ int ncopy = min(remaining, requested);
+
+ void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
+ void *psrc = (void *)(data);
+
+ if(ncopy > 0 ){
+ if(data != NULL) {
+ memcpy(pdst, psrc, ncopy);
+ } else {
+ memset(pdst, 0, ncopy);
+ }
+ }
+
+ tx_produce_offset += ncopy;
+
+ return ncopy;
+
+#else
+ void *pdst, *psrc;
+ const int dlen = ETH_FRAG_SIZE;
+ int copy = 0;
+ int soff = 0;
+
+ if(send_idx == -1) {
+ send_idx = LPC_EMAC->TxProduceIndex;
+ }
+
+ if(slen + send_doff > ethernet_MTU_SIZE) {
+ return -1;
+ }
+
+ do {
+ copy = min(slen - soff, dlen - send_doff);
+ pdst = (void *)(txdesc[send_idx].Packet + send_doff);
+ psrc = (void *)(data + soff);
+ if(send_doff + copy > ETH_FRAG_SIZE) {
+ txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
+ send_idx = rinc(send_idx, NUM_TX_FRAG);
+ send_doff = 0;
+ }
+
+ if(data != NULL) {
+ memcpy(pdst, psrc, copy);
+ } else {
+ memset(pdst, 0, copy);
+ }
+
+ soff += copy;
+ send_doff += copy;
+ send_size += copy;
+ } while(soff != slen);
+
+ return soff;
+#endif
+}
+
+int ethernet_send() {
+
+#if NEW_LOGIC
+ if(tx_produce_offset < 0) { // no buffer active
+ return -1;
+ }
+
+ // ensure there is a link
+ if(!ethernet_link()) {
+ return -2;
+ }
+
+ // we have been writing in to a buffer, so finalise it
+ int size = tx_produce_offset;
+ int index = LPC_EMAC->TxProduceIndex;
+ txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
+
+ // Increment ProduceIndex to allow it to be sent
+ // We can only do this if the next slot is free
+ int next = rinc(index, NUM_TX_FRAG);
+ while(next == LPC_EMAC->TxConsumeIndex) {
+ for(int i=0; i<1000; i++) { __NOP(); }
+ }
+
+ LPC_EMAC->TxProduceIndex = next;
+ tx_produce_offset = -1;
+ return size;
+
+#else
+ int s = send_size;
+ txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
+ send_idx = rinc(send_idx, NUM_TX_FRAG);
+ LPC_EMAC->TxProduceIndex = send_idx;
+ send_doff = 0;
+ send_idx = -1;
+ send_size = 0;
+ return s;
+#endif
+}
+
+// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
+// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
+//
+// if(RxConsumeIndex == RxProduceIndex) buffer array is empty
+// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
+
+// Recevies an arrived ethernet packet.
+// Receiving an ethernet packet will drop the last received ethernet packet
+// and make a new ethernet packet ready to read.
+// Returns size of packet, else 0 if nothing to receive
+
+// We read from RxConsumeIndex from position rx_consume_offset
+// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
+// rx_consume_offset = -1 // no frame
+// rx_consume_offset = 0 // start of frame
+// Assumption: A fragment should alway be a whole frame
+
+int ethernet_receive() {
+#if NEW_LOGIC
+
+ // if we are currently reading a valid RxConsume buffer, increment to the next one
+ if(rx_consume_offset >= 0) {
+ LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
+ }
+
+ // if the buffer is empty, mark it as no valid buffer
+ if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
+ rx_consume_offset = -1;
+ return 0;
+ }
+
+ uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
+ rx_consume_offset = 0;
+
+ // check if it is not marked as last or for errors
+ if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
+ return -1;
+ }
+
+ int size = (info & RINFO_SIZE) + 1;
+ return size - 4; // don't include checksum bytes
+
+#else
+ if(receive_idx == -1) {
+ receive_idx = LPC_EMAC->RxConsumeIndex;
+ } else {
+ while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && (receive_idx != LPC_EMAC->RxProduceIndex)) {
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ }
+ unsigned int info = rxstat[receive_idx].Info;
+ int slen = (info & RINFO_SIZE) + 1;
+
+ if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
+ /* Invalid frame, ignore it and free buffer. */
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ }
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ receive_soff = 0;
+
+ LPC_EMAC->RxConsumeIndex = receive_idx;
+ }
+
+ if(receive_idx == LPC_EMAC->RxProduceIndex) {
+ receive_idx = -1;
+ return 0;
+ }
+
+ return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
+#endif
+}
+
+// Read from an recevied ethernet packet.
+// After receive returnd a number bigger than 0 it is
+// possible to read bytes from this packet.
+// Read will write up to size bytes into data.
+// It is possible to use read multible times.
+// Each time read will start reading after the last read byte before.
+
+int ethernet_read(char *data, int dlen) {
+#if NEW_LOGIC
+ // Check we have a valid buffer to read
+ if(rx_consume_offset < 0) {
+ return 0;
+ }
+
+ // Assume 1 fragment block
+ uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
+ int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
+
+ int remaining = size - rx_consume_offset;
+ int requested = dlen;
+ int ncopy = min(remaining, requested);
+
+ void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
+ void *pdst = (void *)(data);
+
+ if(data != NULL && ncopy > 0) {
+ memcpy(pdst, psrc, ncopy);
+ }
+
+ rx_consume_offset += ncopy;
+
+ return ncopy;
+#else
+ int slen;
+ int copy = 0;
+ unsigned int more;
+ unsigned int info;
+ void *pdst, *psrc;
+ int doff = 0;
+
+ if(receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
+ return 0;
+ }
+
+ do {
+ info = rxstat[receive_idx].Info;
+ more = !(info & RINFO_LAST_FLAG);
+ slen = (info & RINFO_SIZE) + 1;
+
+ if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
+ /* Invalid frame, ignore it and free buffer. */
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ } else {
+
+ copy = min(slen - receive_soff, dlen - doff);
+ psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
+ pdst = (void *)(data + doff);
+
+ if(data != NULL) {
+ /* check if Buffer available */
+ memcpy(pdst, psrc, copy);
+ }
+
+ receive_soff += copy;
+ doff += copy;
+
+ if((more && (receive_soff == slen))) {
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ receive_soff = 0;
+ }
+ }
+ } while(more && !(doff == dlen) && !receive_soff);
+
+ return doff;
+#endif
+}
+
+int ethernet_link(void) {
+
+ if (phy_id == DP83848C_ID) {
+ return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
+ }
+ else { // LAN8720_ID
+ return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
+ }
+}
+
+static int phy_write(unsigned int PhyReg, unsigned short Data) {
+ unsigned int timeOut;
+
+ LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+ LPC_EMAC->MWTD = Data;
+
+ for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) { /* Wait until operation completed */
+ if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+
+static int phy_read(unsigned int PhyReg) {
+ unsigned int timeOut;
+
+ LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+ LPC_EMAC->MCMD = MCMD_READ;
+
+ for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */
+ if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+ LPC_EMAC->MCMD = 0;
+ return LPC_EMAC->MRDD; /* Return a 16-bit value. */
+ }
+ }
+
+ return -1;
+}
+
+
+static void txdscr_init() {
+ int i;
+
+ for(i = 0; i < NUM_TX_FRAG; i++) {
+ txdesc[i].Packet = (uint32_t)&txbuf[i];
+ txdesc[i].Ctrl = 0;
+ txstat[i].Info = 0;
+ }
+
+ LPC_EMAC->TxDescriptor = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */
+ LPC_EMAC->TxStatus = (uint32_t)txstat;
+ LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
+
+ LPC_EMAC->TxProduceIndex = 0; /* Tx Descriptors Point to 0 */
+}
+
+
+static void rxdscr_init() {
+ int i;
+
+ for(i = 0; i < NUM_RX_FRAG; i++) {
+ rxdesc[i].Packet = (uint32_t)&rxbuf[i];
+ rxdesc[i].Ctrl = RCTRL_INT | (ETH_FRAG_SIZE-1);
+ rxstat[i].Info = 0;
+ rxstat[i].HashCRC = 0;
+ }
+
+ LPC_EMAC->RxDescriptor = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */
+ LPC_EMAC->RxStatus = (uint32_t)rxstat;
+ LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
+
+ LPC_EMAC->RxConsumeIndex = 0; /* Rx Descriptors Point to 0 */
+}
+
+void ethernet_address(char *mac) {
+ mbed_mac_address(mac);
+}
+
+void ethernet_set_link(int speed, int duplex) {
+ unsigned short phy_data;
+ int tout;
+
+ if((speed < 0) || (speed > 1)) {
+ phy_data = PHY_AUTO_NEG;
+ } else {
+ phy_data = (((unsigned short) speed << 13) |
+ ((unsigned short) duplex << 8));
+ }
+
+ phy_write(PHY_REG_BMCR, phy_data);
+
+ for (tout = 100; tout; tout--) { __NOP(); } /* A short delay */
+
+ switch(phy_id) {
+ case DP83848C_ID:
+ phy_data = phy_read(PHY_REG_STS);
+
+ if(phy_data & PHY_STS_DUPLEX) {
+ LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
+ LPC_EMAC->Command |= CR_FULL_DUP;
+ LPC_EMAC->IPGT = IPGT_FULL_DUP;
+ } else {
+ LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
+ LPC_EMAC->Command &= ~CR_FULL_DUP;
+ LPC_EMAC->IPGT = IPGT_HALF_DUP;
+ }
+
+ if(phy_data & PHY_STS_SPEED) {
+ LPC_EMAC->SUPP &= ~SUPP_SPEED;
+ } else {
+ LPC_EMAC->SUPP |= SUPP_SPEED;
+ }
+ break;
+
+ case LAN8720_ID:
+ phy_data = phy_read(PHY_REG_SCSR);
+
+ if (phy_data & PHY_SCSR_DUPLEX) {
+ LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
+ LPC_EMAC->Command |= CR_FULL_DUP;
+ LPC_EMAC->IPGT = IPGT_FULL_DUP;
+ } else {
+ LPC_EMAC->Command &= ~CR_FULL_DUP;
+ LPC_EMAC->IPGT = IPGT_HALF_DUP;
+ }
+
+ if(phy_data & PHY_SCSR_100MBIT) {
+ LPC_EMAC->SUPP |= SUPP_SPEED;
+ } else {
+ LPC_EMAC->SUPP &= ~SUPP_SPEED;
+ }
+
+ break;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+
+uint32_t gpio_set(PinName pin) {
+ pin_function(pin, 0);
+ return (1 << ((int)pin & 0x1F));
+}
+
+void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
+ if (pin == NC) return;
+
+ obj->pin = pin;
+ obj->mask = gpio_set(pin);
+
+ LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *) ((int)(LPC_GPIO0_BASE+pin) & ~0x1F);
+
+ obj->reg_set = &port_reg->SET;
+ obj->reg_clr = &port_reg->CLR;
+ obj->reg_in = &port_reg->PIN;
+ obj->reg_dir = &port_reg->DIR;
+
+ gpio_dir(obj, direction);
+ switch (direction) {
+ case PIN_OUTPUT: pin_mode(pin, PullNone); break;
+ case PIN_INPUT : pin_mode(pin, PullDown); break;
+ }
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+ pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+ switch (direction) {
+ case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+ case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_irq_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,144 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "gpio_irq_api.h"
+#include "error.h"
+#include "cmsis.h"
+
+#define CHANNEL_NUM 64
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+
+static void handle_interrupt_in(void) {
+ // Read in all current interrupt registers. We do this once as the
+ // GPIO interrupt registers are on the APB bus, and this is slow.
+ uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
+ uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
+ uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
+ uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
+ uint32_t mask0 = 0;
+ uint32_t mask2 = 0;
+ int i;
+
+ // P0.0-0.31
+ for (i = 0; i < 32; i++) {
+ uint32_t pmask = (1 << i);
+ if (rise0 & pmask) {
+ mask0 |= pmask;
+ if (channel_ids[i] != 0)
+ irq_handler(channel_ids[i], IRQ_RISE);
+ }
+ if (fall0 & pmask) {
+ mask0 |= pmask;
+ if (channel_ids[i] != 0)
+ irq_handler(channel_ids[i], IRQ_FALL);
+ }
+ }
+
+ // P2.0-2.31
+ for (i = 0; i < 32; i++) {
+ uint32_t pmask = (1 << i);
+ int channel_index = i + 32;
+ if (rise2 & pmask) {
+ mask2 |= pmask;
+ if (channel_ids[channel_index] != 0)
+ irq_handler(channel_ids[channel_index], IRQ_RISE);
+ }
+ if (fall2 & pmask) {
+ mask2 |= pmask;
+ if (channel_ids[channel_index] != 0)
+ irq_handler(channel_ids[channel_index], IRQ_FALL);
+ }
+ }
+
+ // Clear the interrupts we just handled
+ LPC_GPIOINT->IO0IntClr = mask0;
+ LPC_GPIOINT->IO2IntClr = mask2;
+}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+ if (pin == NC) return -1;
+
+ irq_handler = handler;
+
+ obj->port = ((int)(LPC_GPIO0_BASE+pin) & ~0x1F);
+ obj->pin = (int)pin % 32;
+
+ // Interrupts available only on GPIO0 and GPIO2
+ if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
+ error("pins on this port cannot generate interrupts\n");
+ }
+
+ // put us in the interrupt table
+ int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
+ channel_ids[index] = id;
+ obj->ch = index;
+
+ NVIC_SetVector(GPIO_IRQn, (uint32_t)handle_interrupt_in);
+ NVIC_EnableIRQ(GPIO_IRQn);
+
+ return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+ channel_ids[obj->ch] = 0;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+ // ensure nothing is pending
+ switch (obj->port) {
+ case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
+ case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
+ }
+
+ // enable the pin interrupt
+ if (event == IRQ_RISE) {
+ switch (obj->port) {
+ case LPC_GPIO0_BASE:
+ if (enable) {
+ LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
+ } else {
+ LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
+ }
+ break;
+ case LPC_GPIO2_BASE:
+ if (enable) {
+ LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
+ } else {
+ LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
+ }
+ break;
+ }
+ } else {
+ switch (obj->port) {
+ case LPC_GPIO0_BASE:
+ if (enable) {
+ LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
+ } else {
+ LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
+ }
+ break;
+ case LPC_GPIO2_BASE:
+ if (enable) {
+ LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
+ } else {
+ LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
+ }
+ break;
+ }
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_object.h Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value)
+ *obj->reg_set = obj->mask;
+ else
+ *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/i2c_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,409 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_I2C_SDA[] = {
+ {P0_0 , I2C_1, 3},
+ {P0_10, I2C_2, 2},
+ {P0_19, I2C_1, 3},
+ {P0_27, I2C_0, 1},
+ {P1_15, I2C_2, 3},
+ {P1_30, I2C_0, 4},
+ {P2_14, I2C_1, 2},
+ {P2_30, I2C_2, 2},
+ {P4_20, I2C_2, 4},
+ {P5_2, I2C_0, 5},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+ {P0_1 , I2C_1, 3},
+ {P0_11, I2C_2, 2},
+ {P0_20, I2C_1, 3},
+ {P0_28, I2C_0, 1},
+ {P1_31, I2C_0, 4},
+ {P2_15, I2C_1, 2},
+ {P2_31, I2C_2, 2},
+ {P4_21, I2C_2, 2},
+ {P4_29, I2C_2, 4},
+ {P5_3, I2C_0, 5},
+ {NC , NC, 0}
+};
+
+#define I2C_CONSET(x) (x->i2c->CONSET)
+#define I2C_CONCLR(x) (x->i2c->CONCLR)
+#define I2C_STAT(x) (x->i2c->STAT)
+#define I2C_DAT(x) (x->i2c->DAT)
+#define I2C_SCLL(x, val) (x->i2c->SCLL = val)
+#define I2C_SCLH(x, val) (x->i2c->SCLH = val)
+
+static const uint32_t I2C_addr_offset[2][4] = {
+ {0x0C, 0x20, 0x24, 0x28},
+ {0x30, 0x34, 0x38, 0x3C}
+};
+
+static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+ I2C_CONCLR(obj) = (start << 5)
+ | (stop << 4)
+ | (interrupt << 3)
+ | (acknowledge << 2);
+}
+
+static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+ I2C_CONSET(obj) = (start << 5)
+ | (stop << 4)
+ | (interrupt << 3)
+ | (acknowledge << 2);
+}
+
+// Clear the Serial Interrupt (SI)
+static inline void i2c_clear_SI(i2c_t *obj) {
+ i2c_conclr(obj, 0, 0, 1, 0);
+}
+
+static inline int i2c_status(i2c_t *obj) {
+ return I2C_STAT(obj);
+}
+
+// Wait until the Serial Interrupt (SI) is set
+static int i2c_wait_SI(i2c_t *obj) {
+ int timeout = 0;
+ while (!(I2C_CONSET(obj) & (1 << 3))) {
+ timeout++;
+ if (timeout > 100000) return -1;
+ }
+ return 0;
+}
+
+static inline void i2c_interface_enable(i2c_t *obj) {
+ I2C_CONSET(obj) = 0x40;
+}
+
+static inline void i2c_power_enable(i2c_t *obj) {
+ switch ((int)obj->i2c) {
+ case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
+ case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
+ case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
+ }
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+ // determine the SPI to use
+ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+ obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
+ if ((int)obj->i2c == NC) {
+ error("I2C pin mapping failed");
+ }
+
+ // enable power
+ i2c_power_enable(obj);
+
+ // set default frequency at 100k
+ i2c_frequency(obj, 100000);
+ i2c_conclr(obj, 1, 1, 1, 1);
+ i2c_interface_enable(obj);
+
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+}
+
+inline int i2c_start(i2c_t *obj) {
+ int status = 0;
+ // 8.1 Before master mode can be entered, I2CON must be initialised to:
+ // - I2EN STA STO SI AA - -
+ // - 1 0 0 0 x - -
+ // if AA = 0, it can't enter slave mode
+ i2c_conclr(obj, 1, 1, 1, 1);
+
+ // The master mode may now be entered by setting the STA bit
+ // this will generate a start condition when the bus becomes free
+ i2c_conset(obj, 1, 0, 0, 1);
+
+ i2c_wait_SI(obj);
+ status = i2c_status(obj);
+
+ // Clear start bit now transmitted, and interrupt bit
+ i2c_conclr(obj, 1, 0, 0, 0);
+ return status;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+ int timeout = 0;
+
+ // write the stop bit
+ i2c_conset(obj, 0, 1, 0, 0);
+ i2c_clear_SI(obj);
+
+ // wait for STO bit to reset
+ while(I2C_CONSET(obj) & (1 << 4)) {
+ timeout ++;
+ if (timeout > 100000) return 1;
+ }
+
+ return 0;
+}
+
+
+static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
+ // write the data
+ I2C_DAT(obj) = value;
+
+ // clear SI to init a send
+ i2c_clear_SI(obj);
+
+ // wait and return status
+ i2c_wait_SI(obj);
+ return i2c_status(obj);
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+ // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
+ if(last) {
+ i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
+ } else {
+ i2c_conset(obj, 0, 0, 0, 1); // send a ACK
+ }
+
+ // accept byte
+ i2c_clear_SI(obj);
+
+ // wait for it to arrive
+ i2c_wait_SI(obj);
+
+ // return the data
+ return (I2C_DAT(obj) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+ uint32_t PCLK = PeripheralClock;
+ uint32_t pulse = PCLK / (hz * 2);
+
+ // I2C Rate
+ I2C_SCLL(obj, pulse);
+ I2C_SCLH(obj, pulse);
+}
+
+// The I2C does a read or a write as a whole operation
+// There are two types of error conditions it can encounter
+// 1) it can not obtain the bus
+// 2) it gets error responses at part of the transmission
+//
+// We tackle them as follows:
+// 1) we retry until we get the bus. we could have a "timeout" if we can not get it
+// which basically turns it in to a 2)
+// 2) on error, we use the standard error mechanisms to report/debug
+//
+// Therefore an I2C transaction should always complete. If it doesn't it is usually
+// because something is setup wrong (e.g. wiring), and we don't need to programatically
+// check for that
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+ int count, status;
+
+ status = i2c_start(obj);
+
+ if ((status != 0x10) && (status != 0x08)) {
+ i2c_stop(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+
+ status = i2c_do_write(obj, (address | 0x01), 1);
+ if (status != 0x40) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ // Read in all except last byte
+ for (count = 0; count < (length - 1); count++) {
+ int value = i2c_do_read(obj, 0);
+ status = i2c_status(obj);
+ if (status != 0x50) {
+ i2c_stop(obj);
+ return count;
+ }
+ data[count] = (char) value;
+ }
+
+ // read in last byte
+ int value = i2c_do_read(obj, 1);
+ status = i2c_status(obj);
+ if (status != 0x58) {
+ i2c_stop(obj);
+ return length - 1;
+ }
+
+ data[count] = (char) value;
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ }
+
+ return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+ int i, status;
+
+ status = i2c_start(obj);
+
+ if ((status != 0x10) && (status != 0x08)) {
+ i2c_stop(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+
+ status = i2c_do_write(obj, (address & 0xFE), 1);
+ if (status != 0x18) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ for (i=0; i<length; i++) {
+ status = i2c_do_write(obj, data[i], 0);
+ if (status != 0x28) {
+ i2c_stop(obj);
+ return i;
+ }
+ }
+
+ // clearing the serial interrupt here might cause an unintended rewrite of the last byte
+ // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
+ // i2c_clear_SI(obj);
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ }
+
+ return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+ i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+ return (i2c_do_read(obj, last) & 0xFF);
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+ int ack;
+ int status = i2c_do_write(obj, (data & 0xFF), 0);
+
+ switch(status) {
+ case 0x18: case 0x28: // Master transmit ACKs
+ ack = 1;
+ break;
+
+ case 0x40: // Master receive address transmitted ACK
+ ack = 1;
+ break;
+
+ case 0xB8: // Slave transmit ACK
+ ack = 1;
+ break;
+
+ default:
+ ack = 0;
+ break;
+ }
+
+ return ack;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+ if (enable_slave != 0) {
+ i2c_conclr(obj, 1, 1, 1, 0);
+ i2c_conset(obj, 0, 0, 0, 1);
+ } else {
+ i2c_conclr(obj, 1, 1, 1, 1);
+ }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+ int status;
+ int retval;
+
+ status = i2c_status(obj);
+ switch(status) {
+ case 0x60: retval = 3; break;
+ case 0x70: retval = 2; break;
+ case 0xA8: retval = 1; break;
+ default : retval = 0; break;
+ }
+
+ return(retval);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+ int count = 0;
+ int status;
+
+ do {
+ i2c_clear_SI(obj);
+ i2c_wait_SI(obj);
+ status = i2c_status(obj);
+ if((status == 0x80) || (status == 0x90)) {
+ data[count] = I2C_DAT(obj) & 0xFF;
+ }
+ count++;
+ } while (((status == 0x80) || (status == 0x90) ||
+ (status == 0x060) || (status == 0x70)) && (count < length));
+
+ if(status != 0xA0) {
+ i2c_stop(obj);
+ }
+
+ i2c_clear_SI(obj);
+
+ return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+ int count = 0;
+ int status;
+
+ if(length <= 0) {
+ return(0);
+ }
+
+ do {
+ status = i2c_do_write(obj, data[count], 0);
+ count++;
+ } while ((count < length) && (status == 0xB8));
+
+ if((status != 0xC0) && (status != 0xC8)) {
+ i2c_stop(obj);
+ }
+
+ i2c_clear_SI(obj);
+
+ return(count);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+ uint32_t addr;
+
+ if ((idx >= 0) && (idx <= 3)) {
+ addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
+ *((uint32_t *) addr) = address & 0xFF;
+ addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
+ *((uint32_t *) addr) = mask & 0xFE;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/objects.h Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t port;
+ uint32_t pin;
+ uint32_t ch;
+};
+
+struct port_s {
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_out;
+ __I uint32_t *reg_in;
+ PortName port;
+ uint32_t mask;
+};
+
+struct pwmout_s {
+ __IO uint32_t *MR;
+ LPC_PWM_TypeDef *pwm;
+ uint32_t channel;
+};
+
+struct serial_s {
+ LPC_UART_TypeDef *uart;
+ int index;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct dac_s {
+ DACName dac;
+};
+
+struct can_s {
+ LPC_CAN_TypeDef *dev;
+};
+
+struct i2c_s {
+ LPC_I2C_TypeDef *i2c;
+};
+
+struct spi_s {
+ LPC_SSP_TypeDef *spi;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/pinmap.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "error.h"
+
+void pin_function(PinName pin, int function) {
+ if (pin == (uint32_t)NC) return;
+
+ __IO uint32_t *reg = (__IO uint32_t*) (LPC_IOCON_BASE + 4 * pin);
+
+ // pin function bits: [2:0] -> 111 = (0x7)
+ *reg = (*reg & ~0x7) | (function & 0x7);
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+ if (pin == (uint32_t)NC) { return; }
+
+ uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2;
+
+ __IO uint32_t *reg = (__IO uint32_t*) (LPC_IOCON_BASE + 4 * pin);
+ uint32_t tmp = *reg;
+
+ // pin mode bits: [4:3] -> 11000 = (0x3 << 3)
+ tmp &= ~(0x3 << 3);
+ tmp |= (mode & 0x3) << 3;
+
+ // drain
+ tmp &= ~(0x1 << 10);
+ tmp |= drain << 10;
+
+ *reg = tmp;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/port_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,70 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+
+PinName port_pin(PortName port, int pin_n) {
+ return (PinName)(LPC_GPIO0_BASE + ((port << PORT_SHIFT) | pin_n));
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+ obj->port = port;
+ obj->mask = mask;
+
+ LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *)(LPC_GPIO0_BASE + ((int)port * 0x20));
+
+ port_reg->MASK = ~mask;
+
+ obj->reg_out = &port_reg->PIN;
+ obj->reg_in = &port_reg->PIN;
+ obj->reg_dir = &port_reg->DIR;
+
+ uint32_t i;
+ // The function is set per pin: reuse gpio logic
+ for (i=0; i<32; i++) {
+ if (obj->mask & (1<<i)) {
+ gpio_set(port_pin(obj->port, i));
+ }
+ }
+
+ port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode) {
+ uint32_t i;
+ // The mode is set per pin: reuse pinmap logic
+ for (i=0; i<32; i++) {
+ if (obj->mask & (1<<i)) {
+ pin_mode(port_pin(obj->port, i), mode);
+ }
+ }
+}
+
+void port_dir(port_t *obj, PinDirection dir) {
+ switch (dir) {
+ case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+ case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
+ }
+}
+
+void port_write(port_t *obj, int value) {
+ *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
+}
+
+int port_read(port_t *obj) {
+ return (*obj->reg_in & obj->mask);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/pwmout_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,190 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#define TCR_CNT_EN 0x00000001
+#define TCR_RESET 0x00000002
+
+// PORT ID, PWM ID, Pin function
+static const PinMap PinMap_PWM[] = {
+ {P1_2, PWM0_1, 3},
+ {P1_3, PWM0_2, 3},
+ {P1_5, PWM0_3, 3},
+ {P1_6, PWM0_4, 3},
+ {P1_7, PWM0_5, 3},
+ {P1_11, PWM0_6, 3},
+ {P1_18, PWM1_1, 2},
+ {P1_20, PWM1_2, 2},
+ {P1_21, PWM1_3, 2},
+ {P1_23, PWM1_4, 2},
+ {P1_24, PWM1_5, 2},
+ {P1_26, PWM1_6, 2},
+ {P2_0, PWM1_1, 1},
+ {P2_1, PWM1_2, 1},
+ {P2_2, PWM1_3, 1},
+ {P2_3, PWM1_4, 1},
+ {P2_4, PWM1_5, 1},
+ {P2_5, PWM1_6, 1},
+ {P3_16, PWM0_1, 2},
+ {P3_17, PWM0_2, 2},
+ {P3_18, PWM0_3, 2},
+ {P3_19, PWM0_4, 2},
+ {P3_20, PWM0_5, 2},
+ {P3_21, PWM0_6, 2},
+ {P3_24, PWM1_1, 2},
+ {P3_25, PWM1_2, 2},
+ {P3_26, PWM1_3, 2},
+ {P3_27, PWM1_4, 2},
+ {P3_28, PWM1_5, 2},
+ {P3_29, PWM1_6, 2},
+ {NC, NC, 0}
+};
+
+static const uint32_t PWM_mr_offset[7] = {
+ 0x18, 0x1C, 0x20, 0x24, 0x40, 0x44, 0x48
+};
+
+#define TCR_PWM_EN 0x00000008
+static unsigned int pwm_clock_mhz;
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+ // determine the channel
+ PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+ if (pwm == (uint32_t)NC)
+ error("PwmOut pin mapping failed");
+
+ obj->channel = pwm;
+ obj->pwm = LPC_PWM0;
+
+ if (obj->channel > 6) { // PWM1 is used if pwm > 6
+ obj->channel -= 6;
+ obj->pwm = LPC_PWM1;
+ }
+
+ obj->MR = (__IO uint32_t *)((uint32_t)obj->pwm + PWM_mr_offset[obj->channel]);
+
+ // ensure the power is on
+ if (obj->pwm == LPC_PWM0) {
+ LPC_SC->PCONP |= 1 << 5;
+ } else {
+ LPC_SC->PCONP |= 1 << 6;
+ }
+
+ obj->pwm->PR = 0; // no pre-scale
+
+ // ensure single PWM mode
+ obj->pwm->MCR = 1 << 1; // reset TC on match 0
+
+ // enable the specific PWM output
+ obj->pwm->PCR |= 1 << (8 + obj->channel);
+
+ pwm_clock_mhz = PeripheralClock / 1000000;
+
+ // default to 20ms: standard for servos, and fine for e.g. brightness control
+ pwmout_period_ms(obj, 20);
+ pwmout_write (obj, 0);
+
+ // Wire pinout
+ pinmap_pinout(pin, PinMap_PWM);
+}
+
+void pwmout_free(pwmout_t* obj) {
+ // [TODO]
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+ if (value < 0.0f) {
+ value = 0.0;
+ } else if (value > 1.0f) {
+ value = 1.0;
+ }
+
+ // set channel match to percentage
+ uint32_t v = (uint32_t)((float)(obj->pwm->MR0) * value);
+
+ // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
+ if (v == obj->pwm->MR0) {
+ v++;
+ }
+
+ *obj->MR = v;
+
+ // accept on next period start
+ obj->pwm->LER |= 1 << obj->channel;
+}
+
+float pwmout_read(pwmout_t* obj) {
+ float v = (float)(*obj->MR) / (float)(obj->pwm->MR0);
+ return (v > 1.0f) ? (1.0f) : (v);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+ pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+ pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us) {
+ // calculate number of ticks
+ uint32_t ticks = pwm_clock_mhz * us;
+
+ // set reset
+ obj->pwm->TCR = TCR_RESET;
+
+ // set the global match register
+ obj->pwm->MR0 = ticks;
+
+ // Scale the pulse width to preserve the duty ratio
+ if (obj->pwm->MR0 > 0) {
+ *obj->MR = (*obj->MR * ticks) / obj->pwm->MR0;
+ }
+
+ // set the channel latch to update value at next period start
+ obj->pwm->LER |= 1 << 0;
+
+ // enable counter and pwm, clear reset
+ obj->pwm->TCR = TCR_CNT_EN | TCR_PWM_EN;
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+ pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+ pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+ // calculate number of ticks
+ uint32_t v = pwm_clock_mhz * us;
+
+ // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
+ if (v == obj->pwm->MR0) {
+ v++;
+ }
+
+ // set the match register value
+ *obj->MR = v;
+
+ // set the channel latch to update value at next period start
+ obj->pwm->LER |= 1 << obj->channel;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/rtc_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,114 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "rtc_api.h"
+
+// ensure rtc is running (unchanged if already running)
+
+/* Setup the RTC based on a time structure, ensuring RTC is enabled
+ *
+ * Can be clocked by a 32.768KHz oscillator or prescale divider based on the APB clock
+ * - We want to use the 32khz clock, allowing for sleep mode
+ *
+ * Most registers are not changed by a Reset
+ * - We must initialize these registers between power-on and setting the RTC into operation
+
+ * Clock Control Register
+ * RTC_CCR[0] : Enable - 0 = Disabled, 1 = Enabled
+ * RTC_CCR[1] : Reset - 0 = Normal, 1 = Reset
+ * RTC_CCR[4] : Clock Source - 0 = Prescaler, 1 = 32k Xtal
+ *
+ * The RTC may already be running, so we should set it up
+ * without impacting if it is the case
+ */
+void rtc_init(void) {
+ LPC_SC->PCONP |= 0x200; // Ensure power is on
+ LPC_RTC->CCR = 0x00;
+
+// clock source on 2368 is special test mode on 1768!
+ LPC_RTC->CCR |= 1 << 0; // Ensure the RTC is enabled
+}
+
+void rtc_free(void) {
+ // [TODO]
+}
+
+/*
+ * Little check routine to see if the RTC has been enabled
+ *
+ * Clock Control Register
+ * RTC_CCR[0] : 0 = Disabled, 1 = Enabled
+ *
+ */
+int rtc_isenabled(void) {
+ return(((LPC_RTC->CCR) & 0x01) != 0);
+}
+
+/*
+ * RTC Registers
+ * RTC_SEC Seconds 0-59
+ * RTC_MIN Minutes 0-59
+ * RTC_HOUR Hour 0-23
+ * RTC_DOM Day of Month 1-28..31
+ * RTC_DOW Day of Week 0-6
+ * RTC_DOY Day of Year 1-365
+ * RTC_MONTH Month 1-12
+ * RTC_YEAR Year 0-4095
+ *
+ * struct tm
+ * tm_sec seconds after the minute 0-61
+ * tm_min minutes after the hour 0-59
+ * tm_hour hours since midnight 0-23
+ * tm_mday day of the month 1-31
+ * tm_mon months since January 0-11
+ * tm_year years since 1900
+ * tm_wday days since Sunday 0-6
+ * tm_yday days since January 1 0-365
+ * tm_isdst Daylight Saving Time flag
+ */
+time_t rtc_read(void) {
+ // Setup a tm structure based on the RTC
+ struct tm timeinfo;
+ timeinfo.tm_sec = LPC_RTC->SEC;
+ timeinfo.tm_min = LPC_RTC->MIN;
+ timeinfo.tm_hour = LPC_RTC->HOUR;
+ timeinfo.tm_mday = LPC_RTC->DOM;
+ timeinfo.tm_mon = LPC_RTC->MONTH - 1;
+ timeinfo.tm_year = LPC_RTC->YEAR - 1900;
+
+ // Convert to timestamp
+ time_t t = mktime(&timeinfo);
+
+ return t;
+}
+
+void rtc_write(time_t t) {
+ // Convert the time in to a tm
+ struct tm *timeinfo = localtime(&t);
+
+ // Pause clock, and clear counter register (clears us count)
+ LPC_RTC->CCR |= 2;
+
+ // Set the RTC
+ LPC_RTC->SEC = timeinfo->tm_sec;
+ LPC_RTC->MIN = timeinfo->tm_min;
+ LPC_RTC->HOUR = timeinfo->tm_hour;
+ LPC_RTC->DOM = timeinfo->tm_mday;
+ LPC_RTC->MONTH = timeinfo->tm_mon + 1;
+ LPC_RTC->YEAR = timeinfo->tm_year + 1900;
+
+ // Restart clock
+ LPC_RTC->CCR &= ~((uint32_t)2);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/serial_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,311 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include <string.h>
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+static const PinMap PinMap_UART_TX[] = {
+ {P0_0, UART_3, 2},
+ {P0_2, UART_0, 1},
+ {P0_10, UART_2, 1},
+ {P0_15, UART_1, 1},
+ {P1_29, UART_4, 5},
+ {P0_25, UART_3, 3},
+ {P2_0 , UART_1, 2},
+ {P2_8 , UART_2, 2},
+ {P3_16, UART_1, 3},
+ {P4_22, UART_2, 2},
+ {P4_28, UART_3, 2},
+ {P5_4, UART_4, 4},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+ {P0_1 , UART_3, 2},
+ {P0_3 , UART_0, 1},
+ {P0_11, UART_2, 1},
+ {P0_16, UART_1, 1},
+ {P0_26, UART_3, 3},
+ {P2_1 , UART_1, 2},
+ {P2_9 , UART_2, 2},
+ {P3_17, UART_1, 3},
+ {P4_23, UART_2, 2},
+ {P4_29, UART_3, 2},
+ {P5_3, UART_4, 4},
+ {NC , NC , 0}
+};
+
+#define UART_NUM 5
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+ int is_stdio_uart = 0;
+
+ // determine the UART to use
+ UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+ UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+ UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+ if ((int)uart == NC) {
+ error("Serial pinout mapping failed");
+ }
+
+ obj->uart = (LPC_UART_TypeDef *)uart;
+ // enable power
+ switch (uart) {
+ case UART_0: LPC_SC->PCONP |= 1 << 3; break;
+ case UART_1: LPC_SC->PCONP |= 1 << 4; break;
+ case UART_2: LPC_SC->PCONP |= 1 << 24; break;
+ case UART_3: LPC_SC->PCONP |= 1 << 25; break;
+ case UART_4: LPC_SC->PCONP |= 1 << 8; break;
+ }
+
+ // enable fifos and default rx trigger level
+ obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
+ | 0 << 1 // Rx Fifo Reset
+ | 0 << 2 // Tx Fifo Reset
+ | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
+
+ // disable irqs
+ obj->uart->IER = 0 << 0 // Rx Data available irq enable
+ | 0 << 1 // Tx Fifo empty irq enable
+ | 0 << 2; // Rx Line Status irq enable
+
+ // set default baud rate and format
+ serial_baud (obj, 9600);
+ serial_format(obj, 8, ParityNone, 1);
+
+ // pinout the chosen uart
+ pinmap_pinout(tx, PinMap_UART_TX);
+ pinmap_pinout(rx, PinMap_UART_RX);
+
+ // set rx/tx pins in PullUp mode
+ pin_mode(tx, PullUp);
+ pin_mode(rx, PullUp);
+
+ switch (uart) {
+ case UART_0: obj->index = 0; break;
+ case UART_1: obj->index = 1; break;
+ case UART_2: obj->index = 2; break;
+ case UART_3: obj->index = 3; break;
+ case UART_4: obj->index = 4; break;
+ }
+
+ is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+
+ if (is_stdio_uart) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj) {
+ serial_irq_ids[obj->index] = 0;
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+ uint32_t PCLK = PeripheralClock;
+
+ // First we check to see if the basic divide with no DivAddVal/MulVal
+ // ratio gives us an integer result. If it does, we set DivAddVal = 0,
+ // MulVal = 1. Otherwise, we search the valid ratio value range to find
+ // the closest match. This could be more elegant, using search methods
+ // and/or lookup tables, but the brute force method is not that much
+ // slower, and is more maintainable.
+ uint16_t DL = PCLK / (16 * baudrate);
+
+ uint8_t DivAddVal = 0;
+ uint8_t MulVal = 1;
+ int hit = 0;
+ uint16_t dlv;
+ uint8_t mv, dav;
+ if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder
+ float err_best = (float) baudrate;
+ uint16_t dlmax = DL;
+ for ( dlv = (dlmax/2); (dlv <= dlmax) && !hit; dlv++) {
+ for ( mv = 1; mv <= 15; mv++) {
+ for ( dav = 1; dav < mv; dav++) {
+ float ratio = 1.0f + ((float) dav / (float) mv);
+ float calcbaud = (float)PCLK / (16.0f * (float) dlv * ratio);
+ float err = fabs(((float) baudrate - calcbaud) / (float) baudrate);
+ if (err < err_best) {
+ DL = dlv;
+ DivAddVal = dav;
+ MulVal = mv;
+ err_best = err;
+ if (err < 0.001f) {
+ hit = 1;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // set LCR[DLAB] to enable writing to divider registers
+ obj->uart->LCR |= (1 << 7);
+
+ // set divider values
+ obj->uart->DLM = (DL >> 8) & 0xFF;
+ obj->uart->DLL = (DL >> 0) & 0xFF;
+ obj->uart->FDR = (uint32_t) DivAddVal << 0
+ | (uint32_t) MulVal << 4;
+
+ // clear LCR[DLAB]
+ obj->uart->LCR &= ~(1 << 7);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+ // 0: 1 stop bits, 1: 2 stop bits
+ if (stop_bits != 1 && stop_bits != 2) {
+ error("Invalid stop bits specified");
+ }
+ stop_bits -= 1;
+
+ // 0: 5 data bits ... 3: 8 data bits
+ if (data_bits < 5 || data_bits > 8) {
+ error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits);
+ }
+ data_bits -= 5;
+
+ int parity_enable, parity_select;
+ switch (parity) {
+ case ParityNone: parity_enable = 0; parity_select = 0; break;
+ case ParityOdd : parity_enable = 1; parity_select = 0; break;
+ case ParityEven: parity_enable = 1; parity_select = 1; break;
+ case ParityForced1: parity_enable = 1; parity_select = 2; break;
+ case ParityForced0: parity_enable = 1; parity_select = 3; break;
+ default:
+ error("Invalid serial parity setting");
+ return;
+ }
+
+ obj->uart->LCR = data_bits << 0
+ | stop_bits << 2
+ | parity_enable << 3
+ | parity_select << 4;
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t iir, uint32_t index) {
+ // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
+ SerialIrq irq_type;
+ switch (iir) {
+ case 1: irq_type = TxIrq; break;
+ case 2: irq_type = RxIrq; break;
+ default: return;
+ }
+
+ if (serial_irq_ids[index] != 0)
+ irq_handler(serial_irq_ids[index], irq_type);
+}
+
+void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0);}
+void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1);}
+void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2);}
+void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3);}
+void uart4_irq() {uart_irq((LPC_UART4->IIR >> 1) & 0x7, 4);}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+ irq_handler = handler;
+ serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+ switch ((int)obj->uart) {
+ case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
+ case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
+ case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
+ case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break;
+ case UART_4: irq_n=UART4_IRQn; vector = (uint32_t)&uart4_irq; break;
+ }
+
+ if (enable) {
+ obj->uart->IER |= 1 << irq;
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+ } else { // disable
+ int all_disabled = 0;
+ SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+ obj->uart->IER &= ~(1 << irq);
+ all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
+ if (all_disabled)
+ NVIC_DisableIRQ(irq_n);
+ }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+ while (!serial_readable(obj));
+ return obj->uart->RBR;
+}
+
+void serial_putc(serial_t *obj, int c) {
+ while (!serial_writable(obj));
+ obj->uart->THR = c;
+
+ uint32_t lsr = obj->uart->LSR;
+ lsr = lsr;
+ uint32_t thr = obj->uart->THR;
+ thr = thr;
+}
+
+int serial_readable(serial_t *obj) {
+ return obj->uart->LSR & 0x01;
+}
+
+int serial_writable(serial_t *obj) {
+ return obj->uart->LSR & 0x20;
+}
+
+void serial_clear(serial_t *obj) {
+ obj->uart->FCR = 1 << 1 // rx FIFO reset
+ | 1 << 2 // tx FIFO reset
+ | 0 << 6; // interrupt depth
+}
+
+void serial_pinout_tx(PinName tx) {
+ pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+ obj->uart->LCR |= (1 << 6);
+}
+
+void serial_break_clear(serial_t *obj) {
+ obj->uart->LCR &= ~(1 << 6);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/sleep.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+
+void sleep(void) {
+ LPC_SC->PCON = 0x0;
+
+ // SRC[SLEEPDEEP] set to 0 = sleep
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+
+ // wait for interrupt
+ __WFI();
+}
+
+/*
+* The mbed lpc1768 does not support the deepsleep mode
+* as a debugger is connected to it (the mbed interface).
+*
+* As mentionned in an application note from NXP:
+*
+* http://www.po-star.com/public/uploads/20120319123122_141.pdf
+*
+* {{{
+* The user should be aware of certain limitations during debugging.
+* The most important is that, due to limitations of the Cortex-M3
+* integration, the LPC17xx cannot wake up in the usual manner from
+* Deep Sleep and Power-down modes. It is recommended not to use these
+* modes during debug. Once an application is downloaded via JTAG/SWD
+* interface, the USB to SWD/JTAG debug adapter (Keil ULINK2 for example)
+* should be removed from the target board, and thereafter, power cycle
+* the LPC17xx to allow wake-up from deep sleep and power-down modes
+* }}}
+*
+* As the interface firmware does not reset the target when a
+* mbed_interface_disconnect() semihosting call is made, the
+* core cannot wake-up from deepsleep.
+*
+* We treat a deepsleep() as a normal sleep().
+*/
+void deepsleep(void) {
+ sleep();
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/spi_api.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,231 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+
+#include "spi_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_SPI_SCLK[] = {
+ {P0_7 , SPI_1, 2},
+ {P0_15, SPI_0, 2},
+ {P1_0, SPI_2, 4},
+ {P1_19, SPI_1, 5},
+ {P1_20, SPI_0, 5},
+ {P1_31, SPI_1, 2},
+ {P2_22, SPI_0, 2},
+ {P4_20, SPI_1, 3},
+ {P5_2, SPI_2, 2},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+ {P0_9 , SPI_1, 2},
+ {P0_13, SPI_1, 2},
+ {P0_18, SPI_0, 2},
+ {P1_1, SPI_2, 4},
+ {P1_22, SPI_1, 5},
+ {P1_24, SPI_0, 5},
+ {P2_27, SPI_0, 2},
+ {P4_23, SPI_1, 3},
+ {P5_0, SPI_2, 2},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+ {P0_8 , SPI_1, 2},
+ {P0_12, SPI_1, 2},
+ {P0_17, SPI_0, 2},
+ {P1_4, SPI_2, 4},
+ {P1_18, SPI_1, 5},
+ {P1_23, SPI_0, 5},
+ {P2_26, SPI_0, 2},
+ {P4_22, SPI_1, 3},
+ {P5_1, SPI_2, 2},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+ {P0_6 , SPI_1, 2},
+ {P0_14, SPI_1, 2},
+ {P0_16, SPI_0, 2},
+ {P1_8, SPI_2, 4},
+ {P1_21, SPI_0, 3},
+ {P1_26, SPI_1, 5},
+ {P1_28, SPI_0, 5},
+ {P2_23, SPI_0, 2},
+ {P4_21, SPI_1, 3},
+ {NC , NC , 0}
+};
+
+static inline int ssp_disable(spi_t *obj);
+static inline int ssp_enable(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+ // determine the SPI to use
+ SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+ SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+ SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+ SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+ obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
+ if ((int)obj->spi == NC) {
+ error("SPI pinout mapping failed");
+ }
+
+ // enable power and clocking
+ switch ((int)obj->spi) {
+ case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
+ case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
+ case SPI_2: LPC_SC->PCONP |= 1 << 20; break;
+ }
+
+ // set default format and frequency
+ if (ssel == NC) {
+ spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
+ } else {
+ spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
+ }
+ spi_frequency(obj, 1000000);
+
+ // enable the ssp channel
+ ssp_enable(obj);
+
+ // pin out the spi pins
+ pinmap_pinout(mosi, PinMap_SPI_MOSI);
+ pinmap_pinout(miso, PinMap_SPI_MISO);
+ pinmap_pinout(sclk, PinMap_SPI_SCLK);
+ if (ssel != NC) {
+ pinmap_pinout(ssel, PinMap_SPI_SSEL);
+ }
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+ ssp_disable(obj);
+
+ if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
+ error("SPI format error");
+ }
+
+ int polarity = (mode & 0x2) ? 1 : 0;
+ int phase = (mode & 0x1) ? 1 : 0;
+
+ // set it up
+ int DSS = bits - 1; // DSS (data select size)
+ int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
+ int SPH = (phase) ? 1 : 0; // SPH - clock out phase
+
+ int FRF = 0; // FRF (frame format) = SPI
+ uint32_t tmp = obj->spi->CR0;
+ tmp &= ~(0xFFFF);
+ tmp |= DSS << 0
+ | FRF << 4
+ | SPO << 6
+ | SPH << 7;
+ obj->spi->CR0 = tmp;
+
+ tmp = obj->spi->CR1;
+ tmp &= ~(0xD);
+ tmp |= 0 << 0 // LBM - loop back mode - off
+ | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
+ | 0 << 3; // SOD - slave output disable - na
+ obj->spi->CR1 = tmp;
+ ssp_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+ ssp_disable(obj);
+
+ uint32_t PCLK = PeripheralClock;
+
+ int prescaler;
+
+ for (prescaler = 2; prescaler <= 254; prescaler += 2) {
+ int prescale_hz = PCLK / prescaler;
+
+ // calculate the divider
+ int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
+
+ // check we can support the divider
+ if (divider < 256) {
+ // prescaler
+ obj->spi->CPSR = prescaler;
+
+ // divider
+ obj->spi->CR0 &= ~(0xFFFF << 8);
+ obj->spi->CR0 |= (divider - 1) << 8;
+ ssp_enable(obj);
+ return;
+ }
+ }
+ error("Couldn't setup requested SPI frequency");
+}
+
+static inline int ssp_disable(spi_t *obj) {
+ return obj->spi->CR1 &= ~(1 << 1);
+}
+
+static inline int ssp_enable(spi_t *obj) {
+ return obj->spi->CR1 |= (1 << 1);
+}
+
+static inline int ssp_readable(spi_t *obj) {
+ return obj->spi->SR & (1 << 2);
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+ return obj->spi->SR & (1 << 1);
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+ while (!ssp_writeable(obj));
+ obj->spi->DR = value;
+}
+
+static inline int ssp_read(spi_t *obj) {
+ while (!ssp_readable(obj));
+ return obj->spi->DR;
+}
+
+static inline int ssp_busy(spi_t *obj) {
+ return (obj->spi->SR & (1 << 4)) ? (1) : (0);
+}
+
+int spi_master_write(spi_t *obj, int value) {
+ ssp_write(obj, value);
+ return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj) {
+ return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+};
+
+int spi_slave_read(spi_t *obj) {
+ return obj->spi->DR;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+ while (ssp_writeable(obj) == 0) ;
+ obj->spi->DR = value;
+}
+
+int spi_busy(spi_t *obj) {
+ return ssp_busy(obj);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/us_ticker.c Wed Aug 07 16:43:59 2013 +0300
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+#define US_TICKER_TIMER ((LPC_TIM_TypeDef *)LPC_TIM3_BASE)
+#define US_TICKER_TIMER_IRQn TIMER3_IRQn
+
+int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+ if (us_ticker_inited) return;
+ us_ticker_inited = 1;
+
+ LPC_SC->PCONP |= 1 << 23; // Clock TIMER_3
+
+ US_TICKER_TIMER->CTCR = 0x0; // timer mode
+ uint32_t PCLK = PeripheralClock;
+
+ US_TICKER_TIMER->TCR = 0x2; // reset
+
+ uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks)
+ US_TICKER_TIMER->PR = prescale - 1;
+ US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0
+
+ NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
+ NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+uint32_t us_ticker_read() {
+ if (!us_ticker_inited)
+ us_ticker_init();
+
+ return US_TICKER_TIMER->TC;
+}
+
+void us_ticker_set_interrupt(unsigned int timestamp) {
+ // set match value
+ US_TICKER_TIMER->MR0 = timestamp;
+ // enable match interrupt
+ US_TICKER_TIMER->MCR |= 1;
+}
+
+void us_ticker_disable_interrupt(void) {
+ US_TICKER_TIMER->MCR &= ~1;
+}
+
+void us_ticker_clear_interrupt(void) {
+ US_TICKER_TIMER->IR = 1;
+}