Revision 137:f9a97811e98c, committed 2014-03-25

Comitter:

mbed_official

Date:

Tue Mar 25 13:45:07 2014 +0000

Parent:

136:f4bb33e41288

Child:

138:ec7ee4660c49

Commit message:

Synchronized with git revision 8b4f07882b14f6152ee6d3e1c72b548d6f340650

Full URL: https://github.com/mbedmicro/mbed/commit/8b4f07882b14f6152ee6d3e1c72b548d6f340650/

[NUCLEO_F302R8] Fix issue with SystemCoreClock variable update.

Changed in this revision

--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f302x8.sct	Tue Mar 25 11:45:07 2014 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f302x8.sct	Tue Mar 25 13:45:07 2014 +0000
@@ -37,7 +37,8 @@
   }
 
   ; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188)
-  RW_IRAM1 (0x20000000+0x188) (0x4000-0x188)  {  ; RW data
+  ; + 4 more bytes reserved for the SystemCoreClock variable
+  RW_IRAM1 (0x20000000+(0x188+4)) (0x4000-(0x188+4))  {  ; RW data
    .ANY (+RW +ZI)
   }
 

--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f302x8.sct	Tue Mar 25 11:45:07 2014 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f302x8.sct	Tue Mar 25 13:45:07 2014 +0000
@@ -37,7 +37,8 @@
   }
 
   ; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188)
-  RW_IRAM1 (0x20000000+0x188) (0x4000-0x188)  {  ; RW data
+  ; + 4 more bytes reserved for the SystemCoreClock variable
+  RW_IRAM1 (0x20000000+(0x188+4)) (0x4000-(0x188+4))  {  ; RW data
    .ANY (+RW +ZI)
   }
 

--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/system_stm32f30x.c	Tue Mar 25 11:45:07 2014 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/system_stm32f30x.c	Tue Mar 25 13:45:07 2014 +0000
@@ -141,7 +141,10 @@
   * @{
   */
 
-uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */
+// [TODO] Do the same for other compilers
+// Warning: the RAM is initialized AFTER the SetSysClock function is called.
+// This variable must be placed outside the initialized section (see scatter file).
+uint32_t SystemCoreClock __attribute__((at(0x20000188))) = 64000000; /* Default with HSI. Will be updated if HSE is used */
 
 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
@@ -208,16 +211,16 @@
   /* Disable all interrupts */
   RCC->CIR = 0x00000000;
 
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
   /* Configure the Vector Table location add offset address ------------------*/
 #ifdef VECT_TAB_SRAM
   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 #else
   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 #endif
-
-  /* Configure the System clock source, PLL Multiplier and Divider factors, 
-     AHB/APBx prescalers and Flash settings */
-  SetSysClock();
 }
 
 /**
@@ -330,9 +333,6 @@
       }
     }
   }
- 
-  /* Update SystemCoreClock variable */
-  SystemCoreClockUpdate();
   
   /* Output SYSCLK on MCO pin(PA8) for debugging purpose */
   /*
@@ -411,7 +411,8 @@
     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
     {
     }
-    
+
+    SystemCoreClock = 72000000;
     return 1; // OK
   }
   else
@@ -459,6 +460,7 @@
   {
   }
 
+  SystemCoreClock = 64000000;
   return 1; // OK
 }