Jim Carver
Garage Door Monitor and Opener
Dependencies: X_NUCLEO_COMMON ST_INTERFACES
Introduction
This system implements a simple garage door opener and environmental monitor. The hardware connects to the internet using Wi-Fi then on to the Pelion Device Management Platform which provides device monitoring and secure firmware updates over the air (FOTA). Pelion Device Management provides a flexible set of REST APIs which we will use to communicate to a web application running on an EC-2 instance in AWS. The web application will serve a web page where we can monitor and control our garage..
This project is intended to work on the DISCO-L475VG-IOT01A from ST Microelectronics It implements a simple actuator to drive a relay to simulate pushing the "open" button on older style garage doors which do not use a rolling code interface.
The system is designed to be mounted over the door so that the on board time of flight sensor can be used to detect if the door is open or closed.
The system also monitors temperature, humidity and barometric pressure.
Hardware Requirements:
DISCO-L475G-IOT01A https://os.mbed.com/platforms/ST-Discovery-L475E-IOT01A/
Seeed Studio Grove Relay module https://www.seeedstudio.com/Grove-Relay.html
Seeed Studio Grove cable, I used this one: https://www.seeedstudio.com/Grove-4-pin-Male-Jumper-to-Grove-4-pin-Conversion-Cable-5-PCs-per-Pack.html
Connect to the PMOD connector like this:
This shows how I installed so that the time of flight sensor can detect when the door is open
To use the project:
You will also need a Pelion developers account.
I suggest you first use the Pelion quick state to become familiar with Pelion Device Management. https://os.mbed.com/guides/connect-device-to-pelion/1/?board=ST-Discovery-L475E-IOT01A
Web Interface
For my web interface I am running node-red under Ubuntu in an EC2 instance on AWS. This can run for 12 month within the constraints of their free tier. Here is a tutorial: https://nodered.org/docs/getting-started/aws
You will also need to install several node-red add ons:
sudo npm install -g node-red-dashboard
sudo npm install -g node-red-contrib-mbed-cloud
sudo npm istall -g node-red-contrib-moment
After starting node-red import the contents of GarageFlow.txt from the project, pin the flow into the page.
To enable your web app to access your Pelion account you need an API key.
First you will neet to use your Pelion account to create an API key.
Now we need to apply that API key to your Node-Red flow.
Revision 31:da14aa77f977, committed 2019-03-11
- Comitter:
- screamer
- Date:
- Mon Mar 11 11:28:07 2019 +0000
- Parent:
- 30:15743b79c6cb
- Child:
- 32:2871fbeb627d
- Commit message:
- Revert back to Mbed OS 5.10.4 due to issues to fit in RAM2 on GCC_ARM
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/storage/COMPONENT_QSPIF/QSPIFBlockDevice.cpp Mon Mar 11 11:28:07 2019 +0000
@@ -0,0 +1,1405 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "QSPIFBlockDevice.h"
+#include <string.h>
+#include "mbed_wait_api.h"
+
+#ifndef MBED_CONF_MBED_TRACE_ENABLE
+#define MBED_CONF_MBED_TRACE_ENABLE 0
+#endif
+
+#include "mbed_trace.h"
+#define TRACE_GROUP "QSPIF"
+
+using namespace mbed;
+
+/* Default QSPIF Parameters */
+/****************************/
+#define QSPIF_DEFAULT_READ_SIZE 1
+#define QSPIF_DEFAULT_PROG_SIZE 1
+#define QSPIF_DEFAULT_PAGE_SIZE 256
+#define QSPIF_DEFAULT_SE_SIZE 4096
+#define QSPI_MAX_STATUS_REGISTER_SIZE 3
+#ifndef UINT64_MAX
+#define UINT64_MAX -1
+#endif
+#define QSPI_NO_ADDRESS_COMMAND UINT64_MAX
+// Status Register Bits
+#define QSPIF_STATUS_BIT_WIP 0x1 //Write In Progress
+#define QSPIF_STATUS_BIT_WEL 0x2 // Write Enable Latch
+
+/* SFDP Header Parsing */
+/***********************/
+#define QSPIF_SFDP_HEADER_SIZE 8
+#define QSPIF_PARAM_HEADER_SIZE 8
+
+/* Basic Parameters Table Parsing */
+/**********************************/
+#define SFDP_DEFAULT_BASIC_PARAMS_TABLE_SIZE_BYTES 64 /* 16 DWORDS */
+//READ Instruction support according to BUS Configuration
+#define QSPIF_BASIC_PARAM_TABLE_FAST_READ_SUPPORT_BYTE 2
+#define QSPIF_BASIC_PARAM_TABLE_QPI_READ_SUPPORT_BYTE 16
+#define QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE 27
+#define QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE 9
+#define QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE 11
+#define QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE 23
+#define QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE 15
+#define QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE 13
+#define QSPIF_BASIC_PARAM_TABLE_PAGE_SIZE_BYTE 40
+// Quad Enable Params
+#define QSPIF_BASIC_PARAM_TABLE_QER_BYTE 58
+#define QSPIF_BASIC_PARAM_TABLE_444_MODE_EN_SEQ_BYTE 56
+// Erase Types Params
+#define QSPIF_BASIC_PARAM_ERASE_TYPE_1_BYTE 29
+#define QSPIF_BASIC_PARAM_ERASE_TYPE_2_BYTE 31
+#define QSPIF_BASIC_PARAM_ERASE_TYPE_3_BYTE 33
+#define QSPIF_BASIC_PARAM_ERASE_TYPE_4_BYTE 35
+#define QSPIF_BASIC_PARAM_ERASE_TYPE_1_SIZE_BYTE 28
+#define QSPIF_BASIC_PARAM_ERASE_TYPE_2_SIZE_BYTE 30
+#define QSPIF_BASIC_PARAM_ERASE_TYPE_3_SIZE_BYTE 32
+#define QSPIF_BASIC_PARAM_ERASE_TYPE_4_SIZE_BYTE 34
+#define QSPIF_BASIC_PARAM_4K_ERASE_TYPE_BYTE 1
+
+// Erase Types Per Region BitMask
+#define ERASE_BITMASK_TYPE4 0x08
+#define ERASE_BITMASK_TYPE1 0x01
+#define ERASE_BITMASK_NONE 0x00
+#define ERASE_BITMASK_ALL 0x0F
+
+#define IS_MEM_READY_MAX_RETRIES 10000
+
+enum qspif_default_instructions {
+ QSPIF_NOP = 0x00, // No operation
+ QSPIF_PP = 0x02, // Page Program data
+ QSPIF_READ = 0x03, // Read data
+ QSPIF_SE = 0x20, // 4KB Sector Erase
+ QSPIF_SFDP = 0x5a, // Read SFDP
+ QSPIF_WRSR = 0x01, // Write Status/Configuration Register
+ QSPIF_WRDI = 0x04, // Write Disable
+ QSPIF_RDSR = 0x05, // Read Status Register
+ QSPIF_WREN = 0x06, // Write Enable
+ QSPIF_RSTEN = 0x66, // Reset Enable
+ QSPIF_RST = 0x99, // Reset
+ QSPIF_RDID = 0x9f, // Read Manufacturer and JDEC Device ID
+};
+
+// Local Function
+static int local_math_power(int base, int exp);
+
+/* Init function to initialize Different Devices CS static list */
+static PinName *generate_initialized_active_qspif_csel_arr();
+// Static Members for different devices csel
+// _devices_mutex is used to lock csel list - only one QSPIFBlockDevice instance per csel is allowed
+SingletonPtr<PlatformMutex> QSPIFBlockDevice::_devices_mutex;
+int QSPIFBlockDevice::_number_of_active_qspif_flash_csel = 0;
+PinName *QSPIFBlockDevice::_active_qspif_flash_csel_arr = generate_initialized_active_qspif_csel_arr();
+
+/********* Public API Functions *********/
+/****************************************/
+QSPIFBlockDevice::QSPIFBlockDevice(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName csel,
+ int clock_mode, int freq)
+ : _qspi(io0, io1, io2, io3, sclk, csel, clock_mode), _csel(csel), _freq(freq), _device_size_bytes(0),
+ _init_ref_count(0),
+ _is_initialized(false)
+{
+ _unique_device_status = add_new_csel_instance(csel);
+
+ if (_unique_device_status == 0) {
+ tr_info("Adding a new QSPIFBlockDevice csel: %d\n", (int)csel);
+ } else if (_unique_device_status == -1) {
+ tr_error("QSPIFBlockDevice with the same csel(%d) already exists\n", (int)csel);
+ } else {
+ tr_error("Too many different QSPIFBlockDevice devices - max allowed: %d\n", QSPIF_MAX_ACTIVE_FLASH_DEVICES);
+ }
+}
+
+int QSPIFBlockDevice::init()
+{
+ if (_unique_device_status == 0) {
+ tr_debug("QSPIFBlockDevice csel: %d", (int)_csel);
+ } else if (_unique_device_status == -1) {
+ tr_error("QSPIFBlockDevice with the same csel(%d) already exists", (int)_csel);
+ return QSPIF_BD_ERROR_DEVICE_NOT_UNIQE;
+ } else {
+ tr_error("Too many different QSPIFBlockDevice devices - max allowed: %d", QSPIF_MAX_ACTIVE_FLASH_DEVICES);
+ return QSPIF_BD_ERROR_DEVICE_MAX_EXCEED;
+ }
+
+ uint8_t vendor_device_ids[4];
+ size_t data_length = 3;
+ int status = QSPIF_BD_ERROR_OK;
+ uint32_t basic_table_addr = 0;
+ size_t basic_table_size = 0;
+ uint32_t sector_map_table_addr = 0;
+ size_t sector_map_table_size = 0;
+ int qspi_status = QSPI_STATUS_OK;
+
+ _mutex.lock();
+
+ if (!_is_initialized) {
+ _init_ref_count = 0;
+ }
+
+ _init_ref_count++;
+
+ if (_init_ref_count != 1) {
+ goto exit_point;
+ }
+
+ //Initialize parameters
+ _min_common_erase_size = 0;
+ _regions_count = 1;
+ _region_erase_types_bitfield[0] = ERASE_BITMASK_NONE;
+
+ //Default Bus Setup 1_1_1 with 0 dummy and mode cycles
+ _inst_width = QSPI_CFG_BUS_SINGLE;
+ _address_width = QSPI_CFG_BUS_SINGLE;
+ _address_size = QSPI_CFG_ADDR_SIZE_24;
+ _data_width = QSPI_CFG_BUS_SINGLE;
+ _dummy_and_mode_cycles = 0;
+ _write_register_inst = QSPIF_WRSR;
+ _read_register_inst = QSPIF_RDSR;
+
+
+ if (QSPI_STATUS_OK != _qspi_set_frequency(_freq)) {
+ tr_error("QSPI Set Frequency Failed");
+ status = QSPIF_BD_ERROR_DEVICE_ERROR;
+ goto exit_point;
+ }
+
+ // Soft Reset
+ if (-1 == _reset_flash_mem()) {
+ tr_error("Init - Unable to initialize flash memory, tests failed");
+ status = QSPIF_BD_ERROR_DEVICE_ERROR;
+ goto exit_point;
+ } else {
+ tr_info("Initialize flash memory OK");
+ }
+
+ /* Read Manufacturer ID (1byte), and Device ID (2bytes)*/
+ qspi_status = _qspi_send_general_command(QSPIF_RDID, QSPI_NO_ADDRESS_COMMAND, NULL, 0, (char *)vendor_device_ids,
+ data_length);
+ if (qspi_status != QSPI_STATUS_OK) {
+ tr_error("Init - Read Vendor ID Failed");
+ status = QSPIF_BD_ERROR_DEVICE_ERROR;
+ goto exit_point;
+ }
+
+ tr_debug("Vendor device ID = 0x%x 0x%x 0x%x 0x%x \n", vendor_device_ids[0],
+ vendor_device_ids[1], vendor_device_ids[2], vendor_device_ids[3]);
+ switch (vendor_device_ids[0]) {
+ case 0xbf:
+ // SST devices come preset with block protection
+ // enabled for some regions, issue write disable instruction to clear
+ _set_write_enable();
+ _qspi_send_general_command(QSPIF_WRDI, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0);
+ break;
+ }
+
+ //Synchronize Device
+ if (false == _is_mem_ready()) {
+ tr_error("Init - _is_mem_ready Failed");
+ status = QSPIF_BD_ERROR_READY_FAILED;
+ goto exit_point;
+ }
+
+ /**************************** Parse SFDP Header ***********************************/
+ if (0 != _sfdp_parse_sfdp_headers(basic_table_addr, basic_table_size, sector_map_table_addr, sector_map_table_size)) {
+ tr_error("Init - Parse SFDP Headers Failed");
+ status = QSPIF_BD_ERROR_PARSING_FAILED;
+ goto exit_point;
+ }
+
+ /**************************** Parse Basic Parameters Table ***********************************/
+ if (0 != _sfdp_parse_basic_param_table(basic_table_addr, basic_table_size)) {
+ tr_error("Init - Parse Basic Param Table Failed");
+ status = QSPIF_BD_ERROR_PARSING_FAILED;
+ goto exit_point;
+ }
+
+ /**************************** Parse Sector Map Table ***********************************/
+ _region_size_bytes[0] =
+ _device_size_bytes; // If there's no region map, we have a single region sized the entire device size
+ _region_high_boundary[0] = _device_size_bytes - 1;
+
+ if ((sector_map_table_addr != 0) && (0 != sector_map_table_size)) {
+ tr_info("Init - Parsing Sector Map Table - addr: 0x%lxh, Size: %d", sector_map_table_addr,
+ sector_map_table_size);
+ if (0 != _sfdp_parse_sector_map_table(sector_map_table_addr, sector_map_table_size)) {
+ tr_error("Init - Parse Sector Map Table Failed");
+ status = QSPIF_BD_ERROR_PARSING_FAILED;
+ goto exit_point;
+ }
+ }
+
+ // Configure BUS Mode to 1_1_1 for all commands other than Read
+ _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
+ QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
+
+ _is_initialized = true;
+
+exit_point:
+ _mutex.unlock();
+
+ return status;
+}
+
+int QSPIFBlockDevice::deinit()
+{
+ int result = QSPIF_BD_ERROR_OK;
+
+ _mutex.lock();
+
+ if (!_is_initialized) {
+ _init_ref_count = 0;
+ _mutex.unlock();
+ return result;
+ }
+
+ _init_ref_count--;
+
+ if (_init_ref_count) {
+ _mutex.unlock();
+ return result;
+ }
+
+ // Disable Device for Writing
+ qspi_status_t status = _qspi_send_general_command(QSPIF_WRDI, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0);
+ if (status != QSPI_STATUS_OK) {
+ tr_error("Write Disable failed");
+ result = QSPIF_BD_ERROR_DEVICE_ERROR;
+ }
+
+ _is_initialized = false;
+
+ _mutex.unlock();
+
+ if (_unique_device_status == 0) {
+ remove_csel_instance(_csel);
+ }
+
+ return result;
+}
+
+int QSPIFBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size)
+{
+ int status = QSPIF_BD_ERROR_OK;
+ tr_info("Read Inst: 0x%xh", _read_instruction);
+
+ _mutex.lock();
+
+ // Configure Bus for Reading
+ _qspi_configure_format(_inst_width, _address_width, _address_size, QSPI_CFG_BUS_SINGLE,
+ QSPI_CFG_ALT_SIZE_8, _data_width, _dummy_and_mode_cycles);
+
+ if (QSPI_STATUS_OK != _qspi_send_read_command(_read_instruction, buffer, addr, size)) {
+ status = QSPIF_BD_ERROR_DEVICE_ERROR;
+ tr_error("Read Command failed");
+ }
+
+ // All commands other than Read use default 1-1-1 Bus mode (Program/Erase are constrained by flash memory performance less than that of the bus)
+ _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
+ QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
+
+ _mutex.unlock();
+ return status;
+
+}
+
+int QSPIFBlockDevice::program(const void *buffer, bd_addr_t addr, bd_size_t size)
+{
+ qspi_status_t result = QSPI_STATUS_OK;
+ bool program_failed = false;
+ int status = QSPIF_BD_ERROR_OK;
+ uint32_t offset = 0;
+ uint32_t chunk = 0;
+ bd_size_t written_bytes = 0;
+
+ tr_debug("Program - Buff: 0x%lxh, addr: %llu, size: %llu", (uint32_t)buffer, addr, size);
+
+ while (size > 0) {
+ // Write on _page_size_bytes boundaries (Default 256 bytes a page)
+ offset = addr % _page_size_bytes;
+ chunk = (offset + size < _page_size_bytes) ? size : (_page_size_bytes - offset);
+ written_bytes = chunk;
+
+ _mutex.lock();
+
+ //Send WREN
+ if (_set_write_enable() != 0) {
+ tr_error("Write Enabe failed");
+ program_failed = true;
+ status = QSPIF_BD_ERROR_WREN_FAILED;
+ goto exit_point;
+ }
+
+ result = _qspi_send_program_command(_prog_instruction, buffer, addr, &written_bytes);
+ if ((result != QSPI_STATUS_OK) || (chunk != written_bytes)) {
+ tr_error("Write failed");
+ program_failed = true;
+ status = QSPIF_BD_ERROR_DEVICE_ERROR;
+ goto exit_point;
+ }
+
+ buffer = static_cast<const uint8_t *>(buffer) + chunk;
+ addr += chunk;
+ size -= chunk;
+
+ if (false == _is_mem_ready()) {
+ tr_error("Device not ready after write, failed");
+ program_failed = true;
+ status = QSPIF_BD_ERROR_READY_FAILED;
+ goto exit_point;
+ }
+ _mutex.unlock();
+ }
+
+exit_point:
+ if (program_failed) {
+ _mutex.unlock();
+ }
+
+ return status;
+}
+
+int QSPIFBlockDevice::erase(bd_addr_t addr, bd_size_t in_size)
+{
+ int type = 0;
+ uint32_t offset = 0;
+ uint32_t chunk = 4096;
+ unsigned int cur_erase_inst = _erase_instruction;
+ int size = (int)in_size;
+ bool erase_failed = false;
+ int status = QSPIF_BD_ERROR_OK;
+ // Find region of erased address
+ int region = _utils_find_addr_region(addr);
+ // Erase Types of selected region
+ uint8_t bitfield = _region_erase_types_bitfield[region];
+
+ tr_debug("Erase - addr: %llu, in_size: %llu", addr, in_size);
+
+ if ((addr + in_size) > _device_size_bytes) {
+ tr_error("Erase exceeds flash device size");
+ return QSPIF_BD_ERROR_INVALID_ERASE_PARAMS;
+ }
+
+ if (((addr % get_erase_size(addr)) != 0) || (((addr + in_size) % get_erase_size(addr + in_size - 1)) != 0)) {
+ tr_error("Invalid erase - unaligned address and size");
+ return QSPIF_BD_ERROR_INVALID_ERASE_PARAMS;
+ }
+
+ // For each iteration erase the largest section supported by current region
+ while (size > 0) {
+ // iterate to find next Largest erase type ( a. supported by region, b. smaller than size)
+ // find the matching instruction and erase size chunk for that type.
+ type = _utils_iterate_next_largest_erase_type(bitfield, size, (int)addr, _region_high_boundary[region]);
+ cur_erase_inst = _erase_type_inst_arr[type];
+ offset = addr % _erase_type_size_arr[type];
+ chunk = ((offset + size) < _erase_type_size_arr[type]) ? size : (_erase_type_size_arr[type] - offset);
+
+ tr_debug("Erase - addr: %llu, size:%d, Inst: 0x%xh, chunk: %lu ",
+ addr, size, cur_erase_inst, chunk);
+ tr_debug("Erase - Region: %d, Type:%d ",
+ region, type);
+
+ _mutex.lock();
+
+ if (_set_write_enable() != 0) {
+ tr_error("QSPI Erase Device not ready - failed");
+ erase_failed = true;
+ status = QSPIF_BD_ERROR_READY_FAILED;
+ goto exit_point;
+ }
+
+ if (QSPI_STATUS_OK != _qspi_send_erase_command(cur_erase_inst, addr, size)) {
+ tr_error("QSPI Erase command failed!");
+ erase_failed = true;
+ status = QSPIF_BD_ERROR_DEVICE_ERROR;
+ goto exit_point;
+ }
+
+ addr += chunk;
+ size -= chunk;
+
+ if ((size > 0) && (addr > _region_high_boundary[region])) {
+ // erase crossed to next region
+ region++;
+ bitfield = _region_erase_types_bitfield[region];
+ }
+
+ if (false == _is_mem_ready()) {
+ tr_error("QSPI After Erase Device not ready - failed");
+ erase_failed = true;
+ status = QSPIF_BD_ERROR_READY_FAILED;
+ goto exit_point;
+ }
+
+ _mutex.unlock();
+ }
+
+exit_point:
+ if (erase_failed) {
+ _mutex.unlock();
+ }
+
+ return status;
+}
+
+bd_size_t QSPIFBlockDevice::get_read_size() const
+{
+ // Assuming all devices support 1byte read granularity
+ return QSPIF_DEFAULT_READ_SIZE;
+}
+
+bd_size_t QSPIFBlockDevice::get_program_size() const
+{
+ // Assuming all devices support 1byte program granularity
+ return QSPIF_DEFAULT_PROG_SIZE;
+}
+
+bd_size_t QSPIFBlockDevice::get_erase_size() const
+{
+ // return minimal erase size supported by all regions (0 if none exists)
+ return _min_common_erase_size;
+}
+
+// Find minimal erase size supported by the region to which the address belongs to
+bd_size_t QSPIFBlockDevice::get_erase_size(bd_addr_t addr)
+{
+ // Find region of current address
+ int region = _utils_find_addr_region(addr);
+
+ int min_region_erase_size = _min_common_erase_size;
+ int8_t type_mask = ERASE_BITMASK_TYPE1;
+ int i_ind = 0;
+
+
+ if (region != -1) {
+ type_mask = 0x01;
+
+ for (i_ind = 0; i_ind < 4; i_ind++) {
+ // loop through erase types bitfield supported by region
+ if (_region_erase_types_bitfield[region] & type_mask) {
+
+ min_region_erase_size = _erase_type_size_arr[i_ind];
+ break;
+ }
+ type_mask = type_mask << 1;
+ }
+
+ if (i_ind == 4) {
+ tr_error("No erase type was found for region addr");
+ }
+ }
+
+ return (bd_size_t)min_region_erase_size;
+}
+
+bd_size_t QSPIFBlockDevice::size() const
+{
+ return _device_size_bytes;
+}
+
+int QSPIFBlockDevice::get_erase_value() const
+{
+ return 0xFF;
+}
+
+/********************************/
+/* Different Device Csel Mgmt */
+/********************************/
+static PinName *generate_initialized_active_qspif_csel_arr()
+{
+ PinName *init_arr = new PinName[QSPIF_MAX_ACTIVE_FLASH_DEVICES];
+ for (int i_ind = 0; i_ind < QSPIF_MAX_ACTIVE_FLASH_DEVICES; i_ind++) {
+ init_arr[i_ind] = NC;
+ }
+ return init_arr;
+}
+
+int QSPIFBlockDevice::add_new_csel_instance(PinName csel)
+{
+ int status = 0;
+ _devices_mutex->lock();
+ if (_number_of_active_qspif_flash_csel >= QSPIF_MAX_ACTIVE_FLASH_DEVICES) {
+ status = -2;
+ goto exit_point;
+ }
+
+ // verify the device is unique(no identical csel already exists)
+ for (int i_ind = 0; i_ind < QSPIF_MAX_ACTIVE_FLASH_DEVICES; i_ind++) {
+ if (_active_qspif_flash_csel_arr[i_ind] == csel) {
+ status = -1;
+ goto exit_point;
+ }
+ }
+
+ // Insert new csel into existing device list
+ for (int i_ind = 0; i_ind < QSPIF_MAX_ACTIVE_FLASH_DEVICES; i_ind++) {
+ if (_active_qspif_flash_csel_arr[i_ind] == NC) {
+ _active_qspif_flash_csel_arr[i_ind] = csel;
+ break;
+ }
+ }
+ _number_of_active_qspif_flash_csel++;
+
+exit_point:
+ _devices_mutex->unlock();
+ return status;
+}
+
+int QSPIFBlockDevice::remove_csel_instance(PinName csel)
+{
+ int status = -1;
+ _devices_mutex->lock();
+ // remove the csel from existing device list
+ for (int i_ind = 0; i_ind < QSPIF_MAX_ACTIVE_FLASH_DEVICES; i_ind++) {
+ if (_active_qspif_flash_csel_arr[i_ind] == csel) {
+ _active_qspif_flash_csel_arr[i_ind] = NC;
+ if (_number_of_active_qspif_flash_csel > 0) {
+ _number_of_active_qspif_flash_csel--;
+ }
+ status = 0;
+ break;
+ }
+ }
+ _devices_mutex->unlock();
+ return status;
+}
+
+/*********************************************************/
+/********** SFDP Parsing and Detection Functions *********/
+/*********************************************************/
+int QSPIFBlockDevice::_sfdp_parse_sector_map_table(uint32_t sector_map_table_addr, size_t sector_map_table_size)
+{
+ uint8_t sector_map_table[SFDP_DEFAULT_BASIC_PARAMS_TABLE_SIZE_BYTES]; /* Up To 16 DWORDS = 64 Bytes */
+ uint32_t tmp_region_size = 0;
+ int i_ind = 0;
+ int prev_boundary = 0;
+ // Default set to all type bits 1-4 are common
+ int min_common_erase_type_bits = ERASE_BITMASK_ALL;
+
+
+ qspi_status_t status = _qspi_send_read_command(QSPIF_SFDP, (char *)sector_map_table, sector_map_table_addr /*address*/,
+ sector_map_table_size);
+ if (status != QSPI_STATUS_OK) {
+ tr_error("Init - Read SFDP First Table Failed");
+ return -1;
+ }
+
+ // Currently we support only Single Map Descriptor
+ if (!((sector_map_table[0] & 0x3) == 0x03) && (sector_map_table[1] == 0x0)) {
+ tr_error("Sector Map - Supporting Only Single! Map Descriptor (not map commands)");
+ return -1;
+ }
+
+ _regions_count = sector_map_table[2] + 1;
+ if (_regions_count > QSPIF_MAX_REGIONS) {
+ tr_error("Supporting up to %d regions, current setup to %d regions - fail",
+ QSPIF_MAX_REGIONS, _regions_count);
+ return -1;
+ }
+
+ // Loop through Regions and set for each one: size, supported erase types, high boundary offset
+ // Calculate minimum Common Erase Type for all Regions
+ for (i_ind = 0; i_ind < _regions_count; i_ind++) {
+ tmp_region_size = ((*((uint32_t *)§or_map_table[(i_ind + 1) * 4])) >> 8) & 0x00FFFFFF; // bits 9-32
+ _region_size_bytes[i_ind] = (tmp_region_size + 1) * 256; // Region size is 0 based multiple of 256 bytes;
+ _region_erase_types_bitfield[i_ind] = sector_map_table[(i_ind + 1) * 4] & 0x0F; // bits 1-4
+ min_common_erase_type_bits &= _region_erase_types_bitfield[i_ind];
+ _region_high_boundary[i_ind] = (_region_size_bytes[i_ind] - 1) + prev_boundary;
+ prev_boundary = _region_high_boundary[i_ind] + 1;
+ }
+
+ // Calc minimum Common Erase Size from min_common_erase_type_bits
+ uint8_t type_mask = ERASE_BITMASK_TYPE1;
+ for (i_ind = 0; i_ind < 4; i_ind++) {
+ if (min_common_erase_type_bits & type_mask) {
+ _min_common_erase_size = _erase_type_size_arr[i_ind];
+ break;
+ }
+ type_mask = type_mask << 1;
+ }
+
+ if (i_ind == 4) {
+ // No common erase type was found between regions
+ _min_common_erase_size = 0;
+ }
+
+ return 0;
+}
+
+int QSPIFBlockDevice::_sfdp_parse_basic_param_table(uint32_t basic_table_addr, size_t basic_table_size)
+{
+ uint8_t param_table[SFDP_DEFAULT_BASIC_PARAMS_TABLE_SIZE_BYTES]; /* Up To 16 DWORDS = 64 Bytes */
+
+ qspi_status_t status = _qspi_send_read_command(QSPIF_SFDP, (char *)param_table, basic_table_addr /*address*/,
+ basic_table_size);
+ if (status != QSPI_STATUS_OK) {
+ tr_error("Init - Read SFDP First Table Failed");
+ return -1;
+ }
+
+ // Check address size, currently only supports 3byte addresses
+ if ((param_table[2] & 0x4) != 0 || (param_table[7] & 0x80) != 0) {
+ tr_error("Init - verify 3byte addressing Failed");
+ return -1;
+ }
+
+ // Get device density (stored in bits - 1)
+ uint32_t density_bits = (
+ (param_table[7] << 24) |
+ (param_table[6] << 16) |
+ (param_table[5] << 8) |
+ param_table[4]);
+ _device_size_bytes = (density_bits + 1) / 8;
+
+ // Set Default read/program/erase Instructions
+ _read_instruction = QSPIF_READ;
+ _prog_instruction = QSPIF_PP;
+ _erase_instruction = QSPIF_SE;
+
+ _erase_instruction = _erase4k_inst;
+
+ // Set Page Size (QSPI write must be done on Page limits)
+ _page_size_bytes = _sfdp_detect_page_size(param_table, basic_table_size);
+
+ // Detect and Set Erase Types
+ bool shouldSetQuadEnable = false;
+ bool is_qpi_mode = false;
+
+ _sfdp_detect_erase_types_inst_and_size(param_table, basic_table_size, _erase4k_inst, _erase_type_inst_arr,
+ _erase_type_size_arr);
+ _erase_instruction = _erase4k_inst;
+
+ // Detect and Set fastest Bus mode (default 1-1-1)
+ _sfdp_detect_best_bus_read_mode(param_table, basic_table_size, shouldSetQuadEnable, is_qpi_mode, _read_instruction);
+ if (true == shouldSetQuadEnable) {
+ _enable_fast_mdoe();
+ // Set Quad Enable and QPI Bus modes if Supported
+ tr_info("Init - Setting Quad Enable");
+ if (0 != _sfdp_set_quad_enabled(param_table)) {
+ tr_error("Device supports Quad bus, but Quad Enable Failed");
+ return -1;
+ }
+ if (true == is_qpi_mode) {
+ tr_info("Init - Setting QPI mode");
+ _sfdp_set_qpi_enabled(param_table);
+ }
+ }
+ return 0;
+}
+
+int QSPIFBlockDevice::_sfdp_parse_sfdp_headers(uint32_t &basic_table_addr, size_t &basic_table_size,
+ uint32_t §or_map_table_addr, size_t §or_map_table_size)
+{
+ uint8_t sfdp_header[QSPIF_SFDP_HEADER_SIZE];
+ uint8_t param_header[QSPIF_PARAM_HEADER_SIZE];
+ size_t data_length = QSPIF_SFDP_HEADER_SIZE;
+ bd_addr_t addr = 0x0;
+
+ // Set 1-1-1 bus mode for SFDP header parsing
+ _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
+ QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 8);
+
+ qspi_status_t status = _qspi_send_read_command(QSPIF_SFDP, (char *)sfdp_header, addr /*address*/, data_length);
+ if (status != QSPI_STATUS_OK) {
+ tr_error("Init - Read SFDP Failed");
+ return -1;
+ }
+
+ // Verify SFDP signature for sanity
+ // Also check that major/minor version is acceptable
+ if (!(memcmp(&sfdp_header[0], "SFDP", 4) == 0 && sfdp_header[5] == 1)) {
+ tr_error("Init - _verify SFDP signature and version Failed");
+ return -1;
+ } else {
+ tr_info("Init - verified SFDP Signature and version Successfully");
+ }
+
+ // Discover Number of Parameter Headers
+ int number_of_param_headers = (int)(sfdp_header[6]) + 1;
+ tr_debug("Number of Param Headers: %d", number_of_param_headers);
+
+
+ addr += QSPIF_SFDP_HEADER_SIZE;
+ data_length = QSPIF_PARAM_HEADER_SIZE;
+
+ // Loop over Param Headers and parse them (currently supported Basic Param Table and Sector Region Map Table)
+ for (int i_ind = 0; i_ind < number_of_param_headers; i_ind++) {
+
+ status = _qspi_send_read_command(QSPIF_SFDP, (char *)param_header, addr, data_length);
+ if (status != QSPI_STATUS_OK) {
+ tr_error("Init - Read Param Table %d Failed", i_ind + 1);
+ return -1;
+ }
+
+ // The SFDP spec indicates the standard table is always at offset 0
+ // in the parameter headers, we check just to be safe
+ if (param_header[2] != 1) {
+ tr_error("Param Table %d - Major Version should be 1!", i_ind + 1);
+ return -1;
+ }
+
+ if ((param_header[0] == 0) && (param_header[7] == 0xFF)) {
+ // Found Basic Params Table: LSB=0x00, MSB=0xFF
+ tr_debug("Found Basic Param Table at Table: %d", i_ind + 1);
+ basic_table_addr = ((param_header[6] << 16) | (param_header[5] << 8) | (param_header[4]));
+ // Supporting up to 64 Bytes Table (16 DWORDS)
+ basic_table_size = ((param_header[3] * 4) < SFDP_DEFAULT_BASIC_PARAMS_TABLE_SIZE_BYTES) ? (param_header[3] * 4) : 64;
+
+ } else if ((param_header[0] == 81) && (param_header[7] == 0xFF)) {
+ // Found Sector Map Table: LSB=0x81, MSB=0xFF
+ tr_debug("Found Sector Map Table at Table: %d", i_ind + 1);
+ sector_map_table_addr = ((param_header[6] << 16) | (param_header[5] << 8) | (param_header[4]));
+ sector_map_table_size = param_header[3] * 4;
+
+ }
+ addr += QSPIF_PARAM_HEADER_SIZE;
+
+ }
+ return 0;
+}
+
+int QSPIFBlockDevice::_sfdp_set_qpi_enabled(uint8_t *basic_param_table_ptr)
+{
+ uint8_t config_reg[1];
+
+ // QPI 4-4-4 Enable Procedure is specified in 5 Bits
+ uint8_t en_seq_444_value = (((basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_MODE_EN_SEQ_BYTE] & 0xF0) >> 4) | ((
+ basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_MODE_EN_SEQ_BYTE + 1] & 0x01) << 4));
+
+ switch (en_seq_444_value) {
+ case 1:
+ case 2:
+ tr_debug("_sfdp_set_qpi_enabled - send command 38h");
+ if (QSPI_STATUS_OK != _qspi_send_general_command(0x38, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0)) {
+ tr_error("_sfdp_set_qpi_enabled - send command 38h Failed");
+ }
+ break;
+
+ case 4:
+ tr_debug("_sfdp_set_qpi_enabled - send command 35h");
+ if (QSPI_STATUS_OK != _qspi_send_general_command(0x35, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0)) {
+ tr_error("_sfdp_set_qpi_enabled - send command 35h Failed");
+ }
+ break;
+
+ case 8:
+ tr_debug("_sfdp_set_qpi_enabled - set config bit 6 and send command 71h");
+ if (QSPI_STATUS_OK != _qspi_send_general_command(0x65, 0x800003, NULL, 0, (char *)config_reg, 1)) {
+ tr_error("_sfdp_set_qpi_enabled - set config bit 6 command 65h Failed");
+ }
+ config_reg[0] |= 0x40; //Set Bit 6
+ if (QSPI_STATUS_OK != _qspi_send_general_command(0x71, 0x800003, NULL, 0, (char *)config_reg, 1)) {
+ tr_error("_sfdp_set_qpi_enabled - send command 71h Failed");
+ }
+ break;
+
+ case 16:
+ tr_debug("_sfdp_set_qpi_enabled - reset config bits 0-7 and send command 61h");
+ if (QSPI_STATUS_OK != _qspi_send_general_command(0x65, QSPI_NO_ADDRESS_COMMAND, NULL, 0, (char *)config_reg, 1)) {
+ tr_error("_sfdp_set_qpi_enabled - send command 65h Failed");
+ }
+ config_reg[0] &= 0x7F; //Reset Bit 7 of CR
+ if (QSPI_STATUS_OK != _qspi_send_general_command(0x61, QSPI_NO_ADDRESS_COMMAND, NULL, 0, (char *)config_reg, 1)) {
+ tr_error("_sfdp_set_qpi_enabled - send command 61 Failed");
+ }
+ break;
+
+ default:
+ tr_warning("_sfdp_set_qpi_enabled - Unsuported En Seq 444 configuration");
+ break;
+ }
+ return 0;
+}
+
+
+
+int QSPIFBlockDevice::_sfdp_set_quad_enabled(uint8_t *basic_param_table_ptr)
+{
+ int sr_read_size = QSPI_MAX_STATUS_REGISTER_SIZE;
+ int sr_write_size = QSPI_MAX_STATUS_REGISTER_SIZE;
+
+ char status_reg_setup[QSPI_MAX_STATUS_REGISTER_SIZE] = {0};
+ char status_reg[QSPI_MAX_STATUS_REGISTER_SIZE] = {0};
+
+ // QUAD Enable procedure is specified by 3 bits
+ uint8_t qer_value = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_QER_BYTE] & 0x70) >> 4;
+
+
+ switch (qer_value) {
+ case 0:
+ tr_debug("Device Does not Have a QE Bit, continue based on Read Inst");
+ return 0;
+
+ case 1:
+ case 4:
+ status_reg_setup[1] = 0x02; //Bit 1 of Status Reg 2
+ tr_debug("Setting QE Bit, Bit 1 of Status Reg 2");
+ break;
+
+ case 2:
+ status_reg_setup[0] = 0x40; // Bit 6 of Status Reg 1
+ sr_write_size = 1;
+ tr_debug("Setting QE Bit, Bit 6 of Status Reg 1");
+ break;
+
+ case 3:
+ status_reg_setup[0] = 0x80; // Bit 7 of Status Reg 1
+ sr_write_size = 1;
+ _write_register_inst = 0x3E;
+ _read_register_inst = 0x3F;
+ tr_debug("Setting QE Bit, Bit 7 of Status Reg 1");
+ break;
+ case 5:
+ status_reg_setup[1] = 0x2; // Bit 1 of status Reg 2
+ _read_register_inst = 0x35;
+ sr_read_size = 1;
+ tr_debug("Setting QE Bit, Bit 1 of Status Reg 2 -special read command");
+ break;
+ default:
+ tr_warning("_setQuadEnable - Unsuported QER configuration");
+ break;
+ }
+
+ // Configure BUS Mode to 1_1_1 for all commands other than Read
+ _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
+ QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
+
+ // Read Status Register
+ if (QSPI_STATUS_OK == _qspi_send_general_command(_read_register_inst, QSPI_NO_ADDRESS_COMMAND, NULL, 0,
+ status_reg,
+ sr_read_size)) { // store received values in status_value
+ tr_debug("Reading Status Register Success: value = 0x%x", (int)status_reg[0]);
+ } else {
+ tr_error("Reading Status Register failed");
+ return -1;
+ }
+
+ // Set Bits for Quad Enable
+ for (int i = 0; i < QSPI_MAX_STATUS_REGISTER_SIZE; i++) {
+ status_reg[i] |= status_reg_setup[i];
+ }
+
+ // Write new Status Register Setup
+ if (_set_write_enable() != 0) {
+ tr_error("Write Enabe failed");
+ return -1;
+ }
+
+ if (QSPI_STATUS_OK == _qspi_send_general_command(_write_register_inst, QSPI_NO_ADDRESS_COMMAND, (char *)status_reg,
+ sr_write_size, NULL,
+ 0)) { // Write QE to status_register
+ tr_debug("_setQuadEnable - Writing Status Register Success: value = 0x%x",
+ (int)status_reg[0]);
+ } else {
+ tr_error("_setQuadEnable - Writing Status Register failed");
+ return -1;
+ }
+
+ if (false == _is_mem_ready()) {
+ tr_error("Device not ready after write, failed");
+ return -1;
+ }
+
+
+ // For Debug
+ memset(status_reg, 0, QSPI_MAX_STATUS_REGISTER_SIZE);
+ if (QSPI_STATUS_OK == _qspi_send_general_command(_read_register_inst, QSPI_NO_ADDRESS_COMMAND, NULL, 0,
+ (char *)status_reg,
+ sr_read_size)) { // store received values in status_value
+ tr_debug("Reading Status Register Success: value = 0x%x", (int)status_reg[0]);
+ } else {
+ tr_error("Reading Status Register failed");
+ return -1;
+ }
+
+ return 0;
+}
+
+int QSPIFBlockDevice::_sfdp_detect_page_size(uint8_t *basic_param_table_ptr, int basic_param_table_size)
+{
+ unsigned int page_size = QSPIF_DEFAULT_PAGE_SIZE;
+
+ if (basic_param_table_size > QSPIF_BASIC_PARAM_TABLE_PAGE_SIZE_BYTE) {
+ // Page Size is specified by 4 Bits (N), calculated by 2^N
+ int page_to_power_size = ((int)basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_PAGE_SIZE_BYTE]) >> 4;
+ page_size = local_math_power(2, page_to_power_size);
+ tr_debug("Detected Page Size: %d", page_size);
+ } else {
+ tr_debug("Using Default Page Size: %d", page_size);
+ }
+ return page_size;
+}
+
+int QSPIFBlockDevice::_sfdp_detect_erase_types_inst_and_size(uint8_t *basic_param_table_ptr, int basic_param_table_size,
+ unsigned int &erase4k_inst,
+ unsigned int *erase_type_inst_arr, unsigned int *erase_type_size_arr)
+{
+ erase4k_inst = 0xff;
+ bool found_4Kerase_type = false;
+ uint8_t bitfield = 0x01;
+
+ // Erase 4K Inst is taken either from param table legacy 4K erase or superseded by erase Instruction for type of size 4K
+ erase4k_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_4K_ERASE_TYPE_BYTE];
+
+ if (basic_param_table_size > QSPIF_BASIC_PARAM_ERASE_TYPE_1_SIZE_BYTE) {
+ // Loop Erase Types 1-4
+ for (int i_ind = 0; i_ind < 4; i_ind++) {
+ erase_type_inst_arr[i_ind] = 0xff; //0xFF default for unsupported type
+ erase_type_size_arr[i_ind] = local_math_power(2,
+ basic_param_table_ptr[QSPIF_BASIC_PARAM_ERASE_TYPE_1_SIZE_BYTE + 2 * i_ind]); // Size given as 2^N
+ tr_info("Erase Type(A) %d - Inst: 0x%xh, Size: %d", (i_ind + 1), erase_type_inst_arr[i_ind],
+ erase_type_size_arr[i_ind]);
+ if (erase_type_size_arr[i_ind] > 1) {
+ // if size==1 type is not supported
+ erase_type_inst_arr[i_ind] = basic_param_table_ptr[QSPIF_BASIC_PARAM_ERASE_TYPE_1_BYTE + 2 * i_ind];
+
+ if ((erase_type_size_arr[i_ind] < _min_common_erase_size) || (_min_common_erase_size == 0)) {
+ //Set default minimal common erase for singal region
+ _min_common_erase_size = erase_type_size_arr[i_ind];
+ }
+
+ // SFDP standard requires 4K Erase type to exist and its instruction to be identical to legacy field erase instruction
+ if (erase_type_size_arr[i_ind] == 4096) {
+ found_4Kerase_type = true;
+ if (erase4k_inst != erase_type_inst_arr[i_ind]) {
+ //Verify 4KErase Type is identical to Legacy 4K erase type specified in Byte 1 of Param Table
+ erase4k_inst = erase_type_inst_arr[i_ind];
+ tr_warning("_detectEraseTypesInstAndSize - Default 4K erase Inst is different than erase type Inst for 4K");
+
+ }
+ }
+ _region_erase_types_bitfield[0] |= bitfield; // If there's no region map, set region "0" types bitfield as defualt;
+ }
+
+ tr_info("Erase Type %d - Inst: 0x%xh, Size: %d", (i_ind + 1), erase_type_inst_arr[i_ind],
+ erase_type_size_arr[i_ind]);
+ bitfield = bitfield << 1;
+ }
+ }
+
+ if (false == found_4Kerase_type) {
+ tr_warning("Couldn't find Erase Type for 4KB size");
+ }
+ return 0;
+}
+
+int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table_ptr, int basic_param_table_size,
+ bool &set_quad_enable,
+ bool &is_qpi_mode, unsigned int &read_inst)
+{
+ set_quad_enable = false;
+ is_qpi_mode = false;
+ uint8_t examined_byte;
+
+ do { // compound statement is the loop body
+
+ if (basic_param_table_size > QSPIF_BASIC_PARAM_TABLE_QPI_READ_SUPPORT_BYTE) {
+ examined_byte = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_QPI_READ_SUPPORT_BYTE];
+
+ if (examined_byte & 0x10) {
+ // QPI 4-4-4 Supported
+ read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE];
+ set_quad_enable = true;
+ is_qpi_mode = true;
+ _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] >> 5)
+ + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] & 0x1F);
+ tr_debug("Read Bus Mode set to 4-4-4, Instruction: 0x%xh", _read_instruction);
+ //_inst_width = QSPI_CFG_BUS_QUAD;
+ _address_width = QSPI_CFG_BUS_QUAD;
+ _data_width = QSPI_CFG_BUS_QUAD;
+
+ break;
+ }
+ }
+
+
+ examined_byte = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_FAST_READ_SUPPORT_BYTE];
+ if (examined_byte & 0x40) {
+ // Fast Read 1-4-4 Supported
+ read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE];
+ set_quad_enable = true;
+ // dummy cycles + mode cycles = Dummy Cycles
+ _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] >> 5)
+ + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] & 0x1F);
+ _address_width = QSPI_CFG_BUS_QUAD;
+ _data_width = QSPI_CFG_BUS_QUAD;
+ tr_debug("Read Bus Mode set to 1-4-4, Instruction: 0x%xh", _read_instruction);
+ break;
+ }
+
+ if (examined_byte & 0x80) {
+ // Fast Read 1-1-4 Supported
+ read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE];
+ set_quad_enable = true;
+ _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] >> 5)
+ + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] & 0x1F);
+ _data_width = QSPI_CFG_BUS_QUAD;
+ tr_debug("Read Bus Mode set to 1-1-4, Instruction: 0x%xh", _read_instruction);
+ break;
+ }
+ examined_byte = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_QPI_READ_SUPPORT_BYTE];
+ if (examined_byte & 0x01) {
+ // Fast Read 2-2-2 Supported
+ read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE];
+ _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] >> 5)
+ + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] & 0x1F);
+ _address_width = QSPI_CFG_BUS_DUAL;
+ _data_width = QSPI_CFG_BUS_DUAL;
+ tr_info("Read Bus Mode set to 2-2-2, Instruction: 0x%xh", _read_instruction);
+ break;
+ }
+
+ examined_byte = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_FAST_READ_SUPPORT_BYTE];
+ if (examined_byte & 0x20) {
+ // Fast Read 1-2-2 Supported
+ read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE];
+ _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] >> 5)
+ + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] & 0x1F);
+ _address_width = QSPI_CFG_BUS_DUAL;
+ _data_width = QSPI_CFG_BUS_DUAL;
+ tr_debug("Read Bus Mode set to 1-2-2, Instruction: 0x%xh", _read_instruction);
+ break;
+ }
+ if (examined_byte & 0x01) {
+ // Fast Read 1-1-2 Supported
+ read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE];
+ _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] >> 5)
+ + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] & 0x1F);
+ _data_width = QSPI_CFG_BUS_DUAL;
+ tr_debug("Read Bus Mode set to 1-1-2, Instruction: 0x%xh", _read_instruction);
+ break;
+ }
+ tr_debug("Read Bus Mode set to 1-1-1, Instruction: 0x%xh", _read_instruction);
+ } while (false);
+
+ return 0;
+}
+
+int QSPIFBlockDevice::_reset_flash_mem()
+{
+ // Perform Soft Reset of the Device prior to initialization
+ int status = 0;
+ char status_value[QSPI_MAX_STATUS_REGISTER_SIZE] = {0};
+ tr_info("_reset_flash_mem:");
+ //Read the Status Register from device
+ if (QSPI_STATUS_OK == _qspi_send_general_command(QSPIF_RDSR, QSPI_NO_ADDRESS_COMMAND, NULL, 0, status_value,
+ QSPI_MAX_STATUS_REGISTER_SIZE)) { // store received values in status_value
+ tr_debug("Reading Status Register Success: value = 0x%x", (int)status_value[0]);
+ } else {
+ tr_error("Reading Status Register failed: value = 0x%x", (int)status_value[0]);
+ status = -1;
+ }
+
+ if (0 == status) {
+ //Send Reset Enable
+ if (QSPI_STATUS_OK == _qspi_send_general_command(QSPIF_RSTEN, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL,
+ 0)) { // store received values in status_value
+ tr_debug("Sending RSTEN Success");
+ } else {
+ tr_error("Sending RSTEN failed");
+ status = -1;
+ }
+
+
+ if (0 == status) {
+ //Send Reset
+ if (QSPI_STATUS_OK == _qspi_send_general_command(QSPIF_RST, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL,
+ 0)) { // store received values in status_value
+ tr_debug("Sending RST Success");
+ } else {
+ tr_error("Sending RST failed");
+ status = -1;
+ }
+
+ _is_mem_ready();
+ }
+ }
+
+ return status;
+}
+
+bool QSPIFBlockDevice::_is_mem_ready()
+{
+ // Check Status Register Busy Bit to Verify the Device isn't Busy
+ char status_value[QSPI_MAX_STATUS_REGISTER_SIZE];
+ int retries = 0;
+ bool mem_ready = true;
+
+ do {
+ wait_ms(1);
+ retries++;
+ //Read the Status Register from device
+ memset(status_value, 0xFF, QSPI_MAX_STATUS_REGISTER_SIZE);
+ if (QSPI_STATUS_OK != _qspi_send_general_command(QSPIF_RDSR, QSPI_NO_ADDRESS_COMMAND, NULL, 0, status_value,
+ QSPI_MAX_STATUS_REGISTER_SIZE)) { // store received values in status_value
+ tr_error("Reading Status Register failed");
+ }
+ } while ((status_value[0] & QSPIF_STATUS_BIT_WIP) != 0 && retries < IS_MEM_READY_MAX_RETRIES);
+
+ if ((status_value[0] & QSPIF_STATUS_BIT_WIP) != 0) {
+ tr_error("_is_mem_ready FALSE: status value = 0x%x ", (int)status_value[0]);
+ mem_ready = false;
+ }
+ return mem_ready;
+}
+
+int QSPIFBlockDevice::_set_write_enable()
+{
+ // Check Status Register Busy Bit to Verify the Device isn't Busy
+ char status_value[QSPI_MAX_STATUS_REGISTER_SIZE];
+ int status = -1;
+
+ do {
+ if (QSPI_STATUS_OK != _qspi_send_general_command(QSPIF_WREN, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0)) {
+ tr_error("Sending WREN command FAILED");
+ break;
+ }
+
+ if (false == _is_mem_ready()) {
+ tr_error("Device not ready, write failed");
+ break;
+ }
+
+ memset(status_value, 0, QSPI_MAX_STATUS_REGISTER_SIZE);
+ if (QSPI_STATUS_OK != _qspi_send_general_command(QSPIF_RDSR, QSPI_NO_ADDRESS_COMMAND, NULL, 0, status_value,
+ QSPI_MAX_STATUS_REGISTER_SIZE)) { // store received values in status_value
+ tr_error("Reading Status Register failed");
+ break;
+ }
+
+ if ((status_value[0] & QSPIF_STATUS_BIT_WEL) == 0) {
+ tr_error("_set_write_enable failed");
+ break;
+ }
+ status = 0;
+ } while (false);
+ return status;
+}
+
+int QSPIFBlockDevice::_enable_fast_mdoe()
+{
+ char status_reg[QSPI_MAX_STATUS_REGISTER_SIZE] = {0};
+ unsigned int read_conf_register_inst = 0x15;
+ char status_reg_qer_setup[QSPI_MAX_STATUS_REGISTER_SIZE] = {0};
+
+ status_reg_qer_setup[2] = 0x2; // Bit 1 of config Reg 2
+
+ // Configure BUS Mode to 1_1_1 for all commands other than Read
+ _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
+ QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
+
+ // Read Status Register
+ if (QSPI_STATUS_OK == _qspi_send_general_command(read_conf_register_inst, QSPI_NO_ADDRESS_COMMAND, NULL, 0,
+ &status_reg[1],
+ QSPI_MAX_STATUS_REGISTER_SIZE - 1)) { // store received values in status_value
+ tr_debug("Reading Config Register Success: value = 0x%x", (int)status_reg[2]);
+ } else {
+ tr_error("Reading Config Register failed");
+ return -1;
+ }
+
+ // Set Bits for Quad Enable
+ for (int i = 0; i < QSPI_MAX_STATUS_REGISTER_SIZE; i++) {
+ status_reg[i] |= status_reg_qer_setup[i];
+ }
+
+ // Write new Status Register Setup
+ if (_set_write_enable() != 0) {
+ tr_error("Write Enabe failed");
+ return -1;
+ }
+
+ if (QSPI_STATUS_OK == _qspi_send_general_command(_write_register_inst, QSPI_NO_ADDRESS_COMMAND, status_reg,
+ QSPI_MAX_STATUS_REGISTER_SIZE, NULL,
+ 0)) { // Write Fast mode bit to status_register
+ tr_debug("fast mode enable - Writing Config Register Success: value = 0x%x",
+ (int)status_reg[2]);
+ } else {
+ tr_error("fast mode enable - Writing Config Register failed");
+ return -1;
+ }
+
+ if (false == _is_mem_ready()) {
+ tr_error("Device not ready after write, failed");
+ return -1;
+ }
+
+ // For Debug
+ memset(status_reg, 0, QSPI_MAX_STATUS_REGISTER_SIZE);
+ if (QSPI_STATUS_OK == _qspi_send_general_command(read_conf_register_inst, QSPI_NO_ADDRESS_COMMAND, NULL, 0,
+ &status_reg[1],
+ QSPI_MAX_STATUS_REGISTER_SIZE - 1)) { // store received values in status_value
+ tr_debug("Verifying Config Register Success: value = 0x%x", (int)status_reg[2]);
+ } else {
+ tr_error("Verifying Config Register failed");
+ return -1;
+ }
+
+ return 0;
+}
+
+/*********************************************/
+/************* Utility Functions *************/
+/*********************************************/
+int QSPIFBlockDevice::_utils_find_addr_region(bd_size_t offset)
+{
+ //Find the region to which the given offset belong to
+ if ((offset > _device_size_bytes) || (_regions_count == 0)) {
+ return -1;
+ }
+
+ if (_regions_count == 1) {
+ return 0;
+ }
+
+ for (int i_ind = _regions_count - 2; i_ind >= 0; i_ind--) {
+
+ if (offset > _region_high_boundary[i_ind]) {
+ return (i_ind + 1);
+ }
+ }
+ return -1;
+
+}
+
+int QSPIFBlockDevice::_utils_iterate_next_largest_erase_type(uint8_t &bitfield, int size, int offset, int boundry)
+{
+ // Iterate on all supported Erase Types of the Region to which the offset belong to.
+ // Iterates from highest type to lowest
+ uint8_t type_mask = ERASE_BITMASK_TYPE4;
+ int i_ind = 0;
+ int largest_erase_type = 0;
+ for (i_ind = 3; i_ind >= 0; i_ind--) {
+ if (bitfield & type_mask) {
+ largest_erase_type = i_ind;
+ if ((size > (int)(_erase_type_size_arr[largest_erase_type])) &&
+ ((boundry - offset) > (int)(_erase_type_size_arr[largest_erase_type]))) {
+ break;
+ } else {
+ bitfield &= ~type_mask;
+ }
+ }
+ type_mask = type_mask >> 1;
+ }
+
+ if (i_ind == 4) {
+ tr_error("No erase type was found for current region addr");
+ }
+ return largest_erase_type;
+
+}
+
+/***************************************************/
+/*********** QSPI Driver API Functions *************/
+/***************************************************/
+qspi_status_t QSPIFBlockDevice::_qspi_set_frequency(int freq)
+{
+ return _qspi.set_frequency(freq);
+}
+
+qspi_status_t QSPIFBlockDevice::_qspi_send_read_command(unsigned int read_inst, void *buffer, bd_addr_t addr,
+ bd_size_t size)
+{
+ // Send Read command to device driver
+ size_t buf_len = size;
+
+ if (_qspi.read(read_inst, -1, (unsigned int)addr, (char *)buffer, &buf_len) != QSPI_STATUS_OK) {
+ tr_error("Read failed");
+ return QSPI_STATUS_ERROR;
+ }
+
+ return QSPI_STATUS_OK;
+
+}
+
+qspi_status_t QSPIFBlockDevice::_qspi_send_program_command(unsigned int progInst, const void *buffer, bd_addr_t addr,
+ bd_size_t *size)
+{
+ // Send Program (write) command to device driver
+ qspi_status_t result = QSPI_STATUS_OK;
+
+ result = _qspi.write(progInst, -1, addr, (char *)buffer, (size_t *)size);
+ if (result != QSPI_STATUS_OK) {
+ tr_error("QSPI Write failed");
+ }
+
+ return result;
+}
+
+qspi_status_t QSPIFBlockDevice::_qspi_send_erase_command(unsigned int erase_inst, bd_addr_t addr, bd_size_t size)
+{
+ // Send Erase Instruction command to driver
+ qspi_status_t result = QSPI_STATUS_OK;
+
+ tr_info("Inst: 0x%xh, addr: %llu, size: %llu", erase_inst, addr, size);
+
+ result = _qspi.command_transfer(erase_inst, // command to send
+ (((int)addr) & 0x00FFF000), // Align addr to 4096
+ NULL, // do not transmit
+ 0, // do not transmit
+ NULL, // just receive two bytes of data
+ 0); // store received values in status_value
+
+ if (QSPI_STATUS_OK != result) {
+ tr_error("QSPI Erase failed");
+ }
+
+ return result;
+
+}
+
+qspi_status_t QSPIFBlockDevice::_qspi_send_general_command(unsigned int instruction, bd_addr_t addr,
+ const char *tx_buffer,
+ size_t tx_length, const char *rx_buffer, size_t rx_length)
+{
+ // Send a general command Instruction to driver
+ qspi_status_t status = _qspi.command_transfer(instruction, (int)addr, tx_buffer, tx_length, rx_buffer, rx_length);
+
+ if (QSPI_STATUS_OK != status) {
+ tr_error("Sending Generic command: %x", instruction);
+ }
+
+ return status;
+}
+
+qspi_status_t QSPIFBlockDevice::_qspi_configure_format(qspi_bus_width_t inst_width, qspi_bus_width_t address_width,
+ qspi_address_size_t address_size, qspi_bus_width_t alt_width, qspi_alt_size_t alt_size, qspi_bus_width_t data_width,
+ int dummy_cycles)
+{
+ // Configure QSPI driver Bus format
+ qspi_status_t status = _qspi.configure_format(inst_width, address_width, address_size, alt_width, alt_size, data_width,
+ dummy_cycles);
+
+ return status;
+}
+
+/*********************************************/
+/************** Local Functions **************/
+/*********************************************/
+static int local_math_power(int base, int exp)
+{
+ // Integer X^Y function, used to calculate size fields given in 2^N format
+ int result = 1;
+ while (exp) {
+ result *= base;
+ exp--;
+ }
+ return result;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/storage/COMPONENT_QSPIF/QSPIFBlockDevice.h Mon Mar 11 11:28:07 2019 +0000
@@ -0,0 +1,364 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_QSPIF_BLOCK_DEVICE_H
+#define MBED_QSPIF_BLOCK_DEVICE_H
+
+#include "QSPI.h"
+#include "BlockDevice.h"
+
+/** Enum qspif standard error codes
+ *
+ * @enum qspif_bd_error
+ */
+enum qspif_bd_error {
+ QSPIF_BD_ERROR_OK = 0, /*!< no error */
+ QSPIF_BD_ERROR_DEVICE_ERROR = BD_ERROR_DEVICE_ERROR, /*!< device specific error -4001 */
+ QSPIF_BD_ERROR_PARSING_FAILED = -4002, /* SFDP Parsing failed */
+ QSPIF_BD_ERROR_READY_FAILED = -4003, /* Wait for Mem Ready failed */
+ QSPIF_BD_ERROR_WREN_FAILED = -4004, /* Write Enable Failed */
+ QSPIF_BD_ERROR_INVALID_ERASE_PARAMS = -4005, /* Erase command not on sector aligned addresses or exceeds device size */
+ QSPIF_BD_ERROR_DEVICE_NOT_UNIQE = -4006, /* Only one instance per csel is allowed */
+ QSPIF_BD_ERROR_DEVICE_MAX_EXCEED = -4007 /* Max active QSPIF devices exceeded */
+};
+
+/** Enum qspif polarity mode
+ *
+ * @enum qspif_polarity_mode
+ */
+enum qspif_polarity_mode {
+ QSPIF_POLARITY_MODE_0 = 0, /* CPOL=0, CPHA=0 */
+ QSPIF_POLARITY_MODE_1 /* CPOL=1, CPHA=1 */
+};
+
+#define QSPIF_MAX_REGIONS 10
+#define MAX_NUM_OF_ERASE_TYPES 4
+#define QSPIF_MAX_ACTIVE_FLASH_DEVICES 10
+
+/** BlockDevice for SFDP based flash devices over QSPI bus
+ *
+ * @code
+ * // Here's an example using QSPI flash device on DISCO_L476VG target
+ * #include "mbed.h"
+ * #include "QSPIFBlockDevice.h"
+ *
+ * QSPIFBlockDevice block_device(QSPI_FLASH1_IO0, QSPI_FLASH1_IO1, QSPI_FLASH1_IO2, QSPI_FLASH1_IO3,
+ * QSPI_FLASH1_SCK, QSPI_FLASH1_CSN, QSPIF_POLARITY_MODE_0, MBED_CONF_QSPIF_QSPI_FREQ);
+ *
+ * int main()
+ * {
+ * printf("QSPI SFDP Flash Block Device example\n");
+ *
+ * // Initialize the SPI flash device and print the memory layout
+ * block_device.init();
+ * bd_size_t sector_size_at_address_0 = block_device.get_erase_size(0);
+ *
+ * printf("QSPIF BD size: %llu\n", block_device.size());
+ * printf("QSPIF BD read size: %llu\n", block_device.get_read_size());
+ * printf("QSPIF BD program size: %llu\n", block_device.get_program_size());
+ * printf("QSPIF BD erase size (at address 0): %llu\n", sector_size_at_address_0);
+ *
+ * // Write "Hello World!" to the first block
+ * char *buffer = (char *) malloc(sector_size_at_address_0);
+ * sprintf(buffer, "Hello World!\n");
+ * block_device.erase(0, sector_size_at_address_0);
+ * block_device.program(buffer, 0, sector_size_at_address_0);
+ *
+ * // Read back what was stored
+ * block_device.read(buffer, 0, sector_size_at_address_0);
+ * printf("%s", buffer);
+ *
+ * // Deinitialize the device
+ * block_device.deinit();
+ * }
+ * @endcode
+ */
+class QSPIFBlockDevice : public BlockDevice {
+public:
+ /** Create QSPIFBlockDevice - An SFDP based Flash Block Device over QSPI bus
+ *
+ * @param io0 1st IO pin used for sending/receiving data during data phase of a transaction
+ * @param io1 2nd IO pin used for sending/receiving data during data phase of a transaction
+ * @param io2 3rd IO pin used for sending/receiving data during data phase of a transaction
+ * @param io3 4th IO pin used for sending/receiving data during data phase of a transaction
+ * @param sclk QSPI Clock pin
+ * @param csel QSPI chip select pin
+ * @param clock_mode specifies the QSPI Clock Polarity mode (QSPIF_POLARITY_MODE_0/QSPIF_POLARITY_MODE_1)
+ * default value = 0
+ * @param freq Clock frequency of the QSPI bus (defaults to 40MHz)
+ *
+ */
+ QSPIFBlockDevice(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName csel,
+ int clock_mode, int freq = MBED_CONF_QSPIF_QSPI_FREQ);
+
+ /** Initialize a block device
+ *
+ * @return QSPIF_BD_ERROR_OK(0) - success
+ * QSPIF_BD_ERROR_DEVICE_ERROR - device driver transaction failed
+ * QSPIF_BD_ERROR_READY_FAILED - Waiting for Memory ready failed or timedout
+ * QSPIF_BD_ERROR_PARSING_FAILED - unexpected format or values in one of the SFDP tables
+ */
+ virtual int init();
+
+ /** Deinitialize a block device
+ *
+ * @return QSPIF_BD_ERROR_OK(0) - success
+ * QSPIF_BD_ERROR_DEVICE_ERROR - device driver transaction failed
+ */
+ virtual int deinit();
+
+ /** Desctruct QSPIFBlockDevie
+ */
+ ~QSPIFBlockDevice()
+ {
+ deinit();
+ }
+
+ /** Read blocks from a block device
+ *
+ * @param buffer Buffer to write blocks to
+ * @param addr Address of block to begin reading from
+ * @param size Size to read in bytes, must be a multiple of read block size
+ * @return QSPIF_BD_ERROR_OK(0) - success
+ * QSPIF_BD_ERROR_DEVICE_ERROR - device driver transaction failed
+ */
+ virtual int read(void *buffer, bd_addr_t addr, bd_size_t size);
+
+ /** Program blocks to a block device
+ *
+ * The blocks must have been erased prior to being programmed
+ *
+ * @param buffer Buffer of data to write to blocks
+ * @param addr Address of block to begin writing to
+ * @param size Size to write in bytes, must be a multiple of program block size
+ * @return QSPIF_BD_ERROR_OK(0) - success
+ * QSPIF_BD_ERROR_DEVICE_ERROR - device driver transaction failed
+ * QSPIF_BD_ERROR_READY_FAILED - Waiting for Memory ready failed or timed out
+ * QSPIF_BD_ERROR_WREN_FAILED - Write Enable failed
+ * QSPIF_BD_ERROR_PARSING_FAILED - unexpected format or values in one of the SFDP tables
+ */
+ virtual int program(const void *buffer, bd_addr_t addr, bd_size_t size);
+
+ /** Erase blocks on a block device
+ *
+ * The state of an erased block is undefined until it has been programmed
+ *
+ * @param addr Address of block to begin erasing
+ * @param size Size to erase in bytes, must be a multiple of erase block size
+ * @return QSPIF_BD_ERROR_OK(0) - success
+ * QSPIF_BD_ERROR_DEVICE_ERROR - device driver transaction failed
+ * QSPIF_BD_ERROR_READY_FAILED - Waiting for Memory ready failed or timed out
+ * QSPIF_BD_ERROR_WREN_FAILED - Write Enable failed
+ * QSPIF_BD_ERROR_PARSING_FAILED - unexpected format or values in one of the SFDP tables
+ * QSPIF_BD_ERROR_INVALID_ERASE_PARAMS - Trying to erase unaligned address or size
+ */
+ virtual int erase(bd_addr_t addr, bd_size_t size);
+
+ /** Get the size of a readable block
+ *
+ * @return Size of a readable block in bytes
+ */
+ virtual bd_size_t get_read_size() const;
+
+ /** Get the size of a programable block
+ *
+ * @return Size of a program block size in bytes
+ * @note Must be a multiple of the read size
+ */
+ virtual bd_size_t get_program_size() const;
+
+ /** Get the size of a eraseable block
+ *
+ * @return Size of a minimal erase block, common to all regions, in bytes
+ * @note Must be a multiple of the program size
+ */
+ virtual bd_size_t get_erase_size() const;
+
+ /** Get the size of minimal eraseable sector size of given address
+ *
+ * @param addr Any address within block queried for erase sector size (can be any address within flash size offset)
+ * @return Size of minimal erase sector size, in given address region, in bytes
+ * @note Must be a multiple of the program size
+ */
+ virtual bd_size_t get_erase_size(bd_addr_t addr);
+
+ /** Get the value of storage byte after it was erased
+ *
+ * If get_erase_value returns a non-negative byte value, the underlying
+ * storage is set to that value when erased, and storage containing
+ * that value can be programmed without another erase.
+ *
+ * @return The value of storage when erased, or -1 if you can't
+ * rely on the value of erased storage
+ */
+ virtual int get_erase_value() const;
+
+ /** Get the total size of the underlying device
+ *
+ * @return Size of the underlying device in bytes
+ */
+ virtual bd_size_t size() const;
+
+private:
+ // Internal functions
+
+
+ /********************************/
+ /* Different Device Csel Mgmt */
+ /********************************/
+ // Add a new QSPI device CS to existing devices list.
+ // Only one QSPIFBlockDevice instance per CS is allowed
+ int add_new_csel_instance(PinName csel);
+
+ // Remove device CS from existing device list upon destroying object (last deinit is called)
+ int remove_csel_instance(PinName csel);
+
+ /********************************/
+ /* Calls to QSPI Driver APIs */
+ /********************************/
+ // Send Program => Write command to Driver
+ qspi_status_t _qspi_send_program_command(unsigned int prog_instruction, const void *buffer, bd_addr_t addr,
+ bd_size_t *size);
+
+ // Send Read command to Driver
+ qspi_status_t _qspi_send_read_command(unsigned int read_instruction, void *buffer, bd_addr_t addr, bd_size_t size);
+
+ // Send Erase Instruction using command_transfer command to Driver
+ qspi_status_t _qspi_send_erase_command(unsigned int erase_instruction, bd_addr_t addr, bd_size_t size);
+
+ // Send Generic command_transfer command to Driver
+ qspi_status_t _qspi_send_general_command(unsigned int instruction_int, bd_addr_t addr, const char *tx_buffer,
+ size_t tx_length, const char *rx_buffer, size_t rx_length);
+
+ // Send Bus configure_format command to Driver
+ qspi_status_t _qspi_configure_format(qspi_bus_width_t inst_width, qspi_bus_width_t address_width,
+ qspi_address_size_t address_size, qspi_bus_width_t alt_width, qspi_alt_size_t alt_size, qspi_bus_width_t data_width,
+ int dummy_cycles);
+
+ // Send set_frequency command to Driver
+ qspi_status_t _qspi_set_frequency(int freq);
+
+ /*********************************/
+ /* Flash Configuration Functions */
+ /*********************************/
+ // Soft Reset Flash Memory
+ int _reset_flash_mem();
+
+ // Configure Write Enable in Status Register
+ int _set_write_enable();
+
+ // Wait on status register until write not-in-progress
+ bool _is_mem_ready();
+
+ // Enable Fast Mode - for flash chips with low power default
+ int _enable_fast_mdoe();
+
+ /****************************************/
+ /* SFDP Detection and Parsing Functions */
+ /****************************************/
+ // Parse SFDP Headers and retrieve Basic Param and Sector Map Tables (if exist)
+ int _sfdp_parse_sfdp_headers(uint32_t &basic_table_addr, size_t &basic_table_size,
+ uint32_t §or_map_table_addr, size_t §or_map_table_size);
+
+ // Parse and Detect required Basic Parameters from Table
+ int _sfdp_parse_basic_param_table(uint32_t basic_table_addr, size_t basic_table_size);
+
+ // Parse and read information required by Regions Secotr Map
+ int _sfdp_parse_sector_map_table(uint32_t sector_map_table_addr, size_t sector_map_table_size);
+
+ // Detect fastest read Bus mode supported by device
+ int _sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table_ptr, int basic_param_table_size, bool &set_quad_enable,
+ bool &is_qpi_mode, unsigned int &read_inst);
+
+ // Enable Quad mode if supported (1-1-4, 1-4-4, 4-4-4 bus modes)
+ int _sfdp_set_quad_enabled(uint8_t *basic_param_table_ptr);
+
+ // Enable QPI mode (4-4-4) is supported
+ int _sfdp_set_qpi_enabled(uint8_t *basic_param_table_ptr);
+
+ // Set Page size for program
+ int _sfdp_detect_page_size(uint8_t *basic_param_table_ptr, int basic_param_table_size);
+
+ // Detect all supported erase types
+ int _sfdp_detect_erase_types_inst_and_size(uint8_t *basic_param_table_ptr, int basic_param_table_size,
+ unsigned int &erase4k_inst,
+ unsigned int *erase_type_inst_arr, unsigned int *erase_type_size_arr);
+
+ /***********************/
+ /* Utilities Functions */
+ /***********************/
+ // Find the region to which the given offset belong to
+ int _utils_find_addr_region(bd_size_t offset);
+
+ // Iterate on all supported Erase Types of the Region to which the offset belong to.
+ // Iterates from highest type to lowest
+ int _utils_iterate_next_largest_erase_type(uint8_t &bitfield, int size, int offset, int boundry);
+
+private:
+ // Internal Members
+
+ // QSPI Driver Object
+ mbed::QSPI _qspi;
+
+ // Static List of different QSPI based Flash devices csel that already exist
+ // Each QSPI Flash device csel can have only 1 QSPIFBlockDevice instance
+ // _devices_mutex is used to lock csel list - only one QSPIFBlockDevice instance per csel is allowed
+ static SingletonPtr<PlatformMutex> _devices_mutex;
+ static int _number_of_active_qspif_flash_csel;
+ static PinName *_active_qspif_flash_csel_arr;
+
+ int _unique_device_status;
+ PinName _csel;
+
+ // Mutex is used to protect Flash device for some QSPI Driver commands that must be done sequentially with no other commands in between
+ // e.g. (1)Set Write Enable, (2)Program, (3)Wait Memory Ready
+ PlatformMutex _mutex;
+
+ // Command Instructions
+ unsigned int _read_instruction;
+ unsigned int _prog_instruction;
+ unsigned int _erase_instruction;
+ unsigned int _erase4k_inst; // Legacy 4K erase instruction (default 0x20h)
+ unsigned int _write_register_inst; // Write status/config register instruction may vary between chips
+ unsigned int _read_register_inst; // Read status/config register instruction may vary between chips
+
+ // Up To 4 Erase Types are supported by SFDP (each with its own command Instruction and Size)
+ unsigned int _erase_type_inst_arr[MAX_NUM_OF_ERASE_TYPES];
+ unsigned int _erase_type_size_arr[MAX_NUM_OF_ERASE_TYPES];
+
+ // Sector Regions Map
+ int _regions_count; //number of regions
+ int _region_size_bytes[QSPIF_MAX_REGIONS]; //regions size in bytes
+ bd_size_t _region_high_boundary[QSPIF_MAX_REGIONS]; //region high address offset boundary
+ //Each Region can support a bit combination of any of the 4 Erase Types
+ uint8_t _region_erase_types_bitfield[QSPIF_MAX_REGIONS];
+ unsigned int _min_common_erase_size; // minimal common erase size for all regions (0 if none exists)
+
+ unsigned int _page_size_bytes; // Page size - 256 Bytes default
+ int _freq;
+ bd_size_t _device_size_bytes;
+
+ // Bus speed configuration
+ qspi_bus_width_t _inst_width; //Bus width for Instruction phase
+ qspi_bus_width_t _address_width; //Bus width for Address phase
+ qspi_address_size_t _address_size; // number of bytes for address
+ qspi_bus_width_t _data_width; //Bus width for Data phase
+ int _dummy_and_mode_cycles; // Number of Dummy and Mode Bits required by Current Bus Mode
+
+ uint32_t _init_ref_count;
+ bool _is_initialized;
+};
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/storage/COMPONENT_QSPIF/TESTS/block_device/qspif/main.cpp Mon Mar 11 11:28:07 2019 +0000
@@ -0,0 +1,292 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "QSPIFBlockDevice.h"
+#include "mbed_trace.h"
+#include "rtos/Thread.h"
+#include <stdlib.h>
+
+using namespace utest::v1;
+
+#define TEST_BLOCK_COUNT 10
+#define TEST_ERROR_MASK 16
+#define QSPIF_TEST_NUM_OF_THREADS 5
+
+const struct {
+ const char *name;
+ bd_size_t (BlockDevice::*method)() const;
+} ATTRS[] = {
+ {"read size", &BlockDevice::get_read_size},
+ {"program size", &BlockDevice::get_program_size},
+ {"erase size", &BlockDevice::get_erase_size},
+ {"total size", &BlockDevice::size},
+};
+
+static SingletonPtr<PlatformMutex> _mutex;
+
+
+// Mutex is protecting rand() per srand for buffer writing and verification.
+// Mutex is also protecting printouts for clear logs.
+// Mutex is NOT protecting Block Device actions: erase/program/read - which is the purpose of the multithreaded test!
+void basic_erase_program_read_test(QSPIFBlockDevice &blockD, bd_size_t block_size, uint8_t *write_block,
+ uint8_t *read_block, unsigned addrwidth)
+{
+ int err = 0;
+ _mutex->lock();
+ // Find a random block
+ bd_addr_t block = (rand() * block_size) % blockD.size();
+
+ // Use next random number as temporary seed to keep
+ // the address progressing in the pseudorandom sequence
+ unsigned seed = rand();
+
+ // Fill with random sequence
+ srand(seed);
+ for (bd_size_t i_ind = 0; i_ind < block_size; i_ind++) {
+ write_block[i_ind] = 0xff & rand();
+ }
+ // Write, sync, and read the block
+ utest_printf("\ntest %0*llx:%llu...", addrwidth, block, block_size);
+ _mutex->unlock();
+
+ err = blockD.erase(block, block_size);
+ TEST_ASSERT_EQUAL(0, err);
+
+ err = blockD.program(write_block, block, block_size);
+ TEST_ASSERT_EQUAL(0, err);
+
+ err = blockD.read(read_block, block, block_size);
+ TEST_ASSERT_EQUAL(0, err);
+
+ _mutex->lock();
+ // Check that the data was unmodified
+ srand(seed);
+ int val_rand;
+ for (bd_size_t i_ind = 0; i_ind < block_size; i_ind++) {
+ val_rand = rand();
+ if ((0xff & val_rand) != read_block[i_ind]) {
+ utest_printf("\n Assert Failed Buf Read - block:size: %llx:%llu \n", block, block_size);
+ utest_printf("\n pos: %llu, exp: %02x, act: %02x, wrt: %02x \n", i_ind, (0xff & val_rand), read_block[i_ind],
+ write_block[i_ind]);
+ }
+ TEST_ASSERT_EQUAL(0xff & val_rand, read_block[i_ind]);
+ }
+ _mutex->unlock();
+}
+
+void test_qspif_random_program_read_erase()
+{
+ utest_printf("\nTest Random Program Read Erase Starts..\n");
+
+ QSPIFBlockDevice blockD(QSPI_FLASH1_IO0, QSPI_FLASH1_IO1, QSPI_FLASH1_IO2, QSPI_FLASH1_IO3,
+ QSPI_FLASH1_SCK, QSPI_FLASH1_CSN, QSPIF_POLARITY_MODE_0, MBED_CONF_QSPIF_QSPI_FREQ);
+
+ int err = blockD.init();
+ TEST_ASSERT_EQUAL(0, err);
+
+ for (unsigned atr = 0; atr < sizeof(ATTRS) / sizeof(ATTRS[0]); atr++) {
+ static const char *prefixes[] = {"", "k", "M", "G"};
+ for (int i_ind = 3; i_ind >= 0; i_ind--) {
+ bd_size_t size = (blockD.*ATTRS[atr].method)();
+ if (size >= (1ULL << 10 * i_ind)) {
+ utest_printf("%s: %llu%sbytes (%llubytes)\n",
+ ATTRS[atr].name, size >> 10 * i_ind, prefixes[i_ind], size);
+ break;
+ }
+ }
+ }
+
+ bd_size_t block_size = blockD.get_erase_size();
+ unsigned addrwidth = ceil(log(float(blockD.size() - 1)) / log(float(16))) + 1;
+
+ uint8_t *write_block = new (std::nothrow) uint8_t[block_size];
+ uint8_t *read_block = new (std::nothrow) uint8_t[block_size];
+ if (!write_block || !read_block) {
+ utest_printf("\n Not enough memory for test");
+ goto end;
+ }
+
+ for (int b = 0; b < TEST_BLOCK_COUNT; b++) {
+ basic_erase_program_read_test(blockD, block_size, write_block, read_block, addrwidth);
+ }
+
+ err = blockD.deinit();
+ TEST_ASSERT_EQUAL(0, err);
+
+end:
+ delete[] write_block;
+ delete[] read_block;
+}
+
+void test_qspif_unaligned_erase()
+{
+
+ utest_printf("\nTest Unaligned Erase Starts..\n");
+
+ QSPIFBlockDevice blockD(QSPI_FLASH1_IO0, QSPI_FLASH1_IO1, QSPI_FLASH1_IO2, QSPI_FLASH1_IO3,
+ QSPI_FLASH1_SCK, QSPI_FLASH1_CSN, QSPIF_POLARITY_MODE_0, MBED_CONF_QSPIF_QSPI_FREQ);
+
+ int err = blockD.init();
+ TEST_ASSERT_EQUAL(0, err);
+
+ for (unsigned atr = 0; atr < sizeof(ATTRS) / sizeof(ATTRS[0]); atr++) {
+ static const char *prefixes[] = {"", "k", "M", "G"};
+ for (int i_ind = 3; i_ind >= 0; i_ind--) {
+ bd_size_t size = (blockD.*ATTRS[atr].method)();
+ if (size >= (1ULL << 10 * i_ind)) {
+ utest_printf("%s: %llu%sbytes (%llubytes)\n",
+ ATTRS[atr].name, size >> 10 * i_ind, prefixes[i_ind], size);
+ break;
+ }
+ }
+ }
+
+ bd_addr_t addr = 0;
+ bd_size_t sector_erase_size = blockD.get_erase_size(addr);
+ unsigned addrwidth = ceil(log(float(blockD.size() - 1)) / log(float(16))) + 1;
+
+ utest_printf("\ntest %0*llx:%llu...", addrwidth, addr, sector_erase_size);
+
+ //unaligned start address
+ addr += 1;
+ err = blockD.erase(addr, sector_erase_size - 1);
+ TEST_ASSERT_EQUAL(QSPIF_BD_ERROR_INVALID_ERASE_PARAMS, err);
+
+ err = blockD.erase(addr, sector_erase_size);
+ TEST_ASSERT_EQUAL(QSPIF_BD_ERROR_INVALID_ERASE_PARAMS, err);
+
+ err = blockD.erase(addr, 1);
+ TEST_ASSERT_EQUAL(QSPIF_BD_ERROR_INVALID_ERASE_PARAMS, err);
+
+ //unaligned end address
+ addr = 0;
+
+ err = blockD.erase(addr, 1);
+ TEST_ASSERT_EQUAL(QSPIF_BD_ERROR_INVALID_ERASE_PARAMS, err);
+
+ err = blockD.erase(addr, sector_erase_size + 1);
+ TEST_ASSERT_EQUAL(QSPIF_BD_ERROR_INVALID_ERASE_PARAMS, err);
+
+ //erase size exceeds flash device size
+ err = blockD.erase(addr, blockD.size() + 1);
+ TEST_ASSERT_EQUAL(QSPIF_BD_ERROR_INVALID_ERASE_PARAMS, err);
+
+ // Valid erase
+ err = blockD.erase(addr, sector_erase_size);
+ TEST_ASSERT_EQUAL(QSPIF_BD_ERROR_OK, err);
+
+ err = blockD.deinit();
+ TEST_ASSERT_EQUAL(0, err);
+}
+
+
+
+static void test_qspif_thread_job(void *vBlockD/*, int thread_num*/)
+{
+ static int thread_num = 0;
+ thread_num++;
+ QSPIFBlockDevice *blockD = (QSPIFBlockDevice *)vBlockD;
+ utest_printf("\n Thread %d Started \n", thread_num);
+
+ bd_size_t block_size = blockD->get_erase_size();
+ unsigned addrwidth = ceil(log(float(blockD->size() - 1)) / log(float(16))) + 1;
+
+ uint8_t *write_block = new (std::nothrow) uint8_t[block_size];
+ uint8_t *read_block = new (std::nothrow) uint8_t[block_size];
+ if (!write_block || !read_block) {
+ utest_printf("\n Not enough memory for test");
+ goto end;
+ }
+
+ for (int b = 0; b < TEST_BLOCK_COUNT; b++) {
+ basic_erase_program_read_test((*blockD), block_size, write_block, read_block, addrwidth);
+ }
+
+end:
+ delete[] write_block;
+ delete[] read_block;
+}
+
+void test_qspif_multi_threads()
+{
+
+ utest_printf("\nTest Multi Threaded Erase/Program/Read Starts..\n");
+
+ QSPIFBlockDevice blockD(QSPI_FLASH1_IO0, QSPI_FLASH1_IO1, QSPI_FLASH1_IO2, QSPI_FLASH1_IO3,
+ QSPI_FLASH1_SCK, QSPI_FLASH1_CSN, QSPIF_POLARITY_MODE_0, MBED_CONF_QSPIF_QSPI_FREQ);
+
+ int err = blockD.init();
+ TEST_ASSERT_EQUAL(0, err);
+
+ for (unsigned atr = 0; atr < sizeof(ATTRS) / sizeof(ATTRS[0]); atr++) {
+ static const char *prefixes[] = {"", "k", "M", "G"};
+ for (int i_ind = 3; i_ind >= 0; i_ind--) {
+ bd_size_t size = (blockD.*ATTRS[atr].method)();
+ if (size >= (1ULL << 10 * i_ind)) {
+ utest_printf("%s: %llu%sbytes (%llubytes)\n",
+ ATTRS[atr].name, size >> 10 * i_ind, prefixes[i_ind], size);
+ break;
+ }
+ }
+ }
+
+ rtos::Thread qspif_bd_thread[QSPIF_TEST_NUM_OF_THREADS];
+
+ osStatus threadStatus;
+ int i_ind;
+
+ for (i_ind = 0; i_ind < QSPIF_TEST_NUM_OF_THREADS; i_ind++) {
+ threadStatus = qspif_bd_thread[i_ind].start(test_qspif_thread_job, (void *)&blockD);
+ if (threadStatus != 0) {
+ utest_printf("\n Thread %d Start Failed!", i_ind + 1);
+ }
+ }
+
+ for (i_ind = 0; i_ind < QSPIF_TEST_NUM_OF_THREADS; i_ind++) {
+ qspif_bd_thread[i_ind].join();
+ }
+
+ err = blockD.deinit();
+ TEST_ASSERT_EQUAL(0, err);
+}
+
+
+
+
+// Test setup
+utest::v1::status_t test_setup(const size_t number_of_cases)
+{
+ GREENTEA_SETUP(60, "default_auto");
+ return verbose_test_setup_handler(number_of_cases);
+}
+
+Case cases[] = {
+ Case("Testing unaligned erase blocks", test_qspif_unaligned_erase),
+ Case("Testing read write random blocks", test_qspif_random_program_read_erase),
+ Case("Testing Multi Threads Erase Program Read", test_qspif_multi_threads)
+};
+
+Specification specification(test_setup, cases);
+
+
+int main()
+{
+ mbed_trace_init();
+ utest_printf("MAIN STARTS\n");
+ return !Harness::run(specification);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/storage/COMPONENT_QSPIF/mbed_lib.json Mon Mar 11 11:28:07 2019 +0000
@@ -0,0 +1,30 @@
+{
+"name": "qspif",
+ "config": {
+ "QSPI_IO0": "QSPI_FLASH1_IO0",
+ "QSPI_IO1": "QSPI_FLASH1_IO1",
+ "QSPI_IO2": "QSPI_FLASH1_IO2",
+ "QSPI_IO3": "QSPI_FLASH1_IO3",
+ "QSPI_SCK": "QSPI_FLASH1_SCK",
+ "QSPI_CSN": "QSPI_FLASH1_CSN",
+ "QSPI_POLARITY_MODE": 0,
+ "QSPI_FREQ": "40000000"
+ },
+ "target_overrides": {
+ "DISCO_F413ZH": {
+ "QSPI_FREQ": "80000000"
+ },
+ "DISCO_L475VG_IOT01A": {
+ "QSPI_FREQ": "8000000"
+ },
+ "DISCO_L476VG": {
+ "QSPI_FREQ": "80000000"
+ },
+ "DISCO_F469NI": {
+ "QSPI_FREQ": "80000000"
+ },
+ "NRF52840_DK": {
+ "QSPI_FREQ": "32000000"
+ }
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/storage/MySystemStorage.cpp Mon Mar 11 11:28:07 2019 +0000
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2018 ARM Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BlockDevice.h"
+#include "FileSystem.h"
+#include "FATFileSystem.h"
+#include "LittleFileSystem.h"
+
+#if COMPONENT_SPIF
+#include "SPIFBlockDevice.h"
+#endif
+
+#if COMPONENT_QSPIF
+#include "QSPIFBlockDevice.h"
+#endif
+
+#if COMPONENT_DATAFLASH
+#include "DataFlashBlockDevice.h"
+#endif
+
+#if COMPONENT_SD
+#include "SDBlockDevice.h"
+#endif
+
+#if COMPONENT_FLASHIAP
+#include "FlashIAPBlockDevice.h"
+#endif
+
+#if COMPONENT_NUSD
+#include "NuSDBlockDevice.h"
+#endif
+
+using namespace mbed;
+
+// Align a value to a specified size.
+// Parameters :
+// val - [IN] Value.
+// size - [IN] Size.
+// Return : Aligned value.
+static inline uint32_t align_up(uint32_t val, uint32_t size)
+{
+ return (((val - 1) / size) + 1) * size;
+}
+
+BlockDevice *BlockDevice::get_default_instance()
+{
+#if COMPONENT_SPIF
+
+ static SPIFBlockDevice default_bd(
+ MBED_CONF_SPIF_DRIVER_SPI_MOSI,
+ MBED_CONF_SPIF_DRIVER_SPI_MISO,
+ MBED_CONF_SPIF_DRIVER_SPI_CLK,
+ MBED_CONF_SPIF_DRIVER_SPI_CS,
+ MBED_CONF_SPIF_DRIVER_SPI_FREQ
+ );
+
+ return &default_bd;
+
+#elif COMPONENT_QSPIF
+
+ static QSPIFBlockDevice default_bd(
+ MBED_CONF_QSPIF_QSPI_IO0,
+ MBED_CONF_QSPIF_QSPI_IO1,
+ MBED_CONF_QSPIF_QSPI_IO2,
+ MBED_CONF_QSPIF_QSPI_IO3,
+ MBED_CONF_QSPIF_QSPI_SCK,
+ MBED_CONF_QSPIF_QSPI_CSN,
+ MBED_CONF_QSPIF_QSPI_POLARITY_MODE,
+ MBED_CONF_QSPIF_QSPI_FREQ
+ );
+
+ return &default_bd;
+
+#elif COMPONENT_DATAFLASH
+
+ static DataFlashBlockDevice default_bd(
+ MBED_CONF_DATAFLASH_SPI_MOSI,
+ MBED_CONF_DATAFLASH_SPI_MISO,
+ MBED_CONF_DATAFLASH_SPI_CLK,
+ MBED_CONF_DATAFLASH_SPI_CS
+ );
+
+ return &default_bd;
+
+#elif COMPONENT_SD
+
+ static SDBlockDevice default_bd(
+ MBED_CONF_SD_SPI_MOSI,
+ MBED_CONF_SD_SPI_MISO,
+ MBED_CONF_SD_SPI_CLK,
+ MBED_CONF_SD_SPI_CS
+ );
+
+ return &default_bd;
+
+#elif COMPONENT_NUSD
+
+ static NuSDBlockDevice default_bd;
+
+ return &default_bd;
+
+#elif COMPONENT_FLASHIAP
+
+#if (MBED_CONF_FLASHIAP_BLOCK_DEVICE_SIZE == 0) && (MBED_CONF_FLASHIAP_BLOCK_DEVICE_BASE_ADDRESS == 0xFFFFFFFF)
+
+ size_t flash_size;
+ uint32_t start_address;
+ uint32_t bottom_address;
+ FlashIAP flash;
+
+ int ret = flash.init();
+ if (ret != 0) {
+ return 0;
+ }
+
+ //Find the start of first sector after text area
+ bottom_address = align_up(FLASHIAP_ROM_END, flash.get_sector_size(FLASHIAP_ROM_END));
+ start_address = flash.get_flash_start();
+ flash_size = flash.get_flash_size();
+
+ ret = flash.deinit();
+
+ static FlashIAPBlockDevice default_bd(bottom_address, start_address + flash_size - bottom_address);
+
+#else
+
+ static FlashIAPBlockDevice default_bd;
+
+#endif
+
+ return &default_bd;
+
+#else
+
+ return NULL;
+
+#endif
+
+}
+
+FileSystem *FileSystem::get_default_instance()
+{
+#if COMPONENT_SPIF || COMPONENT_QSPIF || COMPONENT_DATAFLASH || COMPONENT_NUSD
+
+ static LittleFileSystem flash("flash", BlockDevice::get_default_instance());
+ flash.set_as_default();
+
+ return &flash;
+
+#elif COMPONENT_SD
+
+ static FATFileSystem sdcard("sd", BlockDevice::get_default_instance());
+ sdcard.set_as_default();
+
+ return &sdcard;
+
+#elif COMPONENT_FLASHIAP
+
+ static LittleFileSystem flash("flash", BlockDevice::get_default_instance());
+ flash.set_as_default();
+
+ return &flash;
+
+#else
+
+ return NULL;
+
+#endif
+
+}
--- a/mbed-os.lib Sat Mar 09 00:46:54 2019 +0000 +++ b/mbed-os.lib Mon Mar 11 11:28:07 2019 +0000 @@ -1,1 +1,1 @@ -https://github.com/ARMmbed/mbed-os/#51d55508e8400b60af467005646c4e2164738d48 +https://github.com/ARMmbed/mbed-os/#2fd0c5cfbd83fce62da6308f9d64c0ab64e1f0d6
--- a/targets/TARGET_STM32L475xG_SRAM2/TARGET_MTB_STM_L475/PeripheralNames.h Sat Mar 09 00:46:54 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,96 +0,0 @@
-/* mbed Microcontroller Library
-
-* SPDX-License-Identifier: BSD-3-Clause
- *******************************************************************************
- * Copyright (c) 2017, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- ADC_1 = (int)ADC1_BASE,
- ADC_2 = (int)ADC2_BASE,
- ADC_3 = (int)ADC3_BASE
-} ADCName;
-
-typedef enum {
- DAC_1 = (int)DAC_BASE
-} DACName;
-
-typedef enum {
- UART_1 = (int)USART1_BASE,
- UART_2 = (int)USART2_BASE,
- UART_3 = (int)USART3_BASE,
- UART_4 = (int)UART4_BASE,
- UART_5 = (int)UART5_BASE,
- LPUART_1 = (int)LPUART1_BASE
-} UARTName;
-
-typedef enum {
- SPI_1 = (int)SPI1_BASE,
- SPI_2 = (int)SPI2_BASE,
- SPI_3 = (int)SPI3_BASE
-} SPIName;
-
-typedef enum {
- I2C_1 = (int)I2C1_BASE,
- I2C_2 = (int)I2C2_BASE,
- I2C_3 = (int)I2C3_BASE
-} I2CName;
-
-typedef enum {
- PWM_1 = (int)TIM1_BASE,
- PWM_2 = (int)TIM2_BASE,
- PWM_3 = (int)TIM3_BASE,
- PWM_4 = (int)TIM4_BASE,
- PWM_5 = (int)TIM5_BASE,
- PWM_8 = (int)TIM8_BASE,
- PWM_15 = (int)TIM15_BASE,
- PWM_16 = (int)TIM16_BASE,
- PWM_17 = (int)TIM17_BASE
-} PWMName;
-
-typedef enum {
- CAN_1 = (int)CAN1_BASE
-} CANName;
-
-typedef enum {
- QSPI_1 = (int)QSPI_R_BASE,
-} QSPIName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_STM32L475xG_SRAM2/TARGET_MTB_STM_L475/PeripheralPins.c Sat Mar 09 00:46:54 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,370 +0,0 @@
-/* mbed Microcontroller Library
-
-* SPDX-License-Identifier: BSD-3-Clause
- *******************************************************************************
- * Copyright (c) 2018, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#include "PeripheralPins.h"
-#include "mbed_toolchain.h"
-
-//==============================================================================
-// Notes
-//
-// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
-// HW peripheral instances. You can use them the same way as any other "normal"
-// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
-// pinout image on mbed.org.
-//
-// - The pins which are connected to other components present on the board have
-// the comment "Connected to xxx". The pin function may not work properly in this
-// case. These pins may not be displayed on the board pinout image on mbed.org.
-// Please read the board reference manual and schematic for more information.
-//
-// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
-// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
-//
-//==============================================================================
-
-
-//*** ADC ***
-
-MBED_WEAK const PinMap PinMap_ADC[] = {
- {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
- {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
- {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
- {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6
- {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
- {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7
- {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
- {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8
- {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
- {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
- {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
- {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10
- {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
- {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11
- {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
- {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12
- {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
- {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15
- {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
- {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16
- {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
- {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1
- {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1
- {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
- {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2
- {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2
- {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
- {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3
- {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3
- {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
- {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
- {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4
- {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
- {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13
- {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
- {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
- {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 17, 0)},
- {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 0, 0)},
- {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 18, 0)},
- {NC, NC, 0}
-};
-
-//*** DAC ***
-
-MBED_WEAK const PinMap PinMap_DAC[] = {
- {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 //
- {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 //
- {NC, NC, 0}
-};
-
-//*** I2C ***
-
-MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
- {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
- {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
- {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
- {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
- {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
- {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
- {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
- {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
- {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
- {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
- {NC, NC, 0}
-};
-
-//*** PWM ***
-
-// TIM5 cannot be used because already used by the us_ticker
-MBED_WEAK const PinMap PinMap_PWM[] = {
- {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
-// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
- {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
-// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
- {PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
- {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
-// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
- {PA_2_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1
- {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
-// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
- {PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
- {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
- {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
- {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
- {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
- {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
- {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
- {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
- {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
- {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
- {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
- {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
- {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
- {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
- {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
- {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
- {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
- {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
- {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
- {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
- {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
- {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
- {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
-// {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
-// {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N
-// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
-// {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N
- {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
- {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
- {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
- {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
- {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
- {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
- {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
- {PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
- {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
- {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
- {PB_14_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1
- {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
- {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
- {PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
- {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
- {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
- {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
- {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
- {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
- {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
- {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
- {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
- {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
- {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
- {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
- {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
- {PE_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
- {PE_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
- {PE_3, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
- {PE_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
- {PE_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
- {PE_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
- {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
- {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
- {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
- {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
- {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
- {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
- {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
- {NC, NC, 0}
-};
-
-//*** SERIAL ***
-
-MBED_WEAK const PinMap PinMap_UART_TX[] = {
- {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
- {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
- {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
- {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
- {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
- {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
- {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
- {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
- {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
- {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_UART_RX[] = {
- {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
- {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
- {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
- {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
- {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
- {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
- {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
- {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
- {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
- {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_UART_RTS[] = {
- {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
- {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
- {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
- {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
- {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
- {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
- {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
- {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_UART_CTS[] = {
- {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
- {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
- {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
- {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
- {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
- {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
- {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
- {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
- {NC, NC, 0}
-};
-
-//*** SPI ***
-
-MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
- {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
- {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
- {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
- {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
- {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
- {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
- {PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
- {PE_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
- {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
- {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
- {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
- {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
- {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
- {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
- {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
- {PE_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
- {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
- {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
- {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
- {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
- {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
- {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
- {PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
- {PE_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
- {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
- {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
- {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
- {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
- {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
- {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
- {PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
- {PE_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
- {NC, NC, 0}
-};
-
-//*** CAN ***
-
-MBED_WEAK const PinMap PinMap_CAN_RD[] = {
- {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
- {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
- {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_CAN_TD[] = {
- {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
- {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
- {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
- {NC, NC, 0}
-};
-
-//*** QUADSPI ***
-
-MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
- {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
- {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
- {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
- {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
- {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
- {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
- {PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
- {PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
- {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
- {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
- {NC, NC, 0}
-};
-
-MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
- {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS
- {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS
- {NC, NC, 0}
-};
--- a/targets/TARGET_STM32L475xG_SRAM2/TARGET_MTB_STM_L475/PinNames.h Sat Mar 09 00:46:54 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,323 +0,0 @@
-/* mbed Microcontroller Library
-
-* SPDX-License-Identifier: BSD-3-Clause
- *******************************************************************************
- * Copyright (c) 2018, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-#include "PinNamesTypes.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- ALT0 = 0x100,
- ALT1 = 0x200,
- ALT2 = 0x300,
- ALT3 = 0x400
-} ALTx;
-
-typedef enum {
- PA_0 = 0x00,
- PA_0_ALT0 = PA_0 | ALT0,
- PA_1 = 0x01,
- PA_1_ALT0 = PA_1 | ALT0,
- PA_2 = 0x02,
- PA_2_ALT0 = PA_2 | ALT0,
- PA_3 = 0x03,
- PA_3_ALT0 = PA_3 | ALT0,
- PA_4 = 0x04,
- PA_4_ALT0 = PA_4 | ALT0,
- PA_5 = 0x05,
- PA_5_ALT0 = PA_5 | ALT0,
- PA_6 = 0x06,
- PA_6_ALT0 = PA_6 | ALT0,
- PA_7 = 0x07,
- PA_7_ALT0 = PA_7 | ALT0,
- PA_7_ALT1 = PA_7 | ALT1,
- PA_7_ALT2 = PA_7 | ALT2,
- PA_8 = 0x08,
- PA_9 = 0x09,
- PA_10 = 0x0A,
- PA_11 = 0x0B,
- PA_12 = 0x0C,
- PA_13 = 0x0D,
- PA_14 = 0x0E,
- PA_15 = 0x0F,
- PA_15_ALT0 = PA_15 | ALT0,
-
- PB_0 = 0x10,
- PB_0_ALT0 = PB_0 | ALT0,
- PB_0_ALT1 = PB_0 | ALT1,
- PB_1 = 0x11,
- PB_1_ALT0 = PB_1 | ALT0,
- PB_1_ALT1 = PB_1 | ALT1,
- PB_2 = 0x12,
- PB_3 = 0x13,
- PB_3_ALT0 = PB_3 | ALT0,
- PB_4 = 0x14,
- PB_4_ALT0 = PB_4 | ALT0,
- PB_5 = 0x15,
- PB_5_ALT0 = PB_5 | ALT0,
- PB_6 = 0x16,
- PB_6_ALT0 = PB_6 | ALT0,
- PB_7 = 0x17,
- PB_7_ALT0 = PB_7 | ALT0,
- PB_8 = 0x18,
- PB_8_ALT0 = PB_8 | ALT0,
- PB_9 = 0x19,
- PB_9_ALT0 = PB_9 | ALT0,
- PB_10 = 0x1A,
- PB_11 = 0x1B,
- PB_12 = 0x1C,
- PB_13 = 0x1D,
- PB_13_ALT0 = PB_13 | ALT0,
- PB_14 = 0x1E,
- PB_14_ALT0 = PB_14 | ALT0,
- PB_14_ALT1 = PB_14 | ALT1,
- PB_15 = 0x1F,
- PB_15_ALT0 = PB_15 | ALT0,
- PB_15_ALT1 = PB_15 | ALT1,
-
- PC_0 = 0x20,
- PC_0_ALT0 = PC_0 | ALT0,
- PC_0_ALT1 = PC_0 | ALT1,
- PC_1 = 0x21,
- PC_1_ALT0 = PC_1 | ALT0,
- PC_1_ALT1 = PC_1 | ALT1,
- PC_2 = 0x22,
- PC_2_ALT0 = PC_2 | ALT0,
- PC_2_ALT1 = PC_2 | ALT1,
- PC_3 = 0x23,
- PC_3_ALT0 = PC_3 | ALT0,
- PC_3_ALT1 = PC_3 | ALT1,
- PC_4 = 0x24,
- PC_4_ALT0 = PC_4 | ALT0,
- PC_5 = 0x25,
- PC_5_ALT0 = PC_5 | ALT0,
- PC_6 = 0x26,
- PC_6_ALT0 = PC_6 | ALT0,
- PC_7 = 0x27,
- PC_7_ALT0 = PC_7 | ALT0,
- PC_8 = 0x28,
- PC_8_ALT0 = PC_8 | ALT0,
- PC_9 = 0x29,
- PC_9_ALT0 = PC_9 | ALT0,
- PC_10 = 0x2A,
- PC_10_ALT0 = PC_10 | ALT0,
- PC_11 = 0x2B,
- PC_11_ALT0 = PC_11 | ALT0,
- PC_12 = 0x2C,
- PC_13 = 0x2D,
- PC_14 = 0x2E,
- PC_15 = 0x2F,
-
- PD_0 = 0x30,
- PD_1 = 0x31,
- PD_2 = 0x32,
- PD_3 = 0x33,
- PD_4 = 0x34,
- PD_5 = 0x35,
- PD_6 = 0x36,
- PD_7 = 0x37,
- PD_8 = 0x38,
- PD_9 = 0x39,
- PD_10 = 0x3A,
- PD_11 = 0x3B,
- PD_12 = 0x3C,
- PD_13 = 0x3D,
- PD_14 = 0x3E,
- PD_15 = 0x3F,
-
- PE_0 = 0x40,
- PE_1 = 0x41,
- PE_2 = 0x42,
- PE_3 = 0x43,
- PE_4 = 0x44,
- PE_5 = 0x45,
- PE_6 = 0x46,
- PE_7 = 0x47,
- PE_8 = 0x48,
- PE_9 = 0x49,
- PE_10 = 0x4A,
- PE_11 = 0x4B,
- PE_12 = 0x4C,
- PE_13 = 0x4D,
- PE_14 = 0x4E,
- PE_15 = 0x4F,
-
- PH_0 = 0x70,
- PH_1 = 0x71,
-
- // ADC internal channels
- ADC_TEMP = 0xF0,
- ADC_VREF = 0xF1,
- ADC_VBAT = 0xF2,
-
- // Not connected
- NC = (int)0xFFFFFFFF,
-
- // STDIO for console print
-#ifdef MBED_CONF_TARGET_STDIO_UART_TX
- STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
-#else
- STDIO_UART_TX = PA_9,
-#endif
-#ifdef MBED_CONF_TARGET_STDIO_UART_RX
- STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
-#else
- STDIO_UART_RX = PA_10,
-#endif
-
- // Generic signals namings
- LED1 = PE_2, // Red LED (LD1)
- LED2 = PE_3, // Blue LED (LD2)
- LED3 = PE_4, // Green LED (LD3)
-
- LED_RED = LED1,
- LED_BLUE = LED2,
- LED_GREEN = LED3,
-
- USER_BUTTON = PD_4,
- BUTTON1 = USER_BUTTON,
-
- USBTX = STDIO_UART_TX,
- USBRX = STDIO_UART_RX,
-
- UART1_TX = PA_2,
- UART1_RX = PA_3,
- UART1_CTS = PA_0,
- UART1_RTS = PA_1,
-
- SERIAL_TX = UART1_TX,
- SERIAL_RX = UART1_RX,
- SERIAL_CTS = UART1_CTS,
- SERIAL_RTS = UART1_RTS,
-
- UART2_TX = PC_4,
- UART2_RX = PC_5,
-
- I2C0_SCL = PB_6,
- I2C0_SDA = PB_7,
-
- I2C1_SCL = PC_0,
- I2C1_SDA = PC_1,
-
- SPI0_MOSI = PB_5,
- SPI0_MISO = PA_6,
- SPI0_SCK = PA_5,
- SPI0_CS = PA_15,
-
- SPI1_MOSI = PB_15,
- SPI1_MISO = PB_14,
- SPI1_SCK = PD_3,
- SPI1_CS = PB_9,
-
- SPI2_MOSI = PC_12,
- SPI2_MISO = PC_11,
- SPI2_SCK = PC_10,
- SPI2_CS = PA_4,
-
- //Default SPI
- SPI_MOSI = SPI0_MOSI,
- SPI_MISO = SPI0_MISO,
- SPI_SCK = SPI0_SCK,
- /****************
- //IMPORTANT NOTE: The default CS for SPI is marked as the CS line for the SPI Flash
- //on the MCB reference hardware. Please change as appropriate.
- ****************/
- SPI_CS = PD_2,
-
- CAN1_RX = PD_0, //Test point on MCB
- CAN1_TX = PD_1, //Test point on MCB
-
- /**** OSCILLATOR pins ****/
- RCC_OSC32_IN = PC_14,
- RCC_OSC32_OUT = PC_15,
- RCC_OSC_IN = PH_0,
- RCC_OSC_OUT = PH_1,
-
- /**** DEBUG pins ****/
- SYS_JTCK_SWCLK = PA_14,
- SYS_JTDI = PA_15,
- SYS_JTDO_SWO = PB_3,
- SYS_JTMS_SWDIO = PA_13,
- SYS_JTRST = PB_4,
- SYS_PVD_IN = PB_7,
- SYS_TRACECLK = PE_2,
- SYS_TRACED0 = PE_3,
- SYS_TRACED1 = PE_4,
- SYS_TRACED2 = PE_5,
- SYS_TRACED3 = PE_6,
- SYS_WKUP1 = PA_0,
- SYS_WKUP2 = PC_13,
- SYS_WKUP3 = PE_6,
- SYS_WKUP4 = PA_2,
- SYS_WKUP5 = PC_5,
-
- //MTB aliases
- TX1 = PA_2,
- RX1 = PA_3,
- SDA1 = PB_7,
- SCL1 = PB_6,
- MOSI1 = PB_5,
- MISO1 = PA_6,
- SCK1 = PA_5,
- GP0 = PD_4,
- GP1 = PC_10,
- AIN0 = PA_0, //CTS
- AIN1 = PA_1, // RTS
- AIN2 = PB_0,
-
- GP2 = PE_5, //SD card CS
- GP3 = PE_6,
- SCK2 = PD_3,
- MISO2 = PB_14,
- MOSI2 = PB_15,
- SCL2 = PC_1,
- SDA2 = PC_0,
- RX2 = PC_5,
- TX2 = PC_4,
- GP4 = PE_9,
- GP5 = PE_10, //A0 for LCD on MTB
- GP6 = PE_13, //RESET for LCD on MTB
- GP7 = PE_14, //LCD CS
- GP8 = PE_15
-
-} PinName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_STM32L475xG_SRAM2/TARGET_MTB_STM_L475/system_clock.c Sat Mar 09 00:46:54 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,372 +0,0 @@
-/* mbed Microcontroller Library
-* Copyright (c) 2006-2019 ARM Limited
-
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*/
-
-/**
- * This file configures the system clock as follows:
- *-----------------------------------------------------------------------------
- * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
- * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
- * | 3- USE_PLL_HSI (internal 16 MHz)
- * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
- *-----------------------------------------------------------------------------
- * SYSCLK(MHz) | 80
- * AHBCLK (MHz) | 80
- * APB1CLK (MHz) | 80
- * APB2CLK (MHz) | 80
- * USB capable | YES
- *-----------------------------------------------------------------------------
-**/
-
-#include "stm32l4xx.h"
-#include "nvic_addr.h"
-#include "mbed_error.h"
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-
-
-// clock source is selected with CLOCK_SOURCE in json config
-#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
-#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
-#define USE_PLL_HSI 0x2 // Use HSI internal clock
-#define USE_PLL_MSI 0x1 // Use MSI internal clock
-
-#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
-
-#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
-
-#if ((CLOCK_SOURCE) & USE_PLL_HSI)
-uint8_t SetSysClock_PLL_HSI(void);
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
-
-#if ((CLOCK_SOURCE) & USE_PLL_MSI)
-uint8_t SetSysClock_PLL_MSI(void);
-#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
-
-
-/**
- * @brief Setup the microcontroller system.
- * @param None
- * @retval None
- */
-
-void SystemInit(void)
-{
- /* FPU settings ------------------------------------------------------------*/
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
-#endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set MSION bit */
- RCC->CR |= RCC_CR_MSION;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON , HSION, and PLLON bits */
- RCC->CR &= (uint32_t)0xEAF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x00001000;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIER = 0x00000000;
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-
-/**
- * @brief Configures the System clock source, PLL Multiplier and Divider factors,
- * AHB/APBx prescalers and Flash settings
- * @note This function should be called only once the RCC clock configuration
- * is reset to the default reset state (done in SystemInit() function).
- * @param None
- * @retval None
- */
-
-void SetSysClock(void)
-{
-#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
- /* 1- Try to start with HSE and external clock */
- if (SetSysClock_PLL_HSE(1) == 0)
-#endif
- {
-#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
- /* 2- If fail try to start with HSE and external xtal */
- if (SetSysClock_PLL_HSE(0) == 0)
-#endif
- {
-#if ((CLOCK_SOURCE) & USE_PLL_HSI)
- /* 3- If fail start with HSI clock */
- if (SetSysClock_PLL_HSI() == 0)
-#endif
- {
-#if ((CLOCK_SOURCE) & USE_PLL_MSI)
- /* 4- If fail start with MSI clock */
- if (SetSysClock_PLL_MSI() == 0)
-#endif
- {
- {
- error("SetSysClock failed\n");
- }
- }
- }
- }
- }
-
- // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 1
- HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-#endif
-}
-
-#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
-/******************************************************************************/
-/* PLL (clocked by HSE) used as System clock source */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
- RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
-
- // Used to gain time after DeepSleep in case HSI is used
- if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
- return 0;
- }
-
- // Select MSI as system clock source to allow modification of the PLL configuration
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
- HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-
- // Enable HSE oscillator and activate PLL with HSE as source
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
- if (bypass == 0) {
- RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
- } else {
- RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
- }
- RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
- RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
- RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
- RCC_OscInitStruct.PLL.PLLQ = 2;
- RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
-
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
- return 0; // FAIL
- }
-
- // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
- RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
- return 0; // FAIL
- }
-
- RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
- RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
- if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
- return 0; // FAIL
- }
-
- // Disable MSI Oscillator
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
- RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
- HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
- // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 2
- if (bypass == 0) {
- HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
- } else {
- HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
- }
-#endif
-
- return 1; // OK
-}
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
-
-#if ((CLOCK_SOURCE) & USE_PLL_HSI)
-/******************************************************************************/
-/* PLL (clocked by HSI) used as System clock source */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
- RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
-
- // Select MSI as system clock source to allow modification of the PLL configuration
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
- HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-
- // Enable HSI oscillator and activate PLL with HSI as source
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
- RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
- RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
- RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
- RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
- RCC_OscInitStruct.PLL.PLLQ = 2;
- RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
- return 0; // FAIL
- }
-
- // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
- RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
- return 0; // FAIL
- }
-
- RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
- RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
- if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
- return 0; // FAIL
- }
-
- // Disable MSI Oscillator
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
- RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
- HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
- // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 3
- HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-#endif
-
- return 1; // OK
-}
-#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
-
-#if ((CLOCK_SOURCE) & USE_PLL_MSI)
-/******************************************************************************/
-/* PLL (clocked by MSI) used as System clock source */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_MSI(void)
-{
- RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-
-#if MBED_CONF_TARGET_LSE_AVAILABLE
- // Enable LSE Oscillator to automatically calibrate the MSI clock
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
- RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
- return 0; // FAIL
- }
-
- /* Enable the CSS interrupt in case LSE signal is corrupted or not present */
- HAL_RCCEx_DisableLSECSS();
-#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
-
- /* Enable MSI Oscillator and activate PLL with MSI as source */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
- RCC_OscInitStruct.MSIState = RCC_MSI_ON;
- RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
-
- RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
- RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
- RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
- RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
- RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
- RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
- RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
- return 0; // FAIL
- }
-
-#if MBED_CONF_TARGET_LSE_AVAILABLE
- /* Enable MSI Auto-calibration through LSE */
- HAL_RCCEx_EnableMSIPLLMode();
-#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
-
- /* Select MSI output as USB clock source */
- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
- PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
- HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
- // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
- RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
- return 0; // FAIL
- }
-
- // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 4
- HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
-#endif
-
- return 1; // OK
-}
-#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
--- a/targets/TARGET_STM32L475xG_SRAM2/device/TOOLCHAIN_ARM_MICRO/stm32l475xx.sct Sat Mar 09 00:46:54 2019 +0000
+++ b/targets/TARGET_STM32L475xG_SRAM2/device/TOOLCHAIN_ARM_MICRO/stm32l475xx.sct Mon Mar 11 11:28:07 2019 +0000
@@ -36,13 +36,6 @@
#define MBED_APP_SIZE 0x100000
#endif
-#define MBED_RAM_START 0x20000000
-#define MBED_RAM_SIZE 0x00018000
-#define MBED_CRASH_REPORT_RAM_START (MBED_RAM_START)
-#define MBED_CRASH_REPORT_RAM_SIZE 0x100
-#define MBED_RAM0_START (MBED_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
-#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
-
; 1MB FLASH (0x100000) + 128KB SRAM (0x20000)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
@@ -52,9 +45,7 @@
.ANY (+RO)
}
- RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
- }
- RW_IRAM1 MBED_RAM0_START MBED_RAM0_SIZE { ; RW data 96k L4-SRAM1
+ RW_IRAM1 0x20000000 0x00018000 { ; RW data 96k L4-SRAM1
.ANY (+RW +ZI)
}
; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
--- a/targets/TARGET_STM32L475xG_SRAM2/device/TOOLCHAIN_ARM_STD/startup_stm32l475xx.S Sat Mar 09 00:46:54 2019 +0000 +++ b/targets/TARGET_STM32L475xG_SRAM2/device/TOOLCHAIN_ARM_STD/startup_stm32l475xx.S Mon Mar 11 11:28:07 2019 +0000 @@ -1,388 +1,388 @@ -;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** -;* File Name : startup_stm32l475xx.s -;* Author : MCD Application Team -;* Version : V1.2.0 -;* Date : 28-October-2016 -;* Description : STM32L475xx Ultra Low Power devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -__initial_sp EQU 0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_2_IRQHandler ; ADC1, ADC2 - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 - DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 - DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt - DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt - DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt - DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 - DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 - DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 - DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt - DCD COMP_IRQHandler ; COMP Interrupt - DCD LPTIM1_IRQHandler ; LP TIM1 interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 interrupt - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 - DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD QUADSPI_IRQHandler ; Quad SPI global interrupt - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt - DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TSC_IRQHandler ; Touch Sense Controller global interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD RNG_IRQHandler ; RNG global interrupt - DCD FPU_IRQHandler ; FPU - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_PVM_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_2_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT DFSDM1_FLT3_IRQHandler [WEAK] - EXPORT TIM8_BRK_IRQHandler [WEAK] - EXPORT TIM8_UP_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT ADC3_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDMMC1_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Channel1_IRQHandler [WEAK] - EXPORT DMA2_Channel2_IRQHandler [WEAK] - EXPORT DMA2_Channel3_IRQHandler [WEAK] - EXPORT DMA2_Channel4_IRQHandler [WEAK] - EXPORT DMA2_Channel5_IRQHandler [WEAK] - EXPORT DFSDM1_FLT0_IRQHandler [WEAK] - EXPORT DFSDM1_FLT1_IRQHandler [WEAK] - EXPORT DFSDM1_FLT2_IRQHandler [WEAK] - EXPORT COMP_IRQHandler [WEAK] - EXPORT LPTIM1_IRQHandler [WEAK] - EXPORT LPTIM2_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Channel6_IRQHandler [WEAK] - EXPORT DMA2_Channel7_IRQHandler [WEAK] - EXPORT LPUART1_IRQHandler [WEAK] - EXPORT QUADSPI_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT SAI2_IRQHandler [WEAK] - EXPORT SWPMI1_IRQHandler [WEAK] - EXPORT TSC_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_PVM_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_2_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM15_IRQHandler -TIM1_UP_TIM16_IRQHandler -TIM1_TRG_COM_TIM17_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -DFSDM1_FLT3_IRQHandler -TIM8_BRK_IRQHandler -TIM8_UP_IRQHandler -TIM8_TRG_COM_IRQHandler -TIM8_CC_IRQHandler -ADC3_IRQHandler -FMC_IRQHandler -SDMMC1_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Channel1_IRQHandler -DMA2_Channel2_IRQHandler -DMA2_Channel3_IRQHandler -DMA2_Channel4_IRQHandler -DMA2_Channel5_IRQHandler -DFSDM1_FLT0_IRQHandler -DFSDM1_FLT1_IRQHandler -DFSDM1_FLT2_IRQHandler -COMP_IRQHandler -LPTIM1_IRQHandler -LPTIM2_IRQHandler -OTG_FS_IRQHandler -DMA2_Channel6_IRQHandler -DMA2_Channel7_IRQHandler -LPUART1_IRQHandler -QUADSPI_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -SAI1_IRQHandler -SAI2_IRQHandler -SWPMI1_IRQHandler -TSC_IRQHandler -RNG_IRQHandler -FPU_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** +;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;* File Name : startup_stm32l475xx.s +;* Author : MCD Application Team +;* Version : V1.2.0 +;* Date : 28-October-2016 +;* Description : STM32L475xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DFSDM1_FLT3_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +OTG_FS_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +RNG_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM32L475xG_SRAM2/device/TOOLCHAIN_ARM_STD/stm32l475xx.sct Sat Mar 09 00:46:54 2019 +0000
+++ b/targets/TARGET_STM32L475xG_SRAM2/device/TOOLCHAIN_ARM_STD/stm32l475xx.sct Mon Mar 11 11:28:07 2019 +0000
@@ -1,66 +1,57 @@
-#! armcc -E
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2015, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-; this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-; this list of conditions and the following disclaimer in the documentation
-; and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-; may be used to endorse or promote products derived from this software
-; without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-#if !defined(MBED_APP_START)
- #define MBED_APP_START 0x08000000
-#endif
-
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE 0x100000
-#endif
-
-#define MBED_RAM_START 0x20000000
-#define MBED_RAM_SIZE 0x00018000
-#define MBED_CRASH_REPORT_RAM_START (MBED_RAM_START)
-#define MBED_CRASH_REPORT_RAM_SIZE 0x100
-#define MBED_RAM0_START (MBED_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
-#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
-
-
-; 1MB FLASH (0x100000) + 128KB SRAM (0x20000)
-LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
-
- ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
- }
- RW_IRAM1 MBED_RAM0_START MBED_RAM0_SIZE { ; RW data 96k L4-SRAM1
- .ANY (+RW, +Last)
- }
- ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
- RW_IRAM2 (0x10000000+0x188) (0x08000-0x188) { ; RW data 32k L4-ECC-SRAM2 retained in standby
- .ANY (+ZI)
- }
-
-}
-
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x100000
+#endif
+
+; 1MB FLASH (0x100000) + 128KB SRAM (0x20000)
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 0x20000000 0x00018000 { ; RW data 96k L4-SRAM1
+ .ANY (+RW, +Last)
+ }
+ ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+ RW_IRAM2 (0x10000000+0x188) (0x08000-0x188) { ; RW data 32k L4-ECC-SRAM2 retained in standby
+ .ANY (+ZI)
+ }
+
+}
+
--- a/targets/TARGET_STM32L475xG_SRAM2/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld Sat Mar 09 00:46:54 2019 +0000
+++ b/targets/TARGET_STM32L475xG_SRAM2/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld Mon Mar 11 11:28:07 2019 +0000
@@ -1,181 +1,168 @@
-#if !defined(MBED_APP_START)
- #define MBED_APP_START 0x08000000
-#endif
-
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE 1024k
-#endif
-
-M_CRASH_DATA_RAM_SIZE = 0x100;
-
-/* Linker script to configure memory regions. */
-MEMORY
-{
- FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
- SRAM2 (rwx) : ORIGIN = 0x10000188, LENGTH = 32k - 0x188
- SRAM1 (rwx) : ORIGIN = 0x20000000, LENGTH = 96k
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __end__
- * end
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- * _estack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- .text :
- {
- KEEP(*(.isr_vector))
- *(.text*)
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- KEEP(*(.eh_frame*))
- } > FLASH
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > FLASH
-
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > FLASH
- __exidx_end = .;
-
- __etext = .;
- _sidata = .;
-
- .crash_data_ram :
- {
- . = ALIGN(8);
- __CRASH_DATA_RAM__ = .;
- __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */
- KEEP(*(.keep.crash_data_ram))
- *(.m_crash_data_ram) /* This is a user defined section */
- . += M_CRASH_DATA_RAM_SIZE;
- . = ALIGN(8);
- __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */
- } > SRAM1
-
- .data : AT (__etext)
- {
- __data_start__ = .;
- _sdata = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(8);
- /* preinit data */
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
-
- . = ALIGN(8);
- /* init data */
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE_HIDDEN (__init_array_end = .);
-
-
- . = ALIGN(8);
- /* finit data */
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE_HIDDEN (__fini_array_end = .);
-
- KEEP(*(.jcr*))
- . = ALIGN(8);
- /* All data end */
- __data_end__ = .;
- _edata = .;
-
- } > SRAM1
-
- .bss :
- {
- . = ALIGN(8);
- __bss_start__ = .;
- _sbss = .;
- *(.bss*)
- *(COMMON)
- . = ALIGN(8);
- __bss_end__ = .;
- _ebss = .;
- } > SRAM2
-
- .heap (COPY):
- {
- __end__ = .;
- end = __end__;
- *(.heap*)
- . += (ORIGIN(SRAM1) + LENGTH(SRAM1) - .);
- __HeapLimit = .;
- } > SRAM1
- PROVIDE(__heap_size = SIZEOF(.heap));
- PROVIDE(__mbed_sbrk_start = ADDR(.heap));
- PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
- /* Check if data + heap exceeds RAM1 limit */
- ASSERT((ORIGIN(SRAM1)+LENGTH(SRAM1)) >= __HeapLimit, "SRAM1 overflow")
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy (COPY):
- {
- *(.stack*)
- } > SRAM2
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(SRAM2) + LENGTH(SRAM2);
- _estack = __StackTop;
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
- /* Check if stack exceeds RAM2 limit */
- ASSERT((ORIGIN(SRAM2)+LENGTH(SRAM2)) >= __StackLimit, "SRAM2 overflow")
-
-}
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 1024k
+#endif
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ SRAM2 (rwx) : ORIGIN = 0x10000188, LENGTH = 32k - 0x188
+ SRAM1 (rwx) : ORIGIN = 0x20000000, LENGTH = 96k
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(8);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > SRAM1
+
+ .bss :
+ {
+ . = ALIGN(8);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ _ebss = .;
+ } > SRAM2
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ . += (ORIGIN(SRAM1) + LENGTH(SRAM1) - .);
+ __HeapLimit = .;
+ } > SRAM1
+ PROVIDE(__heap_size = SIZEOF(.heap));
+ PROVIDE(__mbed_sbrk_start = ADDR(.heap));
+ PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
+ /* Check if data + heap exceeds RAM1 limit */
+ ASSERT((ORIGIN(SRAM1)+LENGTH(SRAM1)) >= __HeapLimit, "SRAM1 overflow")
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > SRAM2
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(SRAM2) + LENGTH(SRAM2);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+ /* Check if stack exceeds RAM2 limit */
+ ASSERT((ORIGIN(SRAM2)+LENGTH(SRAM2)) >= __StackLimit, "SRAM2 overflow")
+ /* Check if bss exceeds __StackLimit */
+ ASSERT(__bss_end__ <= __StackLimit, "BSS is too big for RAM2")
+}
--- a/targets/TARGET_STM32L475xG_SRAM2/device/TOOLCHAIN_GCC_ARM/startup_stm32l475xx.S Sat Mar 09 00:46:54 2019 +0000 +++ b/targets/TARGET_STM32L475xG_SRAM2/device/TOOLCHAIN_GCC_ARM/startup_stm32l475xx.S Mon Mar 11 11:28:07 2019 +0000 @@ -1,510 +1,510 @@ -/** - ****************************************************************************** - * @file startup_stm32l475xx.s - * @author MCD Application Team - * @version V1.2.0 - * @date 28-October-2016 - * @brief STM32L475xx devices vector table for GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address, - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata - -.equ BootRAM, 0xF1E0F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* Atollic update: set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - // Calling the crt0 'cold-start' entry point. There __libc_init_array is called - // and when existing hardware_init_hook() and software_init_hook() before - // starting main(). software_init_hook() is available and has to be called due - // to initializsation when using rtos. - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex-M4. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_PVM_IRQHandler - .word TAMP_STAMP_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word CAN1_TX_IRQHandler - .word CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM15_IRQHandler - .word TIM1_UP_TIM16_IRQHandler - .word TIM1_TRG_COM_TIM17_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word DFSDM1_FLT3_IRQHandler - .word TIM8_BRK_IRQHandler - .word TIM8_UP_IRQHandler - .word TIM8_TRG_COM_IRQHandler - .word TIM8_CC_IRQHandler - .word ADC3_IRQHandler - .word FMC_IRQHandler - .word SDMMC1_IRQHandler - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_DAC_IRQHandler - .word TIM7_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_IRQHandler - .word DMA2_Channel5_IRQHandler - .word DFSDM1_FLT0_IRQHandler - .word DFSDM1_FLT1_IRQHandler - .word DFSDM1_FLT2_IRQHandler - .word COMP_IRQHandler - .word LPTIM1_IRQHandler - .word LPTIM2_IRQHandler - .word OTG_FS_IRQHandler - .word DMA2_Channel6_IRQHandler - .word DMA2_Channel7_IRQHandler - .word LPUART1_IRQHandler - .word QUADSPI_IRQHandler - .word I2C3_EV_IRQHandler - .word I2C3_ER_IRQHandler - .word SAI1_IRQHandler - .word SAI2_IRQHandler - .word SWPMI1_IRQHandler - .word TSC_IRQHandler - .word 0 - .word 0 - .word RNG_IRQHandler - .word FPU_IRQHandler - - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_PVM_IRQHandler - .thumb_set PVD_PVM_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM15_IRQHandler - .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM16_IRQHandler - .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM17_IRQHandler - .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak DFSDM1_FLT3_IRQHandler - .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler - - .weak TIM8_BRK_IRQHandler - .thumb_set TIM8_BRK_IRQHandler,Default_Handler - - .weak TIM8_UP_IRQHandler - .thumb_set TIM8_UP_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_IRQHandler - .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak ADC3_IRQHandler - .thumb_set ADC3_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak SDMMC1_IRQHandler - .thumb_set SDMMC1_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_IRQHandler - .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - - .weak DFSDM1_FLT0_IRQHandler - .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler - - .weak DFSDM1_FLT1_IRQHandler - .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler - - .weak DFSDM1_FLT2_IRQHandler - .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler - - .weak COMP_IRQHandler - .thumb_set COMP_IRQHandler,Default_Handler - - .weak LPTIM1_IRQHandler - .thumb_set LPTIM1_IRQHandler,Default_Handler - - .weak LPTIM2_IRQHandler - .thumb_set LPTIM2_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Channel6_IRQHandler - .thumb_set DMA2_Channel6_IRQHandler,Default_Handler - - .weak DMA2_Channel7_IRQHandler - .thumb_set DMA2_Channel7_IRQHandler,Default_Handler - - .weak LPUART1_IRQHandler - .thumb_set LPUART1_IRQHandler,Default_Handler - - .weak QUADSPI_IRQHandler - .thumb_set QUADSPI_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak SAI1_IRQHandler - .thumb_set SAI1_IRQHandler,Default_Handler - - .weak SAI2_IRQHandler - .thumb_set SAI2_IRQHandler,Default_Handler - - .weak SWPMI1_IRQHandler - .thumb_set SWPMI1_IRQHandler,Default_Handler - - .weak TSC_IRQHandler - .thumb_set TSC_IRQHandler,Default_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + ****************************************************************************** + * @file startup_stm32l475xx.s + * @author MCD Application Team + * @version V1.2.0 + * @date 28-October-2016 + * @brief STM32L475xx devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word DFSDM1_FLT3_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FMC_IRQHandler + .word SDMMC1_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word DFSDM1_FLT0_IRQHandler + .word DFSDM1_FLT1_IRQHandler + .word DFSDM1_FLT2_IRQHandler + .word COMP_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word OTG_FS_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word LPUART1_IRQHandler + .word QUADSPI_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SAI1_IRQHandler + .word SAI2_IRQHandler + .word SWPMI1_IRQHandler + .word TSC_IRQHandler + .word 0 + .word 0 + .word RNG_IRQHandler + .word FPU_IRQHandler + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM32L475xG_SRAM2/device/TOOLCHAIN_IAR/stm32l475xx.icf Sat Mar 09 00:46:54 2019 +0000 +++ b/targets/TARGET_STM32L475xG_SRAM2/device/TOOLCHAIN_IAR/stm32l475xx.icf Mon Mar 11 11:28:07 2019 +0000 @@ -12,22 +12,15 @@ define symbol __NVIC_end__ = 0x10000187; define symbol __region_SRAM2_start__ = 0x10000188; define symbol __region_SRAM2_end__ = 0x10007FFF; -define symbol __region_CRASH_DATA_RAM_start__ = 0x20000000; -define symbol __region_CRASH_DATA_RAM_end__ = 0x200000FF; -define symbol __region_SRAM1_start__ = 0x20000100; +define symbol __region_SRAM1_start__ = 0x20000000; define symbol __region_SRAM1_end__ = 0x20017FFF; /* Memory regions */ define memory mem with size = 4G; define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__]; -define region CRASH_DATA_RAM_region = mem:[from __region_CRASH_DATA_RAM_start__ to __region_CRASH_DATA_RAM_end__]; define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__]; -/* Define Crash Data Symbols */ -define exported symbol __CRASH_DATA_RAM_START__ = __region_CRASH_DATA_RAM_start__; -define exported symbol __CRASH_DATA_RAM_END__ = __region_CRASH_DATA_RAM_end__; - /* Stack complete SRAM2 and Heap 2/3 of SRAM1 */ define symbol __size_cstack__ = 0x7e00; define symbol __size_heap__ = 0x10000;