Ivo van Poorten
Library to access LPC17xx peripherals. It uses static inline functions, constant propagation and dead code elimination to be as fast as possible.
Dependents: Chua-VGA Wolfram-1D-VGA WolframRnd-1D-VGA Basin-VGA ... more
Revision 0:7a91348b4a02, committed 2011-07-03
- Comitter:
- Ivop
- Date:
- Sun Jul 03 17:11:55 2011 +0000
- Child:
- 1:bc492a93e116
- Commit message:
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TODO.h Sun Jul 03 17:11:55 2011 +0000 @@ -0,0 +1,20 @@ +/* on a "need to have" basis :) + * + * adc + * can + * dac + * ethernet + * external interrupts + * i2c + * mcpwm + * mpu (memory protection unit) + * quadrature encoder interface + * repetitive interrupt timer + * spi + * ssp + * system timer (systick) + * timer + * usb + * watchdog timer + * + */ \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/clock.h Sun Jul 03 17:11:55 2011 +0000
@@ -0,0 +1,203 @@
+/* Copyright (C) 2010, 2011 by Ivo van Poorten <ivop@euronet.nl>
+ * This file is licensed under the terms of the GNU Lesser
+ * General Public License, version 3.
+ */
+
+/* see chapter 4 of user manual for details on clocks and power */
+
+#ifndef FASTLIB_CLKPWR_H
+#define FASTLIB_CLKPWR_H
+
+#include "fastlib/common.h"
+
+#define FL_CLKSRCSEL ((volatile uint32_t *) 0x400FC10C)
+
+#define FL_PLL0CON ((volatile uint32_t *) 0x400FC080)
+#define FL_PLL0CFG ((volatile uint32_t *) 0x400FC084)
+#define FL_PLL0STAT ((volatile uint32_t *) 0x400FC088)
+#define FL_PLL0FEED ((volatile uint32_t *) 0x400FC08C)
+
+#define FL_PLL1CON ((volatile uint32_t *) 0x400FC0A0)
+#define FL_PLL1CFG ((volatile uint32_t *) 0x400FC0A4)
+#define FL_PLL1STAT ((volatile uint32_t *) 0x400FC0A8)
+#define FL_PLL1FEED ((volatile uint32_t *) 0x400FC0AC)
+
+#define FL_CCLKCFG ((volatile uint32_t *) 0x400FC104)
+#define FL_USBCLKCFG ((volatile uint32_t *) 0x400FC108)
+#define FL_PCLKSEL0 ((volatile uint32_t *) 0x400FC1A8)
+#define FL_PCLKSEL1 ((volatile uint32_t *) 0x400FC1AC)
+
+#define FL_CLKOUTCFG ((volatile uint32_t *) 0x400FC1C8)
+
+/* Internal RC oscillator, nominal frequency is 4MHz
+ * Main oscillator --> mbed: 12MHz slave mode
+ * RTC oscillator --> mbed: FC-135 32.7680kHz 12.5pF
+ */
+
+/* for USB, use only Main oscillator
+ * for CAN over 100 kbit/s, do not use Internal RC oscillator
+ */
+
+#define FL_PLL0_CLOCK_SOURCE_INTERNAL 0
+#define FL_PLL0_CLOCK_SOURCE_MAIN 1
+#define FL_PLL0_CLOCK_SOURCE_RTC 2
+
+static inline void fl_select_pll0_clock_source(const int source) {
+ *FL_CLKSRCSEL = source;
+}
+
+/* PLL0:
+ * input source --> PLL input divider (N) --> PLL multiplier (M)
+ *
+ * input: 32kHz-50MHz -->
+ * N: 1-256 -->
+ * M: 6-512 --> 275MHz-550MHz
+ *
+ * PLL0 output dividers below
+ */
+
+static inline void fl_pll0_control(const int enable, const int connect) {
+ *FL_PLL0CON = enable | (connect<<1);
+}
+
+static inline void fl_pll0_config(const unsigned int N, const unsigned int M) {
+ *FL_PLL0CFG = (M-1) | ((N-1)<<16);
+}
+
+static inline unsigned fl_pll0_get_M(void) {
+ return (*FL_PLL0STAT & 0x7fff) + 1;
+}
+
+static inline unsigned fl_pll0_get_N(void) {
+ return ((*FL_PLL0STAT >> 16) & 0xff) + 1;
+}
+
+static inline int fl_pll0_get_enable(void) {
+ return *FL_PLL0STAT & (1U<<24);
+}
+
+static inline int fl_pll0_get_connect(void) {
+ return *FL_PLL0STAT & (1U<<25);
+}
+
+static inline int fl_pll0_get_lock(void) {
+ return *FL_PLL0STAT & (1U<<26);
+}
+
+static inline void fl_pll0_feed(void) {
+ *FL_PLL0FEED = 0xaa;
+ *FL_PLL0FEED = 0x55;
+}
+
+/* PLL1:
+ * input main oscillator --> PLL multiplier (M) --> output divider (2P)
+ */
+
+static inline void fl_pll1_control(const int enable, const int connect) {
+ *FL_PLL1CON = enable | (connect<<1);
+}
+
+static inline void fl_pll1_config(const unsigned int M, const unsigned int P) {
+ *FL_PLL1CFG = M | (P<<5);
+}
+
+static inline int fl_pll1_get_M(void) {
+ return *FL_PLL1STAT & 0x1f;
+}
+
+static inline int fl_pll1_get_P(void) {
+ return (*FL_PLL1STAT >> 5) & 3;
+}
+
+static inline int fl_pll1_get_enable(void) {
+ return *FL_PLL1STAT & (1U<<8);
+}
+
+static inline int fl_pll1_get_connect(void) {
+ return *FL_PLL1STAT & (1U<<9);
+}
+
+static inline int fl_pll1_get_lock(void) {
+ return *FL_PLL1STAT & (1U<<10);
+}
+
+static inline void fl_pll1_feed(void) {
+ *FL_PLL1FEED = 0xaa;
+ *FL_PLL1FEED = 0x55;
+}
+
+/* PLL0 output --> CPU Clock */
+
+/* CPU clock must be at least 18MHz for USB to function */
+
+/* div: 3-256 */
+static inline void fl_set_cpu_clock_divider(const int div) {
+ *FL_CCLKCFG = div - 1;
+}
+
+static inline int fl_get_cpu_clock_divider(void) {
+ return *FL_CCLKCFG + 1;
+}
+
+/* use only if USBPLL/PLL1 is not connected */
+/* div: 1-16 (only 6, 8 and 10 produce even number multiples */
+static inline void fl_set_pll0_usb_divider(const unsigned int div) {
+ *FL_USBCLKCFG = div - 1;
+}
+
+static inline int fl_get_pll0_usb_divider(void) {
+ return *FL_USBCLKCFG + 1;
+}
+
+#define FL_CLOCK_DIV4 0
+#define FL_CLOCK_DIV1 1
+#define FL_CLOCK_DIV2 2
+#define FL_CLOCK_DIV8 3
+
+#define FL_SELECT_CLOCK(peripheral, reg, pos) \
+ static inline void fl_select_clock_##peripheral(const unsigned int clock) { \
+ *reg &= ~(3U << pos); \
+ *reg |= clock << pos; \
+}
+
+FL_SELECT_CLOCK(wdt, FL_PCLKSEL0, 0)
+FL_SELECT_CLOCK(timer0, FL_PCLKSEL0, 2)
+FL_SELECT_CLOCK(timer1, FL_PCLKSEL0, 4)
+FL_SELECT_CLOCK(uart0, FL_PCLKSEL0, 6)
+FL_SELECT_CLOCK(uart1, FL_PCLKSEL0, 8)
+FL_SELECT_CLOCK(pwm1, FL_PCLKSEL0, 12)
+FL_SELECT_CLOCK(i2c0, FL_PCLKSEL0, 14)
+FL_SELECT_CLOCK(spi, FL_PCLKSEL0, 16)
+FL_SELECT_CLOCK(ssp1, FL_PCLKSEL0, 20)
+FL_SELECT_CLOCK(dac, FL_PCLKSEL0, 22)
+FL_SELECT_CLOCK(adc, FL_PCLKSEL0, 24)
+FL_SELECT_CLOCK(can1, FL_PCLKSEL0, 26)
+FL_SELECT_CLOCK(can2, FL_PCLKSEL0, 28)
+FL_SELECT_CLOCK(acf, FL_PCLKSEL0, 30)
+
+FL_SELECT_CLOCK(qei, FL_PCLKSEL1, 0)
+FL_SELECT_CLOCK(gpioint, FL_PCLKSEL1, 2)
+FL_SELECT_CLOCK(pcb, FL_PCLKSEL1, 4)
+FL_SELECT_CLOCK(i2c1, FL_PCLKSEL1, 6)
+FL_SELECT_CLOCK(ssp0, FL_PCLKSEL1, 10)
+FL_SELECT_CLOCK(timer2, FL_PCLKSEL1, 12)
+FL_SELECT_CLOCK(timer3, FL_PCLKSEL1, 14)
+FL_SELECT_CLOCK(uart2, FL_PCLKSEL1, 16)
+FL_SELECT_CLOCK(uart3, FL_PCLKSEL1, 18)
+FL_SELECT_CLOCK(i2c2, FL_PCLKSEL1, 20)
+FL_SELECT_CLOCK(i2s, FL_PCLKSEL1, 22)
+FL_SELECT_CLOCK(rit, FL_PCLKSEL1, 26)
+FL_SELECT_CLOCK(syscon, FL_PCLKSEL1, 28)
+FL_SELECT_CLOCK(mcpwm, FL_PCLKSEL1, 30)
+
+#define FL_CLOCK_OUT_CPU 0
+#define FL_CLOCK_OUT_MAIN 1
+#define FL_CLOCK_OUT_IRC 2
+#define FL_CLOCK_OUT_USB 3
+#define FL_CLOCK_OUT_RTC 4
+
+static inline void fl_set_output_clock(const int clock) {
+ *FL_CLKOUTCFG = clock;
+}
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/common.h Sun Jul 03 17:11:55 2011 +0000 @@ -0,0 +1,45 @@ +/* Copyright (C) 2010, 2011 by Ivo van Poorten <ivop@euronet.nl> + * This file is licensed under the terms of the GNU Lesser + * General Public License, version 3. + */ + +#ifndef FASTLIB_COMMON_H +#define FASTLIB_COMMON_H + +#include <stdint.h> + +#define FL_IGNORE (-1) + +#define FL_OFF 0 +#define FL_ON 1 + +#define FL_INPUT 0 +#define FL_OUTPUT 1 + +#define FL_RISE 0 +#define FL_FALL 1 +#define FL_BOTH 2 + +#define FL_DISABLE 0 +#define FL_ENABLE 1 + +#define FL_DISCONNECT 0 +#define FL_CONNECT 1 + +#define FL_SINGLE_EDGE 0 +#define FL_DOUBLE_EDGE 1 + +#define FL_8BITS 0 +#define FL_16BITS 1 +#define FL_32BITS 3 + +#define FL_STEREO 0 +#define FL_MONO 1 + +#define FL_MASTER 0 +#define FL_SLAVE 1 + +#define FL_LITTLE_ENDIAN 0 +#define FL_BIG_ENDIAN 1 + +#endif \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/dma.h Sun Jul 03 17:11:55 2011 +0000
@@ -0,0 +1,265 @@
+/* Copyright (C) 2010, 2011 by Ivo van Poorten <ivop@euronet.nl>
+ * This file is licensed under the terms of the GNU Lesser
+ * General Public License, version 3.
+ */
+
+#ifndef FASTLIB_DMA_H
+#define FASTLIB_DMA_H
+
+#include "fastlib/common.h"
+
+#define FL_DMACIntStat ((volatile uint32_t *) 0x50004000)
+#define FL_DMACIntTCStat ((volatile uint32_t *) 0x50004004)
+#define FL_DMACIntTCClear ((volatile uint32_t *) 0x50004008)
+#define FL_DMACIntErrStat ((volatile uint32_t *) 0x5000400C)
+#define FL_DMACIntErrClr ((volatile uint32_t *) 0x50004010)
+#define FL_DMACRawIntTCStat ((volatile uint32_t *) 0x50004014)
+#define FL_DMACRawIntErrStat ((volatile uint32_t *) 0x50004018)
+#define FL_DMACEnbldChns ((volatile uint32_t *) 0x5000401C)
+#define FL_DMACSoftBReq ((volatile uint32_t *) 0x50004020)
+#define FL_DMACSoftSReq ((volatile uint32_t *) 0x50004024)
+#define FL_DMACSoftLBReq ((volatile uint32_t *) 0x50004028)
+#define FL_DMACSoftLSReq ((volatile uint32_t *) 0x5000402C)
+#define FL_DMACConfig ((volatile uint32_t *) 0x50004030)
+#define FL_DMACSync ((volatile uint32_t *) 0x50004034)
+#define FL_DMAReqSel ((volatile uint32_t *) 0x400FC1C4)
+
+#define FL_DMACC0 0x50004100
+#define FL_DMACC1 0x50004120
+#define FL_DMACC2 0x50004140
+#define FL_DMACC3 0x50004160
+#define FL_DMACC4 0x50004180
+#define FL_DMACC5 0x500041A0
+#define FL_DMACC6 0x500041C0
+#define FL_DMACC7 0x500041E0
+
+#define FL_DMA_SrcAddr 0x00
+#define FL_DMA_DestAddr 0x04
+#define FL_DMA_LLI 0x08
+#define FL_DMA_Control 0x0C
+#define FL_DMA_Config 0x10
+
+#define FL_DMA(channel, field) \
+ ((volatile uint32_t *)(fl_dma_channel_to_base(channel) + FL_DMA_##field))
+
+static inline unsigned fl_dma_channel_to_base(const unsigned channel) {
+ switch(channel) {
+ case 0: return FL_DMACC0;
+ case 1: return FL_DMACC1;
+ case 2: return FL_DMACC2;
+ case 3: return FL_DMACC3;
+ case 4: return FL_DMACC4;
+ case 5: return FL_DMACC5;
+ case 6: return FL_DMACC6;
+ default: return FL_DMACC7;
+ }
+}
+
+// channel: 0-7
+static inline unsigned fl_dma_channel_has_active_interrupt_request(const unsigned channel) {
+ return *FL_DMACIntStat & (1U<<channel);
+}
+
+static inline unsigned fl_dma_channel_has_active_terminal_count_interrupt_request(const unsigned channel) {
+ return *FL_DMACIntTCStat & (1U<<channel);
+}
+static inline void fl_dma_clear_terminal_count_interrupt_request(const unsigned channel) {
+ *FL_DMACIntTCClear |= 1U<<channel;
+}
+static inline unsigned fl_dma_channel_has_active_terminal_count_interrupt_request_raw(const unsigned channel) {
+ return *FL_DMACRawIntTCStat & (1U<<channel); // raw is prior to masking
+}
+
+static inline unsigned fl_dma_channel_has_active_error_interrupt_request(const unsigned channel) {
+ return *FL_DMACIntErrStat & (1U<<channel);
+}
+static inline void fl_dma_clear_error_interrupt_request(const unsigned channel) {
+ *FL_DMACIntErrClr |= 1U<<channel;
+}
+static inline unsigned fl_dma_channel_has_active_error_interrupt_request_raw(const unsigned channel) {
+ return *FL_DMACRawIntErrStat & (1U<<channel);
+}
+
+static inline unsigned fl_dma_channel_is_enabled(const unsigned channel) {
+ return *FL_DMACEnbldChns & (1U<<channel);
+}
+
+static inline void fl_dma_generate_software_burst_request(const unsigned request) {
+ *FL_DMACSoftBReq |= 1U << request;
+}
+static inline unsigned fl_dma_software_burst_request_sources(void) {
+ return *FL_DMACSoftBReq;
+}
+
+static inline void fl_dma_generate_software_single_request(const unsigned request) {
+ *FL_DMACSoftSReq |= 1U << request;
+}
+static inline unsigned fl_dma_software_single_request_sources(void) {
+ return *FL_DMACSoftSReq;
+}
+
+static inline void fl_dma_generate_software_last_burst_request(const unsigned request) {
+ *FL_DMACSoftLBReq |= 1U << request;
+}
+static inline unsigned fl_dma_software_last_burst_request_sources(void) {
+ return *FL_DMACSoftLBReq;
+}
+
+static inline void fl_dma_generate_software_last_single_request(const unsigned request) {
+ *FL_DMACSoftLSReq |= 1U << request;
+}
+static inline unsigned fl_dma_software_last_single_request_sources(void) {
+ return *FL_DMACSoftLSReq;
+}
+
+static inline void fl_dma_enable(const unsigned state) {
+ if (state) *FL_DMACConfig |= 1U<<0 ;
+ else *FL_DMACConfig &= ~(1U<<0);
+}
+
+static inline unsigned fl_dma_is_enabled(void) {
+ return *FL_DMACConfig & 1;
+}
+
+static inline void fl_dma_set_endianness(const unsigned endianness) {
+ if (endianness) *FL_DMACConfig |= 1U<<1 ;
+ else *FL_DMACConfig &= ~(1U<<1);
+}
+
+static inline void fl_dma_request_synchronization_enable(const unsigned request, const unsigned state) {
+ if (!state) *FL_DMACSync |= 1U<<request ; // note that 0 is enabled
+ else *FL_DMACSync &= ~(1U<<request);
+}
+
+#define FL_DMA_UART 0
+#define FL_DMA_TIMER 1
+
+// select between uart or timer dma requests for inputs 8 through 15
+// input: 8-16 which: 0-1
+static inline void fl_dma_request_select(const unsigned input, const unsigned which) {
+ if (which) *FL_DMAReqSel |= 1U<<(which-8) ;
+ else *FL_DMAReqSel &= ~(1U<<(which-8));
+}
+
+// channel: 0-7
+static inline void fl_dma_set_srcaddr(const unsigned channel, const void *srcaddr) {
+ *FL_DMA(channel, SrcAddr) = (unsigned) srcaddr;
+}
+
+static inline void fl_dma_set_destaddr(const unsigned channel, const void *destaddr) {
+ *FL_DMA(channel, DestAddr) = (unsigned) destaddr;
+}
+
+// lli must be word-aligned
+static inline void fl_dma_set_next_lli(const unsigned channel, const void *lli) {
+ *FL_DMA(channel, LLI) = (unsigned) lli & (~3U);
+}
+
+#define FL_NO_SRC_INCREMENT 0
+#define FL_SRC_INCREMENT 1
+#define FL_NO_DEST_INCREMENT 0
+#define FL_DEST_INCREMENT 1
+
+static inline unsigned fl_dma_size_to_mask(const unsigned size) {
+ switch(size) {
+ case 4: return 1;
+ case 8: return 2;
+ case 16: return 3;
+ case 32: return 4;
+ case 64: return 5;
+ case 128: return 6;
+ case 256: return 7;
+ default: return 0;
+ }
+}
+
+static inline unsigned fl_dma_width_to_mask(const unsigned width) {
+ switch(width) {
+ case 16: return 1;
+ case 32: return 2;
+ default: return 0;
+ }
+}
+
+// transfer_size: 12 bits
+// size: 1, 4, 8, 16, 32, 64, 128 or 256
+// width: 8, 16 or 32
+// irq: 0-1
+static inline void fl_dma_channel_control(const unsigned channel, const unsigned transfer_size,
+ const unsigned src_burst_size, const unsigned dest_burst_size,
+ const unsigned src_width, const unsigned dest_width,
+ const unsigned src_increment, const unsigned dest_increment,
+ const unsigned terminal_count_irq) {
+ *FL_DMA(channel, Control) = transfer_size & 0xfff
+ | (fl_dma_size_to_mask(src_burst_size) << 12)
+ | (fl_dma_size_to_mask(dest_burst_size) << 15)
+ | (fl_dma_width_to_mask(src_width) << 18)
+ | (fl_dma_width_to_mask(dest_width) << 21)
+ | (src_increment << 26)
+ | (dest_increment << 27)
+ | (terminal_count_irq << 31);
+}
+
+static inline void fl_dma_channel_control_by_mask(const unsigned channel, const unsigned mask) {
+ *FL_DMA(channel, Control) = mask;
+}
+
+static inline unsigned fl_dma_channel_get_control_mask(const unsigned channel) {
+ return *FL_DMA(channel, Control);
+}
+
+static inline void fl_dma_channel_terminal_count_irq_enable(const unsigned channel, const unsigned state) {
+ if (state) *FL_DMA(channel, Control) |= 1U<<31 ;
+ else *FL_DMA(channel, Control) &= ~(1U<<31);
+}
+
+// channel configuration constants, src and dest peripherals
+#define FL_DMA_SINGLE_REQUEST_SSP0_Tx 0
+#define FL_DMA_SINGLE_REQUEST_SSP0_Rx 1
+#define FL_DMA_SINGLE_REQUEST_SSP1_Tx 2
+#define FL_DMA_SINGLE_REQUEST_SSP1_Rx 3
+#define FL_DMA_SINGLE_REQUEST_ADC 4
+
+#define FL_DMA_BURST_REQUEST_SSP0_Tx 0
+#define FL_DMA_BURST_REQUEST_SSP0_Rx 1
+#define FL_DMA_BURST_REQUEST_SSP1_Tx 2
+#define FL_DMA_BURST_REQUEST_SSP1_Rx 3
+#define FL_DMA_BURST_REQUEST_ADC 4
+#define FL_DMA_BURST_REQUEST_I2S_CH0 5
+#define FL_DMA_BURST_REQUEST_I2S_CH1 6
+#define FL_DMA_BURST_REQUEST_DAC 7
+#define FL_DMA_BURST_REQUEST_UART0_Tx 8
+#define FL_DMA_BURST_REQUEST_UART0_Rx 9
+#define FL_DMA_BURST_REQUEST_UART1_Tx 10
+#define FL_DMA_BURST_REQUEST_uART1_Rx 11
+#define FL_DMA_BURST_REQUEST_UART2_Tx 12
+#define FL_DMA_BURST_REQUEST_UART2_Rx 13
+#define FL_DMA_BURST_REQUEST_UART3_Tx 14
+#define FL_DMA_BURST_REQUEST_UART3_Rx 15
+
+#define FL_DMA_PERIPHERAL_IS_MEMORY 0
+
+// transfer types
+#define FL_DMA_MEMORY_TO_MEMORY 0
+#define FL_DMA_MEMORY_TO_PERIPHERAL 1
+#define FL_DMA_PERIPHERAL_TO_MEMORY 2
+#define FL_DMA_PERIPHERAL_TO_PERIPHERAL 3
+
+static inline void fl_dma_channel_config(const unsigned channel,
+ const unsigned enable, const unsigned src_peripheral, const unsigned dest_peripheral,
+ const unsigned transfer_type, const unsigned mask_error, const unsigned mask_tc) {
+ *FL_DMA(channel, Config) = enable | (src_peripheral<<1) | (dest_peripheral<<6) |
+ (transfer_type<<11) | (mask_error<<14) | (mask_tc<<15);
+}
+
+// return 0 or !0 (channel fifo has data)
+static inline unsigned fl_dma_channel_is_active(const unsigned channel) {
+ return *FL_DMA(channel, Config) & (1U<<17);
+}
+
+static inline void fl_dma_channel_halt(const unsigned channel, const unsigned state) {
+ if (state) *FL_DMA(channel, Config) |= 1U<<18 ;
+ else *FL_DMA(channel, Config) &= ~(1U<<18);
+}
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/gpio.h Sun Jul 03 17:11:55 2011 +0000
@@ -0,0 +1,104 @@
+/* Copyright (C) 2010, 2011 by Ivo van Poorten <ivop@euronet.nl>
+ * This file is licensed under the terms of the GNU Lesser
+ * General Public License, version 3.
+ */
+
+#ifndef FASTLIB_GPIO_H
+#define FASTLIB_GPIO_H
+
+#include "fastlib/common.h"
+
+static inline volatile uint32_t *fl_gpio_get_base(const int port) {
+ switch (port) {
+ case 0: return (volatile uint32_t *) 0x2009c000;
+ case 1: return (volatile uint32_t *) 0x2009c020;
+ case 2: return (volatile uint32_t *) 0x2009c040;
+ case 3: return (volatile uint32_t *) 0x2009c060;
+ case 4: return (volatile uint32_t *) 0x2009c080;
+ default: return (volatile uint32_t *) 0;
+ }
+}
+
+#define FL_GPIO_OVERALL_INT_STATUS ((volatile uint32_t *) 0x40028080)
+
+#define FL_GPIO_PORT0_RISE_INT_STATUS ((volatile uint32_t *) 0x40028084)
+#define FL_GPIO_PORT0_FALL_INT_STATUS ((volatile uint32_t *) 0x40028088)
+#define FL_GPIO_PORT0_INT_CLEAR ((volatile uint32_t *) 0x4002808C)
+#define FL_GPIO_PORT0_RISE_INT ((volatile uint32_t *) 0x40028090)
+#define FL_GPIO_PORT0_FALL_INT ((volatile uint32_t *) 0x40028094)
+
+#define FL_GPIO_PORT2_RISE_INT_STATUS ((volatile uint32_t *) 0x400280A4)
+#define FL_GPIO_PORT2_FALL_INT_STATUS ((volatile uint32_t *) 0x400280A8)
+#define FL_GPIO_PORT2_INT_CLEAR ((volatile uint32_t *) 0x400280AC)
+#define FL_GPIO_PORT2_RISE_INT ((volatile uint32_t *) 0x400280B0)
+#define FL_GPIO_PORT2_FALL_INT ((volatile uint32_t *) 0x400280B4)
+
+/* dir: 0=input, 1=output */
+static inline void fl_gpio_set_direction(const unsigned port, const unsigned int bitmask, const unsigned dir) {
+ if (dir) *(fl_gpio_get_base(port)) |= bitmask;
+ else *(fl_gpio_get_base(port)) &= ~bitmask;
+}
+
+static inline void fl_gpio_set_value(const unsigned port, const unsigned bitmask) {
+ *(fl_gpio_get_base(port) + 6) = bitmask;
+}
+
+static inline void fl_gpio_clear_value(const unsigned port, const unsigned bitmask) {
+ *(fl_gpio_get_base(port) + 7) = bitmask;
+}
+
+static inline uint32_t fl_gpio_get_value(const unsigned port, const unsigned bitmask) {
+ return *(fl_gpio_get_base(port) + 5);
+}
+
+static inline void fl_gpio_set_mask(const unsigned port, const unsigned bitmask) {
+ *(fl_gpio_get_base(port) + 4) |= bitmask;
+}
+
+static inline void fl_gpio_clear_mask(const unsigned port, const unsigned bitmask) {
+ *(fl_gpio_get_base(port) + 4) &= ~bitmask;
+}
+
+/* interrupts only on port 0 or 2 */
+
+/* return: 0 = none, !0 = at least one */
+static inline int fl_gpio_port_interrupt_status(const unsigned port) {
+ return *FL_GPIO_OVERALL_INT_STATUS & (1U<<port);
+}
+
+static inline void fl_gpio_interrupt_enable(const unsigned port, const unsigned bitmask, const unsigned edge) {
+ if (port == 0) {
+ if (edge == FL_RISE) *FL_GPIO_PORT0_RISE_INT |= bitmask;
+ else *FL_GPIO_PORT0_FALL_INT |= bitmask;
+ } else {
+ if (edge == FL_RISE) *FL_GPIO_PORT2_RISE_INT |= bitmask;
+ else *FL_GPIO_PORT2_FALL_INT |= bitmask;
+ }
+}
+
+static inline void fl_gpio_interrupt_disable(const unsigned port, const unsigned bitmask, const unsigned edge) {
+ if (port == 0) {
+ if (edge == FL_RISE) *FL_GPIO_PORT0_RISE_INT &= ~bitmask;
+ else *FL_GPIO_PORT0_FALL_INT &= ~bitmask;
+ } else {
+ if (edge == FL_RISE) *FL_GPIO_PORT2_RISE_INT &= ~bitmask;
+ else *FL_GPIO_PORT2_FALL_INT &= ~bitmask;
+ }
+}
+
+static inline uint32_t fl_gpio_interrupt_status(const unsigned port, const unsigned bitmask, const unsigned edge) {
+ if (port == 0) {
+ if (edge == FL_RISE) return *FL_GPIO_PORT0_RISE_INT_STATUS & bitmask;
+ else return *FL_GPIO_PORT0_FALL_INT_STATUS & bitmask;
+ } else {
+ if (edge == FL_RISE) return *FL_GPIO_PORT2_RISE_INT_STATUS & bitmask;
+ else return *FL_GPIO_PORT2_FALL_INT_STATUS & bitmask;
+ }
+}
+
+static inline void fl_gpio_interrupt_clear(const unsigned port, const unsigned bitmask) {
+ if (port == 0) *FL_GPIO_PORT0_INT_CLEAR = bitmask;
+ else *FL_GPIO_PORT2_INT_CLEAR = bitmask;
+}
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/i2s.h Sun Jul 03 17:11:55 2011 +0000
@@ -0,0 +1,139 @@
+/* Copyright (C) 2010, 2011 by Ivo van Poorten <ivop@euronet.nl>
+ * This file is licensed under the terms of the GNU Lesser
+ * General Public License, version 3.
+ */
+
+#ifndef FASTLIB_I2S_H
+#define FASTLIB_I2S_H
+
+#include "fastlib/common.h"
+
+/* important: in mono mode, each word is transmitted twice(!) */
+
+#define FL_I2SDAO ((volatile uint32_t *) 0x400A8000)
+#define FL_I2SDAI ((volatile uint32_t *) 0x400A8004)
+#define FL_I2STXFIFO ((volatile uint32_t *) 0x400A8008)
+#define FL_I2SRXFIFO ((volatile uint32_t *) 0x400A800C)
+#define FL_I2SSTATE ((volatile uint32_t *) 0x400A8010)
+#define FL_I2SDMA1 ((volatile uint32_t *) 0x400A8014)
+#define FL_I2SDMA2 ((volatile uint32_t *) 0x400A8018)
+#define FL_I2SIRQ ((volatile uint32_t *) 0x400A801C)
+#define FL_I2STXRATE ((volatile uint32_t *) 0x400A8020)
+#define FL_I2SRXRATE ((volatile uint32_t *) 0x400A8024)
+#define FL_I2STXBITRATE ((volatile uint32_t *) 0x400A8028)
+#define FL_I2SRXBITRATE ((volatile uint32_t *) 0x400A802C)
+#define FL_I2STXMODE ((volatile uint32_t *) 0x400A8030)
+#define FL_I2SRXMODE ((volatile uint32_t *) 0x400A8034)
+
+static inline void fl_i2s_output_set_config(const unsigned width, const unsigned mono, const unsigned halfperiod,
+ const unsigned stop, const unsigned reset, const unsigned mute, const unsigned slave) {
+ *FL_I2SDAO = width | (mono<<2) | ((halfperiod-1)<<6) | (stop<<3) | (reset<<4) | (mute<<15) | (slave<<5);
+}
+
+static inline unsigned fl_i2s_output_get_config(void) {
+ return *FL_I2SDAO;
+}
+
+static inline void fl_i2s_input_set_config(const unsigned width, const unsigned mono, const unsigned halfperiod,
+ const unsigned stop, const unsigned reset, const unsigned mute, const unsigned slave) {
+ *FL_I2SDAI = width | (mono<<2) | ((halfperiod-1)<<6) | (stop<<3) | (reset<<4) | (mute<<15) | (slave<<5);
+}
+
+static inline unsigned fl_i2s_input_get_config(void) {
+ return *FL_I2SDAI;
+}
+
+static inline void fl_i2s_write_tx_fifo(const unsigned value) {
+ *FL_I2STXFIFO = value;
+}
+
+static inline unsigned fl_i2s_read_rx_fifo(void) {
+ return *FL_I2SRXFIFO;
+}
+
+static inline unsigned fl_i2s_status_irq(void) {
+ return *FL_I2SSTATE & (1U<<0);
+}
+
+static inline unsigned fl_i2s_status_dmareq1(void) {
+ return *FL_I2SSTATE & (1U<<1);
+}
+
+static inline unsigned fl_i2s_status_dmareq2(void) {
+ return *FL_I2SSTATE & (1U<<2);
+}
+
+static inline unsigned fl_i2s_get_rx_level(void) {
+ return (*FL_I2SSTATE >> 8) & 15;
+}
+
+static inline unsigned fl_i2s_get_tx_level(void) {
+ return (*FL_I2SSTATE >> 16) & 15;
+}
+
+/* rx/tx_state: 0-1 rx/tx-level: 0-15 */
+static inline void fl_i2s_config_dma1(const unsigned rx_state, const unsigned tx_state, const unsigned rx_level, const unsigned tx_level) {
+ *FL_I2SDMA1 = rx_state | (tx_state<<1) | (rx_level<<8) | (tx_level<<16);
+}
+static inline void fl_i2s_config_dma2(const unsigned rx_state, const unsigned tx_state, const unsigned rx_level, const unsigned tx_level) {
+ *FL_I2SDMA2 = rx_state | (tx_state<<1) | (rx_level<<8) | (tx_level<<16);
+}
+
+/* rx/tx_irq: 0-1 */
+static inline void fl_i2s_config_irq(const unsigned rx_irq, const unsigned tx_irq, const unsigned rx_level, const unsigned tx_level) {
+ *FL_I2SIRQ = rx_irq | (tx_irq<<1) | (rx_level<<8) | (tx_level<<16);
+}
+
+/* tx rate = PCLK_I2S * (X/Y) / 2 X and Y: 1-255 (0=no clock) */
+static inline void fl_i2s_set_tx_rate(const unsigned X, const unsigned Y) {
+ *FL_I2STXRATE = Y | (X<<8);
+}
+static inline void fl_i2s_set_rx_rate(const unsigned X, const unsigned Y) {
+ *FL_I2SRXRATE = Y | (X<<8);
+}
+
+/* bitrate: 1-32 */
+static inline void fl_i2s_set_tx_bitrate(const unsigned bitrate) {
+ *FL_I2STXBITRATE = bitrate-1;
+}
+static inline void fl_i2s_set_rx_bitrate(const unsigned bitrate) {
+ *FL_I2SRXBITRATE = bitrate-1;
+}
+
+#define FL_TX_FRACTIONAL_RATE_DIVIDER 0
+#define FL_TX_USE_RX_CLOCK 1
+
+static inline void fl_i2s_tx_mode_clock(const unsigned tx_clock) {
+ if (tx_clock) *FL_I2STXMODE |= 1U<<1;
+ else *FL_I2STXMODE &= ~(1U<<1);
+}
+
+#define FL_RX_FRACTIONAL_RATE_DIVIDER 0
+#define FL_RX_USE_TX_CLOCK 1
+
+static inline void fl_i2s_rx_mode_clock(const unsigned rx_clock) {
+ if (rx_clock) *FL_I2SRXMODE |= 1U<<1;
+ else *FL_I2SRXMODE &= ~(1U<<1);
+}
+
+static inline void fl_i2s_tx_mode_4pin(const unsigned state) {
+ if (state) *FL_I2STXMODE |= 1U<<2;
+ else *FL_I2STXMODE &= ~(1U<<2);
+}
+
+static inline void fl_i2s_rx_mode_4pin(const unsigned state) {
+ if (state) *FL_I2SRXMODE |= 1U<<2;
+ else *FL_I2SRXMODE &= ~(1U<<2);
+}
+
+static inline void fl_i2s_tx_clock_output(const unsigned state) {
+ if (state) *FL_I2STXMODE |= 1U<<3;
+ else *FL_I2STXMODE &= ~(1U<<3);
+}
+
+static inline void fl_i2s_rx_clock_output(const unsigned state) {
+ if (state) *FL_I2SRXMODE |= 1U<<3;
+ else *FL_I2SRXMODE &= ~(1U<<3);
+}
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/license/gpl.h Sun Jul 03 17:11:55 2011 +0000 @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/> + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. We, the Free Software Foundation, use the +GNU General Public License for most of our software; it applies also to +any other work released this way by its authors. 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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/license/lgpl.h Sun Jul 03 17:11:55 2011 +0000 @@ -0,0 +1,165 @@ + GNU LESSER GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/> + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + + This version of the GNU Lesser General Public License incorporates +the terms and conditions of version 3 of the GNU General Public +License, supplemented by the additional permissions listed below. + + 0. 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--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/nvic.h Sun Jul 03 17:11:55 2011 +0000
@@ -0,0 +1,101 @@
+/* Copyright (C) 2011 by Ivo van Poorten <ivop@euronet.nl>
+ * This file is licensed under the terms of the GNU Lesser
+ * General Public License, version 3.
+ */
+
+#ifndef FASTLIB_NVIC_H
+#define FASTLIB_NVIC_H
+
+#include "fastlib/common.h"
+
+#define FL_NVIC_ISER0 ((volatile uint32_t *) 0xE000E100)
+#define FL_NVIC_ISER1 ((volatile uint32_t *) 0xE000E104)
+#define FL_NVIC_ICER0 ((volatile uint32_t *) 0xE000E180)
+#define FL_NVIC_ICER1 ((volatile uint32_t *) 0xE000E184)
+#define FL_NVIC_ISPR0 ((volatile uint32_t *) 0xE000E200)
+#define FL_NVIC_ISPR1 ((volatile uint32_t *) 0xE000E204)
+#define FL_NVIC_ICPR0 ((volatile uint32_t *) 0xE000E280)
+#define FL_NVIC_ICPR1 ((volatile uint32_t *) 0xE000E284)
+#define FL_NVIC_IABR0 ((volatile uint32_t *) 0xE000E300)
+#define FL_NVIC_IABR1 ((volatile uint32_t *) 0xE000E304)
+#define FL_NVIC_IPR0 ((volatile uint32_t *) 0xE000E400)
+#define FL_NVIC_IPR1 ((volatile uint32_t *) 0xE000E404)
+#define FL_NVIC_IPR2 ((volatile uint32_t *) 0xE000E408)
+#define FL_NVIC_IPR3 ((volatile uint32_t *) 0xE000E40C)
+#define FL_NVIC_IPR4 ((volatile uint32_t *) 0xE000E410)
+#define FL_NVIC_IPR5 ((volatile uint32_t *) 0xE000E414)
+#define FL_NVIC_IPR6 ((volatile uint32_t *) 0xE000E418)
+#define FL_NVIC_IPR7 ((volatile uint32_t *) 0xE000E41C)
+#define FL_NVIC_IPR8 ((volatile uint32_t *) 0xE000E420)
+#define FL_NVIC_STIR ((volatile uint32_t *) 0xE000EF00)
+
+#define FL_NVIC_INT_WDT 0
+#define FL_NVIC_INT_TIMER0 1
+#define FL_NVIC_INT_TIMER1 2
+#define FL_NVIC_INT_TIMER2 3
+#define FL_NVIC_INT_TIMER3 4
+#define FL_NVIC_INT_UART0 5
+#define FL_NVIC_INT_UART1 6
+#define FL_NVIC_INT_UART2 7
+#define FL_NVIC_INT_UART3 8
+#define FL_NVIC_INT_PWM 9
+#define FL_NVIC_INT_I2C0 10
+#define FL_NVIC_INT_I2C1 11
+#define FL_NVIC_INT_I2C2 12
+#define FL_NVIC_INT_SPI 13
+#define FL_NVIC_INT_SSP0 14
+#define FL_NVIC_INT_SSP1 15
+#define FL_NVIC_INT_PLL0 16
+#define FL_NVIC_INT_RTC 17
+#define FL_NVIC_INT_EINT0 18
+#define FL_NVIC_INT_EINT1 19
+#define FL_NVIC_INT_EINT2 20
+#define FL_NVIC_INT_EINT3 21
+#define FL_NVIC_INT_ADC 22
+#define FL_NVIC_INT_BOD 23
+#define FL_NVIC_INT_USB 24
+#define FL_NVIC_INT_CAN 25
+#define FL_NVIC_INT_DMA 26
+#define FL_NVIC_INT_I2S 27
+#define FL_NVIC_INT_ENET 28
+#define FL_NVIC_INT_RIT 29
+#define FL_NVIC_INT_MCPWM 30
+#define FL_NVIC_INT_QEI 31
+
+#define FL_NVIC_INT_PLL1 32
+#define FL_NVIC_INT_USBACT 33
+#define FL_NVIC_INT_CANACT 34
+
+#define FL_NVIC_INTERRUPT_FUNC(x, y) \
+ static inline void fl_nvic_interrupt_##x(const unsigned interrupt) { \
+ if (interrupt < 32) *FL_NVIC_##y##0 |= 1U<<interrupt; \
+ else *FL_NVIC_##y##1 |= 1U<<(interrupt-32); \
+ } \
+ static inline unsigned fl_nvic_interrupt_##x##_status(const unsigned interrupt) { \
+ if (interrupt < 32) return (*FL_NVIC_##y##0) & (1U<<interrupt); \
+ else return (*FL_NVIC_##y##1) & (1U<<(interrupt-32)); \
+ }
+
+FL_NVIC_INTERRUPT_FUNC(set_enable, ISER)
+FL_NVIC_INTERRUPT_FUNC(clear_enable, ICER)
+FL_NVIC_INTERRUPT_FUNC(set_pending, ISPR)
+FL_NVIC_INTERRUPT_FUNC(clear_pending, ICPR)
+
+static inline unsigned fl_nvic_interrupt_active_bit_status(const unsigned interrupt) {
+ if (interrupt < 32) return (*FL_NVIC_IABR0) & (1U<<interrupt);
+ else return (*FL_NVIC_IABR1) & (1U<<(interrupt-32));
+}
+
+static inline void fl_nvic_interrupt_set_priority(const unsigned interrupt, const unsigned priority) {
+ const unsigned i = interrupt >> 3,
+ j = (31 <<3) << ((interrupt&3)<<3),
+ k = (priority<<3) << ((interrupt&3)<<3);
+ *(FL_NVIC_IPR0 + i) &= ~j;
+ *(FL_NVIC_IPR0 + i) |= k;
+}
+
+static inline void fl_nvic_interrupt_software_trigger(const unsigned interrupt) {
+ *FL_NVIC_STIR = interrupt;
+}
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/pinsel.h Sun Jul 03 17:11:55 2011 +0000
@@ -0,0 +1,78 @@
+/* Copyright (C) 2010, 2011 by Ivo van Poorten <ivop@euronet.nl>
+ * This file is licensed under the terms of the GNU Lesser
+ * General Public License, version 3.
+ */
+
+#ifndef FASTLIB_PINSEL_H
+#define FASTLIB_PINSEL_H
+
+#include "fastlib/common.h"
+
+#define FL_PINSEL0 ((volatile uint32_t *) 0x4002c000)
+#define FL_PINMODE0 ((volatile uint32_t *) 0x4002c040)
+#define FL_PINMODE_OD0 ((volatile uint32_t *) 0x4002c068)
+
+#define FL_PULLUP 0
+#define FL_REPEATER 1
+#define FL_TRISTATE 2
+#define FL_FLOATING 2
+#define FL_PULLDOWN 3
+
+#define FL_FUNC_DEFAULT 0
+#define FL_FUNC_ALT1 1
+#define FL_FUNC_ALT2 2
+#define FL_FUNC_ALT3 3
+
+/* fl_pinsel(port,pin,func,resistor,opendrain) :
+ *
+ * port 0-4
+ * pin 0-31
+ * func 0-3 (-1 is ignore) default/alt1/alt2/alt3
+ * resistor 0-3 (-1 is ignore) pull-up, repeater, tri-state, pull-down
+ * opendrain 0-1 (-1 is ignore) off, on
+ */
+
+static inline void fl_pinsel(unsigned port, unsigned pin, const int func, const int resistor, const int opendrain) {
+ if (opendrain >= 0) {
+ *(FL_PINMODE_OD0 + port) &= ~( 1U << pin);
+ *(FL_PINMODE_OD0 + port) |= opendrain << pin ;
+ }
+
+ if (func == -1 && resistor == -1) return;
+
+ port <<= 1;
+ if (pin >= 16) {
+ pin -= 16;
+ port++;
+ }
+ pin <<= 1;
+
+ if (func >= 0) {
+ *(FL_PINSEL0 + port) &= ~( 3U << pin);
+ *(FL_PINSEL0 + port) |= func << pin ;
+ }
+ if (resistor >= 0) {
+ *(FL_PINMODE0 + port) &= ~((uint32_t) 3U << pin);
+ *(FL_PINMODE0 + port) |= (uint32_t)resistor << pin ;
+ }
+}
+
+/* Perhaps move this to i2c.h later??? */
+
+#define FL_I2CPADCFG ((volatile uint32_t *) 0x4002C07C)
+
+#define FL_SDA0_STANDARD_DRIVE (0<<0)
+#define FL_SDA0_FAST_DRIVE (1<<0)
+#define FL_SDA0_GLITCH_ENABLE (0<<1)
+#define FL_SDA0_GLITCH_DISABLE (1<<1)
+#define FL_SCL0_STANDARD_DRIVE (0<<2)
+#define FL_SCL0_FAST_DRIVE (1<<2)
+#define FL_SCL0_GLITCH_ENABLE (0<<3)
+#define FL_SCL0_GLITCH_DISABLE (1<<3)
+
+/* pins P0.27 and P0.28 */
+static inline void fl_i2c_pad_config(const unsigned config) {
+ *FL_I2CPADCFG = config;
+}
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/power.h Sun Jul 03 17:11:55 2011 +0000
@@ -0,0 +1,77 @@
+/* Copyright (C) 2010, 2011 by Ivo van Poorten <ivop@euronet.nl>
+ * This file is licensed under the terms of the GNU Lesser
+ * General Public License, version 3.
+ */
+
+/* see chapter 4 of user manual for details on clocks and power */
+
+#ifndef FASTLIB_POWER_H
+#define FASTLIB_POWER_H
+
+#include "fastlib/common.h"
+
+#define FL_PCON ((volatile uint32_t *) 0x400FC0C0)
+#define FL_PCONP ((volatile uint32_t *) 0x400FC0C4)
+
+#define FL_POWER_DOWN (1<<0)
+#define FL_DEEP_POWER_DOWN (1<<1)
+#define FL_BROWN_OUT_REDUCED_POWER_MODE (1<<2)
+#define FL_BROWN_OUT_GLOBAL_DISABLE (1<<3)
+#define FL_BROWN_OUT_RESET_DISABLE (1<<4)
+
+#define FL_FLAG_SLEEP_MODE (1<<8)
+#define FL_FLAG_DEEP_SLEEP_MODE (1<<9)
+#define FL_FLAG_POWER_DOWN (1<<10)
+#define FL_FLAG_DEEP_POWER_DOWN (1<<11)
+
+static inline void fl_set_power_mode(const unsigned mode) {
+ *FL_PCON = mode;
+}
+
+static inline unsigned fl_get_power_mode(void) {
+ return *FL_PCON;
+}
+
+#define FL_POWER(peripheral, pos) \
+ static inline void fl_power_##peripheral(const unsigned on_off) { \
+ *FL_PCONP &= ~( 1U<<pos); \
+ *FL_PCONP |= (unsigned)on_off<<pos; \
+ }
+
+FL_POWER(timer0, 1)
+FL_POWER(timer1, 2)
+FL_POWER(uart0, 3)
+FL_POWER(uart1, 4)
+FL_POWER(pwm1, 6)
+FL_POWER(i2c0, 7)
+FL_POWER(spi, 8)
+FL_POWER(rtc, 9)
+FL_POWER(ssp1, 10)
+FL_POWER(adc, 12)
+FL_POWER(can1, 13)
+FL_POWER(can2, 14)
+FL_POWER(gpio, 15)
+FL_POWER(rit, 16)
+FL_POWER(mcpwm, 17)
+FL_POWER(qei, 18)
+FL_POWER(i2c1, 19)
+FL_POWER(ssp0, 21)
+FL_POWER(timer2, 22)
+FL_POWER(timer3, 23)
+FL_POWER(uart2, 24)
+FL_POWER(uart3, 25)
+FL_POWER(i2c2, 26)
+FL_POWER(i2s, 27)
+FL_POWER(gpdma, 29)
+FL_POWER(enet, 30)
+FL_POWER(usb, 31)
+
+static inline void fl_power_off_all_peripherals(void) {
+ *FL_PCONP = 0;
+}
+
+static inline void fl_power_on_all_peripherals(void) {
+ *FL_PCONP = ~((1<<0) | (1<<5) | (1<<11) | (1<<20) | (1<<28));
+}
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/pwm.h Sun Jul 03 17:11:55 2011 +0000
@@ -0,0 +1,145 @@
+/* Copyright (C) 2010, 2011 by Ivo van Poorten <ivop@euronet.nl>
+ * This file is licensed under the terms of the GNU Lesser
+ * General Public License, version 3.
+ */
+
+#ifndef FASTLIB_PWM_H
+#define FASTLIB_PWM_H
+
+#include "fastlib/common.h"
+
+#define FL_PWM1IR ((volatile uint32_t *) 0x40018000)
+
+#define FL_PWM1TCR ((volatile uint32_t *) 0x40018004)
+#define FL_PWM1TC ((volatile uint32_t *) 0x40018008)
+
+#define FL_PWM1PR ((volatile uint32_t *) 0x4001800C)
+#define FL_PWM1PC ((volatile uint32_t *) 0x40018010)
+
+#define FL_PWM1MCR ((volatile uint32_t *) 0x40018014)
+#define FL_PWM1MR0 ((volatile uint32_t *) 0x40018018)
+#define FL_PWM1MR1 ((volatile uint32_t *) 0x4001801C)
+#define FL_PWM1MR2 ((volatile uint32_t *) 0x40018020)
+#define FL_PWM1MR3 ((volatile uint32_t *) 0x40018024)
+#define FL_PWM1MR4 ((volatile uint32_t *) 0x40018040)
+#define FL_PWM1MR5 ((volatile uint32_t *) 0x40018044)
+#define FL_PWM1MR6 ((volatile uint32_t *) 0x40018048)
+
+#define FL_PWM1CCR ((volatile uint32_t *) 0x40018028)
+#define FL_PWM1CR0 ((volatile uint32_t *) 0x4001802C)
+#define FL_PWM1CR1 ((volatile uint32_t *) 0x40018030)
+#define FL_PWM1CR2 ((volatile uint32_t *) 0x40018034)
+#define FL_PWM1CR3 ((volatile uint32_t *) 0x40018038)
+
+#define FL_PWM1PCR ((volatile uint32_t *) 0x4001804C)
+#define FL_PWM1LER ((volatile uint32_t *) 0x40018050)
+#define FL_PWM1CTCR ((volatile uint32_t *) 0x40018070)
+
+/* match channel: 0-8 (0-6 pwm, 7-8 cap0-1)
+ * returns 0 or !0
+ */
+static inline int fl_pwm_interrupt_status(const unsigned channel) {
+ int remap;
+ if (channel >= 7) remap = -3;
+ else if (channel >= 4) remap = 4;
+ return *FL_PWM1IR & (1U << (channel+remap));
+}
+
+static inline void fl_pwm_interrupt_clear(const unsigned channel) {
+ int remap;
+ if (channel >= 7) remap = -3;
+ else if (channel >= 4) remap = 4;
+ *FL_PWM1IR = 1U << (channel+remap);
+}
+
+static inline void fl_pwm_timer_counter_enable(const unsigned state) {
+ if (state) *FL_PWM1TCR |= 1;
+ else *FL_PWM1TCR &= ~1U;
+}
+
+static inline void fl_pwm_timer_counter_reset(const unsigned state) {
+ if (state) *FL_PWM1TCR |= 2;
+ else *FL_PWM1TCR &= ~2U;
+}
+
+static inline void fl_pwm_enable(const unsigned state) {
+ if (state) *FL_PWM1TCR |= 8;
+ else *FL_PWM1TCR &= ~8U;
+}
+
+static inline unsigned fl_pwm_get_timer_counter(void) {
+ return *FL_PWM1TC;
+}
+
+static inline void fl_pwm_set_timer_counter(unsigned value) {
+ *FL_PWM1TC = value;
+}
+
+/* value: 1-... */
+static inline void fl_pwm_set_prescale(const unsigned value) {
+ *FL_PWM1PR = value - 1;
+}
+
+static inline unsigned fl_pwm_get_prescale_counter(void) {
+ return *FL_PWM1PR + 1;
+}
+
+static inline void fl_pwm_set_timer_mode(void) {
+ *FL_PWM1CTCR &= ~3U;
+}
+
+/* mode: 1-3 (FL_RISE/FALL/BOTH) pcap1: 0-1 */
+static inline void fl_pwm_set_counter_mode(const unsigned mode, const unsigned pcap1n) {
+ *FL_PWM1CTCR = mode | (pcap1n << 2);
+}
+
+/* channel: 0-6 */
+static inline void fl_pwm_config_match(const unsigned channel, const unsigned interrupt, const unsigned reset, const unsigned stop) {
+ const unsigned mask = (interrupt | (reset << 1) | (stop << 2)) << ((channel<<1)+channel);
+ *FL_PWM1MCR &= ~mask;
+ *FL_PWM1MCR |= mask;
+}
+
+/* channel: 0-6 */
+static inline void fl_pwm_set_match(const unsigned channel, const unsigned value) {
+ if (channel <= 3) *(FL_PWM1MR0+channel) = value;
+ else *(FL_PWM1MR0+channel+0x18) = value;
+}
+
+/* pcap1n: 0-1 */
+static inline void fl_pwm_config_capture(const unsigned pcap1n, const unsigned rise, const unsigned fall, const unsigned interrupt) {
+ const unsigned mask = (rise | (fall << 1) | (interrupt << 2)) << ((pcap1n<<1)+pcap1n);
+ *FL_PWM1CCR &= ~mask;
+ *FL_PWM1CCR |= mask;
+}
+
+/* pcap1n: 0-1 (2,3?) */
+static inline unsigned fl_pwm_get_capture(const unsigned pcap1n) {
+ return *(FL_PWM1CR0+pcap1n);
+}
+
+/* channel: 2-6 edges: 0-1 (single/double) */
+static inline void fl_pwm_config_edges(const unsigned channel, const unsigned edges) {
+ if (edges) *FL_PWM1PCR |= edges << channel ;
+ else *FL_PWM1PCR &= ~(edges << channel);
+}
+
+/* channel: 1-6 state: 0-1 */
+static inline void fl_pwm_output_enable(const unsigned channel, const unsigned state) {
+ if (state) *FL_PWM1PCR |= 1U << (channel+8) ;
+ else *FL_PWM1PCR &= ~(1U << (channel+8));
+}
+
+static inline void fl_pwm_latch_match_channel(const unsigned channel) {
+ *FL_PWM1LER |= 1U << channel;
+}
+
+static inline void fl_pwm_latch_match_mask(const unsigned mask) {
+ *FL_PWM1LER = mask;
+}
+
+static inline void fl_pwm_latch_match_all(void) {
+ fl_pwm_latch_match_mask(0x7f);
+}
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/uart.h Sun Jul 03 17:11:55 2011 +0000
@@ -0,0 +1,348 @@
+/* Copyright (C) 2010, 2011 by Ivo van Poorten <ivop@euronet.nl>
+ * This file is licensed under the terms of the GNU Lesser
+ * General Public License, version 3.
+ */
+
+#ifndef FASTLIB_UART_H
+#define FASTLIB_UART_H
+
+#include "fastlib/common.h"
+
+#define FL_UART_RBR 0x00
+#define FL_UART_THR 0x00
+#define FL_UART_DLL 0x00
+
+#define FL_UART_DLM 0x04
+#define FL_UART_IER 0x04
+
+#define FL_UART_IIR 0x08
+#define FL_UART_FCR 0x08
+
+#define FL_UART_LCR 0x0C
+#define FL_UART_MCR 0x10 /* UART1 only */
+#define FL_UART_LSR 0x14
+#define FL_UART_MSR 0x18 /* UART1 only */
+#define FL_UART_SCR 0x1C
+#define FL_UART_ACR 0x20
+#define FL_UART_ICR 0x24 /* UART023 only */
+#define FL_UART_FDR 0x28
+#define FL_UART_TER 0x30
+
+#define FL_UART_RS485CTRL 0x4C /* UART1 only */
+#define FL_UART_RS485ADRMATCH 0x50 /* UART1 only */
+#define FL_UART_RS485DLY 0x54 /* UART1 only */
+
+#define FL_UART0_BASE 0x4000C000
+#define FL_UART1_BASE 0x40010000
+#define FL_UART2_BASE 0x40098000
+#define FL_UART3_BASE 0x4009C000
+
+#define FL_UART(num, field) \
+ ((volatile uint32_t *)(fl_uart_num_to_base(num) + FL_UART_##field))
+
+static inline unsigned fl_uart_num_to_base(const unsigned num) {
+ switch(num) {
+ case 0: return FL_UART0_BASE;
+ case 1: return FL_UART1_BASE;
+ case 2: return FL_UART2_BASE;
+ default: return FL_UART3_BASE;
+ }
+}
+
+static inline unsigned fl_uart_receive_byte(const unsigned uart) {
+ return *FL_UART(uart, RBR);
+}
+
+static inline void fl_uart_send_byte(const unsigned uart, const unsigned byte) {
+ *FL_UART(uart, THR);
+}
+
+static inline unsigned fl_uart_get_divisor_latch(const unsigned uart) {
+ unsigned divisor;
+ *FL_UART(uart, LCR) |= 1U<<7; // enable access to latch
+
+ divisor = *FL_UART(uart, DLL) | (*FL_UART(uart, DLM) << 8);
+
+ *FL_UART(uart, LCR) &= ~(1U<<7); // disable access to latch
+ return divisor;
+}
+
+/* divisor: 16-bit value */
+static inline void fl_uart_set_divisor_latch(const unsigned uart, const unsigned divisor) {
+ *FL_UART(uart, LCR) |= 1U<<7; // enable access to latch
+
+ *FL_UART(uart, DLL) = divisor & 0xff;
+ *FL_UART(uart, DLM) = (divisor >> 8) & 0xff;
+
+ *FL_UART(uart, LCR) &= ~(1U<<7); // disable access to latch
+}
+
+static inline void fl_uart_rx_data_available_interrupt_enable(const unsigned uart, const unsigned state) {
+ if (state) *FL_UART(uart, IER) |= (1U<<0);
+ else *FL_UART(uart, IER) &= ~(1U<<0);
+}
+
+static inline void fl_uart_tx_fifo_empty_interrupt_enable(const unsigned uart, const unsigned state) {
+ if (state) *FL_UART(uart, IER) |= (1U<<1);
+ else *FL_UART(uart, IER) &= ~(1U<<1);
+}
+
+static inline void fl_uart_rx_line_status_interrupt_enable(const unsigned uart, const unsigned state) {
+ if (state) *FL_UART(uart, IER) |= (1U<<2);
+ else *FL_UART(uart, IER) &= ~(1U<<2);
+}
+
+static inline void fl_uart_end_of_autobaud_interrupt_enable(const unsigned uart, const unsigned state) {
+ if (state) *FL_UART(uart, IER) |= (1U<<8);
+ else *FL_UART(uart, IER) &= ~(1U<<8);
+}
+
+static inline void fl_uart_timeout_autobaud_interrupt_enable(const unsigned uart, const unsigned state) {
+ if (state) *FL_UART(uart, IER) |= (1U<<9);
+ else *FL_UART(uart, IER) &= ~(1U<<9);
+}
+
+static inline unsigned fl_uart_interrupt_status(const unsigned uart) {
+ return !(*FL_UART(uart, IIR) & 1); // negate, because status is active low
+}
+
+#define FL_UART_INTERRUPT_RLS 3 /* rx line status */
+#define FL_UART_INTERRUPT_RDA 2 /* rx data available */
+#define FL_UART_INTERRUPT_CTI 6 /* character time-out */
+#define FL_UART_INTERRUPT_THRE 1 /* tx fifo empty */
+#define FL_UART_INTERRUPT_MODEM 0 /* modem interrupt, uart1 only */
+
+static inline unsigned fl_uart_get_interrupt_identification(const unsigned uart) {
+ return (*FL_UART(uart, IIR) >> 1) & 7;
+}
+
+/* returns 0 or !0 */
+static inline unsigned fl_uart_end_of_autobaud_interrupt(const unsigned uart) {
+ return *FL_UART(uart, IIR) & (1U<<8);
+}
+static inline unsigned fl_uart_timeout_autobaud_interrupt(const unsigned uart) {
+ return *FL_UART(uart, IIR) & (1U<<9);
+}
+
+/* call is more or less mandatory for application (page 305) */
+static inline void fl_uart_enable_fifos(const unsigned uart) {
+ *FL_UART(uart, FCR) |= 1U<<0;
+}
+/* disable/enable cycle clears fifo */
+static inline void fl_uart_disable_fifos(const unsigned uart) {
+ *FL_UART(uart, FCR) &= ~(1U<<0);
+}
+
+static inline void fl_uart_reset_rx_fifo(const unsigned uart) {
+ *FL_UART(uart, FCR) |= 1U<<1; // bit is self-clearing
+}
+
+static inline void fl_uart_reset_tx_fifo(const unsigned uart) {
+ *FL_UART(uart, FCR) |= 1U<<2; // bit is self-clearing
+}
+
+static inline void fl_uart_enable_dma_mode(const unsigned uart, const unsigned state) {
+ if (state) *FL_UART(uart, FCR) |= 1U<<3 ;
+ else *FL_UART(uart, FCR) &= ~(1U<<3);
+}
+
+static inline void fl_uart_set_rx_trigger_level(const unsigned uart, const unsigned level) {
+ if (level != 14) *FL_UART(uart, FCR) &= ~(3U<<6);
+ switch(level) {
+ default: return;
+ case 4: *FL_UART(uart, FCR) |= 1U<<6; return;
+ case 8: *FL_UART(uart, FCR) |= 2U<<6; return;
+ case 14: *FL_UART(uart, FCR) |= 3U<<6; return;
+ }
+}
+
+#define FL_UART_5BIT 0
+#define FL_UART_6BIT 1
+#define FL_UART_7BIT 2
+#define FL_UART_8BIT 3
+
+#define FL_UART_1STOPBIT 0
+#define FL_UART_2STOPBITS 1
+
+#define FL_UART_NO_PARITY 0
+#define FL_UART_PARITY 1
+
+#define FL_UART_ODD 0
+#define FL_UART_EVEN 1
+#define FL_UART_FORCE1 2
+#define FL_UART_FORCE0 3
+
+static inline void fl_uart_line_config(const unsigned uart, const unsigned wordlength, const unsigned stopbit, \
+ const unsigned parity_enable, const unsigned parity_type) {
+ const unsigned combined = wordlength | (stopbit << 2) | (parity_enable << 3) | (parity_type << 4);
+ *FL_UART(uart, LCR) &= ~(0x3fU);
+ *FL_UART(uart, LCR) |= combined;
+}
+
+static inline void fl_uart_break_transmission(const unsigned uart, const unsigned state) {
+ if (state) *FL_UART(uart, LCR) |= 1U<<6 ;
+ else *FL_UART(uart, LCR) &= ~(1U<<6);
+}
+
+static inline unsigned fl_uart_get_line_status(const unsigned uart) {
+ return *FL_UART(uart, LSR);
+}
+
+/* read status first and use functions below to test what is happening */
+/* the reason for this is that a status read clears several bits */
+
+#define FL_LSR_TEST(what, where) \
+ static inline unsigned fl_uart_##what(const unsigned status) { \
+ return status & (where); \
+ }
+
+FL_LSR_TEST(rx_fifo_not_empty, 1U<<0);
+FL_LSR_TEST(rx_fifo_overun_error, 1U<<1);
+FL_LSR_TEST(rx_parity_error, 1U<<2);
+FL_LSR_TEST(rx_framing_error, 1U<<3);
+FL_LSR_TEST(rx_break_interrupt, 1U<<4); /* associated with top of fifo */
+FL_LSR_TEST(tx_send_register_empty, 1U<<5);
+FL_LSR_TEST(tx_empty, 1U<<6); /* both send and status register */
+FL_LSR_TEST(rx_error_entered_fifo, 1U<<7);
+
+static inline void fl_uart_write_scratch_pad(const unsigned uart, const unsigned byte) {
+ *FL_UART(uart, SCR) = byte & 0xff;
+}
+
+static inline unsigned fl_uart_read_scratch_pad(const unsigned uart) {
+ return *FL_UART(uart, SCR);
+}
+
+static inline void fl_uart_autobaud_config(const unsigned uart, const unsigned mode, const unsigned autorestart) {
+ *FL_UART(uart, ACR) = (mode << 1) | (autorestart << 2); // writing zeroes to other bits has no impact (p.308/309)
+}
+
+static inline void fl_uart_start_autobaud(const unsigned uart) {
+ *FL_UART(uart, ACR) |= 1; // bit is auto-clearing
+}
+
+static inline void fl_uart_clear_end_of_autobaud_interrupt(const unsigned uart) {
+ *FL_UART(uart, ACR) |= 1U<<8;
+}
+
+static inline void fl_uart_clear_autobaud_timeout_interrupt(const unsigned uart) {
+ *FL_UART(uart, ACR) |= 1U<<9;
+}
+
+static inline void fl_uart_set_fractional_divider(const unsigned uart, const unsigned divaddval, const unsigned mulval) {
+ *FL_UART(uart, FDR) &= ~(0xff);
+ *FL_UART(uart, FDR) |= divaddval | (mulval<<4);
+}
+
+static inline unsigned fl_uart_get_fractional_divider(const unsigned uart) {
+ return *FL_UART(uart, FDR);
+}
+
+static inline void fl_uart_transmitter_enable(const unsigned uart, const unsigned state) {
+ if (state) *FL_UART(uart, TER) |= 1U<<7 ;
+ else *FL_UART(uart, TER) &= ~(1U<<7);
+}
+
+// infrared mode only works on uart0, 2 and 3
+
+static inline void fl_uart_infrared_mode(const unsigned uart, const unsigned state) {
+ if (state) *FL_UART(uart, ICR) |= 1U<<0;
+ else *FL_UART(uart, ICR) &= ~(1U<<0);
+}
+static inline void fl_uart_infrared_input_inverted(const unsigned uart, const unsigned state) {
+ if (state) *FL_UART(uart, ICR) |= 1U<<1;
+ else *FL_UART(uart, ICR) &= ~(1U<<1);
+}
+static inline void fl_uart_infrared_fixed_pulsewidth(const unsigned uart, const unsigned state) {
+ if (state) *FL_UART(uart, ICR) |= 1U<<2;
+ else *FL_UART(uart, ICR) &= ~(1U<<2);
+}
+// see UM10360 page 312 for pulsediv values (0-7)
+static inline void fl_uart_infrared_config_pulse(const unsigned uart, const unsigned pulsediv) {
+ *FL_UART(uart, ICR) &= ~(7U<<3);
+ *FL_UART(uart, ICR) |= pulsediv << 3;
+}
+
+
+// functions below only work for uart1 (full modem interface)
+
+static inline void fl_modem_status_interrupt_enable(const unsigned state) {
+ if (state) *FL_UART(1, IER) |= (1U<<3);
+ else *FL_UART(1, IER) &= ~(1U<<3);
+}
+
+static inline void fl_modem_cts_interrupt_enable(const unsigned state) {
+ if (state) *FL_UART(1, IER) |= (1U<<7);
+ else *FL_UART(1, IER) &= ~(1U<<7);
+}
+
+static inline void fl_modem_control(const unsigned dtr_control, const unsigned rts_control, const unsigned loopback,
+ const unsigned rts, const unsigned cts) {
+ *FL_UART(1, MCR) = dtr_control | (rts_control << 1) | (loopback << 4) | (rts << 6) | (cts << 7);
+}
+
+static inline unsigned fl_modem_get_status(void) {
+ return *FL_UART(1, MSR);
+}
+
+/* read status first and use functions below to test what is happening */
+/* the reason for this is that a status read clears several bits */
+
+#define FL_MSR_TEST(what, where) \
+ static inline unsigned fl_modem_##what(const unsigned status) { \
+ return status & (where); \
+ }
+
+FL_MSR_TEST(cts_state_changed, 1U<<0);
+FL_MSR_TEST(dsr_state_changed, 1U<<1);
+FL_MSR_TEST(low_to_high_ri, 1U<<2);
+FL_MSR_TEST(dcd_state_changed, 1U<<3);
+FL_MSR_TEST(cts_state, 1U<<4); /* clear to send */
+FL_MSR_TEST(dsr_state, 1U<<5); /* data set ready */
+FL_MSR_TEST(ri_state, 1U<<6); /* ring indicator */
+FL_MSR_TEST(dcd_state, 1U<<7); /* data carrier detect */
+
+// RS-485/EIA-485 mode functions, also uart1 only
+
+static inline void fl_rs485_normal_multidrop_mode_enable(const unsigned state) {
+ if (state) *FL_UART(1, RS485CTRL) |= 1U<<0 ;
+ else *FL_UART(1, RS485CTRL) &= ~(1U<<0);
+}
+
+static inline void fl_rs485_receiver_enable(const unsigned state) {
+ if (state) *FL_UART(1, RS485CTRL) |= 1U<<1 ;
+ else *FL_UART(1, RS485CTRL) &= ~(1U<<1);
+}
+
+static inline void fl_rs485_auto_address_detect_enable(const unsigned state) {
+ if (state) *FL_UART(1, RS485CTRL) |= 1U<<2 ;
+ else *FL_UART(1, RS485CTRL) &= ~(1U<<2);
+}
+
+static inline void fl_rs485_auto_direction_control_enable(const unsigned state) {
+ if (state) *FL_UART(1, RS485CTRL) |= 1U<<4 ;
+ else *FL_UART(1, RS485CTRL) &= ~(1U<<4);
+}
+
+static inline void fl_rs485_direction_control_on_rts_pin(void) {
+ *FL_UART(1, RS485CTRL) &= ~(1U<<3);
+}
+
+static inline void fl_rs485_direction_control_on_dtr_pin(void) {
+ *FL_UART(1, RS485CTRL) |= 1U<<3;
+}
+
+static inline void fl_rs485_direction_control_polarity(const unsigned oinv) {
+ if (oinv) *FL_UART(1, RS485CTRL) |= 1U<<5 ;
+ else *FL_UART(1, RS485CTRL) &= ~(1U<<5);
+}
+
+static inline void fl_rs485_set_address_match(const unsigned byte) {
+ *FL_UART(1, RS485ADRMATCH) = byte & 0xff;
+}
+
+static inline void fl_rs485_set_delay_time(const unsigned byte) {
+ *FL_UART(1, RS485DLY) = byte & 0xff;
+}
+
+#endif
\ No newline at end of file