Revision 0:12d93184b350, committed 2014-03-09

Comitter:

Info

Date:

Sun Mar 09 09:33:14 2014 +0000

Commit message:

Automatic module changer for MCU Gear. It make circuit each time. You don't need to think about the Bank.

Changed in this revision

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MCUGearA.cpp	Sun Mar 09 09:33:14 2014 +0000
@@ -0,0 +1,123 @@
+/* MCU Gear Library, only for testing MCUGear without any circuit you connected.
+ * Copyright (c) 2013, NestEgg Inc., http://www.mcugear.com/
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+#include "mbed.h"
+#include "MCUGearA.h"
+#include "MCUGearBaseA.h"
+
+MCUGear::MCUGear(PinName scl, PinName sda, char addr)
+     : _i2c(scl, sda) {
+    _i2c.frequency(FPGA_I2C_CLOCK);
+    _addr = addr;   //save address
+    write(0xff);    //close Module gate
+    _counter = 0;
+}
+
+void MCUGear::disconnectModule(void){
+    write(0xff);    //close module gate
+    deleteBank(0);
+}
+
+void MCUGear::connectModuleA(void){
+    int i = 0;
+    
+    //make circuit
+    if(_counter!=0){
+        
+        startReg(0);
+        
+        for(i = 0; i < _counter; ++i){
+          fpga_write(_mcuIO[i], _moduleIO[i]);
+        }
+        
+        endReg();
+        
+        changeBank(0);
+    }
+    
+    write(0xf8);    //1111 1000
+}
+
+void MCUGear::fpga_write(unsigned char adr, unsigned char data) {
+  char cmd[2];
+  cmd[0] = adr;
+  cmd[1] = data;
+  _i2c.write(FPGA_I2C_ADR, cmd, 2);
+}
+
+void MCUGear::startReg(char bank){
+    _bank = bank;
+    fpga_write(0x0c,_bank); //End regist
+}
+
+uint8_t MCUGear::setWireA(uint8_t mcuIO, uint8_t direction, uint8_t moduleIO){
+    
+    uint8_t location = ( _pnum + moduleIO );
+    
+    if(moduleIO >= numMaxModuleIO){
+        return 255; //error
+    }
+    
+    if(location >= numBaseboardIO){
+        location = location - numBaseboardIO;
+    }
+    
+    //fpga_write(mcuIO, (IO_REG_EN | (direction | (location))));
+    saveWire(mcuIO, (IO_REG_EN | (direction | (location))));
+    
+    return location;
+}
+
+void MCUGear::saveWire(uint8_t mcuIO, uint8_t moduleIO){
+        _mcuIO[_counter] = mcuIO;
+        _moduleIO[_counter] = moduleIO;
+        ++_counter;
+}
+
+void MCUGear::endReg(void){
+    fpga_write(0x10,_bank);//init regist///////
+}
+
+
+//send I2C signal function
+void MCUGear::write(uint8_t c){
+
+    char cmd[1];
+    cmd[0] = c;
+    _i2c.write(_addr, cmd, 1);
+    
+}
+
+////detect module
+uint8_t MCUGear::detectModule(void) {
+    
+    write(0x7f);   //0111 1111  //1pin GND
+    _pnum = fpga_read(FPGA_I2C_ADR,FPGA_DETECT);//save location
+    write(0xff);    //1111 1111 //close
+    
+    _counter = 0;
+    
+    return _pnum;
+
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MCUGearA.h	Sun Mar 09 09:33:14 2014 +0000
@@ -0,0 +1,62 @@
+/* MCU Gear Library, only for testing MCUGear without any circuit you connected.
+ * Copyright (c) 2013, NestEgg Inc., http://www.mcugear.com/
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "commonA.h"
+
+class MCUGear
+{        
+    public:
+        MCUGear(PinName sda, PinName scl, char addr);
+        void disconnectModule(void);
+        void connectModuleA(void);
+        void savePinSetting(uint8_t number, unsigned char CPUPin, unsigned char Direction ,unsigned char ModulePin);
+        uint8_t detectModule(void);
+        //void startReg(char bank);
+        uint8_t setWireA(uint8_t mcuIO, uint8_t direction, uint8_t moduleIO);
+        //void endReg(char bank);
+        
+    protected:
+        void fpga_write(unsigned char adr, unsigned char data);
+        void write(uint8_t c);
+        void startReg(char bank);
+        void endReg(void);
+        void saveWire(uint8_t mcuIO, uint8_t moduleIO);
+        
+        uint8_t _addr;
+        uint8_t _pnum;
+        I2C _i2c;
+        char _bank;
+        uint8_t _mcuIO[16];
+        uint8_t _moduleIO[16];
+        int _counter;
+                
+        typedef enum {
+          IO_REG_EN = 0x80,
+          IO_REG_OUT_DIR = 0x40,
+          IO_REG_IN_DIR  = 0x00,
+          IO_REG_DISABLE = 0x3f
+        } en_fpga_io_reg;
+
+};
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MCUGearBaseA.cpp	Sun Mar 09 09:33:14 2014 +0000
@@ -0,0 +1,93 @@
+/* MCU Gear Library, only for testing MCUGear without any circuit you connected.
+ * Copyright (c) 2013, NestEgg Inc., http://www.mcugear.com/
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "mbed.h"
+#include "MCUGearBaseA.h"
+
+#if defined TARGET_LPC1768
+I2C fpga_i2c(p28, p27);
+#endif
+
+#if defined TARGET_KL25Z
+I2C fpga_i2c(PTE0, PTE1);
+#endif
+
+void fpga_write(int dev_adr,unsigned char adr, unsigned char data) {
+  char cmd[2];
+  cmd[0] = adr;
+  cmd[1] = data;
+  fpga_i2c.frequency (FPGA_I2C_CLOCK);
+  fpga_i2c.write(dev_adr, cmd, 2);
+
+}
+
+unsigned char fpga_read(int dev_adr,unsigned char adr) {
+  char cmd[2];
+  cmd[0] = adr;
+  fpga_i2c.write(dev_adr, cmd, 1);
+  fpga_i2c.read(dev_adr, cmd, 1);
+  return cmd[0];
+}
+
+void initBase(void){
+
+    // FPGA reg clear
+     for (int i=0;i<20;i++)
+       fpga_write(FPGA_I2C_ADR,0x80+i,0);
+     
+    // read FPGA registers
+    fpga_read(FPGA_I2C_ADR,FPGA_SYSINFO_0);
+    fpga_read(FPGA_I2C_ADR,FPGA_SYSINFO_0+1);
+    fpga_read(FPGA_I2C_ADR,FPGA_SYSINFO_0+2);
+    fpga_read(FPGA_I2C_ADR,FPGA_SYSINFO_0+3);
+    // FPGA enable
+    fpga_write(FPGA_I2C_ADR,FPGA_ENABLE,1);   
+}
+
+void I2Cwrite(char addr, char data){
+
+    char cmd[1];
+    cmd[0] = data;
+    fpga_i2c.write(addr, cmd, 1);
+    //wait(0.01);
+    
+}
+
+void changeBank(uint8_t bank){
+    fpga_write(FPGA_I2C_ADR,0x10,bank);
+}
+
+void deleteBank(uint8_t bank){
+    fpga_write(FPGA_I2C_ADR,0x0c,(bank|0x80));
+    fpga_write(FPGA_I2C_ADR,0x10, bank);
+}
+/*
+void startReg(uint8_t bank){
+    fpga_write(FPGA_I2C_ADR,0x0c,bank);
+}
+
+void endReg(uint8_t bank){
+    fpga_write(FPGA_I2C_ADR,0x10, (bank|0x04));
+}
+*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MCUGearBaseA.h	Sun Mar 09 09:33:14 2014 +0000
@@ -0,0 +1,151 @@
+/* MCU Gear Library, only for testing MCUGear without any circuit you connected.
+ * Copyright (c) 2013, NestEgg Inc., http://www.mcugear.com/
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "commonA.h"
+
+
+#define FPGA_SYSINFO_0 0x00
+#define FPGA_SYSINFO_1 0x04
+#define FPGA_ENABLE    0x08
+#define FPGA_DETECT    0x14
+
+void fpga_write(int dev_adr,unsigned char adr, unsigned char data);
+unsigned char fpga_read(int dev_adr,unsigned char adr);
+void initBase(void);
+//void startReg(uint8_t bank);
+//void endReg(uint8_t bank);
+void deleteBank(uint8_t bank);
+void changeBank(uint8_t bank);
+
+
+// FGPGA CPU I/O
+typedef enum {
+
+#if defined TARGET_LPC1768
+  IO_MBED_P15 = 0x80,
+  IO_MBED_P13,
+  IO_MBED_P16,
+  IO_MBED_P12,
+  IO_MBED_P5,
+  IO_MBED_P11,
+  IO_MBED_P23,
+  IO_MBED_P22,
+  IO_MBED_P26,
+  IO_MBED_P10,
+  IO_MBED_P21,
+  IO_MBED_P9,
+  IO_MBED_P6,
+  IO_MBED_P7,
+  IO_MBED_P8,
+  IO_MBED_P14,
+  IO_MBED_P24,
+  IO_MBED_P25,
+  IO_MBED_P28,
+  IO_MBED_P27
+#endif
+
+ #if defined TARGET_KL25Z
+
+  IO_MBED_PTA5 = 0x80,
+  IO_MBED_PTC8,
+  IO_MBED_PTC9,
+  IO_MBED_PTD5,
+  IO_MBED_PTA13,
+  IO_MBED_PTD2,
+  IO_MBED_PTB1,
+  IO_MBED_PTB2,
+  IO_MBED_PTA2,
+  IO_MBED_PTD4,
+  IO_MBED_PTB3,
+  IO_MBED_PTA12,
+  IO_MBED_PTD0,
+  IO_MBED_PTD3,
+  IO_MBED_PTD1,
+  IO_MBED_PTA4,
+  IO_MBED_PTB0,
+  IO_MBED_PTA1,
+  IO_MBED_PTE0, //SDA
+  IO_MBED_PTE1  //SCL
+#endif
+  
+} en_cpu_io;
+
+// FPGA EXT I/O
+typedef enum {
+  IO_CON1_1 = 0,
+  IO_CON1_2,
+  IO_CON1_3,
+  IO_CON1_4,
+  IO_CON2_1,
+  IO_CON2_2,
+  IO_CON2_3,
+  IO_CON2_4,
+  IO_CON3_1,
+  IO_CON3_2,
+  IO_CON3_3,
+  IO_CON3_4,
+  IO_CON4_1,
+  IO_CON4_2,
+  IO_CON4_3,
+  IO_CON4_4,
+  IO_CON5_1,
+  IO_CON5_2,
+  IO_CON5_3,
+  IO_CON5_4,
+  IO_CON6_1,
+  IO_CON6_2,
+  IO_CON6_3,
+  IO_CON6_4,
+  IO_CON7_1,
+  IO_CON7_2,
+  IO_CON7_3,
+  IO_CON7_4,
+  IO_CON8_1,
+  IO_CON8_2,
+  IO_CON8_3,
+  IO_CON8_4,
+  IO_CON9_1,
+  IO_CON9_2,
+  IO_CON9_3,
+  IO_CON9_4,
+  IO_CON10_1,
+  IO_CON10_2,
+  IO_CON10_3,
+  IO_CON10_4,
+  IO_CON11_1,
+  IO_CON11_2,
+  IO_CON11_3,
+  IO_CON11_4,
+  IO_CON12_1,
+  IO_CON12_2,
+  IO_CON12_3,
+  IO_CON12_4
+} en_fpga_io;
+
+typedef enum {
+  IO_REG_EN = 0x80,
+  IO_REG_OUT_DIR = 0x40,
+  IO_REG_IN_DIR  = 0x00,
+  IO_REG_DISABLE = 0x3f
+} en_fpga_io_reg;
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/commonA.h	Sun Mar 09 09:33:14 2014 +0000
@@ -0,0 +1,191 @@
+/* MCU Gear Library, only for testing MCUGear without any circuit you connected.
+ * Copyright (c) 2013, NestEgg Inc., http://www.mcugear.com/
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define numBaseboardIO 48
+#define numMaxModuleIO 12
+
+//#define DEBUG //If you need to debug, define this.
+#if defined TARGET_LPC1768
+
+#define BaudRate 9600
+#define FPGA_I2C_CLOCK    1000000
+#define MODULE_I2C_CLOCK    1000000
+
+#endif
+
+ #if defined TARGET_KL25Z
+
+#define BaudRate 19200
+#define FPGA_I2C_CLOCK    2000000   //about 769kHz
+#define MODULE_I2C_CLOCK    2000000
+
+#endif
+
+
+#define FPGA_I2C_ADR 0x78
+
+#ifdef DEBUG
+#define BankMaxNum 3 //you can set 1 to 7 BANKs for Debug Mode.
+
+#else
+#define BankMaxNum 7 //BANK layers
+
+#endif
+
+//PCA9674
+            //VSS = GND VDD = +3.3V
+            //AD2 AD1 AD0
+#define    N_VSS_SCL_VSS    0x20
+#define    N_VSS_SCL_VDD    0x22
+#define    N_VSS_SDA_VSS    0x24
+#define    N_VSS_SDA_VDD    0x26
+#define    N_VDD_SCL_VSS    0x28
+#define    N_VDD_SCL_VDD    0x2A
+#define    N_VDD_SDA_VSS    0x2C
+#define    N_VDD_SDA_VDD    0x2E
+#define    N_VSS_SCL_SCL    0x30
+#define    N_VSS_SCL_SDA    0x32
+#define    N_VSS_SDA_SCL    0x34
+#define    N_VSS_SDA_SDA    0x36
+#define    N_VDD_SCL_SCL    0x38
+#define    N_VDD_SCL_SDA    0x3A
+#define    N_VDD_SDA_SCL    0x3C
+#define    N_VDD_SDA_SDA    0x3E
+#define    N_VSS_VSS_VSS    0x40
+#define    N_VSS_VSS_VDD    0x42
+#define    N_VSS_VDD_VSS    0x44
+#define    N_VSS_VDD_VDD    0x46
+#define    N_VDD_VSS_VSS    0x48
+#define    N_VDD_VSS_VDD    0x4A
+#define    N_VDD_VDD_VSS    0x4C
+#define    N_VDD_VDD_VDD    0x4E
+#define    N_VSS_VSS_SCL    0x50
+#define    N_VSS_VSS_SDA    0x52
+#define    N_VSS_VDD_SCL    0x54
+#define    N_VSS_VDD_SDA    0x56
+#define    N_VDD_VSS_SCL    0x58
+#define    N_VDD_VSS_SDA    0x5A
+#define    N_VDD_VDD_SCL    0x5C
+#define    N_VDD_VDD_SDA    0x5E
+#define    N_SCL_SCL_VSS    0xA0
+#define    N_SCL_SCL_VDD    0xA2
+#define    N_SCL_SDA_VSS    0xA4
+#define    N_SCL_SDA_VDD    0xA6
+#define    N_SDA_SCL_VSS    0xA8
+#define    N_SDA_SCL_VDD    0xAA
+#define    N_SDA_SDA_VSS    0xAC
+#define    N_SDA_SDA_VDD    0xAE
+#define    N_SCL_SCL_SCL    0xB0
+#define    N_SCL_SCL_SDA    0xB2
+#define    N_SCL_SDA_SCL    0xB4
+#define    N_SCL_SDA_SDA    0xB6
+#define    N_SDA_SCL_SCL    0xB8
+#define    N_SDA_SCL_SDA    0xBA
+#define    N_SDA_SDA_SCL    0xBC
+#define    N_SDA_SDA_SDA    0xBE
+#define    N_SCL_VSS_VSS    0xC0
+#define    N_SCL_VSS_VDD    0xC2
+#define    N_SCL_VDD_VSS    0xC4
+#define    N_SCL_VDD_VDD    0xC6
+#define    N_SDA_VSS_VSS    0xC8
+#define    N_SDA_VSS_VDD    0xCA
+#define    N_SDA_VDD_VSS    0xCC
+#define    N_SDA_VDD_VDD    0xCE
+#define    N_SCL_VSS_SCL    0xE0
+#define    N_SCL_VSS_SDA    0xE2
+#define    N_SCL_VDD_SCL    0xE4
+#define    N_SCL_VDD_SDA    0xE6
+#define    N_SDA_VSS_SCL    0xE8
+#define    N_SDA_VSS_SDA    0xEA
+#define    N_SDA_VDD_SCL    0xEC
+#define    N_SDA_VDD_SDA    0xEE
+
+
+//PCA9674A
+    //VSS = GND VDD = +3.3V
+    //AD2 AD1 AD0
+#define    A_VSS_SCL_VSS    0x10
+#define    A_VSS_SCL_VDD    0x12
+#define    A_VSS_SDA_VSS    0x14
+#define    A_VSS_SDA_VDD    0x16
+#define    A_VDD_SCL_VSS    0x18
+#define    A_VDD_SCL_VDD    0x1A
+#define    A_VDD_SDA_VSS    0x1C
+#define    A_VDD_SDA_VDD    0x1E
+#define    A_VSS_SCL_SCL    0x60
+#define    A_VSS_SCL_SDA    0x62
+#define    A_VSS_SDA_SCL    0x64
+#define    A_VSS_SDA_SDA    0x66
+#define    A_VDD_SCL_SCL    0x68
+#define    A_VDD_SCL_SDA    0x6A
+#define    A_VDD_SDA_SCL    0x6C
+#define    A_VDD_SDA_SDA    0x6E
+#define    A_VSS_VSS_VSS    0x70
+#define    A_VSS_VSS_VDD    0x72
+#define    A_VSS_VDD_VSS    0x74
+#define    A_VSS_VDD_VDD    0x76
+//#define    A_VDD_VSS_VSS    0x78 //This is baseboard address. It is reserved.
+#define    A_VDD_VSS_VDD    0x7A
+#define    A_VDD_VDD_VSS    0x7C
+#define    A_VDD_VDD_VDD    0x7E
+#define    A_VSS_VSS_SCL    0x80
+#define    A_VSS_VSS_SDA    0x82
+#define    A_VSS_VDD_SCL    0x84
+#define    A_VSS_VDD_SDA    0x86
+#define    A_VDD_VSS_SCL    0x88
+#define    A_VDD_VSS_SDA    0x8A
+#define    A_VDD_VDD_SCL    0x8C
+#define    A_VDD_VDD_SDA    0x8E
+#define    A_SCL_SCL_VSS    0x90
+#define    A_SCL_SCL_VDD    0x92
+#define    A_SCL_SDA_VSS    0x94
+#define    A_SCL_SDA_VDD    0x96
+#define    A_SDA_SCL_VSS    0x98
+#define    A_SDA_SCL_VDD    0x9A
+#define    A_SDA_SDA_VSS    0x9C
+#define    A_SDA_SDA_VDD    0x9E
+#define    A_SCL_SCL_SCL    0xD0
+#define    A_SCL_SCL_SDA    0xD2
+#define    A_SCL_SDA_SCL    0xD4
+#define    A_SCL_SDA_SDA    0xD6
+#define    A_SDA_SCL_SCL    0xD8
+#define    A_SDA_SCL_SDA    0xDA
+#define    A_SDA_SDA_SCL    0xDC
+#define    A_SDA_SDA_SDA    0xDE
+#define    A_SCL_VSS_VSS    0xF0
+#define    A_SCL_VSS_VDD    0xF2
+#define    A_SCL_VDD_VSS    0xF4
+#define    A_SCL_VDD_VDD    0xF6
+#define    A_SDA_VSS_VSS    0xF8
+#define    A_SDA_VSS_VDD    0xFA
+#define    A_SDA_VDD_VSS    0xFC
+#define    A_SDA_VDD_VDD    0xFE
+#define    A_SCL_VSS_SCL    0x00
+#define    A_SCL_VSS_SDA    0x02
+#define    A_SCL_VDD_SCL    0x04
+#define    A_SCL_VDD_SDA    0x06
+#define    A_SDA_VSS_SCL    0x08
+#define    A_SDA_VSS_SDA    0x0A
+#define    A_SDA_VDD_SCL    0x0C
+#define    A_SDA_VDD_SDA    0x0E
+
+