lpc17xx_clkpwr.h

00001 /* @cond */
00002 /***********************************************************************//**
00003  * @file        lpc17xx_clkpwr.h
00004  * @brief        Contains all macro definitions and function prototypes
00005  *                 support for Clock and Power Control firmware library on LPC17xx
00006  * @version        2.0
00007  * @date        21. May. 2010
00008  * @author        NXP MCU SW Application Team
00009  **************************************************************************
00010  * Software that is described herein is for illustrative purposes only
00011  * which provides customers with programming information regarding the
00012  * products. This software is supplied "AS IS" without any warranties.
00013  * NXP Semiconductors assumes no responsibility or liability for the
00014  * use of the software, conveys no license or title under any patent,
00015  * copyright, or mask work right to the product. NXP Semiconductors
00016  * reserves the right to make changes in the software without
00017  * notification. NXP Semiconductors also make no representation or
00018  * warranty that such application will be suitable for the specified
00019  * use without further testing or modification.
00020  **************************************************************************/
00021 
00022 /* Peripheral group ----------------------------------------------------------- */
00023 /** @defgroup CLKPWR CLKPWR
00024  * @ingroup LPC1700CMSIS_FwLib_Drivers
00025  * @{
00026  */
00027 
00028 #ifndef LPC17XX_CLKPWR_H_
00029 #define LPC17XX_CLKPWR_H_
00030 
00031 /* Includes ------------------------------------------------------------------- */
00032 #include "lpc17xx.h"
00033 #include "lpc_types.h"
00034 
00035 #ifdef __cplusplus
00036 extern "C"
00037 {
00038 #endif
00039 
00040 /* Public Macros -------------------------------------------------------------- */
00041 /** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
00042  * @{
00043  */
00044 
00045 /**********************************************************************
00046  * Peripheral Clock Selection Definitions
00047  **********************************************************************/
00048 /** Peripheral clock divider bit position for WDT */
00049 #define    CLKPWR_PCLKSEL_WDT          ((uint32_t)(0))
00050 /** Peripheral clock divider bit position for TIMER0 */
00051 #define    CLKPWR_PCLKSEL_TIMER0          ((uint32_t)(2))
00052 /** Peripheral clock divider bit position for TIMER1 */
00053 #define    CLKPWR_PCLKSEL_TIMER1          ((uint32_t)(4))
00054 /** Peripheral clock divider bit position for UART0 */
00055 #define    CLKPWR_PCLKSEL_UART0          ((uint32_t)(6))
00056 /** Peripheral clock divider bit position for UART1 */
00057 #define    CLKPWR_PCLKSEL_UART1          ((uint32_t)(8))
00058 /** Peripheral clock divider bit position for PWM1 */
00059 #define    CLKPWR_PCLKSEL_PWM1          ((uint32_t)(12))
00060 /** Peripheral clock divider bit position for I2C0 */
00061 #define    CLKPWR_PCLKSEL_I2C0          ((uint32_t)(14))
00062 /** Peripheral clock divider bit position for SPI */
00063 #define    CLKPWR_PCLKSEL_SPI          ((uint32_t)(16))
00064 /** Peripheral clock divider bit position for SSP1 */
00065 #define    CLKPWR_PCLKSEL_SSP1          ((uint32_t)(20))
00066 /** Peripheral clock divider bit position for DAC */
00067 #define    CLKPWR_PCLKSEL_DAC          ((uint32_t)(22))
00068 /** Peripheral clock divider bit position for ADC */
00069 #define    CLKPWR_PCLKSEL_ADC          ((uint32_t)(24))
00070 /** Peripheral clock divider bit position for CAN1 */
00071 #define    CLKPWR_PCLKSEL_CAN1         ((uint32_t)(26))
00072 /** Peripheral clock divider bit position for CAN2 */
00073 #define    CLKPWR_PCLKSEL_CAN2         ((uint32_t)(28))
00074 /** Peripheral clock divider bit position for ACF */
00075 #define    CLKPWR_PCLKSEL_ACF          ((uint32_t)(30))
00076 /** Peripheral clock divider bit position for QEI */
00077 #define    CLKPWR_PCLKSEL_QEI          ((uint32_t)(32))
00078 /** Peripheral clock divider bit position for PCB */
00079 #define    CLKPWR_PCLKSEL_PCB          ((uint32_t)(36))
00080 /** Peripheral clock divider bit position for  I2C1 */
00081 #define    CLKPWR_PCLKSEL_I2C1          ((uint32_t)(38))
00082 /** Peripheral clock divider bit position for SSP0 */
00083 #define    CLKPWR_PCLKSEL_SSP0          ((uint32_t)(42))
00084 /** Peripheral clock divider bit position for TIMER2 */
00085 #define    CLKPWR_PCLKSEL_TIMER2          ((uint32_t)(44))
00086 /** Peripheral clock divider bit position for  TIMER3 */
00087 #define    CLKPWR_PCLKSEL_TIMER3          ((uint32_t)(46))
00088 /** Peripheral clock divider bit position for UART2 */
00089 #define    CLKPWR_PCLKSEL_UART2          ((uint32_t)(48))
00090 /** Peripheral clock divider bit position for UART3 */
00091 #define    CLKPWR_PCLKSEL_UART3          ((uint32_t)(50))
00092 /** Peripheral clock divider bit position for I2C2 */
00093 #define    CLKPWR_PCLKSEL_I2C2          ((uint32_t)(52))
00094 /** Peripheral clock divider bit position for I2S */
00095 #define    CLKPWR_PCLKSEL_I2S          ((uint32_t)(54))
00096 /** Peripheral clock divider bit position for RIT */
00097 #define    CLKPWR_PCLKSEL_RIT          ((uint32_t)(58))
00098 /** Peripheral clock divider bit position for SYSCON */
00099 #define    CLKPWR_PCLKSEL_SYSCON          ((uint32_t)(60))
00100 /** Peripheral clock divider bit position for MC */
00101 #define    CLKPWR_PCLKSEL_MC              ((uint32_t)(62))
00102 
00103 /** Macro for Peripheral Clock Selection register bit values
00104  * Note: When CCLK_DIV_8, Peripheral�s clock is selected to
00105  * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
00106  * when �11�selects PCLK_xyz = CCLK/6 */
00107 /* Peripheral clock divider is set to 4 from CCLK */
00108 #define    CLKPWR_PCLKSEL_CCLK_DIV_4  ((uint32_t)(0))
00109 /** Peripheral clock divider is the same with CCLK */
00110 #define    CLKPWR_PCLKSEL_CCLK_DIV_1  ((uint32_t)(1))
00111 /** Peripheral clock divider is set to 2 from CCLK */
00112 #define    CLKPWR_PCLKSEL_CCLK_DIV_2  ((uint32_t)(2))
00113 
00114 
00115 /********************************************************************
00116 * Power Control for Peripherals Definitions
00117 **********************************************************************/
00118 /** Timer/Counter 0 power/clock control bit */
00119 #define     CLKPWR_PCONP_PCTIM0    ((uint32_t)(1<<1))
00120 /* Timer/Counter 1 power/clock control bit */
00121 #define     CLKPWR_PCONP_PCTIM1    ((uint32_t)(1<<2))
00122 /** UART0 power/clock control bit */
00123 #define     CLKPWR_PCONP_PCUART0      ((uint32_t)(1<<3))
00124 /** UART1 power/clock control bit */
00125 #define     CLKPWR_PCONP_PCUART1      ((uint32_t)(1<<4))
00126 /** PWM1 power/clock control bit */
00127 #define     CLKPWR_PCONP_PCPWM1    ((uint32_t)(1<<6))
00128 /** The I2C0 interface power/clock control bit */
00129 #define     CLKPWR_PCONP_PCI2C0    ((uint32_t)(1<<7))
00130 /** The SPI interface power/clock control bit */
00131 #define     CLKPWR_PCONP_PCSPI      ((uint32_t)(1<<8))
00132 /** The RTC power/clock control bit */
00133 #define     CLKPWR_PCONP_PCRTC      ((uint32_t)(1<<9))
00134 /** The SSP1 interface power/clock control bit */
00135 #define     CLKPWR_PCONP_PCSSP1    ((uint32_t)(1<<10))
00136 /** A/D converter 0 (ADC0) power/clock control bit */
00137 #define     CLKPWR_PCONP_PCAD      ((uint32_t)(1<<12))
00138 /** CAN Controller 1 power/clock control bit */
00139 #define     CLKPWR_PCONP_PCAN1      ((uint32_t)(1<<13))
00140 /** CAN Controller 2 power/clock control bit */
00141 #define     CLKPWR_PCONP_PCAN2     ((uint32_t)(1<<14))
00142 /** GPIO power/clock control bit */
00143 #define    CLKPWR_PCONP_PCGPIO     ((uint32_t)(1<<15))
00144 /** Repetitive Interrupt Timer power/clock control bit */
00145 #define    CLKPWR_PCONP_PCRIT         ((uint32_t)(1<<16))
00146 /** Motor Control PWM */
00147 #define CLKPWR_PCONP_PCMC         ((uint32_t)(1<<17))
00148 /** Quadrature Encoder Interface power/clock control bit */
00149 #define CLKPWR_PCONP_PCQEI         ((uint32_t)(1<<18))
00150 /** The I2C1 interface power/clock control bit */
00151 #define     CLKPWR_PCONP_PCI2C1      ((uint32_t)(1<<19))
00152 /** The SSP0 interface power/clock control bit */
00153 #define     CLKPWR_PCONP_PCSSP0    ((uint32_t)(1<<21))
00154 /** Timer 2 power/clock control bit */
00155 #define     CLKPWR_PCONP_PCTIM2    ((uint32_t)(1<<22))
00156 /** Timer 3 power/clock control bit */
00157 #define     CLKPWR_PCONP_PCTIM3    ((uint32_t)(1<<23))
00158 /** UART 2 power/clock control bit */
00159 #define     CLKPWR_PCONP_PCUART2      ((uint32_t)(1<<24))
00160 /** UART 3 power/clock control bit */
00161 #define     CLKPWR_PCONP_PCUART3      ((uint32_t)(1<<25))
00162 /** I2C interface 2 power/clock control bit */
00163 #define     CLKPWR_PCONP_PCI2C2    ((uint32_t)(1<<26))
00164 /** I2S interface power/clock control bit*/
00165 #define     CLKPWR_PCONP_PCI2S      ((uint32_t)(1<<27))
00166 /** GP DMA function power/clock control bit*/
00167 #define     CLKPWR_PCONP_PCGPDMA      ((uint32_t)(1<<29))
00168 /** Ethernet block power/clock control bit*/
00169 #define     CLKPWR_PCONP_PCENET    ((uint32_t)(1<<30))
00170 /** USB interface power/clock control bit*/
00171 #define     CLKPWR_PCONP_PCUSB      ((uint32_t)(1<<31))
00172 
00173 
00174 /**
00175  * @}
00176  */
00177 /* Private Macros ------------------------------------------------------------- */
00178 /** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros
00179  * @{
00180  */
00181 
00182 /* --------------------- BIT DEFINITIONS -------------------------------------- */
00183 /*********************************************************************//**
00184  * Macro defines for Clock Source Select Register
00185  **********************************************************************/
00186 /** Internal RC oscillator */
00187 #define CLKPWR_CLKSRCSEL_CLKSRC_IRC            ((uint32_t)(0x00))
00188 /** Main oscillator */
00189 #define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC        ((uint32_t)(0x01))
00190 /** RTC oscillator */
00191 #define CLKPWR_CLKSRCSEL_CLKSRC_RTC            ((uint32_t)(0x02))
00192 /** Clock source selection bit mask */
00193 #define CLKPWR_CLKSRCSEL_BITMASK            ((uint32_t)(0x03))
00194 
00195 /*********************************************************************//**
00196  * Macro defines for Clock Output Configuration Register
00197  **********************************************************************/
00198 /* Clock Output Configuration register definition */
00199 /** Selects the CPU clock as the CLKOUT source */
00200 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU        ((uint32_t)(0x00))
00201 /** Selects the main oscillator as the CLKOUT source */
00202 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC    ((uint32_t)(0x01))
00203 /** Selects the Internal RC oscillator as the CLKOUT source */
00204 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC        ((uint32_t)(0x02))
00205 /** Selects the USB clock as the CLKOUT source */
00206 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB        ((uint32_t)(0x03))
00207 /** Selects the RTC oscillator as the CLKOUT source */
00208 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC        ((uint32_t)(0x04))
00209 /** Integer value to divide the output clock by, minus one */
00210 #define CLKPWR_CLKOUTCFG_CLKOUTDIV(n)        ((uint32_t)((n&0x0F)<<4))
00211 /** CLKOUT enable control */
00212 #define CLKPWR_CLKOUTCFG_CLKOUT_EN            ((uint32_t)(1<<8))
00213 /** CLKOUT activity indication */
00214 #define CLKPWR_CLKOUTCFG_CLKOUT_ACT            ((uint32_t)(1<<9))
00215 /** Clock source selection bit mask */
00216 #define CLKPWR_CLKOUTCFG_BITMASK            ((uint32_t)(0x3FF))
00217 
00218 /*********************************************************************//**
00219  * Macro defines for PPL0 Control Register
00220  **********************************************************************/
00221 /** PLL 0 control enable */
00222 #define CLKPWR_PLL0CON_ENABLE        ((uint32_t)(0x01))
00223 /** PLL 0 control connect */
00224 #define CLKPWR_PLL0CON_CONNECT        ((uint32_t)(0x02))
00225 /** PLL 0 control bit mask */
00226 #define CLKPWR_PLL0CON_BITMASK        ((uint32_t)(0x03))
00227 
00228 /*********************************************************************//**
00229  * Macro defines for PPL0 Configuration Register
00230  **********************************************************************/
00231 /** PLL 0 Configuration MSEL field */
00232 #define CLKPWR_PLL0CFG_MSEL(n)        ((uint32_t)(n&0x7FFF))
00233 /** PLL 0 Configuration NSEL field */
00234 #define CLKPWR_PLL0CFG_NSEL(n)        ((uint32_t)((n<<16)&0xFF0000))
00235 /** PLL 0 Configuration bit mask */
00236 #define CLKPWR_PLL0CFG_BITMASK        ((uint32_t)(0xFF7FFF))
00237 
00238 
00239 /*********************************************************************//**
00240  * Macro defines for PPL0 Status Register
00241  **********************************************************************/
00242 /** PLL 0 MSEL value */
00243 #define CLKPWR_PLL0STAT_MSEL(n)        ((uint32_t)(n&0x7FFF))
00244 /** PLL NSEL get value  */
00245 #define CLKPWR_PLL0STAT_NSEL(n)        ((uint32_t)((n>>16)&0xFF))
00246 /** PLL status enable bit */
00247 #define CLKPWR_PLL0STAT_PLLE        ((uint32_t)(1<<24))
00248 /** PLL status Connect bit */
00249 #define CLKPWR_PLL0STAT_PLLC        ((uint32_t)(1<<25))
00250 /** PLL status lock */
00251 #define CLKPWR_PLL0STAT_PLOCK        ((uint32_t)(1<<26))
00252 
00253 /*********************************************************************//**
00254  * Macro defines for PPL0 Feed Register
00255  **********************************************************************/
00256 /** PLL0 Feed bit mask */
00257 #define CLKPWR_PLL0FEED_BITMASK            ((uint32_t)0xFF)
00258 
00259 /*********************************************************************//**
00260  * Macro defines for PLL1 Control Register
00261  **********************************************************************/
00262 /** USB PLL control enable */
00263 #define CLKPWR_PLL1CON_ENABLE        ((uint32_t)(0x01))
00264 /** USB PLL control connect */
00265 #define CLKPWR_PLL1CON_CONNECT        ((uint32_t)(0x02))
00266 /** USB PLL control bit mask */
00267 #define CLKPWR_PLL1CON_BITMASK        ((uint32_t)(0x03))
00268 
00269 /*********************************************************************//**
00270  * Macro defines for PLL1 Configuration Register
00271  **********************************************************************/
00272 /** USB PLL MSEL set value */
00273 #define CLKPWR_PLL1CFG_MSEL(n)        ((uint32_t)(n&0x1F))
00274 /** USB PLL PSEL set value */
00275 #define CLKPWR_PLL1CFG_PSEL(n)        ((uint32_t)((n&0x03)<<5))
00276 /** USB PLL configuration bit mask */
00277 #define CLKPWR_PLL1CFG_BITMASK        ((uint32_t)(0x7F))
00278 
00279 /*********************************************************************//**
00280  * Macro defines for PLL1 Status Register
00281  **********************************************************************/
00282 /** USB PLL MSEL get value  */
00283 #define CLKPWR_PLL1STAT_MSEL(n)        ((uint32_t)(n&0x1F))
00284 /** USB PLL PSEL get value  */
00285 #define CLKPWR_PLL1STAT_PSEL(n)        ((uint32_t)((n>>5)&0x03))
00286 /** USB PLL status enable bit */
00287 #define CLKPWR_PLL1STAT_PLLE        ((uint32_t)(1<<8))
00288 /** USB PLL status Connect bit */
00289 #define CLKPWR_PLL1STAT_PLLC        ((uint32_t)(1<<9))
00290 /** USB PLL status lock */
00291 #define CLKPWR_PLL1STAT_PLOCK        ((uint32_t)(1<<10))
00292 
00293 /*********************************************************************//**
00294  * Macro defines for PLL1 Feed Register
00295  **********************************************************************/
00296 /** PLL1 Feed bit mask */
00297 #define CLKPWR_PLL1FEED_BITMASK        ((uint32_t)0xFF)
00298 
00299 /*********************************************************************//**
00300  * Macro defines for CPU Clock Configuration Register
00301  **********************************************************************/
00302 /** CPU Clock configuration bit mask */
00303 #define CLKPWR_CCLKCFG_BITMASK        ((uint32_t)(0xFF))
00304 
00305 /*********************************************************************//**
00306  * Macro defines for USB Clock Configuration Register
00307  **********************************************************************/
00308 /** USB Clock Configuration bit mask */
00309 #define CLKPWR_USBCLKCFG_BITMASK    ((uint32_t)(0x0F))
00310 
00311 /*********************************************************************//**
00312  * Macro defines for IRC Trim Register
00313  **********************************************************************/
00314 /** IRC Trim bit mask */
00315 #define CLKPWR_IRCTRIM_BITMASK        ((uint32_t)(0x0F))
00316 
00317 /*********************************************************************//**
00318  * Macro defines for Peripheral Clock Selection Register 0 and 1
00319  **********************************************************************/
00320 /** Peripheral Clock Selection 0 mask bit */
00321 #define CLKPWR_PCLKSEL0_BITMASK        ((uint32_t)(0xFFF3F3FF))
00322 /** Peripheral Clock Selection 1 mask bit */
00323 #define CLKPWR_PCLKSEL1_BITMASK        ((uint32_t)(0xFCF3F0F3))
00324 /** Macro to set peripheral clock of each type
00325  * p: position of two bits that hold divider of peripheral clock
00326  * n: value of divider of peripheral clock  to be set */
00327 #define CLKPWR_PCLKSEL_SET(p,n)        _SBF(p,n)
00328 /** Macro to mask peripheral clock of each type */
00329 #define CLKPWR_PCLKSEL_BITMASK(p)    _SBF(p,0x03)
00330 /** Macro to get peripheral clock of each type */
00331 #define CLKPWR_PCLKSEL_GET(p, n)    ((uint32_t)((n>>p)&0x03))
00332 
00333 /*********************************************************************//**
00334  * Macro defines for Power Mode Control Register
00335  **********************************************************************/
00336 /** Power mode control bit 0 */
00337 #define CLKPWR_PCON_PM0            ((uint32_t)(1<<0))
00338 /** Power mode control bit 1 */
00339 #define CLKPWR_PCON_PM1            ((uint32_t)(1<<1))
00340 /** Brown-Out Reduced Power Mode */
00341 #define CLKPWR_PCON_BODPDM        ((uint32_t)(1<<2))
00342 /** Brown-Out Global Disable */
00343 #define CLKPWR_PCON_BOGD        ((uint32_t)(1<<3))
00344 /** Brown Out Reset Disable */
00345 #define CLKPWR_PCON_BORD        ((uint32_t)(1<<4))
00346 /** Sleep Mode entry flag */
00347 #define CLKPWR_PCON_SMFLAG        ((uint32_t)(1<<8))
00348 /** Deep Sleep entry flag */
00349 #define CLKPWR_PCON_DSFLAG        ((uint32_t)(1<<9))
00350 /** Power-down entry flag */
00351 #define CLKPWR_PCON_PDFLAG        ((uint32_t)(1<<10))
00352 /** Deep Power-down entry flag */
00353 #define CLKPWR_PCON_DPDFLAG        ((uint32_t)(1<<11))
00354 
00355 /*********************************************************************//**
00356  * Macro defines for Power Control for Peripheral Register
00357  **********************************************************************/
00358 /** Power Control for Peripherals bit mask */
00359 #define CLKPWR_PCONP_BITMASK    0xEFEFF7DE
00360 
00361 /**
00362  * @}
00363  */
00364 
00365 
00366 /* Public Functions ----------------------------------------------------------- */
00367 /** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
00368  * @{
00369  */
00370 
00371 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
00372 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
00373 uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
00374 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
00375 void CLKPWR_Sleep(void);
00376 void CLKPWR_DeepSleep(void);
00377 void CLKPWR_PowerDown(void);
00378 void CLKPWR_DeepPowerDown(void);
00379 
00380 /**
00381  * @}
00382  */
00383 
00384 
00385 #ifdef __cplusplus
00386 }
00387 #endif
00388 
00389 #endif /* LPC17XX_CLKPWR_H_ */
00390 
00391 /**
00392  * @}
00393  */
00394 
00395 /* --------------------------------- End Of File ------------------------------ */
00396 /* @endcond */