Benoît Locher
Rewrite from scratch a TCP/IP stack for mbed. So far the following parts are usable: Drivers: - EMAC driver (from CMSIS 2.0) Protocols: - Ethernet protocol - ARP over ethernet for IPv4 - IPv4 over Ethernet - ICMPv4 over IPv4 - UDPv4 over IPv4 APIs: - Sockets for UDPv4 The structure of this stack is designed to be very modular. Each protocol can register one or more protocol to handle its payload, and in each protocol, an API can be hooked (like Sockets for example). This is an early release.
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lpc17xx.h
00001 /* @cond */ 00002 /**************************************************************************//** 00003 * @file LPC17xx.h 00004 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for 00005 * NXP LPC17xx Device Series 00006 * @version: V1.08 00007 * @date: 21. December 2009 00008 * 00009 * @note 00010 * Copyright (C) 2009 ARM Limited. All rights reserved. 00011 * 00012 * @par 00013 * ARM Limited (ARM) is supplying this software for use with Cortex-M 00014 * processor based microcontrollers. This file can be freely distributed 00015 * within development tools that are supporting such ARM based processors. 00016 * 00017 * @par 00018 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 00019 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 00020 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 00021 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 00022 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 00023 * 00024 ******************************************************************************/ 00025 00026 00027 #ifndef __LPC17xx_H__ 00028 #define __LPC17xx_H__ 00029 00030 /* 00031 * ========================================================================== 00032 * ---------- Interrupt Number Definition ----------------------------------- 00033 * ========================================================================== 00034 */ 00035 00036 /** @addtogroup LPC17xx_System 00037 * @{ 00038 */ 00039 00040 /** @brief IRQ interrupt source definition */ 00041 typedef enum IRQn 00042 { 00043 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ 00044 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 00045 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 00046 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 00047 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 00048 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 00049 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 00050 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 00051 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 00052 00053 /****** LPC17xx Specific Interrupt Numbers *******************************************************/ 00054 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ 00055 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ 00056 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ 00057 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ 00058 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ 00059 UART0_IRQn = 5, /*!< UART0 Interrupt */ 00060 UART1_IRQn = 6, /*!< UART1 Interrupt */ 00061 UART2_IRQn = 7, /*!< UART2 Interrupt */ 00062 UART3_IRQn = 8, /*!< UART3 Interrupt */ 00063 PWM1_IRQn = 9, /*!< PWM1 Interrupt */ 00064 I2C0_IRQn = 10, /*!< I2C0 Interrupt */ 00065 I2C1_IRQn = 11, /*!< I2C1 Interrupt */ 00066 I2C2_IRQn = 12, /*!< I2C2 Interrupt */ 00067 SPI_IRQn = 13, /*!< SPI Interrupt */ 00068 SSP0_IRQn = 14, /*!< SSP0 Interrupt */ 00069 SSP1_IRQn = 15, /*!< SSP1 Interrupt */ 00070 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ 00071 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ 00072 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ 00073 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ 00074 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ 00075 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ 00076 ADC_IRQn = 22, /*!< A/D Converter Interrupt */ 00077 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ 00078 USB_IRQn = 24, /*!< USB Interrupt */ 00079 CAN_IRQn = 25, /*!< CAN Interrupt */ 00080 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ 00081 I2S_IRQn = 27, /*!< I2S Interrupt */ 00082 ENET_IRQn = 28, /*!< Ethernet Interrupt */ 00083 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ 00084 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ 00085 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ 00086 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ 00087 USBActivity_IRQn = 33, /*!< USB Activity Interrupt */ 00088 CANActivity_IRQn = 34, /*!< CAN Activity Interrupt */ 00089 } IRQn_Type; 00090 00091 00092 /* 00093 * ========================================================================== 00094 * ----------- Processor and Core Peripheral Section ------------------------ 00095 * ========================================================================== 00096 */ 00097 00098 /* Configuration of the Cortex-M3 Processor and Core Peripherals */ 00099 #define __MPU_PRESENT 1 /*!< MPU present or not */ 00100 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ 00101 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 00102 00103 00104 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ 00105 #include "system_LPC17xx.h" /* System Header */ 00106 00107 00108 /******************************************************************************/ 00109 /* Device Specific Peripheral registers structures */ 00110 /******************************************************************************/ 00111 00112 #if defined ( __CC_ARM ) 00113 #pragma anon_unions 00114 #endif 00115 00116 /*------------- System Control (SC) ------------------------------------------*/ 00117 /** @brief System Control (SC) register structure definition */ 00118 typedef struct 00119 { 00120 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ 00121 uint32_t RESERVED0[31]; 00122 __IO uint32_t PLL0CON; /* Clocking and Power Control */ 00123 __IO uint32_t PLL0CFG; 00124 __I uint32_t PLL0STAT; 00125 __O uint32_t PLL0FEED; 00126 uint32_t RESERVED1[4]; 00127 __IO uint32_t PLL1CON; 00128 __IO uint32_t PLL1CFG; 00129 __I uint32_t PLL1STAT; 00130 __O uint32_t PLL1FEED; 00131 uint32_t RESERVED2[4]; 00132 __IO uint32_t PCON; 00133 __IO uint32_t PCONP; 00134 uint32_t RESERVED3[15]; 00135 __IO uint32_t CCLKCFG; 00136 __IO uint32_t USBCLKCFG; 00137 __IO uint32_t CLKSRCSEL; 00138 __IO uint32_t CANSLEEPCLR; 00139 __IO uint32_t CANWAKEFLAGS; 00140 uint32_t RESERVED4[10]; 00141 __IO uint32_t EXTINT; /* External Interrupts */ 00142 uint32_t RESERVED5; 00143 __IO uint32_t EXTMODE; 00144 __IO uint32_t EXTPOLAR; 00145 uint32_t RESERVED6[12]; 00146 __IO uint32_t RSID; /* Reset */ 00147 uint32_t RESERVED7[7]; 00148 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ 00149 __IO uint32_t IRCTRIM; /* Clock Dividers */ 00150 __IO uint32_t PCLKSEL0; 00151 __IO uint32_t PCLKSEL1; 00152 uint32_t RESERVED8[4]; 00153 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ 00154 __IO uint32_t DMAREQSEL; 00155 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ 00156 } LPC_SC_TypeDef; 00157 00158 /*------------- Pin Connect Block (PINCON) -----------------------------------*/ 00159 /** @brief Pin Connect Block (PINCON) register structure definition */ 00160 typedef struct 00161 { 00162 __IO uint32_t PINSEL0; 00163 __IO uint32_t PINSEL1; 00164 __IO uint32_t PINSEL2; 00165 __IO uint32_t PINSEL3; 00166 __IO uint32_t PINSEL4; 00167 __IO uint32_t PINSEL5; 00168 __IO uint32_t PINSEL6; 00169 __IO uint32_t PINSEL7; 00170 __IO uint32_t PINSEL8; 00171 __IO uint32_t PINSEL9; 00172 __IO uint32_t PINSEL10; 00173 uint32_t RESERVED0[5]; 00174 __IO uint32_t PINMODE0; 00175 __IO uint32_t PINMODE1; 00176 __IO uint32_t PINMODE2; 00177 __IO uint32_t PINMODE3; 00178 __IO uint32_t PINMODE4; 00179 __IO uint32_t PINMODE5; 00180 __IO uint32_t PINMODE6; 00181 __IO uint32_t PINMODE7; 00182 __IO uint32_t PINMODE8; 00183 __IO uint32_t PINMODE9; 00184 __IO uint32_t PINMODE_OD0; 00185 __IO uint32_t PINMODE_OD1; 00186 __IO uint32_t PINMODE_OD2; 00187 __IO uint32_t PINMODE_OD3; 00188 __IO uint32_t PINMODE_OD4; 00189 __IO uint32_t I2CPADCFG; 00190 } LPC_PINCON_TypeDef; 00191 00192 /*------------- General Purpose Input/Output (GPIO) --------------------------*/ 00193 /** @brief General Purpose Input/Output (GPIO) register structure definition */ 00194 typedef struct 00195 { 00196 union { 00197 __IO uint32_t FIODIR; 00198 struct { 00199 __IO uint16_t FIODIRL; 00200 __IO uint16_t FIODIRH; 00201 }; 00202 struct { 00203 __IO uint8_t FIODIR0; 00204 __IO uint8_t FIODIR1; 00205 __IO uint8_t FIODIR2; 00206 __IO uint8_t FIODIR3; 00207 }; 00208 }; 00209 uint32_t RESERVED0[3]; 00210 union { 00211 __IO uint32_t FIOMASK; 00212 struct { 00213 __IO uint16_t FIOMASKL; 00214 __IO uint16_t FIOMASKH; 00215 }; 00216 struct { 00217 __IO uint8_t FIOMASK0; 00218 __IO uint8_t FIOMASK1; 00219 __IO uint8_t FIOMASK2; 00220 __IO uint8_t FIOMASK3; 00221 }; 00222 }; 00223 union { 00224 __IO uint32_t FIOPIN; 00225 struct { 00226 __IO uint16_t FIOPINL; 00227 __IO uint16_t FIOPINH; 00228 }; 00229 struct { 00230 __IO uint8_t FIOPIN0; 00231 __IO uint8_t FIOPIN1; 00232 __IO uint8_t FIOPIN2; 00233 __IO uint8_t FIOPIN3; 00234 }; 00235 }; 00236 union { 00237 __IO uint32_t FIOSET; 00238 struct { 00239 __IO uint16_t FIOSETL; 00240 __IO uint16_t FIOSETH; 00241 }; 00242 struct { 00243 __IO uint8_t FIOSET0; 00244 __IO uint8_t FIOSET1; 00245 __IO uint8_t FIOSET2; 00246 __IO uint8_t FIOSET3; 00247 }; 00248 }; 00249 union { 00250 __O uint32_t FIOCLR; 00251 struct { 00252 __O uint16_t FIOCLRL; 00253 __O uint16_t FIOCLRH; 00254 }; 00255 struct { 00256 __O uint8_t FIOCLR0; 00257 __O uint8_t FIOCLR1; 00258 __O uint8_t FIOCLR2; 00259 __O uint8_t FIOCLR3; 00260 }; 00261 }; 00262 } LPC_GPIO_TypeDef; 00263 00264 /** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */ 00265 typedef struct 00266 { 00267 __I uint32_t IntStatus; 00268 __I uint32_t IO0IntStatR; 00269 __I uint32_t IO0IntStatF; 00270 __O uint32_t IO0IntClr; 00271 __IO uint32_t IO0IntEnR; 00272 __IO uint32_t IO0IntEnF; 00273 uint32_t RESERVED0[3]; 00274 __I uint32_t IO2IntStatR; 00275 __I uint32_t IO2IntStatF; 00276 __O uint32_t IO2IntClr; 00277 __IO uint32_t IO2IntEnR; 00278 __IO uint32_t IO2IntEnF; 00279 } LPC_GPIOINT_TypeDef; 00280 00281 /*------------- Timer (TIM) --------------------------------------------------*/ 00282 /** @brief Timer (TIM) register structure definition */ 00283 typedef struct 00284 { 00285 __IO uint32_t IR; 00286 __IO uint32_t TCR; 00287 __IO uint32_t TC; 00288 __IO uint32_t PR; 00289 __IO uint32_t PC; 00290 __IO uint32_t MCR; 00291 __IO uint32_t MR0; 00292 __IO uint32_t MR1; 00293 __IO uint32_t MR2; 00294 __IO uint32_t MR3; 00295 __IO uint32_t CCR; 00296 __I uint32_t CR0; 00297 __I uint32_t CR1; 00298 uint32_t RESERVED0[2]; 00299 __IO uint32_t EMR; 00300 uint32_t RESERVED1[12]; 00301 __IO uint32_t CTCR; 00302 } LPC_TIM_TypeDef; 00303 00304 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ 00305 /** @brief Pulse-Width Modulation (PWM) register structure definition */ 00306 typedef struct 00307 { 00308 __IO uint32_t IR; 00309 __IO uint32_t TCR; 00310 __IO uint32_t TC; 00311 __IO uint32_t PR; 00312 __IO uint32_t PC; 00313 __IO uint32_t MCR; 00314 __IO uint32_t MR0; 00315 __IO uint32_t MR1; 00316 __IO uint32_t MR2; 00317 __IO uint32_t MR3; 00318 __IO uint32_t CCR; 00319 __I uint32_t CR0; 00320 __I uint32_t CR1; 00321 __I uint32_t CR2; 00322 __I uint32_t CR3; 00323 uint32_t RESERVED0; 00324 __IO uint32_t MR4; 00325 __IO uint32_t MR5; 00326 __IO uint32_t MR6; 00327 __IO uint32_t PCR; 00328 __IO uint32_t LER; 00329 uint32_t RESERVED1[7]; 00330 __IO uint32_t CTCR; 00331 } LPC_PWM_TypeDef; 00332 00333 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ 00334 /** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */ 00335 typedef struct 00336 { 00337 union { 00338 __I uint8_t RBR; 00339 __O uint8_t THR; 00340 __IO uint8_t DLL; 00341 uint32_t RESERVED0; 00342 }; 00343 union { 00344 __IO uint8_t DLM; 00345 __IO uint32_t IER; 00346 }; 00347 union { 00348 __I uint32_t IIR; 00349 __O uint8_t FCR; 00350 }; 00351 __IO uint8_t LCR; 00352 uint8_t RESERVED1[7]; 00353 __I uint8_t LSR; 00354 uint8_t RESERVED2[7]; 00355 __IO uint8_t SCR; 00356 uint8_t RESERVED3[3]; 00357 __IO uint32_t ACR; 00358 __IO uint8_t ICR; 00359 uint8_t RESERVED4[3]; 00360 __IO uint8_t FDR; 00361 uint8_t RESERVED5[7]; 00362 __IO uint8_t TER; 00363 uint8_t RESERVED6[39]; 00364 __I uint8_t FIFOLVL; 00365 } LPC_UART_TypeDef; 00366 00367 /** @brief Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */ 00368 typedef struct 00369 { 00370 union { 00371 __I uint8_t RBR; 00372 __O uint8_t THR; 00373 __IO uint8_t DLL; 00374 uint32_t RESERVED0; 00375 }; 00376 union { 00377 __IO uint8_t DLM; 00378 __IO uint32_t IER; 00379 }; 00380 union { 00381 __I uint32_t IIR; 00382 __O uint8_t FCR; 00383 }; 00384 __IO uint8_t LCR; 00385 uint8_t RESERVED1[7]; 00386 __I uint8_t LSR; 00387 uint8_t RESERVED2[7]; 00388 __IO uint8_t SCR; 00389 uint8_t RESERVED3[3]; 00390 __IO uint32_t ACR; 00391 __IO uint8_t ICR; 00392 uint8_t RESERVED4[3]; 00393 __IO uint8_t FDR; 00394 uint8_t RESERVED5[7]; 00395 __IO uint8_t TER; 00396 uint8_t RESERVED6[39]; 00397 __I uint8_t FIFOLVL; 00398 } LPC_UART0_TypeDef; 00399 00400 /** @brief Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition */ 00401 typedef struct 00402 { 00403 union { 00404 __I uint8_t RBR; 00405 __O uint8_t THR; 00406 __IO uint8_t DLL; 00407 uint32_t RESERVED0; 00408 }; 00409 union { 00410 __IO uint8_t DLM; 00411 __IO uint32_t IER; 00412 }; 00413 union { 00414 __I uint32_t IIR; 00415 __O uint8_t FCR; 00416 }; 00417 __IO uint8_t LCR; 00418 uint8_t RESERVED1[3]; 00419 __IO uint8_t MCR; 00420 uint8_t RESERVED2[3]; 00421 __I uint8_t LSR; 00422 uint8_t RESERVED3[3]; 00423 __I uint8_t MSR; 00424 uint8_t RESERVED4[3]; 00425 __IO uint8_t SCR; 00426 uint8_t RESERVED5[3]; 00427 __IO uint32_t ACR; 00428 uint32_t RESERVED6; 00429 __IO uint32_t FDR; 00430 uint32_t RESERVED7; 00431 __IO uint8_t TER; 00432 uint8_t RESERVED8[27]; 00433 __IO uint8_t RS485CTRL; 00434 uint8_t RESERVED9[3]; 00435 __IO uint8_t ADRMATCH; 00436 uint8_t RESERVED10[3]; 00437 __IO uint8_t RS485DLY; 00438 uint8_t RESERVED11[3]; 00439 __I uint8_t FIFOLVL; 00440 } LPC_UART1_TypeDef; 00441 00442 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/ 00443 /** @brief Serial Peripheral Interface (SPI) register structure definition */ 00444 typedef struct 00445 { 00446 __IO uint32_t SPCR; 00447 __I uint32_t SPSR; 00448 __IO uint32_t SPDR; 00449 __IO uint32_t SPCCR; 00450 uint32_t RESERVED0[3]; 00451 __IO uint32_t SPINT; 00452 } LPC_SPI_TypeDef; 00453 00454 /*------------- Synchronous Serial Communication (SSP) -----------------------*/ 00455 /** @brief Synchronous Serial Communication (SSP) register structure definition */ 00456 typedef struct 00457 { 00458 __IO uint32_t CR0; 00459 __IO uint32_t CR1; 00460 __IO uint32_t DR; 00461 __I uint32_t SR; 00462 __IO uint32_t CPSR; 00463 __IO uint32_t IMSC; 00464 __IO uint32_t RIS; 00465 __IO uint32_t MIS; 00466 __IO uint32_t ICR; 00467 __IO uint32_t DMACR; 00468 } LPC_SSP_TypeDef; 00469 00470 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ 00471 /** @brief Inter-Integrated Circuit (I2C) register structure definition */ 00472 typedef struct 00473 { 00474 __IO uint32_t I2CONSET; 00475 __I uint32_t I2STAT; 00476 __IO uint32_t I2DAT; 00477 __IO uint32_t I2ADR0; 00478 __IO uint32_t I2SCLH; 00479 __IO uint32_t I2SCLL; 00480 __O uint32_t I2CONCLR; 00481 __IO uint32_t MMCTRL; 00482 __IO uint32_t I2ADR1; 00483 __IO uint32_t I2ADR2; 00484 __IO uint32_t I2ADR3; 00485 __I uint32_t I2DATA_BUFFER; 00486 __IO uint32_t I2MASK0; 00487 __IO uint32_t I2MASK1; 00488 __IO uint32_t I2MASK2; 00489 __IO uint32_t I2MASK3; 00490 } LPC_I2C_TypeDef; 00491 00492 /*------------- Inter IC Sound (I2S) -----------------------------------------*/ 00493 /** @brief Inter IC Sound (I2S) register structure definition */ 00494 typedef struct 00495 { 00496 __IO uint32_t I2SDAO; 00497 __IO uint32_t I2SDAI; 00498 __O uint32_t I2STXFIFO; 00499 __I uint32_t I2SRXFIFO; 00500 __I uint32_t I2SSTATE; 00501 __IO uint32_t I2SDMA1; 00502 __IO uint32_t I2SDMA2; 00503 __IO uint32_t I2SIRQ; 00504 __IO uint32_t I2STXRATE; 00505 __IO uint32_t I2SRXRATE; 00506 __IO uint32_t I2STXBITRATE; 00507 __IO uint32_t I2SRXBITRATE; 00508 __IO uint32_t I2STXMODE; 00509 __IO uint32_t I2SRXMODE; 00510 } LPC_I2S_TypeDef; 00511 00512 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ 00513 /** @brief Repetitive Interrupt Timer (RIT) register structure definition */ 00514 typedef struct 00515 { 00516 __IO uint32_t RICOMPVAL; 00517 __IO uint32_t RIMASK; 00518 __IO uint8_t RICTRL; 00519 uint8_t RESERVED0[3]; 00520 __IO uint32_t RICOUNTER; 00521 } LPC_RIT_TypeDef; 00522 00523 /*------------- Real-Time Clock (RTC) ----------------------------------------*/ 00524 /** @brief Real-Time Clock (RTC) register structure definition */ 00525 typedef struct 00526 { 00527 __IO uint8_t ILR; 00528 uint8_t RESERVED0[7]; 00529 __IO uint8_t CCR; 00530 uint8_t RESERVED1[3]; 00531 __IO uint8_t CIIR; 00532 uint8_t RESERVED2[3]; 00533 __IO uint8_t AMR; 00534 uint8_t RESERVED3[3]; 00535 __I uint32_t CTIME0; 00536 __I uint32_t CTIME1; 00537 __I uint32_t CTIME2; 00538 __IO uint8_t SEC; 00539 uint8_t RESERVED4[3]; 00540 __IO uint8_t MIN; 00541 uint8_t RESERVED5[3]; 00542 __IO uint8_t HOUR; 00543 uint8_t RESERVED6[3]; 00544 __IO uint8_t DOM; 00545 uint8_t RESERVED7[3]; 00546 __IO uint8_t DOW; 00547 uint8_t RESERVED8[3]; 00548 __IO uint16_t DOY; 00549 uint16_t RESERVED9; 00550 __IO uint8_t MONTH; 00551 uint8_t RESERVED10[3]; 00552 __IO uint16_t YEAR; 00553 uint16_t RESERVED11; 00554 __IO uint32_t CALIBRATION; 00555 __IO uint32_t GPREG0; 00556 __IO uint32_t GPREG1; 00557 __IO uint32_t GPREG2; 00558 __IO uint32_t GPREG3; 00559 __IO uint32_t GPREG4; 00560 __IO uint8_t RTC_AUXEN; 00561 uint8_t RESERVED12[3]; 00562 __IO uint8_t RTC_AUX; 00563 uint8_t RESERVED13[3]; 00564 __IO uint8_t ALSEC; 00565 uint8_t RESERVED14[3]; 00566 __IO uint8_t ALMIN; 00567 uint8_t RESERVED15[3]; 00568 __IO uint8_t ALHOUR; 00569 uint8_t RESERVED16[3]; 00570 __IO uint8_t ALDOM; 00571 uint8_t RESERVED17[3]; 00572 __IO uint8_t ALDOW; 00573 uint8_t RESERVED18[3]; 00574 __IO uint16_t ALDOY; 00575 uint16_t RESERVED19; 00576 __IO uint8_t ALMON; 00577 uint8_t RESERVED20[3]; 00578 __IO uint16_t ALYEAR; 00579 uint16_t RESERVED21; 00580 } LPC_RTC_TypeDef; 00581 00582 /*------------- Watchdog Timer (WDT) -----------------------------------------*/ 00583 /** @brief Watchdog Timer (WDT) register structure definition */ 00584 typedef struct 00585 { 00586 __IO uint8_t WDMOD; 00587 uint8_t RESERVED0[3]; 00588 __IO uint32_t WDTC; 00589 __O uint8_t WDFEED; 00590 uint8_t RESERVED1[3]; 00591 __I uint32_t WDTV; 00592 __IO uint32_t WDCLKSEL; 00593 } LPC_WDT_TypeDef; 00594 00595 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ 00596 /** @brief Analog-to-Digital Converter (ADC) register structure definition */ 00597 typedef struct 00598 { 00599 __IO uint32_t ADCR; 00600 __IO uint32_t ADGDR; 00601 uint32_t RESERVED0; 00602 __IO uint32_t ADINTEN; 00603 __I uint32_t ADDR0; 00604 __I uint32_t ADDR1; 00605 __I uint32_t ADDR2; 00606 __I uint32_t ADDR3; 00607 __I uint32_t ADDR4; 00608 __I uint32_t ADDR5; 00609 __I uint32_t ADDR6; 00610 __I uint32_t ADDR7; 00611 __I uint32_t ADSTAT; 00612 __IO uint32_t ADTRM; 00613 } LPC_ADC_TypeDef; 00614 00615 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ 00616 /** @brief Digital-to-Analog Converter (DAC) register structure definition */ 00617 typedef struct 00618 { 00619 __IO uint32_t DACR; 00620 __IO uint32_t DACCTRL; 00621 __IO uint16_t DACCNTVAL; 00622 } LPC_DAC_TypeDef; 00623 00624 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ 00625 /** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */ 00626 typedef struct 00627 { 00628 __I uint32_t MCCON; 00629 __O uint32_t MCCON_SET; 00630 __O uint32_t MCCON_CLR; 00631 __I uint32_t MCCAPCON; 00632 __O uint32_t MCCAPCON_SET; 00633 __O uint32_t MCCAPCON_CLR; 00634 __IO uint32_t MCTIM0; 00635 __IO uint32_t MCTIM1; 00636 __IO uint32_t MCTIM2; 00637 __IO uint32_t MCPER0; 00638 __IO uint32_t MCPER1; 00639 __IO uint32_t MCPER2; 00640 __IO uint32_t MCPW0; 00641 __IO uint32_t MCPW1; 00642 __IO uint32_t MCPW2; 00643 __IO uint32_t MCDEADTIME; 00644 __IO uint32_t MCCCP; 00645 __IO uint32_t MCCR0; 00646 __IO uint32_t MCCR1; 00647 __IO uint32_t MCCR2; 00648 __I uint32_t MCINTEN; 00649 __O uint32_t MCINTEN_SET; 00650 __O uint32_t MCINTEN_CLR; 00651 __I uint32_t MCCNTCON; 00652 __O uint32_t MCCNTCON_SET; 00653 __O uint32_t MCCNTCON_CLR; 00654 __I uint32_t MCINTFLAG; 00655 __O uint32_t MCINTFLAG_SET; 00656 __O uint32_t MCINTFLAG_CLR; 00657 __O uint32_t MCCAP_CLR; 00658 } LPC_MCPWM_TypeDef; 00659 00660 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ 00661 /** @brief Quadrature Encoder Interface (QEI) register structure definition */ 00662 typedef struct 00663 { 00664 __O uint32_t QEICON; 00665 __I uint32_t QEISTAT; 00666 __IO uint32_t QEICONF; 00667 __I uint32_t QEIPOS; 00668 __IO uint32_t QEIMAXPOS; 00669 __IO uint32_t CMPOS0; 00670 __IO uint32_t CMPOS1; 00671 __IO uint32_t CMPOS2; 00672 __I uint32_t INXCNT; 00673 __IO uint32_t INXCMP; 00674 __IO uint32_t QEILOAD; 00675 __I uint32_t QEITIME; 00676 __I uint32_t QEIVEL; 00677 __I uint32_t QEICAP; 00678 __IO uint32_t VELCOMP; 00679 __IO uint32_t FILTER; 00680 uint32_t RESERVED0[998]; 00681 __O uint32_t QEIIEC; 00682 __O uint32_t QEIIES; 00683 __I uint32_t QEIINTSTAT; 00684 __I uint32_t QEIIE; 00685 __O uint32_t QEICLR; 00686 __O uint32_t QEISET; 00687 } LPC_QEI_TypeDef; 00688 00689 /*------------- Controller Area Network (CAN) --------------------------------*/ 00690 /** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */ 00691 typedef struct 00692 { 00693 __IO uint32_t mask[512]; /* ID Masks */ 00694 } LPC_CANAF_RAM_TypeDef; 00695 00696 /** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */ 00697 typedef struct /* Acceptance Filter Registers */ 00698 { 00699 __IO uint32_t AFMR; 00700 __IO uint32_t SFF_sa; 00701 __IO uint32_t SFF_GRP_sa; 00702 __IO uint32_t EFF_sa; 00703 __IO uint32_t EFF_GRP_sa; 00704 __IO uint32_t ENDofTable; 00705 __I uint32_t LUTerrAd; 00706 __I uint32_t LUTerr; 00707 __IO uint32_t FCANIE; 00708 __IO uint32_t FCANIC0; 00709 __IO uint32_t FCANIC1; 00710 } LPC_CANAF_TypeDef; 00711 00712 /** @brief Controller Area Network Central (CANCR) register structure definition */ 00713 typedef struct /* Central Registers */ 00714 { 00715 __I uint32_t CANTxSR; 00716 __I uint32_t CANRxSR; 00717 __I uint32_t CANMSR; 00718 } LPC_CANCR_TypeDef; 00719 00720 /** @brief Controller Area Network Controller (CAN) register structure definition */ 00721 typedef struct /* Controller Registers */ 00722 { 00723 __IO uint32_t MOD; 00724 __O uint32_t CMR; 00725 __IO uint32_t GSR; 00726 __I uint32_t ICR; 00727 __IO uint32_t IER; 00728 __IO uint32_t BTR; 00729 __IO uint32_t EWL; 00730 __I uint32_t SR; 00731 __IO uint32_t RFS; 00732 __IO uint32_t RID; 00733 __IO uint32_t RDA; 00734 __IO uint32_t RDB; 00735 __IO uint32_t TFI1; 00736 __IO uint32_t TID1; 00737 __IO uint32_t TDA1; 00738 __IO uint32_t TDB1; 00739 __IO uint32_t TFI2; 00740 __IO uint32_t TID2; 00741 __IO uint32_t TDA2; 00742 __IO uint32_t TDB2; 00743 __IO uint32_t TFI3; 00744 __IO uint32_t TID3; 00745 __IO uint32_t TDA3; 00746 __IO uint32_t TDB3; 00747 } LPC_CAN_TypeDef; 00748 00749 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ 00750 /** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */ 00751 typedef struct /* Common Registers */ 00752 { 00753 __I uint32_t DMACIntStat; 00754 __I uint32_t DMACIntTCStat; 00755 __O uint32_t DMACIntTCClear; 00756 __I uint32_t DMACIntErrStat; 00757 __O uint32_t DMACIntErrClr; 00758 __I uint32_t DMACRawIntTCStat; 00759 __I uint32_t DMACRawIntErrStat; 00760 __I uint32_t DMACEnbldChns; 00761 __IO uint32_t DMACSoftBReq; 00762 __IO uint32_t DMACSoftSReq; 00763 __IO uint32_t DMACSoftLBReq; 00764 __IO uint32_t DMACSoftLSReq; 00765 __IO uint32_t DMACConfig; 00766 __IO uint32_t DMACSync; 00767 } LPC_GPDMA_TypeDef; 00768 00769 /** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */ 00770 typedef struct /* Channel Registers */ 00771 { 00772 __IO uint32_t DMACCSrcAddr; 00773 __IO uint32_t DMACCDestAddr; 00774 __IO uint32_t DMACCLLI; 00775 __IO uint32_t DMACCControl; 00776 __IO uint32_t DMACCConfig; 00777 } LPC_GPDMACH_TypeDef; 00778 00779 /*------------- Universal Serial Bus (USB) -----------------------------------*/ 00780 /** @brief Universal Serial Bus (USB) register structure definition */ 00781 typedef struct 00782 { 00783 __I uint32_t HcRevision; /* USB Host Registers */ 00784 __IO uint32_t HcControl; 00785 __IO uint32_t HcCommandStatus; 00786 __IO uint32_t HcInterruptStatus; 00787 __IO uint32_t HcInterruptEnable; 00788 __IO uint32_t HcInterruptDisable; 00789 __IO uint32_t HcHCCA; 00790 __I uint32_t HcPeriodCurrentED; 00791 __IO uint32_t HcControlHeadED; 00792 __IO uint32_t HcControlCurrentED; 00793 __IO uint32_t HcBulkHeadED; 00794 __IO uint32_t HcBulkCurrentED; 00795 __I uint32_t HcDoneHead; 00796 __IO uint32_t HcFmInterval; 00797 __I uint32_t HcFmRemaining; 00798 __I uint32_t HcFmNumber; 00799 __IO uint32_t HcPeriodicStart; 00800 __IO uint32_t HcLSTreshold; 00801 __IO uint32_t HcRhDescriptorA; 00802 __IO uint32_t HcRhDescriptorB; 00803 __IO uint32_t HcRhStatus; 00804 __IO uint32_t HcRhPortStatus1; 00805 __IO uint32_t HcRhPortStatus2; 00806 uint32_t RESERVED0[40]; 00807 __I uint32_t Module_ID; 00808 00809 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ 00810 __IO uint32_t OTGIntEn; 00811 __O uint32_t OTGIntSet; 00812 __O uint32_t OTGIntClr; 00813 __IO uint32_t OTGStCtrl; 00814 __IO uint32_t OTGTmr; 00815 uint32_t RESERVED1[58]; 00816 00817 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ 00818 __IO uint32_t USBDevIntEn; 00819 __O uint32_t USBDevIntClr; 00820 __O uint32_t USBDevIntSet; 00821 00822 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ 00823 __I uint32_t USBCmdData; 00824 00825 __I uint32_t USBRxData; /* USB Device Transfer Registers */ 00826 __O uint32_t USBTxData; 00827 __I uint32_t USBRxPLen; 00828 __O uint32_t USBTxPLen; 00829 __IO uint32_t USBCtrl; 00830 __O uint32_t USBDevIntPri; 00831 00832 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ 00833 __IO uint32_t USBEpIntEn; 00834 __O uint32_t USBEpIntClr; 00835 __O uint32_t USBEpIntSet; 00836 __O uint32_t USBEpIntPri; 00837 00838 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ 00839 __O uint32_t USBEpInd; 00840 __IO uint32_t USBMaxPSize; 00841 00842 __I uint32_t USBDMARSt; /* USB Device DMA Registers */ 00843 __O uint32_t USBDMARClr; 00844 __O uint32_t USBDMARSet; 00845 uint32_t RESERVED2[9]; 00846 __IO uint32_t USBUDCAH; 00847 __I uint32_t USBEpDMASt; 00848 __O uint32_t USBEpDMAEn; 00849 __O uint32_t USBEpDMADis; 00850 __I uint32_t USBDMAIntSt; 00851 __IO uint32_t USBDMAIntEn; 00852 uint32_t RESERVED3[2]; 00853 __I uint32_t USBEoTIntSt; 00854 __O uint32_t USBEoTIntClr; 00855 __O uint32_t USBEoTIntSet; 00856 __I uint32_t USBNDDRIntSt; 00857 __O uint32_t USBNDDRIntClr; 00858 __O uint32_t USBNDDRIntSet; 00859 __I uint32_t USBSysErrIntSt; 00860 __O uint32_t USBSysErrIntClr; 00861 __O uint32_t USBSysErrIntSet; 00862 uint32_t RESERVED4[15]; 00863 00864 union { 00865 __I uint32_t I2C_RX; /* USB OTG I2C Registers */ 00866 __O uint32_t I2C_TX; 00867 }; 00868 __I uint32_t I2C_STS; 00869 __IO uint32_t I2C_CTL; 00870 __IO uint32_t I2C_CLKHI; 00871 __O uint32_t I2C_CLKLO; 00872 uint32_t RESERVED5[824]; 00873 00874 union { 00875 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ 00876 __IO uint32_t OTGClkCtrl; 00877 }; 00878 union { 00879 __I uint32_t USBClkSt; 00880 __I uint32_t OTGClkSt; 00881 }; 00882 } LPC_USB_TypeDef; 00883 00884 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ 00885 /** @brief Ethernet Media Access Controller (EMAC) register structure definition */ 00886 typedef struct 00887 { 00888 __IO uint32_t MAC1; /* MAC Registers */ 00889 __IO uint32_t MAC2; 00890 __IO uint32_t IPGT; 00891 __IO uint32_t IPGR; 00892 __IO uint32_t CLRT; 00893 __IO uint32_t MAXF; 00894 __IO uint32_t SUPP; 00895 __IO uint32_t TEST; 00896 __IO uint32_t MCFG; 00897 __IO uint32_t MCMD; 00898 __IO uint32_t MADR; 00899 __O uint32_t MWTD; 00900 __I uint32_t MRDD; 00901 __I uint32_t MIND; 00902 uint32_t RESERVED0[2]; 00903 __IO uint32_t SA0; 00904 __IO uint32_t SA1; 00905 __IO uint32_t SA2; 00906 uint32_t RESERVED1[45]; 00907 __IO uint32_t Command; /* Control Registers */ 00908 __I uint32_t Status; 00909 __IO uint32_t RxDescriptor; 00910 __IO uint32_t RxStatus; 00911 __IO uint32_t RxDescriptorNumber; 00912 __I uint32_t RxProduceIndex; 00913 __IO uint32_t RxConsumeIndex; 00914 __IO uint32_t TxDescriptor; 00915 __IO uint32_t TxStatus; 00916 __IO uint32_t TxDescriptorNumber; 00917 __IO uint32_t TxProduceIndex; 00918 __I uint32_t TxConsumeIndex; 00919 uint32_t RESERVED2[10]; 00920 __I uint32_t TSV0; 00921 __I uint32_t TSV1; 00922 __I uint32_t RSV; 00923 uint32_t RESERVED3[3]; 00924 __IO uint32_t FlowControlCounter; 00925 __I uint32_t FlowControlStatus; 00926 uint32_t RESERVED4[34]; 00927 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ 00928 __IO uint32_t RxFilterWoLStatus; 00929 __IO uint32_t RxFilterWoLClear; 00930 uint32_t RESERVED5; 00931 __IO uint32_t HashFilterL; 00932 __IO uint32_t HashFilterH; 00933 uint32_t RESERVED6[882]; 00934 __I uint32_t IntStatus; /* Module Control Registers */ 00935 __IO uint32_t IntEnable; 00936 __O uint32_t IntClear; 00937 __O uint32_t IntSet; 00938 uint32_t RESERVED7; 00939 __IO uint32_t PowerDown; 00940 uint32_t RESERVED8; 00941 __IO uint32_t Module_ID; 00942 } LPC_EMAC_TypeDef; 00943 00944 00945 #if defined ( __CC_ARM ) 00946 #pragma no_anon_unions 00947 #endif 00948 00949 00950 /******************************************************************************/ 00951 /* Peripheral memory map */ 00952 /******************************************************************************/ 00953 /* Base addresses */ 00954 #define LPC_FLASH_BASE (0x00000000UL) 00955 #define LPC_RAM_BASE (0x10000000UL) 00956 #ifdef __LPC17XX_REV00 00957 #define LPC_AHBRAM0_BASE (0x20000000UL) 00958 #define LPC_AHBRAM1_BASE (0x20004000UL) 00959 #else 00960 #define LPC_AHBRAM0_BASE (0x2007C000UL) 00961 #define LPC_AHBRAM1_BASE (0x20080000UL) 00962 #endif 00963 #define LPC_GPIO_BASE (0x2009C000UL) 00964 #define LPC_APB0_BASE (0x40000000UL) 00965 #define LPC_APB1_BASE (0x40080000UL) 00966 #define LPC_AHB_BASE (0x50000000UL) 00967 #define LPC_CM3_BASE (0xE0000000UL) 00968 00969 /* APB0 peripherals */ 00970 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) 00971 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) 00972 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) 00973 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) 00974 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) 00975 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) 00976 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) 00977 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) 00978 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) 00979 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) 00980 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) 00981 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) 00982 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) 00983 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) 00984 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) 00985 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) 00986 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) 00987 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) 00988 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) 00989 00990 /* APB1 peripherals */ 00991 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) 00992 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) 00993 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) 00994 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) 00995 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) 00996 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) 00997 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) 00998 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) 00999 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) 01000 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) 01001 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) 01002 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) 01003 01004 /* AHB peripherals */ 01005 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) 01006 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) 01007 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) 01008 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) 01009 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) 01010 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) 01011 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) 01012 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) 01013 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) 01014 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) 01015 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) 01016 01017 /* GPIOs */ 01018 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) 01019 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) 01020 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) 01021 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) 01022 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) 01023 01024 /******************************************************************************/ 01025 /* Peripheral declaration */ 01026 /******************************************************************************/ 01027 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) 01028 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) 01029 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) 01030 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) 01031 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) 01032 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) 01033 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) 01034 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) 01035 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) 01036 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) 01037 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) 01038 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) 01039 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) 01040 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) 01041 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) 01042 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) 01043 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) 01044 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) 01045 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) 01046 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) 01047 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) 01048 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) 01049 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) 01050 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) 01051 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) 01052 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) 01053 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) 01054 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) 01055 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) 01056 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) 01057 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) 01058 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) 01059 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) 01060 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) 01061 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) 01062 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) 01063 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) 01064 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) 01065 #define DMAREQSEL (*(__IO uint32_t *) ( 0x4000C1C4)) 01066 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) 01067 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) 01068 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) 01069 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) 01070 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) 01071 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) 01072 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) 01073 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) 01074 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) 01075 01076 /** 01077 * @} 01078 */ 01079 01080 #endif // __LPC17xx_H__ 01081 /* @endcond */
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