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Dependents: mbed_in_china_blink_led
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Revision 103:9b881da47c92, committed 2014-02-20
- Comitter:
- mbed_official
- Date:
- Thu Feb 20 23:00:08 2014 +0000
- Parent:
- 102:df370e11fcad
- Child:
- 104:a6a92e2e5a92
- Commit message:
- Synchronized with git revision 1f2da5f6047218c8c45334c11bdaaaeab3c18841
Full URL: https://github.com/mbedmicro/mbed/commit/1f2da5f6047218c8c45334c11bdaaaeab3c18841/
NXP master merge
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,1721 @@ + +/****************************************************************************************************//** + * @file LPC15xx.h + * + * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for + * LPC15xx from . + * + * @version V0.3 + * @date 17. July 2013 + * + * @note Generated with SVDConv V2.80 + * from CMSIS SVD File 'H2_v0.3.svd' Version 0.3, + * + * modified by Keil + * modified by ytsuboi + *******************************************************************************************************/ + + + +/** @addtogroup (null) + * @{ + */ + +/** @addtogroup LPC15xx + * @{ + */ + +#ifndef LPC15XX_H +#define LPC15XX_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */ + WDT_IRQn = 0, /*!< 0 WDT */ + BOD_IRQn = 1, /*!< 1 BOD */ + FLASH_IRQn = 2, /*!< 2 FLASH */ + EE_IRQn = 3, /*!< 3 EE */ + DMA_IRQn = 4, /*!< 4 DMA */ + GINT0_IRQn = 5, /*!< 5 GINT0 */ + GINT1_IRQn = 6, /*!< 6 GINT1 */ + PIN_INT0_IRQn = 7, /*!< 7 PIN_INT0 */ + PIN_INT1_IRQn = 8, /*!< 8 PIN_INT1 */ + PIN_INT2_IRQn = 9, /*!< 9 PIN_INT2 */ + PIN_INT3_IRQn = 10, /*!< 10 PIN_INT3 */ + PIN_INT4_IRQn = 11, /*!< 11 PIN_INT4 */ + PIN_INT5_IRQn = 12, /*!< 12 PIN_INT5 */ + PIN_INT6_IRQn = 13, /*!< 13 PIN_INT6 */ + PIN_INT7_IRQn = 14, /*!< 14 PIN_INT7 */ + RIT_IRQn = 15, /*!< 15 RIT */ + SCT0_IRQn = 16, /*!< 16 SCT0 */ + SCT1_IRQn = 17, /*!< 17 SCT1 */ + SCT2_IRQn = 18, /*!< 18 SCT2 */ + SCT3_IRQn = 19, /*!< 19 SCT3 */ + MRT_IRQn = 20, /*!< 20 MRT */ + UART0_IRQn = 21, /*!< 21 UART0 */ + UART1_IRQn = 22, /*!< 22 UART1 */ + UART2_IRQn = 23, /*!< 23 UART2 */ + I2C0_IRQn = 24, /*!< 24 I2C0 */ + SPI0_IRQn = 25, /*!< 25 SPI0 */ + SPI1_IRQn = 26, /*!< 26 SPI1 */ + C_CAN0_IRQn = 27, /*!< 27 C_CAN0 */ + USB_IRQ_IRQn = 28, /*!< 28 USB_IRQ */ + USB_FIQ_IRQn = 29, /*!< 29 USB_FIQ */ + USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */ + ADC0_SEQA_IRQn = 31, /*!< 31 ADC0_SEQA */ + ADC0_SEQB_IRQn = 32, /*!< 32 ADC0_SEQB */ + ADC0_THCMP_IRQn = 33, /*!< 33 ADC0_THCMP */ + ADC0_OVR_IRQn = 34, /*!< 34 ADC0_OVR */ + ADC1_SEQA_IRQn = 35, /*!< 35 ADC1_SEQA */ + ADC1_SEQB_IRQn = 36, /*!< 36 ADC1_SEQB */ + ADC1_THCMP_IRQn = 37, /*!< 37 ADC1_THCMP */ + ADC1_OVR_IRQn = 38, /*!< 38 ADC1_OVR */ + DAC_IRQn = 39, /*!< 39 DAC */ + CMP0_IRQn = 40, /*!< 40 CMP0 */ + CMP1_IRQn = 41, /*!< 41 CMP1 */ + CMP2_IRQn = 42, /*!< 42 CMP2 */ + CMP3_IRQn = 43, /*!< 43 CMP3 */ + QEI_IRQn = 44, /*!< 44 QEI */ + RTC_ALARM_IRQn = 45, /*!< 45 RTC_ALARM */ + RTC_WAKE_IRQn = 46 /*!< 46 RTC_WAKE */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */ +#define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */ +#include "system_LPC15xx.h" /*!< LPC15xx System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + + + +/* ================================================================================ */ +/* ================ GPIO_PORT ================ */ +/* ================================================================================ */ + + +/** + * @brief General Purpose I/O (GPIO) (GPIO_PORT) + */ + +typedef struct { /*!< GPIO_PORT Structure */ + __IO uint8_t B[76]; /*!< Byte pin registers */ + __I uint32_t RESERVED0[45]; + __IO uint32_t W[76]; /*!< Word pin registers */ + __I uint32_t RESERVED1[1908]; + __IO uint32_t DIR[3]; /*!< Port Direction registers */ + __I uint32_t RESERVED2[29]; + __IO uint32_t MASK[3]; /*!< Port Mask register */ + __I uint32_t RESERVED3[29]; + __IO uint32_t PIN[3]; /*!< Port pin register */ + __I uint32_t RESERVED4[29]; + __IO uint32_t MPIN[3]; /*!< Masked port register */ + __I uint32_t RESERVED5[29]; + __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */ + __I uint32_t RESERVED6[29]; + __O uint32_t CLR[3]; /*!< Clear port */ + __I uint32_t RESERVED7[29]; + __O uint32_t NOT[3]; /*!< Toggle port */ +} LPC_GPIO_PORT_Type; + + +/* ================================================================================ */ +/* ================ DMA ================ */ +/* ================================================================================ */ + + +/** + * @brief DMA controller (DMA) + */ + +typedef struct { /*!< DMA Structure */ + __IO uint32_t CTRL; /*!< DMA control. */ + __I uint32_t INTSTAT; /*!< Interrupt status. */ + __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */ + __I uint32_t RESERVED0[5]; + __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */ + __I uint32_t RESERVED1; + __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */ + __I uint32_t RESERVED2; + __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */ + __I uint32_t RESERVED3; + __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */ + __I uint32_t RESERVED4; + __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */ + __I uint32_t RESERVED5; + __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */ + __I uint32_t RESERVED6; + __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */ + __I uint32_t RESERVED7; + __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */ + __I uint32_t RESERVED8; + __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */ + __I uint32_t RESERVED9; + __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */ + __I uint32_t RESERVED10; + __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */ + __I uint32_t RESERVED11; + __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */ + __I uint32_t RESERVED12[225]; + __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED13; + __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED14; + __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED15; + __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED16; + __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED17; + __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED18; + __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED19; + __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED20; + __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED21; + __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED22; + __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED23; + __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED24; + __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED25; + __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED26; + __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED27; + __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED28; + __IO uint32_t CFG16; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT16; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG16; /*!< Transfer configuration register for DMA channel 0. */ + __I uint32_t RESERVED29; + __IO uint32_t CFG17; /*!< Configuration register for DMA channel 0. */ + __I uint32_t CTLSTAT17; /*!< Control and status register for DMA channel 0. */ + __IO uint32_t XFERCFG17; /*!< Transfer configuration register for DMA channel 0. */ +} LPC_DMA_Type; + + +/* ================================================================================ */ +/* ================ USB ================ */ +/* ================================================================================ */ + + +/** + * @brief USB device controller (USB) + */ + +typedef struct { /*!< USB Structure */ + __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */ + __IO uint32_t INFO; /*!< USB Info register */ + __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */ + __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */ + __IO uint32_t LPM; /*!< Link Power Management register */ + __IO uint32_t EPSKIP; /*!< USB Endpoint skip */ + __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */ + __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */ + __IO uint32_t INTSTAT; /*!< USB interrupt status register */ + __IO uint32_t INTEN; /*!< USB interrupt enable register */ + __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */ + __IO uint32_t INTROUTING; /*!< USB interrupt routing register */ + __I uint32_t RESERVED0; + __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */ +} LPC_USB_Type; + + +/* ================================================================================ */ +/* ================ CRC ================ */ +/* ================================================================================ */ + + +/** + * @brief Cyclic Redundancy Check (CRC) engine (CRC) + */ + +typedef struct { /*!< CRC Structure */ + __IO uint32_t MODE; /*!< CRC mode register */ + __IO uint32_t SEED; /*!< CRC seed register */ + + union { + __O uint32_t WR_DATA; /*!< CRC data register */ + __I uint32_t SUM; /*!< CRC checksum register */ + }; +} LPC_CRC_Type; + + +/* ================================================================================ */ +/* ================ SCT0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0) + */ + +typedef struct { /*!< SCT0 Structure */ + __IO uint32_t CONFIG; /*!< SCT configuration register */ + __IO uint32_t CTRL; /*!< SCT control register */ + __IO uint32_t LIMIT; /*!< SCT limit register */ + __IO uint32_t HALT; /*!< SCT halt condition register */ + __IO uint32_t STOP; /*!< SCT stop condition register */ + __IO uint32_t START; /*!< SCT start condition register */ + __IO uint32_t DITHER; /*!< SCT dither condition register */ + __I uint32_t RESERVED0[9]; + __IO uint32_t COUNT; /*!< SCT counter register */ + __IO uint32_t STATE; /*!< SCT state register */ + __I uint32_t INPUT; /*!< SCT input register */ + __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */ + __IO uint32_t OUTPUT; /*!< SCT output register */ + __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */ + __IO uint32_t RES; /*!< SCT conflict resolution register */ + __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */ + __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */ + __I uint32_t RESERVED1[35]; + __IO uint32_t EVEN; /*!< SCT event enable register */ + __IO uint32_t EVFLAG; /*!< SCT event flag register */ + __IO uint32_t CONEN; /*!< SCT conflict enable register */ + __IO uint32_t CONFLAG; /*!< SCT conflict flag register */ + + union { + __I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + }; + + union { + __I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + }; + + union { + __I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + }; + + union { + __I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + }; + + union { + __I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + }; + + union { + __I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + __IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + }; + + union { + __I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + __IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + __I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + }; + + union { + __I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + __IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + __I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + }; + + union { + __IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + __I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + }; + + union { + __IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + __I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + }; + + union { + __IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + __I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + }; + + union { + __IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + __I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + }; + + union { + __I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + __IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0 + to REGMODE15 = 0 */ + __I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to + REGMODE15 = 1 */ + }; + __IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers + 0 to 5. */ + __IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers + 0 to 5. */ + __IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers + 0 to 5. */ + __IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers + 0 to 5. */ + __IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers + 0 to 5. */ + __IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers + 0 to 5. */ + __I uint32_t RESERVED2[42]; + + union { + __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + }; + + union { + __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + }; + + union { + __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + }; + + union { + __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + }; + + union { + __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + }; + + union { + __IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + __IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + }; + + union { + __IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + __IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + }; + + union { + __IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + __IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + }; + + union { + __IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + __IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + }; + + union { + __IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + __IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + }; + + union { + __IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + __IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + }; + + union { + __IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + __IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + }; + + union { + __IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + __IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + }; + + union { + __IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + __IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + }; + + union { + __IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + __IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + }; + + union { + __IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 + = 1 */ + __IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 + = 0 */ + }; + __IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value + registers 0 to 5. */ + __IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value + registers 0 to 5. */ + __IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value + registers 0 to 5. */ + __IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value + registers 0 to 5. */ + __IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value + registers 0 to 5. */ + __IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value + registers 0 to 5. */ + __I uint32_t RESERVED3[42]; + __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV6_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV6_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV7_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV7_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV8_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV8_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV9_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV9_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV10_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV10_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV11_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV11_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV12_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV12_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV13_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV13_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV14_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV14_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV15_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV15_CTRL; /*!< SCT event control register 0 */ + __I uint32_t RESERVED4[96]; + __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */ + __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */ + __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */ + __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */ + __IO uint32_t OUT4_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT4_CLR; /*!< SCT output 0 clear register */ + __IO uint32_t OUT5_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT5_CLR; /*!< SCT output 0 clear register */ + __IO uint32_t OUT6_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT6_CLR; /*!< SCT output 0 clear register */ + __IO uint32_t OUT7_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT7_CLR; /*!< SCT output 0 clear register */ + __IO uint32_t OUT8_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT8_CLR; /*!< SCT output 0 clear register */ + __IO uint32_t OUT9_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT9_CLR; /*!< SCT output 0 clear register */ +} LPC_SCT0_Type; + + +/* ================================================================================ */ +/* ================ SCT2 ================ */ +/* ================================================================================ */ + + +/** + * @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2) + */ + +typedef struct { /*!< SCT2 Structure */ + __IO uint32_t CONFIG; /*!< SCT configuration register */ + __IO uint32_t CTRL; /*!< SCT control register */ + __IO uint32_t LIMIT; /*!< SCT limit register */ + __IO uint32_t HALT; /*!< SCT halt condition register */ + __IO uint32_t STOP; /*!< SCT stop condition register */ + __IO uint32_t START; /*!< SCT start condition register */ + __I uint32_t RESERVED0[10]; + __IO uint32_t COUNT; /*!< SCT counter register */ + __IO uint32_t STATE; /*!< SCT state register */ + __I uint32_t INPUT; /*!< SCT input register */ + __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */ + __IO uint32_t OUTPUT; /*!< SCT output register */ + __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */ + __IO uint32_t RES; /*!< SCT conflict resolution register */ + __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */ + __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */ + __I uint32_t RESERVED1[35]; + __IO uint32_t EVEN; /*!< SCT event enable register */ + __IO uint32_t EVFLAG; /*!< SCT event flag register */ + __IO uint32_t CONEN; /*!< SCT conflict enable register */ + __IO uint32_t CONFLAG; /*!< SCT conflict flag register */ + + union { + __I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 + = 1 */ + __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to + REGMODE7 = 0 */ + }; + + union { + __I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 + = 1 */ + __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to + REGMODE7 = 0 */ + }; + + union { + __I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 + = 1 */ + __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to + REGMODE7 = 0 */ + }; + + union { + __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to + REGMODE7 = 0 */ + __I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 + = 1 */ + }; + + union { + __I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 + = 1 */ + __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to + REGMODE7 = 0 */ + }; + + union { + __IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to + REGMODE7 = 0 */ + __I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 + = 1 */ + }; + + union { + __I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 + = 1 */ + __IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to + REGMODE7 = 0 */ + }; + + union { + __I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7 + = 1 */ + __IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to + REGMODE7 = 0 */ + }; + __I uint32_t RESERVED2[56]; + + union { + __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 + = 1 */ + __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 + = 0 */ + }; + + union { + __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 + = 1 */ + __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 + = 0 */ + }; + + union { + __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 + = 1 */ + __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 + = 0 */ + }; + + union { + __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 + = 0 */ + __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 + = 1 */ + }; + + union { + __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 + = 1 */ + __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 + = 0 */ + }; + + union { + __IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 + = 0 */ + __IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 + = 1 */ + }; + + union { + __IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 + = 1 */ + __IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 + = 0 */ + }; + + union { + __IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7 + = 1 */ + __IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 + = 0 */ + }; + __I uint32_t RESERVED3[56]; + __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV6_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV6_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV7_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV7_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV8_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV8_CTRL; /*!< SCT event control register 0 */ + __IO uint32_t EV9_STATE; /*!< SCT event state register 0 */ + __IO uint32_t EV9_CTRL; /*!< SCT event control register 0 */ + __I uint32_t RESERVED4[108]; + __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */ + __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */ + __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */ + __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */ + __IO uint32_t OUT4_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT4_CLR; /*!< SCT output 0 clear register */ + __IO uint32_t OUT5_SET; /*!< SCT output 0 set register */ + __IO uint32_t OUT5_CLR; /*!< SCT output 0 clear register */ +} LPC_SCT2_Type; + + +/* ================================================================================ */ +/* ================ ADC0 ================ */ +/* ================================================================================ */ + + +/** + * @brief 12-bit ADC controller ADC0/1 (ADC0) + */ + +typedef struct { /*!< ADC0 Structure */ + __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable + bits for each sequence and the A/D power-down bit. */ + __IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and + internal source for various channels */ + __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering + and channel selection for conversion sequence-A. Also specifies + interrupt mode for sequence-A. */ + __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering + and channel selection for conversion sequence-B. Also specifies + interrupt mode for sequence-B. */ + __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains + the result of the most recent A/D conversion performed under + sequence-A */ + __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains + the result of the most recent A/D conversion performed under + sequence-B */ + __I uint32_t RESERVED0[2]; + __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result + of the most recent conversion completed on channel 0. */ + __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold + level for automatic threshold comparison for any channels linked + to threshold pair 0. */ + __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold + level for automatic threshold comparison for any channels linked + to threshold pair 1. */ + __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold + level for automatic threshold comparison for any channels linked + to threshold pair 0. */ + __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold + level for automatic threshold comparison for any channels linked + to threshold pair 1. */ + __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of + threshold compare registers are to be used for each channel */ + __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable + bits that enable the sequence-A, sequence-B, threshold compare + and data overrun interrupts to be generated. */ + __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags + and the individual component overrun and threshold-compare flags. + (The overrun bits replicate information stored in the result + registers). */ + __IO uint32_t TRM; /*!< ADC trim register. */ +} LPC_ADC0_Type; + + +/* ================================================================================ */ +/* ================ DAC ================ */ +/* ================================================================================ */ + + +/** + * @brief 12-bit DAC Modification (DAC) + */ + +typedef struct { /*!< DAC Structure */ + __IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital + value to be converted to analog. */ + __IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure + DAC operation and the interrupt/dma request flag. */ + __IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload + value for the internal DAC DMA/Interrupt timer. */ +} LPC_DAC_Type; + + +/* ================================================================================ */ +/* ================ ACMP ================ */ +/* ================================================================================ */ + + +/** + * @brief Analog comparators ACMP0/1/2/3 (ACMP) + */ + +typedef struct { /*!< ACMP Structure */ + __IO uint32_t CTRL; /*!< Comparator block control register */ + __IO uint32_t CMP0; /*!< Comparator 0 source control */ + __IO uint32_t CMPFILTR0; /*!< Comparator 0 pin filter set-up */ + __IO uint32_t CMP1; /*!< Comparator 1 source control */ + __IO uint32_t CMPFILTR1; /*!< Comparator 0 pin filter set-up */ + __IO uint32_t CMP2; /*!< Comparator 2 source control */ + __IO uint32_t CMPFILTR2; /*!< Comparator 0 pin filter set-up */ + __IO uint32_t CMP3; /*!< Comparator 3 source control */ + __IO uint32_t CMPFILTR3; /*!< Comparator 0 pin filter set-up */ +} LPC_ACMP_Type; + + +/* ================================================================================ */ +/* ================ INMUX ================ */ +/* ================================================================================ */ + + +/** + * @brief Input multiplexing (INMUX) (INMUX) + */ + +typedef struct { /*!< INMUX Structure */ + __IO uint32_t SCT0_INMUX[7]; /*!< Pinmux register for SCT0 input 0 */ + __I uint32_t RESERVED0; + __IO uint32_t SCT1_INMUX[7]; /*!< Pinmux register for SCT1 input 0 */ + __I uint32_t RESERVED1; + __IO uint32_t SCT2_INMUX[3]; /*!< Pinmux register for SCT2 input 0 */ + __I uint32_t RESERVED2[5]; + __IO uint32_t SCT3_INMUX[3]; /*!< Pinmux register for SCT3 input 0 */ + __I uint32_t RESERVED3[21]; + __IO uint32_t PINTSEL[8]; /*!< Pin interrupt select register 0 */ + __IO uint32_t DMA_ITRIG_INMUX[18]; /*!< Trigger input for DMA channel 0 select register. */ + __I uint32_t RESERVED4[14]; + __IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference + clock */ + __IO uint32_t FREQMEAS_TARGET; /*!< Clock selection for frequency measurement function target clock */ +} LPC_INMUX_Type; + + +/* ================================================================================ */ +/* ================ RTC ================ */ +/* ================================================================================ */ + + +/** + * @brief Real-Time Clock (RTC) (RTC) + */ + +typedef struct { /*!< RTC Structure */ + __IO uint32_t CTRL; /*!< RTC control register */ + __IO uint32_t MATCH; /*!< RTC match register */ + __IO uint32_t COUNT; /*!< RTC counter register */ + __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */ +} LPC_RTC_Type; + + +/* ================================================================================ */ +/* ================ WWDT ================ */ +/* ================================================================================ */ + + +/** + * @brief Windowed Watchdog Timer (WWDT) (WWDT) + */ + +typedef struct { /*!< WWDT Structure */ + __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode + and status of the Watchdog Timer. */ + __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines + the time-out value. */ + __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 + to this register reloads the Watchdog timer with the value contained + in WDTC. */ + __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out + the current value of the Watchdog timer. */ + __I uint32_t RESERVED0; + __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */ + __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */ +} LPC_WWDT_Type; + + +/* ================================================================================ */ +/* ================ SWM ================ */ +/* ================================================================================ */ + + +/** + * @brief Switch Matrix (SWM) (SWM) + */ + +typedef struct { /*!< SWM Structure */ + union { + __IO uint32_t PINASSIGN[16]; + struct { + __IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, + U0_RTS, U0_CTS. */ + __IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, + U1_RXD, U1_RTS. */ + __IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, + U2_TXD, U2_RXD. */ + __IO uint32_t PINASSIGN3; /*!< Pin assign register 3. Assign movable function . */ + __IO uint32_t PINASSIGN4; /*!< Pin assign register 4. Assign movable functions */ + __IO uint32_t PINASSIGN5; /*!< Pin assign register 5. Assign movable functions */ + __IO uint32_t PINASSIGN6; /*!< Pin assign register 6. Assign movable functions */ + __IO uint32_t PINASSIGN7; /*!< Pin assign register 7. Assign movable functions */ + __IO uint32_t PINASSIGN8; /*!< Pin assign register 8. Assign movable functions */ + __IO uint32_t PINASSIGN9; /*!< Pin assign register 9. Assign movable functions */ + __IO uint32_t PINASSIGN10; /*!< Pin assign register 10. Assign movable functions */ + __IO uint32_t PINASSIGN11; /*!< Pin assign register 11. Assign movable functions */ + __IO uint32_t PINASSIGN12; /*!< Pin assign register 12. Assign movable functions */ + __IO uint32_t PINASSIGN13; /*!< Pin assign register 13. Assign movable functions */ + __IO uint32_t PINASSIGN14; /*!< Pin assign register 14. Assign movable functions */ + __IO uint32_t PINASSIGN15; /*!< Pin assign register 15. Assign movable functions */ + }; + }; + __I uint32_t RESERVED0[96]; + __IO uint32_t PINENABLE0; /*!< Pin enable register 0. Enables fixed-pin functions */ + __IO uint32_t PINENABLE1; /*!< Pin enable register 0. Enables fixed-pin functions */ +} LPC_SWM_Type; + + +/* ================================================================================ */ +/* ================ PMU ================ */ +/* ================================================================================ */ + + +/** + * @brief Power Management Unit (PMU) (PMU) + */ + +typedef struct { /*!< PMU Structure */ + __IO uint32_t PCON; /*!< Power control register */ + __IO uint32_t GPREG0; /*!< General purpose register 0 */ + __IO uint32_t GPREG1; /*!< General purpose register 0 */ + __IO uint32_t GPREG2; /*!< General purpose register 0 */ + __IO uint32_t GPREG3; /*!< General purpose register 0 */ + __IO uint32_t DPDCTRL; /*!< Deep power-down control register */ +} LPC_PMU_Type; + + +/* ================================================================================ */ +/* ================ USART0 ================ */ +/* ================================================================================ */ + + +/** + * @brief USART0 (USART0) + */ + +typedef struct { /*!< USART0 Structure */ + __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings + that typically are not changed during operation. */ + __IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more + likely to change during operation. */ + __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read + here. Writing ones clears some bits in the register. Some bits + can be cleared by writing a 1 to them. */ + __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual + interrupt enable bit for each potential USART interrupt. A complete + value may be read from this register. Writing a 1 to any implemented + bit position causes that bit to be set. */ + __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination + of bits in the INTENSET register. Writing a 1 to any implemented + bit position causes the corresponding bit to be cleared. */ + __I uint32_t RXDATA; /*!< Receiver Data register. Contains the last character received. */ + __I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character + received with the current USART receive status. Allows DMA or + software to recover incoming data and status together. */ + __IO uint32_t TXDATA; /*!< Transmit Data register. Data to be transmitted is written here. */ + __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor + value. */ + __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently + enabled. */ +} LPC_USART0_Type; + + +/* ================================================================================ */ +/* ================ SPI0 ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI0 (SPI0) + */ + +typedef struct { /*!< SPI0 Structure */ + __IO uint32_t CFG; /*!< SPI Configuration register */ + __IO uint32_t DLY; /*!< SPI Delay register */ + __IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1 + to that bit position */ + __IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read + from this register. Writing a 1 to any implemented bit position + causes that bit to be set. */ + __O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit + position causes the corresponding bit in INTENSET to be cleared. */ + __I uint32_t RXDAT; /*!< SPI Receive Data */ + __IO uint32_t TXDATCTL; /*!< SPI Transmit Data with Control */ + __IO uint32_t TXDAT; /*!< SPI Transmit Data with Control */ + __IO uint32_t TXCTL; /*!< SPI Transmit Control */ + __IO uint32_t DIV; /*!< SPI clock Divider */ + __I uint32_t INTSTAT; /*!< SPI Interrupt Status */ +} LPC_SPI0_Type; + + +/* ================================================================================ */ +/* ================ I2C0 ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C-bus interface (I2C0) + */ + +typedef struct { /*!< I2C0 Structure */ + __IO uint32_t CFG; /*!< Configuration for shared functions. */ + __IO uint32_t STAT; /*!< Status register for Master, Slave, and Monitor functions. */ + __IO uint32_t INTENSET; /*!< Interrupt Enable Set and read register. */ + __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. */ + __IO uint32_t TIMEOUT; /*!< Time-out value register. */ + __IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines + what time increments are used for the MSTTIME and SLVTIME registers. */ + __I uint32_t INTSTAT; /*!< Interrupt Status register for Master, Slave, and Monitor functions. */ + __I uint32_t RESERVED0; + __IO uint32_t MSTCTL; /*!< Master control register. */ + __IO uint32_t MSTTIME; /*!< Master timing configuration. */ + __IO uint32_t MSTDAT; /*!< Combined Master receiver and transmitter data register. */ + __I uint32_t RESERVED1[5]; + __IO uint32_t SLVCTL; /*!< Slave control register. */ + __IO uint32_t SLVDAT; /*!< Combined Slave receiver and transmitter data register. */ + __IO uint32_t SLVADR0; /*!< Slave address 0. */ + __IO uint32_t SLVADR1; /*!< Slave address 0. */ + __IO uint32_t SLVADR2; /*!< Slave address 0. */ + __IO uint32_t SLVADR3; /*!< Slave address 0. */ + __IO uint32_t SLVQUAL0; /*!< Slave Qualification for address 0. */ + __I uint32_t RESERVED2[9]; + __I uint32_t MONRXDAT; /*!< Monitor receiver data register. */ +} LPC_I2C0_Type; + + +/* ================================================================================ */ +/* ================ QEI ================ */ +/* ================================================================================ */ + + +/** + * @brief Quadrature Encoder Interface (QEI) (QEI) + */ + +typedef struct { /*!< QEI Structure */ + __O uint32_t CON; /*!< Control register */ + __I uint32_t STAT; /*!< Encoder status register */ + __IO uint32_t CONF; /*!< Configuration register */ + __I uint32_t POS; /*!< Position register */ + __IO uint32_t MAXPOS; /*!< Maximum position register */ + __IO uint32_t CMPOS0; /*!< position compare register 0 */ + __IO uint32_t CMPOS1; /*!< position compare register 1 */ + __IO uint32_t CMPOS2; /*!< position compare register 2 */ + __I uint32_t INXCNT; /*!< Index count register */ + __IO uint32_t INXCMP0; /*!< Index compare register 0 */ + __IO uint32_t LOAD; /*!< Velocity timer reload register */ + __I uint32_t TIME; /*!< Velocity timer register */ + __I uint32_t VEL; /*!< Velocity counter register */ + __I uint32_t CAP; /*!< Velocity capture register */ + __IO uint32_t VELCOMP; /*!< Velocity compare register */ + __IO uint32_t FILTERPHA; /*!< Digital filter register on input phase A (QEI_A) */ + __IO uint32_t FILTERPHB; /*!< Digital filter register on input phase B (QEI_B) */ + __IO uint32_t FILTERINX; /*!< Digital filter register on input index (QEI_IDX) */ + __IO uint32_t WINDOW; /*!< Index acceptance window register */ + __IO uint32_t INXCMP1; /*!< Index compare register 1 */ + __IO uint32_t INXCMP2; /*!< Index compare register 2 */ + __I uint32_t RESERVED0[993]; + __O uint32_t IEC; /*!< Interrupt enable clear register */ + __O uint32_t IES; /*!< Interrupt enable set register */ + __I uint32_t INTSTAT; /*!< Interrupt status register */ + __O uint32_t IE; /*!< Interrupt enable clear register */ + __O uint32_t CLR; /*!< Interrupt status clear register */ + __O uint32_t SET; /*!< Interrupt status set register */ +} LPC_QEI_Type; + + +/* ================================================================================ */ +/* ================ SYSCON ================ */ +/* ================================================================================ */ + + +/** + * @brief System configuration (SYSCON) (SYSCON) + */ + +typedef struct { /*!< SYSCON Structure */ + __IO uint32_t SYSMEMREMAP; /*!< System memory remap */ + __I uint32_t RESERVED0[4]; + __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */ + __I uint32_t RESERVED1; + __IO uint32_t NMISRC; /*!< NMI Source Control */ + __I uint32_t RESERVED2[8]; + __IO uint32_t SYSRSTSTAT; /*!< System reset status register */ + __IO uint32_t PRESETCTRL0; /*!< Peripheral reset control 0 */ + __IO uint32_t PRESETCTRL1; /*!< Peripheral reset control 1 */ + __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */ + __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */ + __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 2 */ + __I uint32_t RESERVED3[10]; + __IO uint32_t MAINCLKSELA; /*!< Main clock source select A */ + __IO uint32_t MAINCLKSELB; /*!< Main clock source select B */ + __IO uint32_t USBCLKSEL; /*!< USB clock source select */ + __IO uint32_t ADCASYNCCLKSEL; /*!< ADC asynchronous clock source select */ + __I uint32_t RESERVED4; + __IO uint32_t CLKOUTSELA; /*!< CLKOUT clock source select A */ + __IO uint32_t CLKOUTSELB; /*!< CLKOUT clock source select B */ + __I uint32_t RESERVED5; + __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */ + __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */ + __IO uint32_t SCTPLLCLKSEL; /*!< SCT PLL clock source select */ + __I uint32_t RESERVED6[5]; + __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */ + __IO uint32_t SYSAHBCLKCTRL0; /*!< System clock control 0 */ + __IO uint32_t SYSAHBCLKCTRL1; /*!< System clock control 1 */ + __IO uint32_t SYSTICKCLKDIV; /*!< SYSTICK clock divider */ + __IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional + baud rate generator. */ + __IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch + filter */ + __IO uint32_t TRACECLKDIV; /*!< ARM trace clock divider */ + __I uint32_t RESERVED7[4]; + __IO uint32_t USBCLKDIV; /*!< USB clock divider */ + __IO uint32_t ADCASYNCCLKDIV; /*!< Asynchronous ADC clock divider */ + __I uint32_t RESERVED8; + __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */ + __I uint32_t RESERVED9[11]; + __IO uint32_t FRGCTRL; /*!< USART fractional baud rate generator control */ + __IO uint32_t USBCLKCTRL; /*!< USB clock control */ + __IO uint32_t USBCLKST; /*!< USB clock status */ + __I uint32_t RESERVED10[19]; + __IO uint32_t BODCTRL; /*!< Brown-Out Detect */ + __I uint32_t RESERVED11; + __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */ + __I uint32_t RESERVED12; + __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator control */ + __I uint32_t RESERVED13; + __IO uint32_t SYSPLLCTRL; /*!< System PLL control */ + __I uint32_t SYSPLLSTAT; /*!< System PLL status */ + __IO uint32_t USBPLLCTRL; /*!< USB PLL control */ + __I uint32_t USBPLLSTAT; /*!< USB PLL status */ + __IO uint32_t SCTPLLCTRL; /*!< SCT PLL control */ + __I uint32_t SCTPLLSTAT; /*!< SCT PLL status */ + __I uint32_t RESERVED14[21]; + __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */ + __IO uint32_t PDRUNCFG; /*!< Power configuration register */ + __I uint32_t RESERVED15[3]; + __IO uint32_t STARTERP0; /*!< Start logic 0 wake-up enable register */ + __IO uint32_t STARTERP1; /*!< Start logic 1 wake-up enable register */ +} LPC_SYSCON_Type; + + +/* ================================================================================ */ +/* ================ MRT ================ */ +/* ================================================================================ */ + + +/** + * @brief Multi-Rate Timer (MRT) (MRT) + */ + +typedef struct { /*!< MRT Structure */ + __IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into + the TIMER0 register. */ + __I uint32_t TIMER0; /*!< MRT0 Timer register. This register reads the value of the down-counter. */ + __IO uint32_t CTRL0; /*!< MRT0 Control register. This register controls the MRT0 modes. */ + __IO uint32_t STAT0; /*!< MRT0 Status register. */ + __IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into + the TIMER0 register. */ + __I uint32_t TIMER1; /*!< MRT0 Timer register. This register reads the value of the down-counter. */ + __IO uint32_t CTRL1; /*!< MRT0 Control register. This register controls the MRT0 modes. */ + __IO uint32_t STAT1; /*!< MRT0 Status register. */ + __IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into + the TIMER0 register. */ + __I uint32_t TIMER2; /*!< MRT0 Timer register. This register reads the value of the down-counter. */ + __IO uint32_t CTRL2; /*!< MRT0 Control register. This register controls the MRT0 modes. */ + __IO uint32_t STAT2; /*!< MRT0 Status register. */ + __IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into + the TIMER0 register. */ + __I uint32_t TIMER3; /*!< MRT0 Timer register. This register reads the value of the down-counter. */ + __IO uint32_t CTRL3; /*!< MRT0 Control register. This register controls the MRT0 modes. */ + __IO uint32_t STAT3; /*!< MRT0 Status register. */ + __I uint32_t RESERVED0[45]; + __I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the + first idle channel. */ + __IO uint32_t IRQ_FLAG; /*!< Global interrupt flag register */ +} LPC_MRT_Type; + + +/* ================================================================================ */ +/* ================ PINT ================ */ +/* ================================================================================ */ + + +/** + * @brief Pin interruptand pattern match (PINT) (PINT) + */ + +typedef struct { /*!< PINT Structure */ + __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */ + __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */ + __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */ + __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */ + __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable + register */ + __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */ + __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */ + __IO uint32_t RISE; /*!< Pin interrupt rising edge register */ + __IO uint32_t FALL; /*!< Pin interrupt falling edge register */ + __IO uint32_t IST; /*!< Pin interrupt status register */ + __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */ + __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */ + __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */ +} LPC_PINT_Type; + + +/* ================================================================================ */ +/* ================ GINT0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Group interrupt 0/1 (GINT0/1) (GINT0) + */ + +typedef struct { /*!< GINT0 Structure */ + __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */ + __I uint32_t RESERVED0[7]; + __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */ + __I uint32_t RESERVED1[5]; + __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port 0 enable register */ +} LPC_GINT0_Type; + + +/* ================================================================================ */ +/* ================ RIT ================ */ +/* ================================================================================ */ + + +/** + * @brief Repetitive Interrupt Timer (RIT) (RIT) + */ + +typedef struct { /*!< RIT Structure */ + __IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare + value. */ + __IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask + value. A 1 written to any bit will force a compare on the corresponding + bit of the counter and compare register. */ + __IO uint32_t CTRL; /*!< Control register. */ + __IO uint32_t COUNTER; /*!< Counter LSB register. 32 LSBs of the counter. */ + __IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare + value. */ + __IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask + value. A 1 written to any bit will force a compare on the corresponding + bit of the counter and compare register. */ + __I uint32_t RESERVED0; + __IO uint32_t COUNTER_H; /*!< Counter MSB register. 16 MSBs of the counter. */ +} LPC_RIT_Type; + + +/* ================================================================================ */ +/* ================ SCTIPU ================ */ +/* ================================================================================ */ + + +/** + * @brief SCT Input Processing Unit (IPU) (SCTIPU) + */ + +typedef struct { /*!< SCTIPU Structure */ + __IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects, + latch/sample-enable mux selects, and sample overrride bits for + the SAMPLE module. */ + __I uint32_t RESERVED0[7]; + __IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes + to ORed Abort Output 0. */ + __IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which + input source caused abort output 0. */ + __I uint32_t RESERVED1[6]; + __IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes + to ORed Abort Output 0. */ + __IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which + input source caused abort output 0. */ + __I uint32_t RESERVED2[6]; + __IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes + to ORed Abort Output 0. */ + __IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which + input source caused abort output 0. */ + __I uint32_t RESERVED3[6]; + __IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes + to ORed Abort Output 0. */ + __IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which + input source caused abort output 0. */ +} LPC_SCTIPU_Type; + + +/* ================================================================================ */ +/* ================ FLASHCTRL ================ */ +/* ================================================================================ */ + + +/** + * @brief Flash controller (FLASHCTRL) + */ + +typedef struct { /*!< FLASHCTRL Structure */ + __I uint32_t RESERVED0[8]; + __IO uint32_t FMSSTART; /*!< Signature start address register */ + __IO uint32_t FMSSTOP; /*!< Signature stop-address register */ + __I uint32_t RESERVED1; + __I uint32_t FMSW0; /*!< Signature word */ +} LPC_FLASHCTRL_Type; + + +/* ================================================================================ */ +/* ================ C_CAN0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Controller Area Network C_CAN0 (C_CAN0) + */ + +typedef struct { /*!< C_CAN0 Structure */ + __IO uint32_t CANCNTL; /*!< CAN control */ + __IO uint32_t CANSTAT; /*!< Status register */ + __I uint32_t CANEC; /*!< Error counter */ + __IO uint32_t CANBT; /*!< Bit timing register */ + __I uint32_t CANINT; /*!< Interrupt register */ + __IO uint32_t CANTEST; /*!< Test register */ + __IO uint32_t CANBRPE; /*!< Baud rate prescaler extension register */ + __I uint32_t RESERVED0; + __IO uint32_t CANIF1_CMDREQ; /*!< Message interface 1 command request */ + + union { + __IO uint32_t CANIF1_CMDMSK_R; /*!< Message interface 1 command mask (read direction) */ + __IO uint32_t CANIF1_CMDMSK_W; /*!< Message interface 1 command mask (write direction) */ + }; + __IO uint32_t CANIF1_MSK1; /*!< Message interface 1 mask 1 */ + __IO uint32_t CANIF1_MSK2; /*!< Message interface 1 mask 2 */ + __IO uint32_t CANIF1_ARB1; /*!< Message interface 1 arbitration 1 */ + __IO uint32_t CANIF1_ARB2; /*!< Message interface 1 arbitration 2 */ + __IO uint32_t CANIF1_MCTRL; /*!< Message interface 1 message control */ + __IO uint32_t CANIF1_DA1; /*!< Message interface 1 data A1 */ + __IO uint32_t CANIF1_DA2; /*!< Message interface 1 data A2 */ + __IO uint32_t CANIF1_DB1; /*!< Message interface 1 data B1 */ + __IO uint32_t CANIF1_DB2; /*!< Message interface 1 data B2 */ + __I uint32_t RESERVED1[13]; + __IO uint32_t CANIF2_CMDREQ; /*!< Message interface 1 command request */ + + union { + __IO uint32_t CANIF2_CMDMSK_W; /*!< Message interface 1 command mask (write direction) */ + __IO uint32_t CANIF2_CMDMSK_R; /*!< Message interface 1 command mask (read direction) */ + }; + __IO uint32_t CANIF2_MSK1; /*!< Message interface 1 mask 1 */ + __IO uint32_t CANIF2_MSK2; /*!< Message interface 1 mask 2 */ + __IO uint32_t CANIF2_ARB1; /*!< Message interface 1 arbitration 1 */ + __IO uint32_t CANIF2_ARB2; /*!< Message interface 1 arbitration 2 */ + __IO uint32_t CANIF2_MCTRL; /*!< Message interface 1 message control */ + __I uint32_t RESERVED2[25]; + __I uint32_t CANTXREQ1; /*!< Transmission request 1 */ + __I uint32_t CANTXREQ2; /*!< Transmission request 2 */ + __I uint32_t RESERVED3[6]; + __I uint32_t CANND1; /*!< New data 1 */ + __I uint32_t CANND2; /*!< New data 2 */ + __I uint32_t RESERVED4[6]; + __I uint32_t CANIR1; /*!< Interrupt pending 1 */ + __I uint32_t CANIR2; /*!< Interrupt pending 2 */ + __I uint32_t RESERVED5[6]; + __I uint32_t CANMSGV1; /*!< Message valid 1 */ + __I uint32_t CANMSGV2; /*!< Message valid 2 */ + __I uint32_t RESERVED6[6]; + __IO uint32_t CANCLKDIV; /*!< Can clock divider register */ +} LPC_C_CAN0_Type; + + +/* ================================================================================ */ +/* ================ IOCON ================ */ +/* ================================================================================ */ + + +/** + * @brief I/O pin configuration (IOCON) (IOCON) + */ + +typedef struct { /*!< IOCON Structure */ + __IO uint32_t PIO0_0; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_1; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_2; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_3; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_4; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_5; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_6; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_7; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_8; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_9; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_10; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_11; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_12; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_13; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_14; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_15; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_16; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_17; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_18; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_19; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_20; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_21; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */ + __IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for + the I2C-bus SCL function. */ + __IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for + the I2C-bus SCL function. */ + __IO uint32_t PIO0_24; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */ + __IO uint32_t PIO0_25; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */ + __IO uint32_t PIO0_26; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */ + __IO uint32_t PIO0_27; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */ + __IO uint32_t PIO0_28; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */ + __IO uint32_t PIO0_29; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */ + __IO uint32_t PIO0_30; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */ + __IO uint32_t PIO0_31; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */ + __IO uint32_t PIO1_0; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_1; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_2; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_3; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_4; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_5; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_6; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_7; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_8; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_9; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_10; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_11; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_12; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_13; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_14; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_15; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_16; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_17; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_18; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_19; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_20; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_21; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_22; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_23; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_24; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_25; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_26; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_27; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_28; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_29; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_30; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO1_31; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */ + __IO uint32_t PIO2_0; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */ + __IO uint32_t PIO2_1; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */ + __IO uint32_t PIO2_2; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */ + __IO uint32_t PIO2_3; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */ + __IO uint32_t PIO2_4; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */ + __IO uint32_t PIO2_5; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */ + __IO uint32_t PIO2_6; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */ + __IO uint32_t PIO2_7; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */ + __IO uint32_t PIO2_8; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */ + __IO uint32_t PIO2_9; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */ + __IO uint32_t PIO2_10; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */ + __IO uint32_t PIO2_11; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */ +} LPC_IOCON_Type; + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define LPC_GPIO_PORT_BASE 0x1C000000UL +#define LPC_DMA_BASE 0x1C004000UL +#define LPC_USB_BASE 0x1C00C000UL +#define LPC_CRC_BASE 0x1C010000UL +#define LPC_SCT0_BASE 0x1C018000UL +#define LPC_SCT1_BASE 0x1C01C000UL +#define LPC_SCT2_BASE 0x1C020000UL +#define LPC_SCT3_BASE 0x1C024000UL +#define LPC_ADC0_BASE 0x40000000UL +#define LPC_DAC_BASE 0x40004000UL +#define LPC_ACMP_BASE 0x40008000UL +#define LPC_INMUX_BASE 0x40014000UL +#define LPC_RTC_BASE 0x40028000UL +#define LPC_WWDT_BASE 0x4002C000UL +#define LPC_SWM_BASE 0x40038000UL +#define LPC_PMU_BASE 0x4003C000UL +#define LPC_USART0_BASE 0x40040000UL +#define LPC_USART1_BASE 0x40044000UL +#define LPC_SPI0_BASE 0x40048000UL +#define LPC_SPI1_BASE 0x4004C000UL +#define LPC_I2C0_BASE 0x40050000UL +#define LPC_QEI_BASE 0x40058000UL +#define LPC_SYSCON_BASE 0x40074000UL +#define LPC_ADC1_BASE 0x40080000UL +#define LPC_MRT_BASE 0x400A0000UL +#define LPC_PINT_BASE 0x400A4000UL +#define LPC_GINT0_BASE 0x400A8000UL +#define LPC_GINT1_BASE 0x400AC000UL +#define LPC_RIT_BASE 0x400B4000UL +#define LPC_SCTIPU_BASE 0x400B8000UL +#define LPC_FLASHCTRL_BASE 0x400BC000UL +#define LPC_USART2_BASE 0x400C0000UL +#define LPC_C_CAN0_BASE 0x400F0000UL +#define LPC_IOCON_BASE 0x400F8000UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE) +#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE) +#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE) +#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE) +#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE) +#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE) +#define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE) +#define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE) +#define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE) +#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE) +#define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE) +#define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE) +#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE) +#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) +#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE) +#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE) +#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE) +#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE) +#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE) +#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE) +#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE) +#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE) +#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE) +#define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE) +#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE) +#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE) +#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE) +#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE) +#define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE) +#define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE) +#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE) +#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE) +#define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE) +#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group LPC15xx */ +/** @} */ /* End of group (null) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* LPC15XX_H */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/LPC15xx.sct Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,13 @@ + +LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k) + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100 + ; 36kB(0x9000) - 0x100 = 0x8F00 + RW_IRAM1 (0x02000000+0x100) (0x9000-0x100) { + .ANY (+RW +ZI) + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/startup_LPC15xx.s Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,316 @@ +;/**************************************************************************//** +; * @file startup_LPC15xx.s +; * @brief CMSIS Cortex-M3 Core Device Startup File for +; * NXP LPC15xx Device Series +; * @version V1.00 +; * @date 17. July 2013 +; * +; * @note +; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 16+ 0 Windowed watchdog timer interrupt + DCD BOD_IRQHandler ; 16+ 1 BOD interrupt + DCD FLASH_IRQHandler ; 16+ 2 Flash controller interrupt + DCD EE_IRQHandler ; 16+ 3 EEPROM controller interrupt + DCD DMA_IRQHandler ; 16+ 4 DMA interrupt + DCD GINT0_IRQHandler ; 16+ 5 GPIO group0 interrupt + DCD GINT1_IRQHandler ; 16+ 6 GPIO group1 interrupt + DCD PIN_INT0_IRQHandler ; 16+ 7 Pin interrupt 0 or pattern match engine slice 0 interrupt + DCD PIN_INT1_IRQHandler ; 16+ 8 Pin interrupt 1 or pattern match engine slice 1 interrupt + DCD PIN_INT2_IRQHandler ; 16+ 9 Pin interrupt 2 or pattern match engine slice 2 interrupt + DCD PIN_INT3_IRQHandler ; 16+10 Pin interrupt 3 or pattern match engine slice 3 interrupt + DCD PIN_INT4_IRQHandler ; 16+11 Pin interrupt 4 or pattern match engine slice 4 interrupt + DCD PIN_INT5_IRQHandler ; 16+12 Pin interrupt 5 or pattern match engine slice 5 interrupt + DCD PIN_INT6_IRQHandler ; 16+13 Pin interrupt 6 or pattern match engine slice 6 interrupt + DCD PIN_INT7_IRQHandler ; 16+14 Pin interrupt 7 or pattern match engine slice 7 interrupt + DCD RIT_IRQHandler ; 16+15 RIT interrupt + DCD SCT0_IRQHandler ; 16+16 State configurable timer interrupt + DCD SCT1_IRQHandler ; 16+17 State configurable timer interrupt + DCD SCT2_IRQHandler ; 16+18 State configurable timer interrupt + DCD SCT3_IRQHandler ; 16+19 State configurable timer interrupt + DCD MRT_IRQHandler ; 16+20 Multi-rate timer interrupt + DCD UART0_IRQHandler ; 16+21 USART0 interrupt + DCD UART1_IRQHandler ; 16+22 USART1 interrupt + DCD UART2_IRQHandler ; 16+23 USART2 interrupt + DCD I2C0_IRQHandler ; 16+24 I2C0 interrupt + DCD SPI0_IRQHandler ; 16+25 SPI0 interrupt + DCD SPI1_IRQHandler ; 16+26 SPI1 interrupt + DCD C_CAN0_IRQHandler ; 16+27 C_CAN0 interrupt + DCD USB_IRQ_IRQHandler ; 16+28 USB interrupt + DCD USB_FIQ_IRQHandler ; 16+29 USB interrupt + DCD USBWAKEUP_IRQHandler ; 16+30 USB wake-up interrupt + DCD ADC0_SEQA_IRQHandler ; 16+31 ADC0 sequence A completion. + DCD ADC0_SEQB_IRQHandler ; 16+32 ADC0 sequence B completion. + DCD ADC0_THCMP_IRQHandler ; 16+33 ADC0 threshold compare + DCD ADC0_OVR_IRQHandler ; 16+34 ADC0 overrun + DCD ADC1_SEQA_IRQHandler ; 16+35 ADC1 sequence A completion. + DCD ADC1_SEQB_IRQHandler ; 16+36 ADC1 sequence B completion. + DCD ADC1_THCMP_IRQHandler ; 16+37 ADC1 threshold compare + DCD ADC1_OVR_IRQHandler ; 16+38 ADC1 overrun + DCD DAC_IRQHandler ; 16+39 DAC interrupt + DCD CMP0_IRQHandler ; 16+40 Analog comparator 0 interrupt (ACMP0) + DCD CMP1_IRQHandler ; 16+41 Analog comparator 1 interrupt (ACMP1) + DCD CMP2_IRQHandler ; 16+42 Analog comparator 2 interrupt (ACMP2) + DCD CMP3_IRQHandler ; 16+43 Analog comparator 3 interrupt (ACMP3) + DCD QEI_IRQHandler ; 16+44 QEI interrupt + DCD RTC_ALARM_IRQHandler ; 16+45 RTC alarm interrupt + DCD RTC_WAKE_IRQHandler ; 16+46 RTC wake-up interrut + +; <h> Code Read Protection +; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled +; <0x12345678=>CRP Level 1 +; <0x87654321=>CRP Level 2 +; <0x43218765=>CRP Level 3 (ARE YOU SURE?) +; <0x4E697370=>NO ISP (ARE YOU SURE?) +; </h> + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY + DCD 0xFFFFFFFF + ENDIF + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + +;--- enable SRAM1 and SRAM2 memory + LDR R0, =0x400740C4 ; SYSAHBCLKCTRL0 register addr + LDR R2, [R0] ; read SYSAHBCLKCTRL0 + ORR R2, R2, #0x18 ; enable SRAM1, SRAM2 + STR R2, [R0] ; store SYSAHBCLKCTRL0 +;--- + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EE_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT PIN_INT0_IRQHandler [WEAK] + EXPORT PIN_INT1_IRQHandler [WEAK] + EXPORT PIN_INT2_IRQHandler [WEAK] + EXPORT PIN_INT3_IRQHandler [WEAK] + EXPORT PIN_INT4_IRQHandler [WEAK] + EXPORT PIN_INT5_IRQHandler [WEAK] + EXPORT PIN_INT6_IRQHandler [WEAK] + EXPORT PIN_INT7_IRQHandler [WEAK] + EXPORT RIT_IRQHandler [WEAK] + EXPORT SCT0_IRQHandler [WEAK] + EXPORT SCT1_IRQHandler [WEAK] + EXPORT SCT2_IRQHandler [WEAK] + EXPORT SCT3_IRQHandler [WEAK] + EXPORT MRT_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT C_CAN0_IRQHandler [WEAK] + EXPORT USB_IRQ_IRQHandler [WEAK] + EXPORT USB_FIQ_IRQHandler [WEAK] + EXPORT USBWAKEUP_IRQHandler [WEAK] + EXPORT ADC0_SEQA_IRQHandler [WEAK] + EXPORT ADC0_SEQB_IRQHandler [WEAK] + EXPORT ADC0_THCMP_IRQHandler [WEAK] + EXPORT ADC0_OVR_IRQHandler [WEAK] + EXPORT ADC1_SEQA_IRQHandler [WEAK] + EXPORT ADC1_SEQB_IRQHandler [WEAK] + EXPORT ADC1_THCMP_IRQHandler [WEAK] + EXPORT ADC1_OVR_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT CMP3_IRQHandler [WEAK] + EXPORT QEI_IRQHandler [WEAK] + EXPORT RTC_ALARM_IRQHandler [WEAK] + EXPORT RTC_WAKE_IRQHandler [WEAK] + +WDT_IRQHandler +BOD_IRQHandler +FLASH_IRQHandler +EE_IRQHandler +DMA_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +PIN_INT0_IRQHandler +PIN_INT1_IRQHandler +PIN_INT2_IRQHandler +PIN_INT3_IRQHandler +PIN_INT4_IRQHandler +PIN_INT5_IRQHandler +PIN_INT6_IRQHandler +PIN_INT7_IRQHandler +RIT_IRQHandler +SCT0_IRQHandler +SCT1_IRQHandler +SCT2_IRQHandler +SCT3_IRQHandler +MRT_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +C_CAN0_IRQHandler +USB_IRQ_IRQHandler +USB_FIQ_IRQHandler +USBWAKEUP_IRQHandler +ADC0_SEQA_IRQHandler +ADC0_SEQB_IRQHandler +ADC0_THCMP_IRQHandler +ADC0_OVR_IRQHandler +ADC1_SEQA_IRQHandler +ADC1_SEQB_IRQHandler +ADC1_THCMP_IRQHandler +ADC1_OVR_IRQHandler +DAC_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +CMP3_IRQHandler +QEI_IRQHandler +RTC_ALARM_IRQHandler +RTC_WAKE_IRQHandler + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/sys.cpp Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rt_misc.h> +#include <stdint.h> + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis.h Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC8xx specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "LPC15xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.c Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,30 @@ +/* mbed Microcontroller Library - cmsis_nvic for LPC11U24 + * Copyright (c) 2011 ARM Limited. All rights reserved. + * + * CMSIS-style functionality to support dynamic vectors + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x02000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; i<NVIC_NUM_VECTORS; i++) { + vectors[i] = old_vectors[i]; + } + SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + 16] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + 16]; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.h Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,26 @@ +/* mbed Microcontroller Library - cmsis_nvic + * Copyright (c) 2009-2011 ARM Limited. All rights reserved. + * + * CMSIS-style functionality to support dynamic vectors + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 + 47) // CORE + MCU Peripherals +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,517 @@ +/**************************************************************************//** + * @file system_LPC15xx.c + * @brief CMSIS Cortex-M3 Device System Source File for + * NXP LPC15xx Device Series + * @version V1.00 + * @date 19. July 2013 + * + * @note + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include <stdint.h> +#include "LPC15xx.h" + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*- SystemCoreClock Configuration -------------------------------------------*/ +// <e0> SystemCoreClock Configuration +#define CLOCK_SETUP 1 +// +// <h> System Oscillator Control (SYSOSCCTRL) +// <o.0> BYPASS: System Oscillator Bypass Enable +// <i> If enabled then PLL input (sys_osc_clk) is fed +// <i> directly from XTALIN and XTALOUT pins. +// <o.1> FREQRANGE: System Oscillator Frequency Range +// <i> Determines frequency range for Low-power oscillator. +// <0=> 1 - 20 MHz +// <1=> 15 - 25 MHz +// </h> +#define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000 +// +// <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL) +// <0=> IRC Oscillator +// <1=> Crystal Oscillator (SYSOSC) +#define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000 +// +// <e> Clock Configuration (Manual) +#define CLOCK_SETUP_REG 1 +// +// <o.0..1> Main Clock Source Select A (MAINCLKSELA) +// <0=> IRC Oscillator +// <1=> System Oscillator +// <2=> WD Oscillator +#define MAINCLKSELA_Val 0x00000001 // Reset value: 0x000 +// +// <o.0..1> Main Clock Source Select B (MAINCLKSELB) +// <0=> MAINCLKSELA +// <1=> System PLL Input +// <2=> System PLL Output +// <3=> RTC Oscillator +#define MAINCLKSELB_Val 0x00000002 // Reset value: 0x000 +// +// <h> System PLL Setting (SYSPLLCTRL) +// <i> F_clkout = M * F_clkin = F_CCO / (2 * P) +// <i> F_clkin must be in the range of 10 MHz to 25 MHz +// <i> F_CCO must be in the range of 156 MHz to 320 MHz +// <o.0..5> MSEL: Feedback Divider Selection +// <i> M = MSEL + 1 +// <0-31> +// <o.5..7> PSEL: Post Divider Selection +// <i> Post divider ratio P. Division ratio is 2 * P +// <0=> P = 1 +// <1=> P = 2 +// <2=> P = 4 +// <3=> P = 8 +// </h> +#define SYSPLLCTRL_Val 0x00000005 // Reset value: 0x000 +// +// <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV) +// <i> Divides main clock to provide system clock to core, memories, and peripherals. +// <i> 0 = is disabled +// <0-255> +#define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001 +// </e> +// +// <e> Clock Configuration (via ROM PLL API) +#define CLOCK_SETUP_API 0 +// +// <o> PLL API Mode Select +// <0=> Exact +// <1=> Less than or equal +// <2=> Greater than or equal +// <3=> As close as possible +#define PLL_API_MODE_Val 0 +// +// <o> CPU Frequency [Hz] <1000000-72000000:1000> +#define PLL_API_FREQ_Val 72000000 +// </e> +// +// <e> USB Clock Configuration +#define USB_CLOCK_SETUP 0 +// <h> USB PLL Control (USBPLLCTRL) +// <i> F_clkout = M * F_clkin = F_CCO / (2 * P) +// <i> F_clkin must be in the range of 10 MHz to 25 MHz +// <i> F_CCO must be in the range of 156 MHz to 320 MHz +// <o.0..5> MSEL: Feedback Divider Selection +// <i> M = MSEL + 1 +// <0-31> +// <o.7..6> PSEL: Post Divider Selection +// <i> Post divider ratio P. Division ratio is 2 * P +// <0=> P = 1 +// <1=> P = 2 +// <2=> P = 4 +// <3=> P = 8 +// </h> +#define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000 +// +// <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL) +// <0=> IRC Oscillator +// <1=> System Oscillator +#define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000 +// +// <o.0..1> USB Clock Source Select (USBCLKSEL.SEL) +// <0=> IRC Oscillator +// <1=> System Oscillator +// <2=> USB PLL out +// <3=> Main clock +#define USBCLKSEL_Val 0x00000002 // Reset value: 0x000 +// +// <o.0..7> USB Clock Divider (USBCLKDIV.DIV) +// <i> Divides USB clock to 48 MHz. +// <i> 0 = is disabled +// <0-255> +#define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001 +// </e> +// +// <e> SCT Clock Configuration +#define SCT_CLOCK_SETUP 1 +// <h> SCT PLL Control (SCTPLLCTRL) +// <i> F_clkout = M * F_clkin = F_CCO / (2 * P) +// <i> F_clkin must be in the range of 10 MHz to 25 MHz +// <i> F_CCO must be in the range of 156 MHz to 320 MHz +// <o.0..5> MSEL: Feedback Divider Selection +// <i> M = MSEL + 1 +// <0-31> +// <o.7..6> PSEL: Post Divider Selection +// <i> Post divider ratio P. Division ratio is 2 * P +// <0=> P = 1 +// <1=> P = 2 +// <2=> P = 4 +// <3=> P = 8 +// </h> +#define SCTPLLCTRL_Val 0x00000005 // Reset value: 0x000 +// +// <o.0..1> SCT PLL Clock Source Select (SCTPLLCLKSEL.SEL) +// <0=> IRC Oscillator +// <1=> System Oscillator +#define SCTPLLCLKSEL_Val 0x00000001 // Reset value: 0x000 +// </e> +// +// </e> +// +// <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000> +// <i> XTAL frequency must be in the range of 1 MHz to 25 MHz +// +#define XTAL_CLK_Val 12000000 + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */ +#define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */ +#define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */ +#define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */ +#define __WDT_OSC_CLK ( 503000UL) /* WDT oscillator freq */ + +/*---------------------------------------------------------------------------- + Check the register settings + *----------------------------------------------------------------------------*/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) +#define CHECK_RSVD(val, mask) (val & mask) + +#if (CHECK_RANGE((SYSOSCCTRL_Val), 0, 1)) + #error "SYSOSCCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3)) + #error "SYSPLLCLKSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000000FF)) + #error "SYSPLLCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((MAINCLKSELA_Val), 0, 2)) + #error "MAINCLKSELA: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((MAINCLKSELB_Val), ~0x00000003)) + #error "MAINCLKSELB: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) + #error "SYSAHBCLKDIV: Value out of range!" +#endif + +#if ( CLOCK_SETUP_REG == CLOCK_SETUP_API ) + #error "You must select either manual or API based Clock Configuration!" +#endif + +#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1)) + #error "USBPLLCLKSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x00000FF)) + #error "USBPLLCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((USBCLKSEL_Val), 0, 3)) + #error "USBCLKSEL: Value out of range!" +#endif + +#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255)) + #error "USBCLKDIV: Value out of range!" +#endif + +#if (CHECK_RANGE((SCTPLLCLKSEL_Val), 0, 1)) + #error "SCTPLLCLKSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((SCTPLLCTRL_Val), ~0x00000FF)) + #error "SCTPLLCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000)) + #error "XTAL frequency is out of bounds" +#endif + +#if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3)) + #error "PLL API Mode Select not valid" +#endif + +#if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 72000000)) + #error "CPU Frequency (API mode) not valid" +#endif + + + +/*---------------------------------------------------------------------------- + Calculate system core clock + *----------------------------------------------------------------------------*/ +#if (CLOCK_SETUP) /* Clock Setup */ + + /* sys_pllclkin calculation */ + #if ((SYSPLLCLKSEL_Val & 0x03) == 0) + #define __SYS_PLLCLKIN (__IRC_OSC_CLK) + #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) + #define __SYS_PLLCLKIN (__SYS_OSC_CLK) + #else + #error "Oops" + #endif + + #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */ + + #if ((MAINCLKSELA_Val & 0x03) == 0) + #define __MAINA_CLOCK (__IRC_OSC_CLK) + #elif ((MAINCLKSELA_Val & 0x03) == 1) + #define __MAINA_CLOCK (__SYS_OSC_CLK) + #elif ((MAINCLKSELA_Val & 0x03) == 2) + #define __MAINA_CLOCK (__WDT_OSC_CLK) + #else + #error "Oops" + #endif + + #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) + + /* main clock calculation */ + #if ((MAINCLKSELB_Val & 0x03) == 0) + #define __MAINB_CLOCK (__MAINA_CLOCK) + #elif ((MAINCLKSELB_Val & 0x03) == 1) + #define __MAINB_CLOCK (__SYS_PLLCLKIN) + #elif ((MAINCLKSELB_Val & 0x03) == 2) + #define __MAINB_CLOCK (__SYS_PLLCLKOUT) + #elif ((MAINCLKSELB_Val & 0x03) == 3) + #define __MAINB_CLOCK (__RTC_OSC_CLK) + #else + #error "Oops" + #endif + + #define __SYSTEM_CLOCK (__MAINB_CLOCK / SYSAHBCLKDIV_Val) + #endif /* Clock Setup via Register */ + + #if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */ + #define __SYSTEM_CLOCK (PLL_API_FREQ_Val) + #endif /* Clock Setup via PLL API */ + +#else + #define __SYSTEM_CLOCK (__IRC_OSC_CLK) +#endif /* CLOCK_SETUP */ + + + +#if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */ +#include "power_api.h" + +typedef struct _ROM { + const unsigned p_dev0; + const unsigned p_dev1; + const unsigned p_dev2; + const PWRD * pPWRD; /* ROM Power Management API */ + const unsigned p_dev4; + const unsigned p_dev5; + const unsigned p_dev6; + const unsigned p_dev7; +} ROM; + +/*---------------------------------------------------------------------------- + PLL API Function + *----------------------------------------------------------------------------*/ +static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq) +{ + uint32_t cmd[5], res[5]; + ROM ** rom = (ROM **) 0x03000200; /* pointer to power API calls */ + + cmd[0] = pllInFreq; /* PLL's input freq in KHz */ + cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */ + cmd[2] = pllMode; + cmd[3] = 0; /* no timeout for PLL to lock */ + + /* Execute API call */ + (*rom)->pPWRD->set_pll(cmd, res); /* call API function */ + if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */ + while(1); /* ... stay here */ + } +} +#endif + + + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + /* Determine clock frequency according to clock register values */ + switch (LPC_SYSCON->MAINCLKSELB & 0x03) { + case 0: /* MAINCLKSELA clock sel */ + switch (LPC_SYSCON->MAINCLKSELA & 0x03) { + case 0: /* Internal RC oscillator */ + SystemCoreClock = __IRC_OSC_CLK; + break; + case 1: /* System oscillator */ + SystemCoreClock = __SYS_OSC_CLK; + break; + case 2: /* Watchdog oscillator */ + SystemCoreClock = __WDT_OSC_CLK; + break; + case 3: /* Reserved */ + SystemCoreClock = 0; + break; + } + break; + case 1: /* Input Clock to System PLL */ + switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { + case 0: /* Internal RC oscillator */ + SystemCoreClock = __IRC_OSC_CLK; + break; + case 1: /* System oscillator */ + SystemCoreClock = __SYS_OSC_CLK; + break; + case 2: /* Reserved */ + case 3: /* Reserved */ + SystemCoreClock = 0; + break; + } + break; + case 2: /* System PLL Clock Out */ + switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { + case 0: /* Internal RC oscillator */ + SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + break; + case 1: /* System oscillator */ + SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + break; + case 2: /* Reserved */ + case 3: /* Reserved */ + SystemCoreClock = 0; + break; + } + break; + case 3: /* WDT Oscillator */ + SystemCoreClock = __WDT_OSC_CLK; + break; + } + + SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + */ +void SystemInit (void) { +#if (CLOCK_SETUP) + volatile uint32_t i; +#endif + +#if (CLOCK_SETUP) /* Clock Setup */ + +#if ((SYSPLLCLKSEL_Val & 0x03) == 1) + LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; + LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */ + for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */ +#endif + + LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ + +#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */ + +#if (((MAINCLKSELA_Val & 0x03) == 1) ) + LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; + LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */ + for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */ +#endif + +#if (((MAINCLKSELA_Val & 0x03) == 2) ) + LPC_SYSCON->PDRUNCFG &= ~(1 << 20); /* Power-up WDT Clock */ + for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */ +#endif + +#if ((MAINCLKSELB_Val & 0x03) == 3) + LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */ + for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */ +#endif + + LPC_SYSCON->MAINCLKSELA = MAINCLKSELA_Val; /* select MAINCLKA clock */ + +#if ((MAINCLKSELB_Val & 0x03) == 2) /* Main Clock is PLL Out */ + LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; + LPC_SYSCON->PDRUNCFG &= ~(1 << 22); /* Power-up SYSPLL */ + while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ +#endif + + LPC_SYSCON->MAINCLKSELB = MAINCLKSELB_Val; /* select Main clock */ + + LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; +#endif /* Clock Setup via Register */ + +#if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */ +// LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */ + + LPC_SYSCON->MAINCLKSELB = (1 << 2); /* Select System PLL output */ + + LPC_SYSCON->SYSAHBCLKDIV = 1; + + setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000); +#endif /* Clock Setup via PLL API */ + +#if (USB_CLOCK_SETUP == 1) /* USB clock is used */ + LPC_SYSCON->PDRUNCFG &= ~(1 << 9); /* Power-up USB PHY */ + +#if ((USBCLKSEL_Val & 0x003) == 2) /* USB clock is USB PLL out */ + LPC_SYSCON->PDRUNCFG &= ~(1 << 23); /* Power-up USB PLL */ + LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */ + + LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val; + while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */ + + LPC_SYSCON->USBCLKSEL = 0x02; /* Select USB PLL */ +#endif + + LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */ + LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */ + +#else /* USB clock is not used */ + LPC_SYSCON->PDRUNCFG |= (1 << 9); /* Power-down USB PHY */ + LPC_SYSCON->PDRUNCFG |= (1 << 23); /* Power-down USB PLL */ +#endif + +#if (SCT_CLOCK_SETUP == 1) /* SCT clock is used */ + LPC_SYSCON->PDRUNCFG &= ~(1 << 24); /* Power-up SCT PLL */ + LPC_SYSCON->SCTPLLCLKSEL = SCTPLLCLKSEL_Val; /* Select PLL Input */ + + LPC_SYSCON->SCTPLLCTRL = SCTPLLCTRL_Val; + while (!(LPC_SYSCON->SCTPLLSTAT & 0x01)); /* Wait Until PLL Locked */ +#else /* SCT clock is not used */ + LPC_SYSCON->PDRUNCFG |= (1 << 24); /* Power-down SCT PLL */ +#endif + +#endif /* Clock Setup */ + + + LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << 12); /* enable clock for SWM */ + +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.h Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file system_LPC15xx.h + * @brief CMSIS Cortex-M3 Device System Header File for + * NXP LPC15xx Device Series + * @version V1.00 + * @date 19. July 2013 + * + * @note + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_LPC15xx_H +#define __SYSTEM_LPC15xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + +/** @addtogroup LPC15xx_System + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* __SYSTEM_LPC15xx_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/PeripheralNames.h Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,57 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC0_0 = 0, + ADC0_1, + ADC0_2, + ADC0_3, + ADC0_4, + ADC0_5, + ADC0_6, + ADC0_7, + ADC0_8, + ADC0_9, + ADC0_10, + ADC0_11, + ADC1_0, + ADC1_1, + ADC1_2, + ADC1_3, + ADC1_4, + ADC1_5, + ADC1_6, + ADC1_7, + ADC1_8, + ADC1_9, + ADC1_10, + ADC1_11, +} ADCName; + + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/PinNames.h Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,99 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2014 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + // LPC Pin Names + P0_0 = 0, + P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31, + P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31, + P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, + + LED_RED = P0_25, + LED_GREEN = P0_3, + LED_BLUE = P1_1, + + // mbed original LED naming + LED1 = LED_BLUE, + LED2 = LED_GREEN, + LED3 = LED_RED, + LED4 = LED_RED, + + // Serial to USB pins + USBTX = P0_18, + USBRX = P0_13, + + // Arduino Shield Receptacles Names + D0 = P0_13, + D1 = P0_18, + D2 = P0_29, + D3 = P0_9, + D4 = P0_10, + D5 = P0_16, // same port as D13 + D6 = P1_3, + D7 = P0_0, + D8 = P0_24, + D9 = P1_0, + D10= P0_27, + D11= P0_28, + D12= P0_12, + D13= P0_16, // same port as D5 + A0 = P0_8, + A1 = P0_7, + A2 = P0_6, + A3 = P0_5, + A4 = P0_23, // same port as SDA + A5 = P0_22, // same port as SCL + SDA= P0_23, // same port as A4 + SCL= P0_22, // same port as A5 + + // Not connected + NC = (int)0xFFFFFFFF, +} PinName; + +typedef enum { + PullUp = 2, + PullDown = 1, + PullNone = 0, + Repeater = 3, + OpenDrain = 4 +} PinMode; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +typedef struct { + unsigned char n; + unsigned char offset; +} SWM_Map; + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/PortNames.h Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,32 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2014 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1, + Port2 = 2 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,152 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "analogin_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "error.h" + +#define ANALOGIN_MEDIAN_FILTER 1 + +#define ADC_10BIT_RANGE 0x3FF +#define ADC_12BIT_RANGE 0xFFF + +#define ADC_RANGE ADC_12BIT_RANGE + +static const PinMap PinMap_ADC[] = { + {P0_8 , ADC0_0, 0}, + {P0_7 , ADC0_1, 0}, + {P0_6 , ADC0_2, 0}, + {P0_5 , ADC0_3, 0}, + {P0_4 , ADC0_4, 0}, + {P0_3 , ADC0_5, 0}, + {P0_2 , ADC0_6, 0}, + {P0_1 , ADC0_7, 0}, + {P1_0 , ADC0_8, 0}, + {P0_31, ADC0_9, 0}, + {P0_0 , ADC0_10,0}, + {P0_30, ADC0_11,0}, + {P1_1 , ADC1_0, 0}, + {P0_9 , ADC1_1, 0}, + {P0_10, ADC1_2, 0}, + {P0_11, ADC1_3, 0}, + {P1_2 , ADC1_4, 0}, + {P1_3 , ADC1_5, 0}, + {P0_13, ADC1_6, 0}, + {P0_14, ADC1_7, 0}, + {P0_15, ADC1_8, 0}, + {P0_16, ADC1_9, 0}, + {P1_4 , ADC1_10,0}, + {P1_5 , ADC1_11,0}, +}; + +void analogin_init(analogin_t *obj, PinName pin) { + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + if (obj->adc == (uint32_t)NC) { + error("ADC pin mapping failed"); + } + uint32_t port = (pin >> 5); + // enable clock for GPIOx + LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << (14 + port)); + // pin enable + LPC_SWM->PINENABLE0 &= ~(1UL << obj->adc); + // configure GPIO as input + LPC_GPIO_PORT->DIR[port] &= ~(1UL << (pin & 0x1F)); + + // power up ADC + if (obj->adc < ADC1_0) + { + // ADC0 + LPC_SYSCON->PDRUNCFG &= ~(1 << 10); + LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 27); + } + else { + // ADC1 + LPC_SYSCON->PDRUNCFG &= ~(1 << 11); + LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 28); + } + + // select IRC as async. clock, divided by 1 + LPC_SYSCON->ADCASYNCCLKSEL = 0; + LPC_SYSCON->ADCASYNCCLKDIV = 1; + + __IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1); + + // start calibration + adc_reg->CTRL |= (1UL << 30); + __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); + + // asynchronous mode + adc_reg->CTRL = (1UL << 8); + +} + +static inline uint32_t adc_read(analogin_t *obj) { + + __IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1); + + // select channel + adc_reg->SEQA_CTRL &= ~(0xFFF); + adc_reg->SEQA_CTRL |= (1UL << (obj->adc & 0x1F)); + + // start conversion and sequence enable + adc_reg->SEQA_CTRL |= ((1UL << 26) | (1UL << 31)); + + // Repeatedly get the sample data until DONE bit + volatile uint32_t data; + do { + data = adc_reg->SEQA_GDAT; + } while ((data & (1UL << 31)) == 0); + + // Stop conversion + adc_reg->SEQA_CTRL &= ~(1UL << 31); + + return ((data >> 4) & ADC_RANGE); +} + +static inline void order(uint32_t *a, uint32_t *b) { + if (*a > *b) { + uint32_t t = *a; + *a = *b; + *b = t; + } +} + +static inline uint32_t adc_read_u32(analogin_t *obj) { + uint32_t value; +#if ANALOGIN_MEDIAN_FILTER + uint32_t v1 = adc_read(obj); + uint32_t v2 = adc_read(obj); + uint32_t v3 = adc_read(obj); + order(&v1, &v2); + order(&v2, &v3); + order(&v1, &v2); + value = v2; +#else + value = adc_read(obj); +#endif + return value; +} + +uint16_t analogin_read_u16(analogin_t *obj) { + uint32_t value = adc_read_u32(obj); + return (value << 4) | ((value >> 8) & 0x000F); // 12 bit +} + +float analogin_read(analogin_t *obj) { + uint32_t value = adc_read_u32(obj); + return (float)value * (1.0f / (float)ADC_RANGE); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/device.h Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2014 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 0 +#define DEVICE_PORTOUT 0 +#define DEVICE_PORTINOUT 0 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 +#define DEVICE_SERIAL_FC 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 0 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 + +#define DEVICE_SLEEP 0 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_api.c Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,65 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2014 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "pinmap.h" + +static int gpio_enabled = 0; + +static void gpio_enable(void) { + gpio_enabled = 1; + + /* Enable AHB clock to the GPIO0/1/2 and IOCON domain. */ + LPC_SYSCON->SYSAHBCLKCTRL0 |= (0xFUL << 13); +} + +uint32_t gpio_set(PinName pin) { + + if (!gpio_enabled) + gpio_enable(); + + return (1UL << ((int)pin & 0x1f)); +} + +void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) { + if(pin == NC) return; + + obj->pin = pin; + obj->mask = gpio_set(pin); + + unsigned int port = (unsigned int)(pin >> 5); + + obj->reg_set = &LPC_GPIO_PORT->SET[port]; + obj->reg_clr = &LPC_GPIO_PORT->CLR[port]; + obj->reg_in = &LPC_GPIO_PORT->PIN[port]; + obj->reg_dir = &LPC_GPIO_PORT->DIR[port]; + + gpio_dir(obj, direction); + switch (direction) { + case PIN_OUTPUT: pin_mode(pin, PullNone); break; + case PIN_INPUT : pin_mode(pin, PullDown); break; + } +} + +void gpio_mode(gpio_t *obj, PinMode mode) { + pin_mode(obj->pin, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) { + switch (direction) { + case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; + case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_irq_api.c Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,139 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include <stddef.h> + +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "error.h" + +#define CHANNEL_NUM 8 +#define LPC_GPIO_X LPC_PINT +#define PININT_IRQ PIN_INT0_IRQn + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler irq_handler; + +static inline void handle_interrupt_in(uint32_t channel) { + uint32_t ch_bit = (1 << channel); + // Return immediately if: + // * The interrupt was already served + // * There is no user handler + // * It is a level interrupt, not an edge interrupt + if ( ((LPC_GPIO_X->IST & ch_bit) == 0) || + (channel_ids[channel] == 0 ) || + (LPC_GPIO_X->ISEL & ch_bit ) ) return; + + if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) { + irq_handler(channel_ids[channel], IRQ_RISE); + LPC_GPIO_X->RISE = ch_bit; + } + if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) { + irq_handler(channel_ids[channel], IRQ_FALL); + LPC_GPIO_X->FALL = ch_bit; + } + LPC_GPIO_X->IST = ch_bit; +} + +void gpio_irq0(void) {handle_interrupt_in(0);} +void gpio_irq1(void) {handle_interrupt_in(1);} +void gpio_irq2(void) {handle_interrupt_in(2);} +void gpio_irq3(void) {handle_interrupt_in(3);} +void gpio_irq4(void) {handle_interrupt_in(4);} +void gpio_irq5(void) {handle_interrupt_in(5);} +void gpio_irq6(void) {handle_interrupt_in(6);} +void gpio_irq7(void) {handle_interrupt_in(7);} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { + // PINT only supprt GPIO port 0 and 1 interrupt + if (pin >= P2_0) return -1; + + irq_handler = handler; + + int found_free_channel = 0; + int i = 0; + for (i=0; i<CHANNEL_NUM; i++) { + if (channel_ids[i] == 0) { + channel_ids[i] = id; + obj->ch = i; + found_free_channel = 1; + break; + } + } + if (!found_free_channel) return -1; + + /* Enable AHB clock to the PIN, GPIO0/1, IOCON and MUX domain. */ + LPC_SYSCON->SYSAHBCLKCTRL0 |= ((1 << 18) | (0x1D << 11)); + + LPC_INMUX->PINTSEL[obj->ch] = pin; + + // Interrupt Wake-Up Enable + LPC_SYSCON->STARTERP0 |= (1 << (obj->ch + 5)); + + LPC_GPIO_PORT->DIR[pin >> 5] &= ~(1 << (pin & 0x1F)); + + void (*channels_irq)(void) = NULL; + switch (obj->ch) { + case 0: channels_irq = &gpio_irq0; break; + case 1: channels_irq = &gpio_irq1; break; + case 2: channels_irq = &gpio_irq2; break; + case 3: channels_irq = &gpio_irq3; break; + case 4: channels_irq = &gpio_irq4; break; + case 5: channels_irq = &gpio_irq5; break; + case 6: channels_irq = &gpio_irq6; break; + case 7: channels_irq = &gpio_irq7; break; + } + NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); + NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) { + channel_ids[obj->ch] = 0; + LPC_SYSCON->STARTERP0 &= ~(1 << (obj->ch + 5)); +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { + unsigned int ch_bit = (1 << obj->ch); + + // Clear interrupt + if (!(LPC_GPIO_X->ISEL & ch_bit)) + LPC_GPIO_X->IST = ch_bit; + + // Edge trigger + LPC_GPIO_X->ISEL &= ~ch_bit; + if (event == IRQ_RISE) { + if (enable) { + LPC_GPIO_X->IENR |= ch_bit; + } else { + LPC_GPIO_X->IENR &= ~ch_bit; + } + } else { + if (enable) { + LPC_GPIO_X->IENF |= ch_bit; + } else { + LPC_GPIO_X->IENF &= ~ch_bit; + } + } +} + +void gpio_irq_enable(gpio_irq_t *obj) { + NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); +} + +void gpio_irq_disable(gpio_irq_t *obj) { + NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_object.h Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,48 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + + __IO uint32_t *reg_dir; + __IO uint32_t *reg_set; + __IO uint32_t *reg_clr; + __I uint32_t *reg_in; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) { + if (value) + *obj->reg_set = obj->mask; + else + *obj->reg_clr = obj->mask; +} + +static inline int gpio_read(gpio_t *obj) { + return ((*obj->reg_in & obj->mask) ? 1 : 0); +} + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/i2c_api.c Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,258 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "i2c_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "error.h" + +static uint8_t repeated_start = 0; + +#define I2C_STAT(x) ((LPC_I2C0->STAT >> 1) & (0x07)) + +static inline int i2c_status(i2c_t *obj) { + return I2C_STAT(obj); +} + +// Wait until the Serial Interrupt (SI) is set +static int i2c_wait_SI(i2c_t *obj) { + int timeout = 0; + while (!(LPC_I2C0->STAT & (1 << 0))) { + timeout++; + if (timeout > 100000) return -1; + } + return 0; +} + +static inline void i2c_interface_enable(i2c_t *obj) { + LPC_I2C0->CFG |= (1 << 0); +} + +static inline void i2c_power_enable(i2c_t *obj) { + // Enables clock for I2C0 + LPC_SYSCON->SYSAHBCLKCTRL1 |= (1<<13); +// LPC_SYSCON->PRESETCTRL1 &= ~(0x1<<13); + LPC_SYSCON->PRESETCTRL1 |= (0x1<<13); + LPC_SYSCON->PRESETCTRL1 &= ~(0x1 << 13); + +} + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) { + + // sè`ÌmFǤµæ¤c + + + // enable power + i2c_power_enable(obj); + // pin enable + LPC_SWM->PINENABLE1 &= ~(0x3 << 3); + // set default frequency at 100k + i2c_frequency(obj, 100000); + i2c_interface_enable(obj); +} + +inline int i2c_start(i2c_t *obj) { + int status = 0; + if (repeated_start) { + LPC_I2C0->MSTCTL = (1 << 1) | (1 << 0); + repeated_start = 0; + } else { + LPC_I2C0->MSTCTL = (1 << 1); + } + return status; +} + +inline int i2c_stop(i2c_t *obj) { + int timeout = 0; + + LPC_I2C0->MSTCTL = (1 << 2) | (1 << 0); + while ((LPC_I2C0->STAT & ((1 << 0) | (7 << 1))) != ((1 << 0) | (0 << 1))) { + timeout ++; + if (timeout > 100000) return 1; + } + + return 0; +} + + +static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) { + // write the data + LPC_I2C0->MSTDAT = value; + + if (!addr) + LPC_I2C0->MSTCTL = (1 << 0); + + // wait and return status + i2c_wait_SI(obj); + return i2c_status(obj); +} + +static inline int i2c_do_read(i2c_t *obj, int last) { + // wait for it to arrive + i2c_wait_SI(obj); + if (!last) + LPC_I2C0->MSTCTL = (1 << 0); + + // return the data + //return (I2C_DAT(obj) & 0xFF); + return (LPC_I2C0->MSTDAT & 0xFF); +} + +void i2c_frequency(i2c_t *obj, int hz) { + // No peripheral clock divider on the M0 + uint32_t PCLK = SystemCoreClock; + + uint32_t clkdiv = PCLK / (hz * 4) - 1; + + LPC_I2C0->DIV = clkdiv; + LPC_I2C0->MSTTIME = 0; +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { + int count, status; + int timeout = 0; + + i2c_start(obj); + + //status = i2c_do_write(obj, (address | 0x01), 1); + LPC_I2C0->MSTDAT = (address | 0x01); + LPC_I2C0->MSTCTL |= 0x20; + while (!(LPC_I2C0->STAT & (1 << 0))) { + timeout++; + if (timeout > 100000) return -1; + } + status = ((LPC_I2C0->STAT >> 1) & (0x07)); + + if (status != 0x01) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + // Read in all except last byte + for (count = 0; count < (length - 1); count++) { + //int value = i2c_do_read(obj, 0); + while (!(LPC_I2C0->STAT & (1 << 0))) { + timeout++; + if (timeout > 100000) return -1; + } + if (!0) + LPC_I2C0->MSTCTL = (1 << 0); + data[count] = (LPC_I2C0->MSTDAT & 0xFF); + // + status = ((LPC_I2C0->STAT >> 1) & (0x07)); + if (status != 0x00) { + i2c_stop(obj); + return count; + } + //data[count] = (char) value; + } + + // read in last byte + //int value = i2c_do_read(obj, 1); + while (!(LPC_I2C0->STAT & (1 << 0))) { + timeout++; + if (timeout > 100000) return -1; + } + data[count] = (LPC_I2C0->MSTDAT & 0xFF); + // + status = i2c_status(obj); + if (status != 0x01) { + i2c_stop(obj); + return length - 1; + } + + //data[count] = (char) value; + + // If not repeated start, send stop. + if (stop) { + i2c_stop(obj); + } else { + repeated_start = 1; + } + + return length; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { + int i, status; + int timeout = 0; + + i2c_start(obj); + + //status = i2c_do_write(obj, (address & 0xFE), 1); + LPC_I2C0->MSTDAT = (address & 0xFE); + LPC_I2C0->MSTCTL |= 0x20; + // wait and return status + while (!(LPC_I2C0->STAT & (1 << 0))) { + timeout++; + if (timeout > 100000) return -1; + } + status = ((LPC_I2C0->STAT >> 1) & (0x07)); + + if (status != 0x02) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + for (i=0; i<length; i++) { + //status = i2c_do_write(obj, data[i], 0); + LPC_I2C0->MSTDAT = data[i]; + LPC_I2C0->MSTCTL = (1 << 0); + // wait and return status + while (!(LPC_I2C0->STAT & (1 << 0))) { + timeout++; + if (timeout > 100000) return -1; + } + status = ((LPC_I2C0->STAT >> 1) & (0x07)); + if (status != 0x02) { + i2c_stop(obj); + return i; + } + } + + // If not repeated start, send stop. + if (stop) { + i2c_stop(obj); + } else { + repeated_start = 1; + } + + return length; +} + +void i2c_reset(i2c_t *obj) { + i2c_stop(obj); +} + +int i2c_byte_read(i2c_t *obj, int last) { + return (i2c_do_read(obj, last) & 0xFF); +} + +int i2c_byte_write(i2c_t *obj, int data) { + int ack; + int status = i2c_do_write(obj, (data & 0xFF), 0); + + switch(status) { + case 2: + ack = 1; + break; + default: + ack = 0; + break; + } + + return ack; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/objects.h Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + uint32_t ch; +}; + +struct serial_s { + LPC_USART0_Type *uart; + unsigned char index; +}; + +struct analogin_s { + ADCName adc; +}; + +struct i2c_s { + LPC_I2C0_Type *i2c; +}; + +struct spi_s { + LPC_SPI0_Type *spi; + unsigned char spi_n; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/pinmap.c Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pinmap.h" +#include "error.h" + +void pin_function(PinName pin, int function) { +} + +void pin_mode(PinName pin, PinMode mode) { + if (pin == (uint32_t)NC) { return; } + + if ((pin == P0_22) || (pin == P0_23)) { + // The true open-drain pins PIO0_22 and PIO0_23 can be configured for different I2C-bus speeds. + return; + } + + __IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + (pin * 4)); + + if (mode == OpenDrain) { + *reg |= (1 << 10); + } else { + uint32_t tmp = *reg; + tmp &= ~(0x3 << 3); + tmp |= (mode & 0x3) << 3; + *reg = tmp; + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,328 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// math.h required for floating point operations for baud rate calculation +#include <math.h> +#include <string.h> + +#include "serial_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "error.h" + +/****************************************************************************** + * INITIALIZATION + ******************************************************************************/ +#define UART_NUM 3 + +static const SWM_Map SWM_UART_TX[] = { + {0, 0}, // Pin assign register0, 7:0bit + {1, 8}, // Pin assign register1, 15:8bit + {2, 16}, // Pin assign register2, 23:16bit +}; + +static const SWM_Map SWM_UART_RX[] = { + {0, 8}, + {1, 16}, + {2, 24}, +}; + +static const SWM_Map SWM_UART_RTS[] = { + {0, 16}, + {1, 24}, + {3, 0}, +}; + +static const SWM_Map SWM_UART_CTS[] = { + {0, 24}, + {2, 0}, + {3, 8} +}; + +// bit flags for used UARTs +static unsigned char uart_used = 0; +static int get_available_uart(void) { + int i; + for (i=0; i<3; i++) { + if ((uart_used & (1 << i)) == 0) + return i; + } + return -1; +} + +#define UART_EN (0x01<<0) + +#define CTS_DELTA (0x01<<5) +#define RXBRK (0x01<<10) +#define DELTA_RXBRK (0x01<<11) + +#define RXRDY (0x01<<0) +#define TXRDY (0x01<<2) + +#define TXBRKEN (0x01<<1) +#define CTSEN (0x01<<9) + +static uint32_t UARTSysClk; + +static uint32_t serial_irq_ids[UART_NUM] = {0}; +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + int is_stdio_uart = 0; + + int uart_n = get_available_uart(); + if (uart_n == -1) { + error("No available UART"); + } + obj->index = uart_n; + obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * uart_n)); + uart_used |= (1 << uart_n); + + const SWM_Map *swm; + uint32_t regVal; + + swm = &SWM_UART_TX[uart_n]; + regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); + LPC_SWM->PINASSIGN[swm->n] = regVal | (tx << swm->offset); + + swm = &SWM_UART_RX[uart_n]; + regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); + LPC_SWM->PINASSIGN[swm->n] = regVal | (rx << swm->offset); + + /* uart clock divided by 6 */ + LPC_SYSCON->UARTCLKDIV =6; + + /* disable uart interrupts */ + NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n)); + + /* Enable UART clock */ + LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << (17 + uart_n)); + + /* Peripheral reset control to UART, a "1" bring it out of reset. */ +// LPC_SYSCON->PRESETCTRL1 &= ~(0x1 << (17 + uart_n)); + LPC_SYSCON->PRESETCTRL1 |= (0x1 << (17 + uart_n)); + LPC_SYSCON->PRESETCTRL1 ^= (0x1 << (17 + uart_n)); + + UARTSysClk = SystemCoreClock / LPC_SYSCON->UARTCLKDIV; + + // set default baud rate and format + serial_baud (obj, 9600); + serial_format(obj, 8, ParityNone, 1); + + /* Clear all status bits. */ + obj->uart->STAT = CTS_DELTA | DELTA_RXBRK; + + /* enable uart interrupts */ + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n)); + + /* Enable UART interrupt */ + // obj->uart->INTENSET = RXRDY | TXRDY | DELTA_RXBRK; + + /* Enable UART */ + obj->uart->CFG |= UART_EN; + + is_stdio_uart = ((tx == USBTX) && (rx == USBRX)); + + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + uart_used &= ~(1 << obj->index); + serial_irq_ids[obj->index] = 0; +} + +// serial_baud +// set the baud rate, taking in to account the current SystemFrequency +void serial_baud(serial_t *obj, int baudrate) { + /* Integer divider: + BRG = UARTSysClk/(Baudrate * 16) - 1 + + Frational divider: + FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1) + + where + FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1) + + (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB + register is 0xFF. + (2) In ADD register value, depending on the value of UartSysClk, + baudrate, BRG register value, and SUB register value, be careful + about the order of multiplier and divider and make sure any + multiplier doesn't exceed 32-bit boundary and any divider doesn't get + down below one(integer 0). + (3) ADD should be always less than SUB. + */ + obj->uart->BRG = UARTSysClk / 16 / baudrate - 1; + + // To use of the fractional baud rate generator, you must write 0xFF to the DIV + // value to yield a denominator value of 256. All other values are not supported. + LPC_SYSCON->FRGCTRL = 0xFF; + + LPC_SYSCON->FRGCTRL |= ( ( ((UARTSysClk / 16) * (0xFF + 1)) / + (baudrate * (obj->uart->BRG + 1)) + ) - (0xFF + 1) ) << 8; + +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { + // 0: 1 stop bits, 1: 2 stop bits + if (stop_bits != 1 && stop_bits != 2) { + error("Invalid stop bits specified"); + } + stop_bits -= 1; + + // 0: 7 data bits ... 2: 9 data bits + if (data_bits < 7 || data_bits > 9) { + error("Invalid number of bits (%d) in serial format, should be 7..9", data_bits); + } + data_bits -= 7; + + int paritysel; + switch (parity) { + case ParityNone: paritysel = 0; break; + case ParityEven: paritysel = 2; break; + case ParityOdd : paritysel = 3; break; + default: + error("Invalid serial parity setting"); + return; + } + + obj->uart->CFG = (data_bits << 2) + | (paritysel << 4) + | (stop_bits << 6); +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint32_t iir, uint32_t index) { + // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling + SerialIrq irq_type; + switch (iir) { + case 1: irq_type = TxIrq; break; + case 2: irq_type = RxIrq; break; + default: return; + } + + if (serial_irq_ids[index] != 0) + irq_handler(serial_irq_ids[index], irq_type); +} + +void uart0_irq() {uart_irq((LPC_USART0->STAT & (1 << 2)) ? 2 : 1, 0);} +void uart1_irq() {uart_irq((LPC_USART1->STAT & (1 << 2)) ? 2 : 1, 1);} +void uart2_irq() {uart_irq((LPC_USART2->STAT & (1 << 2)) ? 2 : 1, 2);} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + switch ((int)obj->uart) { + case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break; + case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break; + case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break; + } + + if (enable) { + obj->uart->INTENSET = (1 << ((irq == RxIrq) ? 0 : 2)); + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + } else { // disable + int all_disabled = 0; + SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); + obj->uart->INTENSET &= ~(1 << ((irq == RxIrq) ? 0 : 2)); + all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0; + if (all_disabled) + NVIC_DisableIRQ(irq_n); + } +} + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ +int serial_getc(serial_t *obj) { + while (!serial_readable(obj)); + return obj->uart->RXDATA; +} + +void serial_putc(serial_t *obj, int c) { + while (!serial_writable(obj)); + obj->uart->TXDATA = c; +} + +int serial_readable(serial_t *obj) { + return obj->uart->STAT & RXRDY; +} + +int serial_writable(serial_t *obj) { + return obj->uart->STAT & TXRDY; +} + +void serial_clear(serial_t *obj) { + // [TODO] +} + +void serial_pinout_tx(PinName tx) { + +} + +void serial_break_set(serial_t *obj) { + obj->uart->CTRL |= TXBRKEN; +} + +void serial_break_clear(serial_t *obj) { + obj->uart->CTRL &= ~TXBRKEN; +} + +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { + const SWM_Map *swm_rts, *swm_cts; + uint32_t regVal_rts, regVal_cts; + + swm_rts = &SWM_UART_RTS[obj->index]; + swm_cts = &SWM_UART_CTS[obj->index]; + regVal_rts = LPC_SWM->PINASSIGN[swm_rts->n] & ~(0xFF << swm_rts->offset); + regVal_cts = LPC_SWM->PINASSIGN[swm_cts->n] & ~(0xFF << swm_cts->offset); + + if (FlowControlNone == type) { + LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset); + LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset); + obj->uart->CFG &= ~CTSEN; + return; + } + if ((FlowControlRTS == type || FlowControlRTSCTS == type) && (rxflow != NC)) { + LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (rxflow << swm_rts->offset); + if (FlowControlRTS == type) { + LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset); + obj->uart->CFG &= ~CTSEN; + } + } + if ((FlowControlCTS == type || FlowControlRTSCTS == type) && (txflow != NC)) { + LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (txflow << swm_cts->offset); + obj->uart->CFG |= CTSEN; + if (FlowControlCTS == type) { + LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset); + } + } +} +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/spi_api.c Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,215 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include <math.h> + +#include "spi_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "error.h" + +static const SWM_Map SWM_SPI_SSEL[] = { + {4, 0}, + {5, 24}, +}; + +static const SWM_Map SWM_SPI_SCLK[] = { + {3, 8}, + {5, 0}, +}; + +static const SWM_Map SWM_SPI_MOSI[] = { + {3, 16}, + {5, 8}, +}; + +static const SWM_Map SWM_SPI_MISO[] = { + {3, 24}, + {5, 16}, +}; + +// bit flags for used SPIs +static unsigned char spi_used = 0; +static int get_available_spi(void) { + int i; + for (i=0; i<2; i++) { + if ((spi_used & (1 << i)) == 0) + return i; + } + return -1; +} + +static inline void spi_disable(spi_t *obj); +static inline void spi_enable(spi_t *obj); + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + int spi_n = get_available_spi(); + if (spi_n == -1) { + error("No available SPI"); + } + + obj->spi_n = spi_n; + spi_used |= (1 << spi_n); + + obj->spi = (spi_n) ? (LPC_SPI0_Type *)(LPC_SPI1_BASE) : (LPC_SPI0_Type *)(LPC_SPI0_BASE); + + const SWM_Map *swm; + uint32_t regVal; + + if (sclk != NC) { + swm = &SWM_SPI_SCLK[obj->spi_n]; + regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); + LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset); + } + + if (mosi != NC) { + swm = &SWM_SPI_MOSI[obj->spi_n]; + regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); + LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset); + } + + if (miso != NC) { + swm = &SWM_SPI_MISO[obj->spi_n]; + regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); + LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset); + } + + if (ssel != NC) { + swm = &SWM_SPI_SSEL[obj->spi_n]; + regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); + LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset); + } + + // clear interrupts + obj->spi->INTENCLR = 0x3f; + + // enable power and clocking + + switch (obj->spi_n) { + case 0: + LPC_SYSCON->SYSAHBCLKCTRL1 |= (0x1<<9); + LPC_SYSCON->PRESETCTRL1 |= (0x1<<9); + LPC_SYSCON->PRESETCTRL1 &= ~(0x1<<9); + break; + case 1: + LPC_SYSCON->SYSAHBCLKCTRL1 |= (0x1<<10); + LPC_SYSCON->PRESETCTRL1 |= (0x1<<10); + LPC_SYSCON->PRESETCTRL1 &= ~(0x1<<10); + break; + } + + // set default format and frequency + if (ssel == NC) { + spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master + } else { + spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave + } + spi_frequency(obj, 1000000); + + // enable the spi channel + spi_enable(obj); +} + +void spi_free(spi_t *obj) {} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + spi_disable(obj); + + if (!(bits >= 1 && bits <= 16) || !(mode >= 0 && mode <= 3)) { + error("SPI format error"); + } + + int polarity = (mode & 0x2) ? 1 : 0; + int phase = (mode & 0x1) ? 1 : 0; + + // set it up + int LEN = bits - 1; // LEN - Data Length + int CPOL = (polarity) ? 1 : 0; // CPOL - Clock Polarity select + int CPHA = (phase) ? 1 : 0; // CPHA - Clock Phase select + + uint32_t tmp = obj->spi->CFG; + tmp &= ~((1 << 5) | (1 << 4) | (1 << 2)); + tmp |= (CPOL << 5) | (CPHA << 4) | ((slave ? 0 : 1) << 2); + obj->spi->CFG = tmp; + + // select frame length + tmp = obj->spi->TXDATCTL; + tmp &= ~(0xf << 24); + tmp |= (LEN << 24); + obj->spi->TXDATCTL = tmp; + + spi_enable(obj); +} + +void spi_frequency(spi_t *obj, int hz) { + spi_disable(obj); + + uint32_t PCLK = SystemCoreClock; + + obj->spi->DIV = PCLK/hz - 1; + obj->spi->DLY = 0; + spi_enable(obj); +} + +static inline void spi_disable(spi_t *obj) { + obj->spi->CFG &= ~(1 << 0); +} + +static inline void spi_enable(spi_t *obj) { + obj->spi->CFG |= (1 << 0); +} + +static inline int spi_readable(spi_t *obj) { + return obj->spi->STAT & (1 << 0); +} + +static inline int spi_writeable(spi_t *obj) { + return obj->spi->STAT & (1 << 1); +} + +static inline void spi_write(spi_t *obj, int value) { + while (!spi_writeable(obj)); + // end of transfer + obj->spi->TXDATCTL |= (1 << 20); + obj->spi->TXDAT = value; +} + +static inline int spi_read(spi_t *obj) { + while (!spi_readable(obj)); + return obj->spi->RXDAT; +} + +static inline int spi_busy(spi_t *obj) { + // checking RXOV(Receiver Overrun interrupt flag) + return obj->spi->STAT & (1 << 2); + } + +int spi_master_write(spi_t *obj, int value) { + spi_write(obj, value); + return spi_read(obj); +} + +int spi_slave_receive(spi_t *obj) { + return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0); +} + +int spi_slave_read(spi_t *obj) { + return obj->spi->RXDAT; +} + +void spi_slave_write(spi_t *obj, int value) { + while (spi_writeable(obj) == 0) ; + obj->spi->TXDAT = value; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/us_ticker.c Thu Feb 20 23:00:08 2014 +0000 @@ -0,0 +1,94 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include <stddef.h> +#include "us_ticker_api.h" +#include "PeripheralNames.h" + +#define US_TICKER_TIMER_IRQn SCT0_IRQn + +int us_ticker_inited = 0; + +void us_ticker_init(void) { + if (us_ticker_inited) return; + us_ticker_inited = 1; + + // Enable the SCT0 clock + LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << 2); + + // Clear peripheral reset the SCT0: + LPC_SYSCON->PRESETCTRL1 |= (1 << 2); + LPC_SYSCON->PRESETCTRL1 &= ~(1 << 2); + + // Unified counter (32 bits) + LPC_SCT0->CONFIG |= 1; + + // halt and clear the counter + LPC_SCT0->CTRL |= (1 << 2) | (1 << 3); + + // System Clock (12)MHz -> us_ticker (1)MHz + LPC_SCT0->CTRL |= ((SystemCoreClock/1000000 - 1) << 5); + + // unhalt the counter: + // - clearing bit 2 of the CTRL register + LPC_SCT0->CTRL &= ~(1 << 2); + + NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); +} + +uint32_t us_ticker_read() { + if (!us_ticker_inited) + us_ticker_init(); + + return LPC_SCT0->COUNT; +} + +void us_ticker_set_interrupt(unsigned int timestamp) { + // halt the counter: + // - setting bit 2 of the CTRL register + LPC_SCT0->CTRL |= (1 << 2); + + // set timestamp in compare register + LPC_SCT0->MATCH0 = timestamp; + + // unhalt the counter: + // - clearing bit 2 of the CTRL register + LPC_SCT0->CTRL &= ~(1 << 2); + + // if events are not enabled, enable them + if (!(LPC_SCT0->EVEN & 0x01)) { + + // comb mode = match only + LPC_SCT0->EV0_CTRL = (1 << 12); + + // ref manual: + // In simple applications that do not + // use states, write 0x01 to this + // register to enable an event + LPC_SCT0->EV0_STATE |= 0x1; + + // enable events + LPC_SCT0->EVEN |= 0x1; + } +} + +void us_ticker_disable_interrupt(void) { + LPC_SCT0->EVEN &= ~1; +} + +void us_ticker_clear_interrupt(void) { + LPC_SCT0->EVFLAG = 1; +}