mbed library sources
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Revision 445:3312ed629f01, committed 2015-01-15
- Comitter:
- mbed_official
- Date:
- Thu Jan 15 19:30:07 2015 +0000
- Parent:
- 444:d80869345ae6
- Child:
- 446:b421ac8a7b41
- Commit message:
- Synchronized with git revision e21c65041d9a718f866ed6438e5791b13f9c6d91
Full URL: https://github.com/mbedmicro/mbed/commit/e21c65041d9a718f866ed6438e5791b13f9c6d91/
Changed in this revision
--- a/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/MK20D5.h Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,5836 +0,0 @@ -/* -** ################################################################### -** Compilers: ARM Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011 -** K20P32M50SF0RM Rev. 1, Oct 2011 -** K20P48M50SF0RM Rev. 1, Oct 2011 -** -** Version: rev. 2.0, 2012-03-19 -** -** Abstract: -** CMSIS Peripheral Access Layer for MK20D5 -** -** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2011-12-15) -** Initial version -** - rev. 2.0 (2012-03-19) -** PDB Peripheral register structure updated. -** DMA Registers and bits for unsupported DMA channels removed. -** -** ################################################################### -*/ - -/** - * @file MK20D5.h - * @version 2.0 - * @date 2012-03-19 - * @brief CMSIS Peripheral Access Layer for MK20D5 - * - * CMSIS Peripheral Access Layer for MK20D5 - */ - -#if !defined(MK20D5_H_) -#define MK20D5_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0200u -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000u - -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -typedef enum IRQn { - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - - /* Device specific interrupts */ - DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */ - DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */ - DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */ - DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */ - DMA_Error_IRQn = 4, /**< DMA error interrupt */ - Reserved21_IRQn = 5, /**< Reserved interrupt 21 */ - FTFL_IRQn = 6, /**< FTFL interrupt */ - Read_Collision_IRQn = 7, /**< Read collision interrupt */ - LVD_LVW_IRQn = 8, /**< Low Voltage Detect, Low Voltage Warning */ - LLW_IRQn = 9, /**< Low Leakage Wakeup */ - Watchdog_IRQn = 10, /**< WDOG interrupt */ - I2C0_IRQn = 11, /**< I2C0 interrupt */ - SPI0_IRQn = 12, /**< SPI0 interrupt */ - I2S0_Tx_IRQn = 13, /**< I2S0 transmit interrupt */ - I2S0_Rx_IRQn = 14, /**< I2S0 receive interrupt */ - UART0_LON_IRQn = 15, /**< UART0 LON interrupt */ - UART0_RX_TX_IRQn = 16, /**< UART0 receive/transmit interrupt */ - UART0_ERR_IRQn = 17, /**< UART0 error interrupt */ - UART1_RX_TX_IRQn = 18, /**< UART1 receive/transmit interrupt */ - UART1_ERR_IRQn = 19, /**< UART1 error interrupt */ - UART2_RX_TX_IRQn = 20, /**< UART2 receive/transmit interrupt */ - UART2_ERR_IRQn = 21, /**< UART2 error interrupt */ - ADC0_IRQn = 22, /**< ADC0 interrupt */ - CMP0_IRQn = 23, /**< CMP0 interrupt */ - CMP1_IRQn = 24, /**< CMP1 interrupt */ - FTM0_IRQn = 25, /**< FTM0 fault, overflow and channels interrupt */ - FTM1_IRQn = 26, /**< FTM1 fault, overflow and channels interrupt */ - CMT_IRQn = 27, /**< CMT interrupt */ - RTC_IRQn = 28, /**< RTC interrupt */ - RTC_Seconds_IRQn = 29, /**< RTC seconds interrupt */ - PIT0_IRQn = 30, /**< PIT timer channel 0 interrupt */ - PIT1_IRQn = 31, /**< PIT timer channel 1 interrupt */ - PIT2_IRQn = 32, /**< PIT timer channel 2 interrupt */ - PIT3_IRQn = 33, /**< PIT timer channel 3 interrupt */ - PDB0_IRQn = 34, /**< PDB0 interrupt */ - USB0_IRQn = 35, /**< USB0 interrupt */ - USBDCD_IRQn = 36, /**< USBDCD interrupt */ - TSI0_IRQn = 37, /**< TSI0 interrupt */ - MCG_IRQn = 38, /**< MCG interrupt */ - LPTimer_IRQn = 39, /**< LPTimer interrupt */ - PORTA_IRQn = 40, /**< Port A interrupt */ - PORTB_IRQn = 41, /**< Port B interrupt */ - PORTC_IRQn = 42, /**< Port C interrupt */ - PORTD_IRQn = 43, /**< Port D interrupt */ - PORTE_IRQn = 44, /**< Port E interrupt */ - SWI_IRQn = 45 /**< Software interrupt */ -} IRQn_Type; - -/** - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M4 Core Configuration - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration - * @{ - */ - -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ - -#include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_MK20D5.h" /* Device specific configuration file */ - -/** - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */ - __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */ - __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */ - __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */ - __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */ - __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */ - __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */ - __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */ - __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */ - __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */ - __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */ - __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */ - __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */ - __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */ - __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */ - __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */ - __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */ - __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */ - __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */ - __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */ - __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */ - __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */ - __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */ - __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK) -#define ADC_SC1_DIFF_MASK 0x20u -#define ADC_SC1_DIFF_SHIFT 5 -#define ADC_SC1_AIEN_MASK 0x40u -#define ADC_SC1_AIEN_SHIFT 6 -#define ADC_SC1_COCO_MASK 0x80u -#define ADC_SC1_COCO_SHIFT 7 -/* CFG1 Bit Fields */ -#define ADC_CFG1_ADICLK_MASK 0x3u -#define ADC_CFG1_ADICLK_SHIFT 0 -#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK) -#define ADC_CFG1_MODE_MASK 0xCu -#define ADC_CFG1_MODE_SHIFT 2 -#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK) -#define ADC_CFG1_ADLSMP_MASK 0x10u -#define ADC_CFG1_ADLSMP_SHIFT 4 -#define ADC_CFG1_ADIV_MASK 0x60u -#define ADC_CFG1_ADIV_SHIFT 5 -#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK) -#define ADC_CFG1_ADLPC_MASK 0x80u -#define ADC_CFG1_ADLPC_SHIFT 7 -/* CFG2 Bit Fields */ -#define ADC_CFG2_ADLSTS_MASK 0x3u -#define ADC_CFG2_ADLSTS_SHIFT 0 -#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK) -#define ADC_CFG2_ADHSC_MASK 0x4u -#define ADC_CFG2_ADHSC_SHIFT 2 -#define ADC_CFG2_ADACKEN_MASK 0x8u -#define ADC_CFG2_ADACKEN_SHIFT 3 -#define ADC_CFG2_MUXSEL_MASK 0x10u -#define ADC_CFG2_MUXSEL_SHIFT 4 -/* R Bit Fields */ -#define ADC_R_D_MASK 0xFFFFu -#define ADC_R_D_SHIFT 0 -#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK) -/* CV1 Bit Fields */ -#define ADC_CV1_CV_MASK 0xFFFFu -#define ADC_CV1_CV_SHIFT 0 -#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK) -/* CV2 Bit Fields */ -#define ADC_CV2_CV_MASK 0xFFFFu -#define ADC_CV2_CV_SHIFT 0 -#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK) -/* SC2 Bit Fields */ -#define ADC_SC2_REFSEL_MASK 0x3u -#define ADC_SC2_REFSEL_SHIFT 0 -#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK) -#define ADC_SC2_DMAEN_MASK 0x4u -#define ADC_SC2_DMAEN_SHIFT 2 -#define ADC_SC2_ACREN_MASK 0x8u -#define ADC_SC2_ACREN_SHIFT 3 -#define ADC_SC2_ACFGT_MASK 0x10u -#define ADC_SC2_ACFGT_SHIFT 4 -#define ADC_SC2_ACFE_MASK 0x20u -#define ADC_SC2_ACFE_SHIFT 5 -#define ADC_SC2_ADTRG_MASK 0x40u -#define ADC_SC2_ADTRG_SHIFT 6 -#define ADC_SC2_ADACT_MASK 0x80u -#define ADC_SC2_ADACT_SHIFT 7 -/* SC3 Bit Fields */ -#define ADC_SC3_AVGS_MASK 0x3u -#define ADC_SC3_AVGS_SHIFT 0 -#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK) -#define ADC_SC3_AVGE_MASK 0x4u -#define ADC_SC3_AVGE_SHIFT 2 -#define ADC_SC3_ADCO_MASK 0x8u -#define ADC_SC3_ADCO_SHIFT 3 -#define ADC_SC3_CALF_MASK 0x40u -#define ADC_SC3_CALF_SHIFT 6 -#define ADC_SC3_CAL_MASK 0x80u -#define ADC_SC3_CAL_SHIFT 7 -/* OFS Bit Fields */ -#define ADC_OFS_OFS_MASK 0xFFFFu -#define ADC_OFS_OFS_SHIFT 0 -#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK) -/* PG Bit Fields */ -#define ADC_PG_PG_MASK 0xFFFFu -#define ADC_PG_PG_SHIFT 0 -#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK) -/* MG Bit Fields */ -#define ADC_MG_MG_MASK 0xFFFFu -#define ADC_MG_MG_SHIFT 0 -#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK) -/* CLPD Bit Fields */ -#define ADC_CLPD_CLPD_MASK 0x3Fu -#define ADC_CLPD_CLPD_SHIFT 0 -#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK) -/* CLPS Bit Fields */ -#define ADC_CLPS_CLPS_MASK 0x3Fu -#define ADC_CLPS_CLPS_SHIFT 0 -#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK) -/* CLP4 Bit Fields */ -#define ADC_CLP4_CLP4_MASK 0x3FFu -#define ADC_CLP4_CLP4_SHIFT 0 -#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK) -/* CLP3 Bit Fields */ -#define ADC_CLP3_CLP3_MASK 0x1FFu -#define ADC_CLP3_CLP3_SHIFT 0 -#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK) -/* CLP2 Bit Fields */ -#define ADC_CLP2_CLP2_MASK 0xFFu -#define ADC_CLP2_CLP2_SHIFT 0 -#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK) -/* CLP1 Bit Fields */ -#define ADC_CLP1_CLP1_MASK 0x7Fu -#define ADC_CLP1_CLP1_SHIFT 0 -#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK) -/* CLP0 Bit Fields */ -#define ADC_CLP0_CLP0_MASK 0x3Fu -#define ADC_CLP0_CLP0_SHIFT 0 -#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK) -/* CLMD Bit Fields */ -#define ADC_CLMD_CLMD_MASK 0x3Fu -#define ADC_CLMD_CLMD_SHIFT 0 -#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK) -/* CLMS Bit Fields */ -#define ADC_CLMS_CLMS_MASK 0x3Fu -#define ADC_CLMS_CLMS_SHIFT 0 -#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK) -/* CLM4 Bit Fields */ -#define ADC_CLM4_CLM4_MASK 0x3FFu -#define ADC_CLM4_CLM4_SHIFT 0 -#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK) -/* CLM3 Bit Fields */ -#define ADC_CLM3_CLM3_MASK 0x1FFu -#define ADC_CLM3_CLM3_SHIFT 0 -#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK) -/* CLM2 Bit Fields */ -#define ADC_CLM2_CLM2_MASK 0xFFu -#define ADC_CLM2_CLM2_SHIFT 0 -#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK) -/* CLM1 Bit Fields */ -#define ADC_CLM1_CLM1_MASK 0x7Fu -#define ADC_CLM1_CLM1_SHIFT 0 -#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK) -/* CLM0 Bit Fields */ -#define ADC_CLM0_CLM0_MASK 0x3Fu -#define ADC_CLM0_CLM0_SHIFT 0 -#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK) - -/** - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -/** Peripheral ADC0 base address */ -#define ADC0_BASE (0x4003B000u) -/** Peripheral ADC0 base pointer */ -#define ADC0 ((ADC_Type *)ADC0_BASE) - -/** - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CMP Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer - * @{ - */ - -/** CMP - Register Layout Typedef */ -typedef struct { - __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ - __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ - __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ - __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ - __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ - __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ -} CMP_Type; - -/* ---------------------------------------------------------------------------- - -- CMP Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup CMP_Register_Masks CMP Register Masks - * @{ - */ - -/* CR0 Bit Fields */ -#define CMP_CR0_HYSTCTR_MASK 0x3u -#define CMP_CR0_HYSTCTR_SHIFT 0 -#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK) -#define CMP_CR0_FILTER_CNT_MASK 0x70u -#define CMP_CR0_FILTER_CNT_SHIFT 4 -#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK) -/* CR1 Bit Fields */ -#define CMP_CR1_EN_MASK 0x1u -#define CMP_CR1_EN_SHIFT 0 -#define CMP_CR1_OPE_MASK 0x2u -#define CMP_CR1_OPE_SHIFT 1 -#define CMP_CR1_COS_MASK 0x4u -#define CMP_CR1_COS_SHIFT 2 -#define CMP_CR1_INV_MASK 0x8u -#define CMP_CR1_INV_SHIFT 3 -#define CMP_CR1_PMODE_MASK 0x10u -#define CMP_CR1_PMODE_SHIFT 4 -#define CMP_CR1_WE_MASK 0x40u -#define CMP_CR1_WE_SHIFT 6 -#define CMP_CR1_SE_MASK 0x80u -#define CMP_CR1_SE_SHIFT 7 -/* FPR Bit Fields */ -#define CMP_FPR_FILT_PER_MASK 0xFFu -#define CMP_FPR_FILT_PER_SHIFT 0 -#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK) -/* SCR Bit Fields */ -#define CMP_SCR_COUT_MASK 0x1u -#define CMP_SCR_COUT_SHIFT 0 -#define CMP_SCR_CFF_MASK 0x2u -#define CMP_SCR_CFF_SHIFT 1 -#define CMP_SCR_CFR_MASK 0x4u -#define CMP_SCR_CFR_SHIFT 2 -#define CMP_SCR_IEF_MASK 0x8u -#define CMP_SCR_IEF_SHIFT 3 -#define CMP_SCR_IER_MASK 0x10u -#define CMP_SCR_IER_SHIFT 4 -#define CMP_SCR_DMAEN_MASK 0x40u -#define CMP_SCR_DMAEN_SHIFT 6 -/* DACCR Bit Fields */ -#define CMP_DACCR_VOSEL_MASK 0x3Fu -#define CMP_DACCR_VOSEL_SHIFT 0 -#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK) -#define CMP_DACCR_VRSEL_MASK 0x40u -#define CMP_DACCR_VRSEL_SHIFT 6 -#define CMP_DACCR_DACEN_MASK 0x80u -#define CMP_DACCR_DACEN_SHIFT 7 -/* MUXCR Bit Fields */ -#define CMP_MUXCR_MSEL_MASK 0x7u -#define CMP_MUXCR_MSEL_SHIFT 0 -#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK) -#define CMP_MUXCR_PSEL_MASK 0x38u -#define CMP_MUXCR_PSEL_SHIFT 3 -#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK) - -/** - * @} - */ /* end of group CMP_Register_Masks */ - - -/* CMP - Peripheral instance base addresses */ -/** Peripheral CMP0 base address */ -#define CMP0_BASE (0x40073000u) -/** Peripheral CMP0 base pointer */ -#define CMP0 ((CMP_Type *)CMP0_BASE) -/** Peripheral CMP1 base address */ -#define CMP1_BASE (0x40073008u) -/** Peripheral CMP1 base pointer */ -#define CMP1 ((CMP_Type *)CMP1_BASE) - -/** - * @} - */ /* end of group CMP_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CMT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer - * @{ - */ - -/** CMT - Register Layout Typedef */ -typedef struct { - __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */ - __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */ - __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */ - __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */ - __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */ - __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */ - __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */ - __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */ - __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */ - __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */ - __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */ - __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */ -} CMT_Type; - -/* ---------------------------------------------------------------------------- - -- CMT Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup CMT_Register_Masks CMT Register Masks - * @{ - */ - -/* CGH1 Bit Fields */ -#define CMT_CGH1_PH_MASK 0xFFu -#define CMT_CGH1_PH_SHIFT 0 -#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK) -/* CGL1 Bit Fields */ -#define CMT_CGL1_PL_MASK 0xFFu -#define CMT_CGL1_PL_SHIFT 0 -#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK) -/* CGH2 Bit Fields */ -#define CMT_CGH2_SH_MASK 0xFFu -#define CMT_CGH2_SH_SHIFT 0 -#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK) -/* CGL2 Bit Fields */ -#define CMT_CGL2_SL_MASK 0xFFu -#define CMT_CGL2_SL_SHIFT 0 -#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK) -/* OC Bit Fields */ -#define CMT_OC_IROPEN_MASK 0x20u -#define CMT_OC_IROPEN_SHIFT 5 -#define CMT_OC_CMTPOL_MASK 0x40u -#define CMT_OC_CMTPOL_SHIFT 6 -#define CMT_OC_IROL_MASK 0x80u -#define CMT_OC_IROL_SHIFT 7 -/* MSC Bit Fields */ -#define CMT_MSC_MCGEN_MASK 0x1u -#define CMT_MSC_MCGEN_SHIFT 0 -#define CMT_MSC_EOCIE_MASK 0x2u -#define CMT_MSC_EOCIE_SHIFT 1 -#define CMT_MSC_FSK_MASK 0x4u -#define CMT_MSC_FSK_SHIFT 2 -#define CMT_MSC_BASE_MASK 0x8u -#define CMT_MSC_BASE_SHIFT 3 -#define CMT_MSC_EXSPC_MASK 0x10u -#define CMT_MSC_EXSPC_SHIFT 4 -#define CMT_MSC_CMTDIV_MASK 0x60u -#define CMT_MSC_CMTDIV_SHIFT 5 -#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK) -#define CMT_MSC_EOCF_MASK 0x80u -#define CMT_MSC_EOCF_SHIFT 7 -/* CMD1 Bit Fields */ -#define CMT_CMD1_MB_MASK 0xFFu -#define CMT_CMD1_MB_SHIFT 0 -#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK) -/* CMD2 Bit Fields */ -#define CMT_CMD2_MB_MASK 0xFFu -#define CMT_CMD2_MB_SHIFT 0 -#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK) -/* CMD3 Bit Fields */ -#define CMT_CMD3_SB_MASK 0xFFu -#define CMT_CMD3_SB_SHIFT 0 -#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK) -/* CMD4 Bit Fields */ -#define CMT_CMD4_SB_MASK 0xFFu -#define CMT_CMD4_SB_SHIFT 0 -#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK) -/* PPS Bit Fields */ -#define CMT_PPS_PPSDIV_MASK 0xFu -#define CMT_PPS_PPSDIV_SHIFT 0 -#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK) -/* DMA Bit Fields */ -#define CMT_DMA_DMA_MASK 0x1u -#define CMT_DMA_DMA_SHIFT 0 - -/** - * @} - */ /* end of group CMT_Register_Masks */ - - -/* CMT - Peripheral instance base addresses */ -/** Peripheral CMT base address */ -#define CMT_BASE (0x40062000u) -/** Peripheral CMT base pointer */ -#define CMT ((CMT_Type *)CMT_BASE) - -/** - * @} - */ /* end of group CMT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - union { /* offset: 0x0 */ - struct { /* offset: 0x0 */ - __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */ - __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */ - } ACCESS16BIT; - __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */ - struct { /* offset: 0x0 */ - __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */ - __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */ - __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */ - __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */ - } ACCESS8BIT; - }; - union { /* offset: 0x4 */ - struct { /* offset: 0x4 */ - __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ - __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ - } GPOLY_ACCESS16BIT; - __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */ - struct { /* offset: 0x4 */ - __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ - __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ - __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ - __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ - } GPOLY_ACCESS8BIT; - }; - union { /* offset: 0x8 */ - __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */ - struct { /* offset: 0x8 */ - uint8_t RESERVED_0[3]; - __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ - } CTRL_ACCESS8BIT; - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/* CRCL Bit Fields */ -#define CRC_CRCL_CRCL_MASK 0xFFFFu -#define CRC_CRCL_CRCL_SHIFT 0 -#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK) -/* CRCH Bit Fields */ -#define CRC_CRCH_CRCH_MASK 0xFFFFu -#define CRC_CRCH_CRCH_SHIFT 0 -#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK) -/* CRC Bit Fields */ -#define CRC_CRC_LL_MASK 0xFFu -#define CRC_CRC_LL_SHIFT 0 -#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK) -#define CRC_CRC_LU_MASK 0xFF00u -#define CRC_CRC_LU_SHIFT 8 -#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK) -#define CRC_CRC_HL_MASK 0xFF0000u -#define CRC_CRC_HL_SHIFT 16 -#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK) -#define CRC_CRC_HU_MASK 0xFF000000u -#define CRC_CRC_HU_SHIFT 24 -#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK) -/* CRCLL Bit Fields */ -#define CRC_CRCLL_CRCLL_MASK 0xFFu -#define CRC_CRCLL_CRCLL_SHIFT 0 -#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK) -/* CRCLU Bit Fields */ -#define CRC_CRCLU_CRCLU_MASK 0xFFu -#define CRC_CRCLU_CRCLU_SHIFT 0 -#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK) -/* CRCHL Bit Fields */ -#define CRC_CRCHL_CRCHL_MASK 0xFFu -#define CRC_CRCHL_CRCHL_SHIFT 0 -#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK) -/* CRCHU Bit Fields */ -#define CRC_CRCHU_CRCHU_MASK 0xFFu -#define CRC_CRCHU_CRCHU_SHIFT 0 -#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK) -/* GPOLYL Bit Fields */ -#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu -#define CRC_GPOLYL_GPOLYL_SHIFT 0 -#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK) -/* GPOLYH Bit Fields */ -#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu -#define CRC_GPOLYH_GPOLYH_SHIFT 0 -#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK) -/* GPOLY Bit Fields */ -#define CRC_GPOLY_LOW_MASK 0xFFFFu -#define CRC_GPOLY_LOW_SHIFT 0 -#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK) -#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u -#define CRC_GPOLY_HIGH_SHIFT 16 -#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK) -/* GPOLYLL Bit Fields */ -#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu -#define CRC_GPOLYLL_GPOLYLL_SHIFT 0 -#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK) -/* GPOLYLU Bit Fields */ -#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu -#define CRC_GPOLYLU_GPOLYLU_SHIFT 0 -#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK) -/* GPOLYHL Bit Fields */ -#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu -#define CRC_GPOLYHL_GPOLYHL_SHIFT 0 -#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK) -/* GPOLYHU Bit Fields */ -#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu -#define CRC_GPOLYHU_GPOLYHU_SHIFT 0 -#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK) -/* CTRL Bit Fields */ -#define CRC_CTRL_TCRC_MASK 0x1000000u -#define CRC_CTRL_TCRC_SHIFT 24 -#define CRC_CTRL_WAS_MASK 0x2000000u -#define CRC_CTRL_WAS_SHIFT 25 -#define CRC_CTRL_FXOR_MASK 0x4000000u -#define CRC_CTRL_FXOR_SHIFT 26 -#define CRC_CTRL_TOTR_MASK 0x30000000u -#define CRC_CTRL_TOTR_SHIFT 28 -#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK) -#define CRC_CTRL_TOT_MASK 0xC0000000u -#define CRC_CTRL_TOT_SHIFT 30 -#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK) -/* CTRLHU Bit Fields */ -#define CRC_CTRLHU_TCRC_MASK 0x1u -#define CRC_CTRLHU_TCRC_SHIFT 0 -#define CRC_CTRLHU_WAS_MASK 0x2u -#define CRC_CTRLHU_WAS_SHIFT 1 -#define CRC_CTRLHU_FXOR_MASK 0x4u -#define CRC_CTRLHU_FXOR_SHIFT 2 -#define CRC_CTRLHU_TOTR_MASK 0x30u -#define CRC_CTRLHU_TOTR_SHIFT 4 -#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK) -#define CRC_CTRLHU_TOT_MASK 0xC0u -#define CRC_CTRLHU_TOT_SHIFT 6 -#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK) - -/** - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -/** Peripheral CRC base address */ -#define CRC_BASE (0x40032000u) -/** Peripheral CRC base pointer */ -#define CRC0 ((CRC_Type *)CRC_BASE) - -/** - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CR; /**< Control Register, offset: 0x0 */ - __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ - uint8_t RESERVED_1[4]; - __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ - __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ - __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ - __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ - __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ - __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ - __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ - __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ - __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ - uint8_t RESERVED_2[4]; - __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ - uint8_t RESERVED_4[4]; - __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ - uint8_t RESERVED_5[200]; - __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ - __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ - __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ - __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ - uint8_t RESERVED_6[3836]; - struct { /* offset: 0x1000, array step: 0x20 */ - __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ - __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ - __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ - union { /* offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */ - }; - __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ - __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ - __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ - union { /* offset: 0x1016, array step: 0x20 */ - __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ - __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ - }; - __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ - __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ - union { /* offset: 0x101E, array step: 0x20 */ - __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ - __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ - }; - } TCD[4]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define DMA_CR_EDBG_MASK 0x2u -#define DMA_CR_EDBG_SHIFT 1 -#define DMA_CR_ERCA_MASK 0x4u -#define DMA_CR_ERCA_SHIFT 2 -#define DMA_CR_HOE_MASK 0x10u -#define DMA_CR_HOE_SHIFT 4 -#define DMA_CR_HALT_MASK 0x20u -#define DMA_CR_HALT_SHIFT 5 -#define DMA_CR_CLM_MASK 0x40u -#define DMA_CR_CLM_SHIFT 6 -#define DMA_CR_EMLM_MASK 0x80u -#define DMA_CR_EMLM_SHIFT 7 -#define DMA_CR_ECX_MASK 0x10000u -#define DMA_CR_ECX_SHIFT 16 -#define DMA_CR_CX_MASK 0x20000u -#define DMA_CR_CX_SHIFT 17 -/* ES Bit Fields */ -#define DMA_ES_DBE_MASK 0x1u -#define DMA_ES_DBE_SHIFT 0 -#define DMA_ES_SBE_MASK 0x2u -#define DMA_ES_SBE_SHIFT 1 -#define DMA_ES_SGE_MASK 0x4u -#define DMA_ES_SGE_SHIFT 2 -#define DMA_ES_NCE_MASK 0x8u -#define DMA_ES_NCE_SHIFT 3 -#define DMA_ES_DOE_MASK 0x10u -#define DMA_ES_DOE_SHIFT 4 -#define DMA_ES_DAE_MASK 0x20u -#define DMA_ES_DAE_SHIFT 5 -#define DMA_ES_SOE_MASK 0x40u -#define DMA_ES_SOE_SHIFT 6 -#define DMA_ES_SAE_MASK 0x80u -#define DMA_ES_SAE_SHIFT 7 -#define DMA_ES_ERRCHN_MASK 0xF00u -#define DMA_ES_ERRCHN_SHIFT 8 -#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK) -#define DMA_ES_CPE_MASK 0x4000u -#define DMA_ES_CPE_SHIFT 14 -#define DMA_ES_ECX_MASK 0x10000u -#define DMA_ES_ECX_SHIFT 16 -#define DMA_ES_VLD_MASK 0x80000000u -#define DMA_ES_VLD_SHIFT 31 -/* ERQ Bit Fields */ -#define DMA_ERQ_ERQ0_MASK 0x1u -#define DMA_ERQ_ERQ0_SHIFT 0 -#define DMA_ERQ_ERQ1_MASK 0x2u -#define DMA_ERQ_ERQ1_SHIFT 1 -#define DMA_ERQ_ERQ2_MASK 0x4u -#define DMA_ERQ_ERQ2_SHIFT 2 -#define DMA_ERQ_ERQ3_MASK 0x8u -#define DMA_ERQ_ERQ3_SHIFT 3 -/* EEI Bit Fields */ -#define DMA_EEI_EEI0_MASK 0x1u -#define DMA_EEI_EEI0_SHIFT 0 -#define DMA_EEI_EEI1_MASK 0x2u -#define DMA_EEI_EEI1_SHIFT 1 -#define DMA_EEI_EEI2_MASK 0x4u -#define DMA_EEI_EEI2_SHIFT 2 -#define DMA_EEI_EEI3_MASK 0x8u -#define DMA_EEI_EEI3_SHIFT 3 -/* CEEI Bit Fields */ -#define DMA_CEEI_CEEI_MASK 0xFu -#define DMA_CEEI_CEEI_SHIFT 0 -#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK) -#define DMA_CEEI_CAEE_MASK 0x40u -#define DMA_CEEI_CAEE_SHIFT 6 -#define DMA_CEEI_NOP_MASK 0x80u -#define DMA_CEEI_NOP_SHIFT 7 -/* SEEI Bit Fields */ -#define DMA_SEEI_SEEI_MASK 0xFu -#define DMA_SEEI_SEEI_SHIFT 0 -#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK) -#define DMA_SEEI_SAEE_MASK 0x40u -#define DMA_SEEI_SAEE_SHIFT 6 -#define DMA_SEEI_NOP_MASK 0x80u -#define DMA_SEEI_NOP_SHIFT 7 -/* CERQ Bit Fields */ -#define DMA_CERQ_CERQ_MASK 0xFu -#define DMA_CERQ_CERQ_SHIFT 0 -#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK) -#define DMA_CERQ_CAER_MASK 0x40u -#define DMA_CERQ_CAER_SHIFT 6 -#define DMA_CERQ_NOP_MASK 0x80u -#define DMA_CERQ_NOP_SHIFT 7 -/* SERQ Bit Fields */ -#define DMA_SERQ_SERQ_MASK 0xFu -#define DMA_SERQ_SERQ_SHIFT 0 -#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK) -#define DMA_SERQ_SAER_MASK 0x40u -#define DMA_SERQ_SAER_SHIFT 6 -#define DMA_SERQ_NOP_MASK 0x80u -#define DMA_SERQ_NOP_SHIFT 7 -/* CDNE Bit Fields */ -#define DMA_CDNE_CDNE_MASK 0xFu -#define DMA_CDNE_CDNE_SHIFT 0 -#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK) -#define DMA_CDNE_CADN_MASK 0x40u -#define DMA_CDNE_CADN_SHIFT 6 -#define DMA_CDNE_NOP_MASK 0x80u -#define DMA_CDNE_NOP_SHIFT 7 -/* SSRT Bit Fields */ -#define DMA_SSRT_SSRT_MASK 0xFu -#define DMA_SSRT_SSRT_SHIFT 0 -#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK) -#define DMA_SSRT_SAST_MASK 0x40u -#define DMA_SSRT_SAST_SHIFT 6 -#define DMA_SSRT_NOP_MASK 0x80u -#define DMA_SSRT_NOP_SHIFT 7 -/* CERR Bit Fields */ -#define DMA_CERR_CERR_MASK 0xFu -#define DMA_CERR_CERR_SHIFT 0 -#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK) -#define DMA_CERR_CAEI_MASK 0x40u -#define DMA_CERR_CAEI_SHIFT 6 -#define DMA_CERR_NOP_MASK 0x80u -#define DMA_CERR_NOP_SHIFT 7 -/* CINT Bit Fields */ -#define DMA_CINT_CINT_MASK 0xFu -#define DMA_CINT_CINT_SHIFT 0 -#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK) -#define DMA_CINT_CAIR_MASK 0x40u -#define DMA_CINT_CAIR_SHIFT 6 -#define DMA_CINT_NOP_MASK 0x80u -#define DMA_CINT_NOP_SHIFT 7 -/* INT Bit Fields */ -#define DMA_INT_INT0_MASK 0x1u -#define DMA_INT_INT0_SHIFT 0 -#define DMA_INT_INT1_MASK 0x2u -#define DMA_INT_INT1_SHIFT 1 -#define DMA_INT_INT2_MASK 0x4u -#define DMA_INT_INT2_SHIFT 2 -#define DMA_INT_INT3_MASK 0x8u -#define DMA_INT_INT3_SHIFT 3 -/* ERR Bit Fields */ -#define DMA_ERR_ERR0_MASK 0x1u -#define DMA_ERR_ERR0_SHIFT 0 -#define DMA_ERR_ERR1_MASK 0x2u -#define DMA_ERR_ERR1_SHIFT 1 -#define DMA_ERR_ERR2_MASK 0x4u -#define DMA_ERR_ERR2_SHIFT 2 -#define DMA_ERR_ERR3_MASK 0x8u -#define DMA_ERR_ERR3_SHIFT 3 -/* HRS Bit Fields */ -#define DMA_HRS_HRS0_MASK 0x1u -#define DMA_HRS_HRS0_SHIFT 0 -#define DMA_HRS_HRS1_MASK 0x2u -#define DMA_HRS_HRS1_SHIFT 1 -#define DMA_HRS_HRS2_MASK 0x4u -#define DMA_HRS_HRS2_SHIFT 2 -#define DMA_HRS_HRS3_MASK 0x8u -#define DMA_HRS_HRS3_SHIFT 3 -/* DCHPRI3 Bit Fields */ -#define DMA_DCHPRI3_CHPRI_MASK 0xFu -#define DMA_DCHPRI3_CHPRI_SHIFT 0 -#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK) -#define DMA_DCHPRI3_DPA_MASK 0x40u -#define DMA_DCHPRI3_DPA_SHIFT 6 -#define DMA_DCHPRI3_ECP_MASK 0x80u -#define DMA_DCHPRI3_ECP_SHIFT 7 -/* DCHPRI2 Bit Fields */ -#define DMA_DCHPRI2_CHPRI_MASK 0xFu -#define DMA_DCHPRI2_CHPRI_SHIFT 0 -#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK) -#define DMA_DCHPRI2_DPA_MASK 0x40u -#define DMA_DCHPRI2_DPA_SHIFT 6 -#define DMA_DCHPRI2_ECP_MASK 0x80u -#define DMA_DCHPRI2_ECP_SHIFT 7 -/* DCHPRI1 Bit Fields */ -#define DMA_DCHPRI1_CHPRI_MASK 0xFu -#define DMA_DCHPRI1_CHPRI_SHIFT 0 -#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK) -#define DMA_DCHPRI1_DPA_MASK 0x40u -#define DMA_DCHPRI1_DPA_SHIFT 6 -#define DMA_DCHPRI1_ECP_MASK 0x80u -#define DMA_DCHPRI1_ECP_SHIFT 7 -/* DCHPRI0 Bit Fields */ -#define DMA_DCHPRI0_CHPRI_MASK 0xFu -#define DMA_DCHPRI0_CHPRI_SHIFT 0 -#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK) -#define DMA_DCHPRI0_DPA_MASK 0x40u -#define DMA_DCHPRI0_DPA_SHIFT 6 -#define DMA_DCHPRI0_ECP_MASK 0x80u -#define DMA_DCHPRI0_ECP_SHIFT 7 -/* SADDR Bit Fields */ -#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu -#define DMA_SADDR_SADDR_SHIFT 0 -#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK) -/* SOFF Bit Fields */ -#define DMA_SOFF_SOFF_MASK 0xFFFFu -#define DMA_SOFF_SOFF_SHIFT 0 -#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK) -/* ATTR Bit Fields */ -#define DMA_ATTR_DSIZE_MASK 0x7u -#define DMA_ATTR_DSIZE_SHIFT 0 -#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK) -#define DMA_ATTR_DMOD_MASK 0xF8u -#define DMA_ATTR_DMOD_SHIFT 3 -#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK) -#define DMA_ATTR_SSIZE_MASK 0x700u -#define DMA_ATTR_SSIZE_SHIFT 8 -#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK) -#define DMA_ATTR_SMOD_MASK 0xF800u -#define DMA_ATTR_SMOD_SHIFT 11 -#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK) -/* NBYTES_MLNO Bit Fields */ -#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu -#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0 -#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK) -/* NBYTES_MLOFFNO Bit Fields */ -#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu -#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0 -#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK) -#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u -#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30 -#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u -#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31 -/* NBYTES_MLOFFYES Bit Fields */ -#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu -#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0 -#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK) -#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u -#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10 -#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK) -#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u -#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30 -#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u -#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31 -/* SLAST Bit Fields */ -#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu -#define DMA_SLAST_SLAST_SHIFT 0 -#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK) -/* DADDR Bit Fields */ -#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu -#define DMA_DADDR_DADDR_SHIFT 0 -#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK) -/* DOFF Bit Fields */ -#define DMA_DOFF_DOFF_MASK 0xFFFFu -#define DMA_DOFF_DOFF_SHIFT 0 -#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK) -/* CITER_ELINKNO Bit Fields */ -#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu -#define DMA_CITER_ELINKNO_CITER_SHIFT 0 -#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK) -#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u -#define DMA_CITER_ELINKNO_ELINK_SHIFT 15 -/* CITER_ELINKYES Bit Fields */ -#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu -#define DMA_CITER_ELINKYES_CITER_SHIFT 0 -#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK) -#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u -#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9 -#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK) -#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u -#define DMA_CITER_ELINKYES_ELINK_SHIFT 15 -/* DLAST_SGA Bit Fields */ -#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu -#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0 -#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK) -/* CSR Bit Fields */ -#define DMA_CSR_START_MASK 0x1u -#define DMA_CSR_START_SHIFT 0 -#define DMA_CSR_INTMAJOR_MASK 0x2u -#define DMA_CSR_INTMAJOR_SHIFT 1 -#define DMA_CSR_INTHALF_MASK 0x4u -#define DMA_CSR_INTHALF_SHIFT 2 -#define DMA_CSR_DREQ_MASK 0x8u -#define DMA_CSR_DREQ_SHIFT 3 -#define DMA_CSR_ESG_MASK 0x10u -#define DMA_CSR_ESG_SHIFT 4 -#define DMA_CSR_MAJORELINK_MASK 0x20u -#define DMA_CSR_MAJORELINK_SHIFT 5 -#define DMA_CSR_ACTIVE_MASK 0x40u -#define DMA_CSR_ACTIVE_SHIFT 6 -#define DMA_CSR_DONE_MASK 0x80u -#define DMA_CSR_DONE_SHIFT 7 -#define DMA_CSR_MAJORLINKCH_MASK 0xF00u -#define DMA_CSR_MAJORLINKCH_SHIFT 8 -#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK) -#define DMA_CSR_BWC_MASK 0xC000u -#define DMA_CSR_BWC_SHIFT 14 -#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK) -/* BITER_ELINKNO Bit Fields */ -#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu -#define DMA_BITER_ELINKNO_BITER_SHIFT 0 -#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK) -#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u -#define DMA_BITER_ELINKNO_ELINK_SHIFT 15 -/* BITER_ELINKYES Bit Fields */ -#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu -#define DMA_BITER_ELINKYES_BITER_SHIFT 0 -#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK) -#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u -#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9 -#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK) -#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u -#define DMA_BITER_ELINKYES_ELINK_SHIFT 15 - -/** - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -/** Peripheral DMA base address */ -#define DMA_BASE (0x40008000u) -/** Peripheral DMA base pointer */ -#define DMA0 ((DMA_Type *)DMA_BASE) - -/** - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMAMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer - * @{ - */ - -/** DMAMUX - Register Layout Typedef */ -typedef struct { - __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */ -} DMAMUX_Type; - -/* ---------------------------------------------------------------------------- - -- DMAMUX Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks - * @{ - */ - -/* CHCFG Bit Fields */ -#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu -#define DMAMUX_CHCFG_SOURCE_SHIFT 0 -#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK) -#define DMAMUX_CHCFG_TRIG_MASK 0x40u -#define DMAMUX_CHCFG_TRIG_SHIFT 6 -#define DMAMUX_CHCFG_ENBL_MASK 0x80u -#define DMAMUX_CHCFG_ENBL_SHIFT 7 - -/** - * @} - */ /* end of group DMAMUX_Register_Masks */ - - -/* DMAMUX - Peripheral instance base addresses */ -/** Peripheral DMAMUX base address */ -#define DMAMUX_BASE (0x40021000u) -/** Peripheral DMAMUX base pointer */ -#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) - -/** - * @} - */ /* end of group DMAMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- EWM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer - * @{ - */ - -/** EWM - Register Layout Typedef */ -typedef struct { - __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ - __O uint8_t SERV; /**< Service Register, offset: 0x1 */ - __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ - __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ -} EWM_Type; - -/* ---------------------------------------------------------------------------- - -- EWM Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup EWM_Register_Masks EWM Register Masks - * @{ - */ - -/* CTRL Bit Fields */ -#define EWM_CTRL_EWMEN_MASK 0x1u -#define EWM_CTRL_EWMEN_SHIFT 0 -#define EWM_CTRL_ASSIN_MASK 0x2u -#define EWM_CTRL_ASSIN_SHIFT 1 -#define EWM_CTRL_INEN_MASK 0x4u -#define EWM_CTRL_INEN_SHIFT 2 -#define EWM_CTRL_INTEN_MASK 0x8u -#define EWM_CTRL_INTEN_SHIFT 3 -/* SERV Bit Fields */ -#define EWM_SERV_SERVICE_MASK 0xFFu -#define EWM_SERV_SERVICE_SHIFT 0 -#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK) -/* CMPL Bit Fields */ -#define EWM_CMPL_COMPAREL_MASK 0xFFu -#define EWM_CMPL_COMPAREL_SHIFT 0 -#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK) -/* CMPH Bit Fields */ -#define EWM_CMPH_COMPAREH_MASK 0xFFu -#define EWM_CMPH_COMPAREH_SHIFT 0 -#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK) - -/** - * @} - */ /* end of group EWM_Register_Masks */ - - -/* EWM - Peripheral instance base addresses */ -/** Peripheral EWM base address */ -#define EWM_BASE (0x40061000u) -/** Peripheral EWM base pointer */ -#define EWM ((EWM_Type *)EWM_BASE) - -/** - * @} - */ /* end of group EWM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer - * @{ - */ - -/** FMC - Register Layout Typedef */ -typedef struct { - __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */ - __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */ - uint8_t RESERVED_0[248]; - struct { /* offset: 0x100, array step: 0x20 */ - __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */ - uint8_t RESERVED_0[24]; - } TAG_WAY[4]; - uint8_t RESERVED_1[132]; - struct { /* offset: 0x204, array step: 0x8 */ - __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */ - uint8_t RESERVED_0[4]; - } DATAW0S[2]; - uint8_t RESERVED_2[48]; - struct { /* offset: 0x244, array step: 0x8 */ - __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */ - uint8_t RESERVED_0[4]; - } DATAW1S[2]; - uint8_t RESERVED_3[48]; - struct { /* offset: 0x284, array step: 0x8 */ - __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */ - uint8_t RESERVED_0[4]; - } DATAW2S[2]; - uint8_t RESERVED_4[48]; - struct { /* offset: 0x2C4, array step: 0x8 */ - __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */ - uint8_t RESERVED_0[4]; - } DATAW3S[2]; -} FMC_Type; - -/* ---------------------------------------------------------------------------- - -- FMC Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup FMC_Register_Masks FMC Register Masks - * @{ - */ - -/* PFAPR Bit Fields */ -#define FMC_PFAPR_M0AP_MASK 0x3u -#define FMC_PFAPR_M0AP_SHIFT 0 -#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK) -#define FMC_PFAPR_M1AP_MASK 0xCu -#define FMC_PFAPR_M1AP_SHIFT 2 -#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK) -#define FMC_PFAPR_M2AP_MASK 0x30u -#define FMC_PFAPR_M2AP_SHIFT 4 -#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK) -#define FMC_PFAPR_M3AP_MASK 0xC0u -#define FMC_PFAPR_M3AP_SHIFT 6 -#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK) -#define FMC_PFAPR_M0PFD_MASK 0x10000u -#define FMC_PFAPR_M0PFD_SHIFT 16 -#define FMC_PFAPR_M1PFD_MASK 0x20000u -#define FMC_PFAPR_M1PFD_SHIFT 17 -#define FMC_PFAPR_M2PFD_MASK 0x40000u -#define FMC_PFAPR_M2PFD_SHIFT 18 -#define FMC_PFAPR_M3PFD_MASK 0x80000u -#define FMC_PFAPR_M3PFD_SHIFT 19 -/* PFB0CR Bit Fields */ -#define FMC_PFB0CR_B0SEBE_MASK 0x1u -#define FMC_PFB0CR_B0SEBE_SHIFT 0 -#define FMC_PFB0CR_B0IPE_MASK 0x2u -#define FMC_PFB0CR_B0IPE_SHIFT 1 -#define FMC_PFB0CR_B0DPE_MASK 0x4u -#define FMC_PFB0CR_B0DPE_SHIFT 2 -#define FMC_PFB0CR_B0ICE_MASK 0x8u -#define FMC_PFB0CR_B0ICE_SHIFT 3 -#define FMC_PFB0CR_B0DCE_MASK 0x10u -#define FMC_PFB0CR_B0DCE_SHIFT 4 -#define FMC_PFB0CR_CRC_MASK 0xE0u -#define FMC_PFB0CR_CRC_SHIFT 5 -#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK) -#define FMC_PFB0CR_B0MW_MASK 0x60000u -#define FMC_PFB0CR_B0MW_SHIFT 17 -#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK) -#define FMC_PFB0CR_S_B_INV_MASK 0x80000u -#define FMC_PFB0CR_S_B_INV_SHIFT 19 -#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u -#define FMC_PFB0CR_CINV_WAY_SHIFT 20 -#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK) -#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u -#define FMC_PFB0CR_CLCK_WAY_SHIFT 24 -#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK) -#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u -#define FMC_PFB0CR_B0RWSC_SHIFT 28 -#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK) -/* TAGVD Bit Fields */ -#define FMC_TAGVD_valid_MASK 0x1u -#define FMC_TAGVD_valid_SHIFT 0 -#define FMC_TAGVD_tag_MASK 0x7FFC0u -#define FMC_TAGVD_tag_SHIFT 6 -#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK) -/* DATAW0S Bit Fields */ -#define FMC_DATAW0S_data_MASK 0xFFFFFFFFu -#define FMC_DATAW0S_data_SHIFT 0 -#define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK) -/* DATAW1S Bit Fields */ -#define FMC_DATAW1S_data_MASK 0xFFFFFFFFu -#define FMC_DATAW1S_data_SHIFT 0 -#define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK) -/* DATAW2S Bit Fields */ -#define FMC_DATAW2S_data_MASK 0xFFFFFFFFu -#define FMC_DATAW2S_data_SHIFT 0 -#define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK) -/* DATAW3S Bit Fields */ -#define FMC_DATAW3S_data_MASK 0xFFFFFFFFu -#define FMC_DATAW3S_data_SHIFT 0 -#define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK) - -/** - * @} - */ /* end of group FMC_Register_Masks */ - - -/* FMC - Peripheral instance base addresses */ -/** Peripheral FMC base address */ -#define FMC_BASE (0x4001F000u) -/** Peripheral FMC base pointer */ -#define FMC ((FMC_Type *)FMC_BASE) - -/** - * @} - */ /* end of group FMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FTFL Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer - * @{ - */ - -/** FTFL - Register Layout Typedef */ -typedef struct { - __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ - __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ - __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ - __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ - __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ - __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ - __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ - __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ - __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ - __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ - __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ - __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ - __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ - __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ - __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ - __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ - __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ - __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ - __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ - __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ - uint8_t RESERVED_0[2]; - __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */ - __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */ -} FTFL_Type; - -/* ---------------------------------------------------------------------------- - -- FTFL Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup FTFL_Register_Masks FTFL Register Masks - * @{ - */ - -/* FSTAT Bit Fields */ -#define FTFL_FSTAT_MGSTAT0_MASK 0x1u -#define FTFL_FSTAT_MGSTAT0_SHIFT 0 -#define FTFL_FSTAT_FPVIOL_MASK 0x10u -#define FTFL_FSTAT_FPVIOL_SHIFT 4 -#define FTFL_FSTAT_ACCERR_MASK 0x20u -#define FTFL_FSTAT_ACCERR_SHIFT 5 -#define FTFL_FSTAT_RDCOLERR_MASK 0x40u -#define FTFL_FSTAT_RDCOLERR_SHIFT 6 -#define FTFL_FSTAT_CCIF_MASK 0x80u -#define FTFL_FSTAT_CCIF_SHIFT 7 -/* FCNFG Bit Fields */ -#define FTFL_FCNFG_EEERDY_MASK 0x1u -#define FTFL_FCNFG_EEERDY_SHIFT 0 -#define FTFL_FCNFG_RAMRDY_MASK 0x2u -#define FTFL_FCNFG_RAMRDY_SHIFT 1 -#define FTFL_FCNFG_PFLSH_MASK 0x4u -#define FTFL_FCNFG_PFLSH_SHIFT 2 -#define FTFL_FCNFG_ERSSUSP_MASK 0x10u -#define FTFL_FCNFG_ERSSUSP_SHIFT 4 -#define FTFL_FCNFG_ERSAREQ_MASK 0x20u -#define FTFL_FCNFG_ERSAREQ_SHIFT 5 -#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u -#define FTFL_FCNFG_RDCOLLIE_SHIFT 6 -#define FTFL_FCNFG_CCIE_MASK 0x80u -#define FTFL_FCNFG_CCIE_SHIFT 7 -/* FSEC Bit Fields */ -#define FTFL_FSEC_SEC_MASK 0x3u -#define FTFL_FSEC_SEC_SHIFT 0 -#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK) -#define FTFL_FSEC_FSLACC_MASK 0xCu -#define FTFL_FSEC_FSLACC_SHIFT 2 -#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK) -#define FTFL_FSEC_MEEN_MASK 0x30u -#define FTFL_FSEC_MEEN_SHIFT 4 -#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK) -#define FTFL_FSEC_KEYEN_MASK 0xC0u -#define FTFL_FSEC_KEYEN_SHIFT 6 -#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK) -/* FOPT Bit Fields */ -#define FTFL_FOPT_OPT_MASK 0xFFu -#define FTFL_FOPT_OPT_SHIFT 0 -#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK) -/* FCCOB3 Bit Fields */ -#define FTFL_FCCOB3_CCOBn_MASK 0xFFu -#define FTFL_FCCOB3_CCOBn_SHIFT 0 -#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK) -/* FCCOB2 Bit Fields */ -#define FTFL_FCCOB2_CCOBn_MASK 0xFFu -#define FTFL_FCCOB2_CCOBn_SHIFT 0 -#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK) -/* FCCOB1 Bit Fields */ -#define FTFL_FCCOB1_CCOBn_MASK 0xFFu -#define FTFL_FCCOB1_CCOBn_SHIFT 0 -#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK) -/* FCCOB0 Bit Fields */ -#define FTFL_FCCOB0_CCOBn_MASK 0xFFu -#define FTFL_FCCOB0_CCOBn_SHIFT 0 -#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK) -/* FCCOB7 Bit Fields */ -#define FTFL_FCCOB7_CCOBn_MASK 0xFFu -#define FTFL_FCCOB7_CCOBn_SHIFT 0 -#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK) -/* FCCOB6 Bit Fields */ -#define FTFL_FCCOB6_CCOBn_MASK 0xFFu -#define FTFL_FCCOB6_CCOBn_SHIFT 0 -#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK) -/* FCCOB5 Bit Fields */ -#define FTFL_FCCOB5_CCOBn_MASK 0xFFu -#define FTFL_FCCOB5_CCOBn_SHIFT 0 -#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK) -/* FCCOB4 Bit Fields */ -#define FTFL_FCCOB4_CCOBn_MASK 0xFFu -#define FTFL_FCCOB4_CCOBn_SHIFT 0 -#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK) -/* FCCOBB Bit Fields */ -#define FTFL_FCCOBB_CCOBn_MASK 0xFFu -#define FTFL_FCCOBB_CCOBn_SHIFT 0 -#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK) -/* FCCOBA Bit Fields */ -#define FTFL_FCCOBA_CCOBn_MASK 0xFFu -#define FTFL_FCCOBA_CCOBn_SHIFT 0 -#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK) -/* FCCOB9 Bit Fields */ -#define FTFL_FCCOB9_CCOBn_MASK 0xFFu -#define FTFL_FCCOB9_CCOBn_SHIFT 0 -#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK) -/* FCCOB8 Bit Fields */ -#define FTFL_FCCOB8_CCOBn_MASK 0xFFu -#define FTFL_FCCOB8_CCOBn_SHIFT 0 -#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK) -/* FPROT3 Bit Fields */ -#define FTFL_FPROT3_PROT_MASK 0xFFu -#define FTFL_FPROT3_PROT_SHIFT 0 -#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK) -/* FPROT2 Bit Fields */ -#define FTFL_FPROT2_PROT_MASK 0xFFu -#define FTFL_FPROT2_PROT_SHIFT 0 -#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK) -/* FPROT1 Bit Fields */ -#define FTFL_FPROT1_PROT_MASK 0xFFu -#define FTFL_FPROT1_PROT_SHIFT 0 -#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK) -/* FPROT0 Bit Fields */ -#define FTFL_FPROT0_PROT_MASK 0xFFu -#define FTFL_FPROT0_PROT_SHIFT 0 -#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK) -/* FEPROT Bit Fields */ -#define FTFL_FEPROT_EPROT_MASK 0xFFu -#define FTFL_FEPROT_EPROT_SHIFT 0 -#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK) -/* FDPROT Bit Fields */ -#define FTFL_FDPROT_DPROT_MASK 0xFFu -#define FTFL_FDPROT_DPROT_SHIFT 0 -#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK) - -/** - * @} - */ /* end of group FTFL_Register_Masks */ - - -/* FTFL - Peripheral instance base addresses */ -/** Peripheral FTFL base address */ -#define FTFL_BASE (0x40020000u) -/** Peripheral FTFL base pointer */ -#define FTFL ((FTFL_Type *)FTFL_BASE) - -/** - * @} - */ /* end of group FTFL_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FTM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer - * @{ - */ - -/** FTM - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ - __IO uint32_t CNT; /**< Counter, offset: 0x4 */ - __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ - struct { /* offset: 0xC, array step: 0x8 */ - __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ - __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ - } CONTROLS[8]; - __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ - __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ - __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ - __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ - __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */ - __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ - __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */ - __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ - __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ - __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ - __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ - __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ - __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ - __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */ - __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ - __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ - __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ - __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ - __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ - __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ -} FTM_Type; - -/* ---------------------------------------------------------------------------- - -- FTM Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup FTM_Register_Masks FTM Register Masks - * @{ - */ - -/* SC Bit Fields */ -#define FTM_SC_PS_MASK 0x7u -#define FTM_SC_PS_SHIFT 0 -#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK) -#define FTM_SC_CLKS_MASK 0x18u -#define FTM_SC_CLKS_SHIFT 3 -#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK) -#define FTM_SC_CPWMS_MASK 0x20u -#define FTM_SC_CPWMS_SHIFT 5 -#define FTM_SC_TOIE_MASK 0x40u -#define FTM_SC_TOIE_SHIFT 6 -#define FTM_SC_TOF_MASK 0x80u -#define FTM_SC_TOF_SHIFT 7 -/* CNT Bit Fields */ -#define FTM_CNT_COUNT_MASK 0xFFFFu -#define FTM_CNT_COUNT_SHIFT 0 -#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK) -/* MOD Bit Fields */ -#define FTM_MOD_MOD_MASK 0xFFFFu -#define FTM_MOD_MOD_SHIFT 0 -#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK) -/* CnSC Bit Fields */ -#define FTM_CnSC_DMA_MASK 0x1u -#define FTM_CnSC_DMA_SHIFT 0 -#define FTM_CnSC_ELSA_MASK 0x4u -#define FTM_CnSC_ELSA_SHIFT 2 -#define FTM_CnSC_ELSB_MASK 0x8u -#define FTM_CnSC_ELSB_SHIFT 3 -#define FTM_CnSC_MSA_MASK 0x10u -#define FTM_CnSC_MSA_SHIFT 4 -#define FTM_CnSC_MSB_MASK 0x20u -#define FTM_CnSC_MSB_SHIFT 5 -#define FTM_CnSC_CHIE_MASK 0x40u -#define FTM_CnSC_CHIE_SHIFT 6 -#define FTM_CnSC_CHF_MASK 0x80u -#define FTM_CnSC_CHF_SHIFT 7 -/* CnV Bit Fields */ -#define FTM_CnV_VAL_MASK 0xFFFFu -#define FTM_CnV_VAL_SHIFT 0 -#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK) -/* CNTIN Bit Fields */ -#define FTM_CNTIN_INIT_MASK 0xFFFFu -#define FTM_CNTIN_INIT_SHIFT 0 -#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK) -/* STATUS Bit Fields */ -#define FTM_STATUS_CH0F_MASK 0x1u -#define FTM_STATUS_CH0F_SHIFT 0 -#define FTM_STATUS_CH1F_MASK 0x2u -#define FTM_STATUS_CH1F_SHIFT 1 -#define FTM_STATUS_CH2F_MASK 0x4u -#define FTM_STATUS_CH2F_SHIFT 2 -#define FTM_STATUS_CH3F_MASK 0x8u -#define FTM_STATUS_CH3F_SHIFT 3 -#define FTM_STATUS_CH4F_MASK 0x10u -#define FTM_STATUS_CH4F_SHIFT 4 -#define FTM_STATUS_CH5F_MASK 0x20u -#define FTM_STATUS_CH5F_SHIFT 5 -#define FTM_STATUS_CH6F_MASK 0x40u -#define FTM_STATUS_CH6F_SHIFT 6 -#define FTM_STATUS_CH7F_MASK 0x80u -#define FTM_STATUS_CH7F_SHIFT 7 -/* MODE Bit Fields */ -#define FTM_MODE_FTMEN_MASK 0x1u -#define FTM_MODE_FTMEN_SHIFT 0 -#define FTM_MODE_INIT_MASK 0x2u -#define FTM_MODE_INIT_SHIFT 1 -#define FTM_MODE_WPDIS_MASK 0x4u -#define FTM_MODE_WPDIS_SHIFT 2 -#define FTM_MODE_PWMSYNC_MASK 0x8u -#define FTM_MODE_PWMSYNC_SHIFT 3 -#define FTM_MODE_CAPTEST_MASK 0x10u -#define FTM_MODE_CAPTEST_SHIFT 4 -#define FTM_MODE_FAULTM_MASK 0x60u -#define FTM_MODE_FAULTM_SHIFT 5 -#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK) -#define FTM_MODE_FAULTIE_MASK 0x80u -#define FTM_MODE_FAULTIE_SHIFT 7 -/* SYNC Bit Fields */ -#define FTM_SYNC_CNTMIN_MASK 0x1u -#define FTM_SYNC_CNTMIN_SHIFT 0 -#define FTM_SYNC_CNTMAX_MASK 0x2u -#define FTM_SYNC_CNTMAX_SHIFT 1 -#define FTM_SYNC_REINIT_MASK 0x4u -#define FTM_SYNC_REINIT_SHIFT 2 -#define FTM_SYNC_SYNCHOM_MASK 0x8u -#define FTM_SYNC_SYNCHOM_SHIFT 3 -#define FTM_SYNC_TRIG0_MASK 0x10u -#define FTM_SYNC_TRIG0_SHIFT 4 -#define FTM_SYNC_TRIG1_MASK 0x20u -#define FTM_SYNC_TRIG1_SHIFT 5 -#define FTM_SYNC_TRIG2_MASK 0x40u -#define FTM_SYNC_TRIG2_SHIFT 6 -#define FTM_SYNC_SWSYNC_MASK 0x80u -#define FTM_SYNC_SWSYNC_SHIFT 7 -/* OUTINIT Bit Fields */ -#define FTM_OUTINIT_CH0OI_MASK 0x1u -#define FTM_OUTINIT_CH0OI_SHIFT 0 -#define FTM_OUTINIT_CH1OI_MASK 0x2u -#define FTM_OUTINIT_CH1OI_SHIFT 1 -#define FTM_OUTINIT_CH2OI_MASK 0x4u -#define FTM_OUTINIT_CH2OI_SHIFT 2 -#define FTM_OUTINIT_CH3OI_MASK 0x8u -#define FTM_OUTINIT_CH3OI_SHIFT 3 -#define FTM_OUTINIT_CH4OI_MASK 0x10u -#define FTM_OUTINIT_CH4OI_SHIFT 4 -#define FTM_OUTINIT_CH5OI_MASK 0x20u -#define FTM_OUTINIT_CH5OI_SHIFT 5 -#define FTM_OUTINIT_CH6OI_MASK 0x40u -#define FTM_OUTINIT_CH6OI_SHIFT 6 -#define FTM_OUTINIT_CH7OI_MASK 0x80u -#define FTM_OUTINIT_CH7OI_SHIFT 7 -/* OUTMASK Bit Fields */ -#define FTM_OUTMASK_CH0OM_MASK 0x1u -#define FTM_OUTMASK_CH0OM_SHIFT 0 -#define FTM_OUTMASK_CH1OM_MASK 0x2u -#define FTM_OUTMASK_CH1OM_SHIFT 1 -#define FTM_OUTMASK_CH2OM_MASK 0x4u -#define FTM_OUTMASK_CH2OM_SHIFT 2 -#define FTM_OUTMASK_CH3OM_MASK 0x8u -#define FTM_OUTMASK_CH3OM_SHIFT 3 -#define FTM_OUTMASK_CH4OM_MASK 0x10u -#define FTM_OUTMASK_CH4OM_SHIFT 4 -#define FTM_OUTMASK_CH5OM_MASK 0x20u -#define FTM_OUTMASK_CH5OM_SHIFT 5 -#define FTM_OUTMASK_CH6OM_MASK 0x40u -#define FTM_OUTMASK_CH6OM_SHIFT 6 -#define FTM_OUTMASK_CH7OM_MASK 0x80u -#define FTM_OUTMASK_CH7OM_SHIFT 7 -/* COMBINE Bit Fields */ -#define FTM_COMBINE_COMBINE0_MASK 0x1u -#define FTM_COMBINE_COMBINE0_SHIFT 0 -#define FTM_COMBINE_COMP0_MASK 0x2u -#define FTM_COMBINE_COMP0_SHIFT 1 -#define FTM_COMBINE_DECAPEN0_MASK 0x4u -#define FTM_COMBINE_DECAPEN0_SHIFT 2 -#define FTM_COMBINE_DECAP0_MASK 0x8u -#define FTM_COMBINE_DECAP0_SHIFT 3 -#define FTM_COMBINE_DTEN0_MASK 0x10u -#define FTM_COMBINE_DTEN0_SHIFT 4 -#define FTM_COMBINE_SYNCEN0_MASK 0x20u -#define FTM_COMBINE_SYNCEN0_SHIFT 5 -#define FTM_COMBINE_FAULTEN0_MASK 0x40u -#define FTM_COMBINE_FAULTEN0_SHIFT 6 -#define FTM_COMBINE_COMBINE1_MASK 0x100u -#define FTM_COMBINE_COMBINE1_SHIFT 8 -#define FTM_COMBINE_COMP1_MASK 0x200u -#define FTM_COMBINE_COMP1_SHIFT 9 -#define FTM_COMBINE_DECAPEN1_MASK 0x400u -#define FTM_COMBINE_DECAPEN1_SHIFT 10 -#define FTM_COMBINE_DECAP1_MASK 0x800u -#define FTM_COMBINE_DECAP1_SHIFT 11 -#define FTM_COMBINE_DTEN1_MASK 0x1000u -#define FTM_COMBINE_DTEN1_SHIFT 12 -#define FTM_COMBINE_SYNCEN1_MASK 0x2000u -#define FTM_COMBINE_SYNCEN1_SHIFT 13 -#define FTM_COMBINE_FAULTEN1_MASK 0x4000u -#define FTM_COMBINE_FAULTEN1_SHIFT 14 -#define FTM_COMBINE_COMBINE2_MASK 0x10000u -#define FTM_COMBINE_COMBINE2_SHIFT 16 -#define FTM_COMBINE_COMP2_MASK 0x20000u -#define FTM_COMBINE_COMP2_SHIFT 17 -#define FTM_COMBINE_DECAPEN2_MASK 0x40000u -#define FTM_COMBINE_DECAPEN2_SHIFT 18 -#define FTM_COMBINE_DECAP2_MASK 0x80000u -#define FTM_COMBINE_DECAP2_SHIFT 19 -#define FTM_COMBINE_DTEN2_MASK 0x100000u -#define FTM_COMBINE_DTEN2_SHIFT 20 -#define FTM_COMBINE_SYNCEN2_MASK 0x200000u -#define FTM_COMBINE_SYNCEN2_SHIFT 21 -#define FTM_COMBINE_FAULTEN2_MASK 0x400000u -#define FTM_COMBINE_FAULTEN2_SHIFT 22 -#define FTM_COMBINE_COMBINE3_MASK 0x1000000u -#define FTM_COMBINE_COMBINE3_SHIFT 24 -#define FTM_COMBINE_COMP3_MASK 0x2000000u -#define FTM_COMBINE_COMP3_SHIFT 25 -#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u -#define FTM_COMBINE_DECAPEN3_SHIFT 26 -#define FTM_COMBINE_DECAP3_MASK 0x8000000u -#define FTM_COMBINE_DECAP3_SHIFT 27 -#define FTM_COMBINE_DTEN3_MASK 0x10000000u -#define FTM_COMBINE_DTEN3_SHIFT 28 -#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u -#define FTM_COMBINE_SYNCEN3_SHIFT 29 -#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u -#define FTM_COMBINE_FAULTEN3_SHIFT 30 -/* DEADTIME Bit Fields */ -#define FTM_DEADTIME_DTVAL_MASK 0x3Fu -#define FTM_DEADTIME_DTVAL_SHIFT 0 -#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK) -#define FTM_DEADTIME_DTPS_MASK 0xC0u -#define FTM_DEADTIME_DTPS_SHIFT 6 -#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK) -/* EXTTRIG Bit Fields */ -#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u -#define FTM_EXTTRIG_CH2TRIG_SHIFT 0 -#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u -#define FTM_EXTTRIG_CH3TRIG_SHIFT 1 -#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u -#define FTM_EXTTRIG_CH4TRIG_SHIFT 2 -#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u -#define FTM_EXTTRIG_CH5TRIG_SHIFT 3 -#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u -#define FTM_EXTTRIG_CH0TRIG_SHIFT 4 -#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u -#define FTM_EXTTRIG_CH1TRIG_SHIFT 5 -#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u -#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6 -#define FTM_EXTTRIG_TRIGF_MASK 0x80u -#define FTM_EXTTRIG_TRIGF_SHIFT 7 -/* POL Bit Fields */ -#define FTM_POL_POL0_MASK 0x1u -#define FTM_POL_POL0_SHIFT 0 -#define FTM_POL_POL1_MASK 0x2u -#define FTM_POL_POL1_SHIFT 1 -#define FTM_POL_POL2_MASK 0x4u -#define FTM_POL_POL2_SHIFT 2 -#define FTM_POL_POL3_MASK 0x8u -#define FTM_POL_POL3_SHIFT 3 -#define FTM_POL_POL4_MASK 0x10u -#define FTM_POL_POL4_SHIFT 4 -#define FTM_POL_POL5_MASK 0x20u -#define FTM_POL_POL5_SHIFT 5 -#define FTM_POL_POL6_MASK 0x40u -#define FTM_POL_POL6_SHIFT 6 -#define FTM_POL_POL7_MASK 0x80u -#define FTM_POL_POL7_SHIFT 7 -/* FMS Bit Fields */ -#define FTM_FMS_FAULTF0_MASK 0x1u -#define FTM_FMS_FAULTF0_SHIFT 0 -#define FTM_FMS_FAULTF1_MASK 0x2u -#define FTM_FMS_FAULTF1_SHIFT 1 -#define FTM_FMS_FAULTF2_MASK 0x4u -#define FTM_FMS_FAULTF2_SHIFT 2 -#define FTM_FMS_FAULTF3_MASK 0x8u -#define FTM_FMS_FAULTF3_SHIFT 3 -#define FTM_FMS_FAULTIN_MASK 0x20u -#define FTM_FMS_FAULTIN_SHIFT 5 -#define FTM_FMS_WPEN_MASK 0x40u -#define FTM_FMS_WPEN_SHIFT 6 -#define FTM_FMS_FAULTF_MASK 0x80u -#define FTM_FMS_FAULTF_SHIFT 7 -/* FILTER Bit Fields */ -#define FTM_FILTER_CH0FVAL_MASK 0xFu -#define FTM_FILTER_CH0FVAL_SHIFT 0 -#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK) -#define FTM_FILTER_CH1FVAL_MASK 0xF0u -#define FTM_FILTER_CH1FVAL_SHIFT 4 -#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK) -#define FTM_FILTER_CH2FVAL_MASK 0xF00u -#define FTM_FILTER_CH2FVAL_SHIFT 8 -#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK) -#define FTM_FILTER_CH3FVAL_MASK 0xF000u -#define FTM_FILTER_CH3FVAL_SHIFT 12 -#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK) -/* FLTCTRL Bit Fields */ -#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u -#define FTM_FLTCTRL_FAULT0EN_SHIFT 0 -#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u -#define FTM_FLTCTRL_FAULT1EN_SHIFT 1 -#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u -#define FTM_FLTCTRL_FAULT2EN_SHIFT 2 -#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u -#define FTM_FLTCTRL_FAULT3EN_SHIFT 3 -#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u -#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4 -#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u -#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5 -#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u -#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6 -#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u -#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7 -#define FTM_FLTCTRL_FFVAL_MASK 0xF00u -#define FTM_FLTCTRL_FFVAL_SHIFT 8 -#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK) -/* QDCTRL Bit Fields */ -#define FTM_QDCTRL_QUADEN_MASK 0x1u -#define FTM_QDCTRL_QUADEN_SHIFT 0 -#define FTM_QDCTRL_TOFDIR_MASK 0x2u -#define FTM_QDCTRL_TOFDIR_SHIFT 1 -#define FTM_QDCTRL_QUADIR_MASK 0x4u -#define FTM_QDCTRL_QUADIR_SHIFT 2 -#define FTM_QDCTRL_QUADMODE_MASK 0x8u -#define FTM_QDCTRL_QUADMODE_SHIFT 3 -#define FTM_QDCTRL_PHBPOL_MASK 0x10u -#define FTM_QDCTRL_PHBPOL_SHIFT 4 -#define FTM_QDCTRL_PHAPOL_MASK 0x20u -#define FTM_QDCTRL_PHAPOL_SHIFT 5 -#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u -#define FTM_QDCTRL_PHBFLTREN_SHIFT 6 -#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u -#define FTM_QDCTRL_PHAFLTREN_SHIFT 7 -/* CONF Bit Fields */ -#define FTM_CONF_NUMTOF_MASK 0x1Fu -#define FTM_CONF_NUMTOF_SHIFT 0 -#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK) -#define FTM_CONF_BDMMODE_MASK 0xC0u -#define FTM_CONF_BDMMODE_SHIFT 6 -#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK) -#define FTM_CONF_GTBEEN_MASK 0x200u -#define FTM_CONF_GTBEEN_SHIFT 9 -#define FTM_CONF_GTBEOUT_MASK 0x400u -#define FTM_CONF_GTBEOUT_SHIFT 10 -/* FLTPOL Bit Fields */ -#define FTM_FLTPOL_FLT0POL_MASK 0x1u -#define FTM_FLTPOL_FLT0POL_SHIFT 0 -#define FTM_FLTPOL_FLT1POL_MASK 0x2u -#define FTM_FLTPOL_FLT1POL_SHIFT 1 -#define FTM_FLTPOL_FLT2POL_MASK 0x4u -#define FTM_FLTPOL_FLT2POL_SHIFT 2 -#define FTM_FLTPOL_FLT3POL_MASK 0x8u -#define FTM_FLTPOL_FLT3POL_SHIFT 3 -/* SYNCONF Bit Fields */ -#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u -#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0 -#define FTM_SYNCONF_CNTINC_MASK 0x4u -#define FTM_SYNCONF_CNTINC_SHIFT 2 -#define FTM_SYNCONF_INVC_MASK 0x10u -#define FTM_SYNCONF_INVC_SHIFT 4 -#define FTM_SYNCONF_SWOC_MASK 0x20u -#define FTM_SYNCONF_SWOC_SHIFT 5 -#define FTM_SYNCONF_SYNCMODE_MASK 0x80u -#define FTM_SYNCONF_SYNCMODE_SHIFT 7 -#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u -#define FTM_SYNCONF_SWRSTCNT_SHIFT 8 -#define FTM_SYNCONF_SWWRBUF_MASK 0x200u -#define FTM_SYNCONF_SWWRBUF_SHIFT 9 -#define FTM_SYNCONF_SWOM_MASK 0x400u -#define FTM_SYNCONF_SWOM_SHIFT 10 -#define FTM_SYNCONF_SWINVC_MASK 0x800u -#define FTM_SYNCONF_SWINVC_SHIFT 11 -#define FTM_SYNCONF_SWSOC_MASK 0x1000u -#define FTM_SYNCONF_SWSOC_SHIFT 12 -#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u -#define FTM_SYNCONF_HWRSTCNT_SHIFT 16 -#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u -#define FTM_SYNCONF_HWWRBUF_SHIFT 17 -#define FTM_SYNCONF_HWOM_MASK 0x40000u -#define FTM_SYNCONF_HWOM_SHIFT 18 -#define FTM_SYNCONF_HWINVC_MASK 0x80000u -#define FTM_SYNCONF_HWINVC_SHIFT 19 -#define FTM_SYNCONF_HWSOC_MASK 0x100000u -#define FTM_SYNCONF_HWSOC_SHIFT 20 -/* INVCTRL Bit Fields */ -#define FTM_INVCTRL_INV0EN_MASK 0x1u -#define FTM_INVCTRL_INV0EN_SHIFT 0 -#define FTM_INVCTRL_INV1EN_MASK 0x2u -#define FTM_INVCTRL_INV1EN_SHIFT 1 -#define FTM_INVCTRL_INV2EN_MASK 0x4u -#define FTM_INVCTRL_INV2EN_SHIFT 2 -#define FTM_INVCTRL_INV3EN_MASK 0x8u -#define FTM_INVCTRL_INV3EN_SHIFT 3 -/* SWOCTRL Bit Fields */ -#define FTM_SWOCTRL_CH0OC_MASK 0x1u -#define FTM_SWOCTRL_CH0OC_SHIFT 0 -#define FTM_SWOCTRL_CH1OC_MASK 0x2u -#define FTM_SWOCTRL_CH1OC_SHIFT 1 -#define FTM_SWOCTRL_CH2OC_MASK 0x4u -#define FTM_SWOCTRL_CH2OC_SHIFT 2 -#define FTM_SWOCTRL_CH3OC_MASK 0x8u -#define FTM_SWOCTRL_CH3OC_SHIFT 3 -#define FTM_SWOCTRL_CH4OC_MASK 0x10u -#define FTM_SWOCTRL_CH4OC_SHIFT 4 -#define FTM_SWOCTRL_CH5OC_MASK 0x20u -#define FTM_SWOCTRL_CH5OC_SHIFT 5 -#define FTM_SWOCTRL_CH6OC_MASK 0x40u -#define FTM_SWOCTRL_CH6OC_SHIFT 6 -#define FTM_SWOCTRL_CH7OC_MASK 0x80u -#define FTM_SWOCTRL_CH7OC_SHIFT 7 -#define FTM_SWOCTRL_CH0OCV_MASK 0x100u -#define FTM_SWOCTRL_CH0OCV_SHIFT 8 -#define FTM_SWOCTRL_CH1OCV_MASK 0x200u -#define FTM_SWOCTRL_CH1OCV_SHIFT 9 -#define FTM_SWOCTRL_CH2OCV_MASK 0x400u -#define FTM_SWOCTRL_CH2OCV_SHIFT 10 -#define FTM_SWOCTRL_CH3OCV_MASK 0x800u -#define FTM_SWOCTRL_CH3OCV_SHIFT 11 -#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u -#define FTM_SWOCTRL_CH4OCV_SHIFT 12 -#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u -#define FTM_SWOCTRL_CH5OCV_SHIFT 13 -#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u -#define FTM_SWOCTRL_CH6OCV_SHIFT 14 -#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u -#define FTM_SWOCTRL_CH7OCV_SHIFT 15 -/* PWMLOAD Bit Fields */ -#define FTM_PWMLOAD_CH0SEL_MASK 0x1u -#define FTM_PWMLOAD_CH0SEL_SHIFT 0 -#define FTM_PWMLOAD_CH1SEL_MASK 0x2u -#define FTM_PWMLOAD_CH1SEL_SHIFT 1 -#define FTM_PWMLOAD_CH2SEL_MASK 0x4u -#define FTM_PWMLOAD_CH2SEL_SHIFT 2 -#define FTM_PWMLOAD_CH3SEL_MASK 0x8u -#define FTM_PWMLOAD_CH3SEL_SHIFT 3 -#define FTM_PWMLOAD_CH4SEL_MASK 0x10u -#define FTM_PWMLOAD_CH4SEL_SHIFT 4 -#define FTM_PWMLOAD_CH5SEL_MASK 0x20u -#define FTM_PWMLOAD_CH5SEL_SHIFT 5 -#define FTM_PWMLOAD_CH6SEL_MASK 0x40u -#define FTM_PWMLOAD_CH6SEL_SHIFT 6 -#define FTM_PWMLOAD_CH7SEL_MASK 0x80u -#define FTM_PWMLOAD_CH7SEL_SHIFT 7 -#define FTM_PWMLOAD_LDOK_MASK 0x200u -#define FTM_PWMLOAD_LDOK_SHIFT 9 - -/** - * @} - */ /* end of group FTM_Register_Masks */ - - -/* FTM - Peripheral instance base addresses */ -/** Peripheral FTM0 base address */ -#define FTM0_BASE (0x40038000u) -/** Peripheral FTM0 base pointer */ -#define FTM0 ((FTM_Type *)FTM0_BASE) -/** Peripheral FTM1 base address */ -#define FTM1_BASE (0x40039000u) -/** Peripheral FTM1 base pointer */ -#define FTM1 ((FTM_Type *)FTM1_BASE) - -/** - * @} - */ /* end of group FTM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ - __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ - __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ - __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ - __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ - __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/* PDOR Bit Fields */ -#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu -#define GPIO_PDOR_PDO_SHIFT 0 -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK) -/* PSOR Bit Fields */ -#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu -#define GPIO_PSOR_PTSO_SHIFT 0 -#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK) -/* PCOR Bit Fields */ -#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu -#define GPIO_PCOR_PTCO_SHIFT 0 -#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK) -/* PTOR Bit Fields */ -#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu -#define GPIO_PTOR_PTTO_SHIFT 0 -#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK) -/* PDIR Bit Fields */ -#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu -#define GPIO_PDIR_PDI_SHIFT 0 -#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK) -/* PDDR Bit Fields */ -#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu -#define GPIO_PDDR_PDD_SHIFT 0 -#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK) - -/** - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -/** Peripheral PTA base address */ -#define PTA_BASE (0x400FF000u) -/** Peripheral PTA base pointer */ -#define PTA ((GPIO_Type *)PTA_BASE) -/** Peripheral PTB base address */ -#define PTB_BASE (0x400FF040u) -/** Peripheral PTB base pointer */ -#define PTB ((GPIO_Type *)PTB_BASE) -/** Peripheral PTC base address */ -#define PTC_BASE (0x400FF080u) -/** Peripheral PTC base pointer */ -#define PTC ((GPIO_Type *)PTC_BASE) -/** Peripheral PTD base address */ -#define PTD_BASE (0x400FF0C0u) -/** Peripheral PTD base pointer */ -#define PTD ((GPIO_Type *)PTD_BASE) -/** Peripheral PTE base address */ -#define PTE_BASE (0x400FF100u) -/** Peripheral PTE base pointer */ -#define PTE ((GPIO_Type *)PTE_BASE) - -/** - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ - __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ - __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ - __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */ - __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ - __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ - __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ - __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ - __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ - __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ - __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ - __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/* A1 Bit Fields */ -#define I2C_A1_AD_MASK 0xFEu -#define I2C_A1_AD_SHIFT 1 -#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK) -/* F Bit Fields */ -#define I2C_F_ICR_MASK 0x3Fu -#define I2C_F_ICR_SHIFT 0 -#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK) -#define I2C_F_MULT_MASK 0xC0u -#define I2C_F_MULT_SHIFT 6 -#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK) -/* C1 Bit Fields */ -#define I2C_C1_DMAEN_MASK 0x1u -#define I2C_C1_DMAEN_SHIFT 0 -#define I2C_C1_WUEN_MASK 0x2u -#define I2C_C1_WUEN_SHIFT 1 -#define I2C_C1_RSTA_MASK 0x4u -#define I2C_C1_RSTA_SHIFT 2 -#define I2C_C1_TXAK_MASK 0x8u -#define I2C_C1_TXAK_SHIFT 3 -#define I2C_C1_TX_MASK 0x10u -#define I2C_C1_TX_SHIFT 4 -#define I2C_C1_MST_MASK 0x20u -#define I2C_C1_MST_SHIFT 5 -#define I2C_C1_IICIE_MASK 0x40u -#define I2C_C1_IICIE_SHIFT 6 -#define I2C_C1_IICEN_MASK 0x80u -#define I2C_C1_IICEN_SHIFT 7 -/* S Bit Fields */ -#define I2C_S_RXAK_MASK 0x1u -#define I2C_S_RXAK_SHIFT 0 -#define I2C_S_IICIF_MASK 0x2u -#define I2C_S_IICIF_SHIFT 1 -#define I2C_S_SRW_MASK 0x4u -#define I2C_S_SRW_SHIFT 2 -#define I2C_S_RAM_MASK 0x8u -#define I2C_S_RAM_SHIFT 3 -#define I2C_S_ARBL_MASK 0x10u -#define I2C_S_ARBL_SHIFT 4 -#define I2C_S_BUSY_MASK 0x20u -#define I2C_S_BUSY_SHIFT 5 -#define I2C_S_IAAS_MASK 0x40u -#define I2C_S_IAAS_SHIFT 6 -#define I2C_S_TCF_MASK 0x80u -#define I2C_S_TCF_SHIFT 7 -/* D Bit Fields */ -#define I2C_D_DATA_MASK 0xFFu -#define I2C_D_DATA_SHIFT 0 -#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK) -/* C2 Bit Fields */ -#define I2C_C2_AD_MASK 0x7u -#define I2C_C2_AD_SHIFT 0 -#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK) -#define I2C_C2_RMEN_MASK 0x8u -#define I2C_C2_RMEN_SHIFT 3 -#define I2C_C2_SBRC_MASK 0x10u -#define I2C_C2_SBRC_SHIFT 4 -#define I2C_C2_HDRS_MASK 0x20u -#define I2C_C2_HDRS_SHIFT 5 -#define I2C_C2_ADEXT_MASK 0x40u -#define I2C_C2_ADEXT_SHIFT 6 -#define I2C_C2_GCAEN_MASK 0x80u -#define I2C_C2_GCAEN_SHIFT 7 -/* FLT Bit Fields */ -#define I2C_FLT_FLT_MASK 0x1Fu -#define I2C_FLT_FLT_SHIFT 0 -#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK) -/* RA Bit Fields */ -#define I2C_RA_RAD_MASK 0xFEu -#define I2C_RA_RAD_SHIFT 1 -#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK) -/* SMB Bit Fields */ -#define I2C_SMB_SHTF2IE_MASK 0x1u -#define I2C_SMB_SHTF2IE_SHIFT 0 -#define I2C_SMB_SHTF2_MASK 0x2u -#define I2C_SMB_SHTF2_SHIFT 1 -#define I2C_SMB_SHTF1_MASK 0x4u -#define I2C_SMB_SHTF1_SHIFT 2 -#define I2C_SMB_SLTF_MASK 0x8u -#define I2C_SMB_SLTF_SHIFT 3 -#define I2C_SMB_TCKSEL_MASK 0x10u -#define I2C_SMB_TCKSEL_SHIFT 4 -#define I2C_SMB_SIICAEN_MASK 0x20u -#define I2C_SMB_SIICAEN_SHIFT 5 -#define I2C_SMB_ALERTEN_MASK 0x40u -#define I2C_SMB_ALERTEN_SHIFT 6 -#define I2C_SMB_FACK_MASK 0x80u -#define I2C_SMB_FACK_SHIFT 7 -/* A2 Bit Fields */ -#define I2C_A2_SAD_MASK 0xFEu -#define I2C_A2_SAD_SHIFT 1 -#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK) -/* SLTH Bit Fields */ -#define I2C_SLTH_SSLT_MASK 0xFFu -#define I2C_SLTH_SSLT_SHIFT 0 -#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK) -/* SLTL Bit Fields */ -#define I2C_SLTL_SSLT_MASK 0xFFu -#define I2C_SLTL_SSLT_SHIFT 0 -#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK) - -/** - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -/** Peripheral I2C0 base address */ -#define I2C0_BASE (0x40066000u) -/** Peripheral I2C0 base pointer */ -#define I2C0 ((I2C_Type *)I2C0_BASE) - -/** - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ - __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ - __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ - __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ - __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ - __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ - uint8_t RESERVED_0[8]; - __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ - uint8_t RESERVED_2[24]; - __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ - uint8_t RESERVED_3[28]; - __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ - __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ - __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ - __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ - __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ - __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ - uint8_t RESERVED_4[8]; - __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ - uint8_t RESERVED_5[24]; - __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_6[24]; - __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ - uint8_t RESERVED_7[28]; - __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ - __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/* TCSR Bit Fields */ -#define I2S_TCSR_FRDE_MASK 0x1u -#define I2S_TCSR_FRDE_SHIFT 0 -#define I2S_TCSR_FWDE_MASK 0x2u -#define I2S_TCSR_FWDE_SHIFT 1 -#define I2S_TCSR_FRIE_MASK 0x100u -#define I2S_TCSR_FRIE_SHIFT 8 -#define I2S_TCSR_FWIE_MASK 0x200u -#define I2S_TCSR_FWIE_SHIFT 9 -#define I2S_TCSR_FEIE_MASK 0x400u -#define I2S_TCSR_FEIE_SHIFT 10 -#define I2S_TCSR_SEIE_MASK 0x800u -#define I2S_TCSR_SEIE_SHIFT 11 -#define I2S_TCSR_WSIE_MASK 0x1000u -#define I2S_TCSR_WSIE_SHIFT 12 -#define I2S_TCSR_FRF_MASK 0x10000u -#define I2S_TCSR_FRF_SHIFT 16 -#define I2S_TCSR_FWF_MASK 0x20000u -#define I2S_TCSR_FWF_SHIFT 17 -#define I2S_TCSR_FEF_MASK 0x40000u -#define I2S_TCSR_FEF_SHIFT 18 -#define I2S_TCSR_SEF_MASK 0x80000u -#define I2S_TCSR_SEF_SHIFT 19 -#define I2S_TCSR_WSF_MASK 0x100000u -#define I2S_TCSR_WSF_SHIFT 20 -#define I2S_TCSR_SR_MASK 0x1000000u -#define I2S_TCSR_SR_SHIFT 24 -#define I2S_TCSR_FR_MASK 0x2000000u -#define I2S_TCSR_FR_SHIFT 25 -#define I2S_TCSR_BCE_MASK 0x10000000u -#define I2S_TCSR_BCE_SHIFT 28 -#define I2S_TCSR_DBGE_MASK 0x20000000u -#define I2S_TCSR_DBGE_SHIFT 29 -#define I2S_TCSR_STOPE_MASK 0x40000000u -#define I2S_TCSR_STOPE_SHIFT 30 -#define I2S_TCSR_TE_MASK 0x80000000u -#define I2S_TCSR_TE_SHIFT 31 -/* TCR1 Bit Fields */ -#define I2S_TCR1_TFW_MASK 0x7u -#define I2S_TCR1_TFW_SHIFT 0 -#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK) -/* TCR2 Bit Fields */ -#define I2S_TCR2_DIV_MASK 0xFFu -#define I2S_TCR2_DIV_SHIFT 0 -#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK) -#define I2S_TCR2_BCD_MASK 0x1000000u -#define I2S_TCR2_BCD_SHIFT 24 -#define I2S_TCR2_BCP_MASK 0x2000000u -#define I2S_TCR2_BCP_SHIFT 25 -#define I2S_TCR2_MSEL_MASK 0xC000000u -#define I2S_TCR2_MSEL_SHIFT 26 -#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK) -#define I2S_TCR2_BCI_MASK 0x10000000u -#define I2S_TCR2_BCI_SHIFT 28 -#define I2S_TCR2_BCS_MASK 0x20000000u -#define I2S_TCR2_BCS_SHIFT 29 -#define I2S_TCR2_SYNC_MASK 0xC0000000u -#define I2S_TCR2_SYNC_SHIFT 30 -#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK) -/* TCR3 Bit Fields */ -#define I2S_TCR3_WDFL_MASK 0x1Fu -#define I2S_TCR3_WDFL_SHIFT 0 -#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK) -#define I2S_TCR3_TCE_MASK 0x30000u -#define I2S_TCR3_TCE_SHIFT 16 -#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK) -/* TCR4 Bit Fields */ -#define I2S_TCR4_FSD_MASK 0x1u -#define I2S_TCR4_FSD_SHIFT 0 -#define I2S_TCR4_FSP_MASK 0x2u -#define I2S_TCR4_FSP_SHIFT 1 -#define I2S_TCR4_FSE_MASK 0x8u -#define I2S_TCR4_FSE_SHIFT 3 -#define I2S_TCR4_MF_MASK 0x10u -#define I2S_TCR4_MF_SHIFT 4 -#define I2S_TCR4_SYWD_MASK 0x1F00u -#define I2S_TCR4_SYWD_SHIFT 8 -#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK) -#define I2S_TCR4_FRSZ_MASK 0x1F0000u -#define I2S_TCR4_FRSZ_SHIFT 16 -#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK) -/* TCR5 Bit Fields */ -#define I2S_TCR5_FBT_MASK 0x1F00u -#define I2S_TCR5_FBT_SHIFT 8 -#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK) -#define I2S_TCR5_W0W_MASK 0x1F0000u -#define I2S_TCR5_W0W_SHIFT 16 -#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK) -#define I2S_TCR5_WNW_MASK 0x1F000000u -#define I2S_TCR5_WNW_SHIFT 24 -#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK) -/* TDR Bit Fields */ -#define I2S_TDR_TDR_MASK 0xFFFFFFFFu -#define I2S_TDR_TDR_SHIFT 0 -#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK) -/* TFR Bit Fields */ -#define I2S_TFR_RFP_MASK 0xFu -#define I2S_TFR_RFP_SHIFT 0 -#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK) -#define I2S_TFR_WFP_MASK 0xF0000u -#define I2S_TFR_WFP_SHIFT 16 -#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK) -/* TMR Bit Fields */ -#define I2S_TMR_TWM_MASK 0xFFFFFFFFu -#define I2S_TMR_TWM_SHIFT 0 -#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK) -/* RCSR Bit Fields */ -#define I2S_RCSR_FRDE_MASK 0x1u -#define I2S_RCSR_FRDE_SHIFT 0 -#define I2S_RCSR_FWDE_MASK 0x2u -#define I2S_RCSR_FWDE_SHIFT 1 -#define I2S_RCSR_FRIE_MASK 0x100u -#define I2S_RCSR_FRIE_SHIFT 8 -#define I2S_RCSR_FWIE_MASK 0x200u -#define I2S_RCSR_FWIE_SHIFT 9 -#define I2S_RCSR_FEIE_MASK 0x400u -#define I2S_RCSR_FEIE_SHIFT 10 -#define I2S_RCSR_SEIE_MASK 0x800u -#define I2S_RCSR_SEIE_SHIFT 11 -#define I2S_RCSR_WSIE_MASK 0x1000u -#define I2S_RCSR_WSIE_SHIFT 12 -#define I2S_RCSR_FRF_MASK 0x10000u -#define I2S_RCSR_FRF_SHIFT 16 -#define I2S_RCSR_FWF_MASK 0x20000u -#define I2S_RCSR_FWF_SHIFT 17 -#define I2S_RCSR_FEF_MASK 0x40000u -#define I2S_RCSR_FEF_SHIFT 18 -#define I2S_RCSR_SEF_MASK 0x80000u -#define I2S_RCSR_SEF_SHIFT 19 -#define I2S_RCSR_WSF_MASK 0x100000u -#define I2S_RCSR_WSF_SHIFT 20 -#define I2S_RCSR_SR_MASK 0x1000000u -#define I2S_RCSR_SR_SHIFT 24 -#define I2S_RCSR_FR_MASK 0x2000000u -#define I2S_RCSR_FR_SHIFT 25 -#define I2S_RCSR_BCE_MASK 0x10000000u -#define I2S_RCSR_BCE_SHIFT 28 -#define I2S_RCSR_DBGE_MASK 0x20000000u -#define I2S_RCSR_DBGE_SHIFT 29 -#define I2S_RCSR_STOPE_MASK 0x40000000u -#define I2S_RCSR_STOPE_SHIFT 30 -#define I2S_RCSR_RE_MASK 0x80000000u -#define I2S_RCSR_RE_SHIFT 31 -/* RCR1 Bit Fields */ -#define I2S_RCR1_RFW_MASK 0x7u -#define I2S_RCR1_RFW_SHIFT 0 -#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK) -/* RCR2 Bit Fields */ -#define I2S_RCR2_DIV_MASK 0xFFu -#define I2S_RCR2_DIV_SHIFT 0 -#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK) -#define I2S_RCR2_BCD_MASK 0x1000000u -#define I2S_RCR2_BCD_SHIFT 24 -#define I2S_RCR2_BCP_MASK 0x2000000u -#define I2S_RCR2_BCP_SHIFT 25 -#define I2S_RCR2_MSEL_MASK 0xC000000u -#define I2S_RCR2_MSEL_SHIFT 26 -#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK) -#define I2S_RCR2_BCI_MASK 0x10000000u -#define I2S_RCR2_BCI_SHIFT 28 -#define I2S_RCR2_BCS_MASK 0x20000000u -#define I2S_RCR2_BCS_SHIFT 29 -#define I2S_RCR2_SYNC_MASK 0xC0000000u -#define I2S_RCR2_SYNC_SHIFT 30 -#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK) -/* RCR3 Bit Fields */ -#define I2S_RCR3_WDFL_MASK 0x1Fu -#define I2S_RCR3_WDFL_SHIFT 0 -#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK) -#define I2S_RCR3_RCE_MASK 0x30000u -#define I2S_RCR3_RCE_SHIFT 16 -#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK) -/* RCR4 Bit Fields */ -#define I2S_RCR4_FSD_MASK 0x1u -#define I2S_RCR4_FSD_SHIFT 0 -#define I2S_RCR4_FSP_MASK 0x2u -#define I2S_RCR4_FSP_SHIFT 1 -#define I2S_RCR4_FSE_MASK 0x8u -#define I2S_RCR4_FSE_SHIFT 3 -#define I2S_RCR4_MF_MASK 0x10u -#define I2S_RCR4_MF_SHIFT 4 -#define I2S_RCR4_SYWD_MASK 0x1F00u -#define I2S_RCR4_SYWD_SHIFT 8 -#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK) -#define I2S_RCR4_FRSZ_MASK 0x1F0000u -#define I2S_RCR4_FRSZ_SHIFT 16 -#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK) -/* RCR5 Bit Fields */ -#define I2S_RCR5_FBT_MASK 0x1F00u -#define I2S_RCR5_FBT_SHIFT 8 -#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK) -#define I2S_RCR5_W0W_MASK 0x1F0000u -#define I2S_RCR5_W0W_SHIFT 16 -#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK) -#define I2S_RCR5_WNW_MASK 0x1F000000u -#define I2S_RCR5_WNW_SHIFT 24 -#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK) -/* RDR Bit Fields */ -#define I2S_RDR_RDR_MASK 0xFFFFFFFFu -#define I2S_RDR_RDR_SHIFT 0 -#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK) -/* RFR Bit Fields */ -#define I2S_RFR_RFP_MASK 0xFu -#define I2S_RFR_RFP_SHIFT 0 -#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK) -#define I2S_RFR_WFP_MASK 0xF0000u -#define I2S_RFR_WFP_SHIFT 16 -#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK) -/* RMR Bit Fields */ -#define I2S_RMR_RWM_MASK 0xFFFFFFFFu -#define I2S_RMR_RWM_SHIFT 0 -#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK) -/* MCR Bit Fields */ -#define I2S_MCR_MICS_MASK 0x3000000u -#define I2S_MCR_MICS_SHIFT 24 -#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK) -#define I2S_MCR_MOE_MASK 0x40000000u -#define I2S_MCR_MOE_SHIFT 30 -#define I2S_MCR_DUF_MASK 0x80000000u -#define I2S_MCR_DUF_SHIFT 31 -/* MDR Bit Fields */ -#define I2S_MDR_DIVIDE_MASK 0xFFFu -#define I2S_MDR_DIVIDE_SHIFT 0 -#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK) -#define I2S_MDR_FRACT_MASK 0xFF000u -#define I2S_MDR_FRACT_SHIFT 12 -#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK) - -/** - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -/** Peripheral I2S0 base address */ -#define I2S0_BASE (0x4002F000u) -/** Peripheral I2S0 base pointer */ -#define I2S0 ((I2S_Type *)I2S0_BASE) - -/** - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LLWU Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer - * @{ - */ - -/** LLWU - Register Layout Typedef */ -typedef struct { - __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */ - __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */ - __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */ - __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */ - __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */ - __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */ - __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */ - __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */ - __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */ - __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */ - __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */ -} LLWU_Type; - -/* ---------------------------------------------------------------------------- - -- LLWU Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup LLWU_Register_Masks LLWU Register Masks - * @{ - */ - -/* PE1 Bit Fields */ -#define LLWU_PE1_WUPE0_MASK 0x3u -#define LLWU_PE1_WUPE0_SHIFT 0 -#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK) -#define LLWU_PE1_WUPE1_MASK 0xCu -#define LLWU_PE1_WUPE1_SHIFT 2 -#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK) -#define LLWU_PE1_WUPE2_MASK 0x30u -#define LLWU_PE1_WUPE2_SHIFT 4 -#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK) -#define LLWU_PE1_WUPE3_MASK 0xC0u -#define LLWU_PE1_WUPE3_SHIFT 6 -#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK) -/* PE2 Bit Fields */ -#define LLWU_PE2_WUPE4_MASK 0x3u -#define LLWU_PE2_WUPE4_SHIFT 0 -#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK) -#define LLWU_PE2_WUPE5_MASK 0xCu -#define LLWU_PE2_WUPE5_SHIFT 2 -#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK) -#define LLWU_PE2_WUPE6_MASK 0x30u -#define LLWU_PE2_WUPE6_SHIFT 4 -#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK) -#define LLWU_PE2_WUPE7_MASK 0xC0u -#define LLWU_PE2_WUPE7_SHIFT 6 -#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK) -/* PE3 Bit Fields */ -#define LLWU_PE3_WUPE8_MASK 0x3u -#define LLWU_PE3_WUPE8_SHIFT 0 -#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK) -#define LLWU_PE3_WUPE9_MASK 0xCu -#define LLWU_PE3_WUPE9_SHIFT 2 -#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK) -#define LLWU_PE3_WUPE10_MASK 0x30u -#define LLWU_PE3_WUPE10_SHIFT 4 -#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK) -#define LLWU_PE3_WUPE11_MASK 0xC0u -#define LLWU_PE3_WUPE11_SHIFT 6 -#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK) -/* PE4 Bit Fields */ -#define LLWU_PE4_WUPE12_MASK 0x3u -#define LLWU_PE4_WUPE12_SHIFT 0 -#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK) -#define LLWU_PE4_WUPE13_MASK 0xCu -#define LLWU_PE4_WUPE13_SHIFT 2 -#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK) -#define LLWU_PE4_WUPE14_MASK 0x30u -#define LLWU_PE4_WUPE14_SHIFT 4 -#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK) -#define LLWU_PE4_WUPE15_MASK 0xC0u -#define LLWU_PE4_WUPE15_SHIFT 6 -#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK) -/* ME Bit Fields */ -#define LLWU_ME_WUME0_MASK 0x1u -#define LLWU_ME_WUME0_SHIFT 0 -#define LLWU_ME_WUME1_MASK 0x2u -#define LLWU_ME_WUME1_SHIFT 1 -#define LLWU_ME_WUME2_MASK 0x4u -#define LLWU_ME_WUME2_SHIFT 2 -#define LLWU_ME_WUME3_MASK 0x8u -#define LLWU_ME_WUME3_SHIFT 3 -#define LLWU_ME_WUME4_MASK 0x10u -#define LLWU_ME_WUME4_SHIFT 4 -#define LLWU_ME_WUME5_MASK 0x20u -#define LLWU_ME_WUME5_SHIFT 5 -#define LLWU_ME_WUME6_MASK 0x40u -#define LLWU_ME_WUME6_SHIFT 6 -#define LLWU_ME_WUME7_MASK 0x80u -#define LLWU_ME_WUME7_SHIFT 7 -/* F1 Bit Fields */ -#define LLWU_F1_WUF0_MASK 0x1u -#define LLWU_F1_WUF0_SHIFT 0 -#define LLWU_F1_WUF1_MASK 0x2u -#define LLWU_F1_WUF1_SHIFT 1 -#define LLWU_F1_WUF2_MASK 0x4u -#define LLWU_F1_WUF2_SHIFT 2 -#define LLWU_F1_WUF3_MASK 0x8u -#define LLWU_F1_WUF3_SHIFT 3 -#define LLWU_F1_WUF4_MASK 0x10u -#define LLWU_F1_WUF4_SHIFT 4 -#define LLWU_F1_WUF5_MASK 0x20u -#define LLWU_F1_WUF5_SHIFT 5 -#define LLWU_F1_WUF6_MASK 0x40u -#define LLWU_F1_WUF6_SHIFT 6 -#define LLWU_F1_WUF7_MASK 0x80u -#define LLWU_F1_WUF7_SHIFT 7 -/* F2 Bit Fields */ -#define LLWU_F2_WUF8_MASK 0x1u -#define LLWU_F2_WUF8_SHIFT 0 -#define LLWU_F2_WUF9_MASK 0x2u -#define LLWU_F2_WUF9_SHIFT 1 -#define LLWU_F2_WUF10_MASK 0x4u -#define LLWU_F2_WUF10_SHIFT 2 -#define LLWU_F2_WUF11_MASK 0x8u -#define LLWU_F2_WUF11_SHIFT 3 -#define LLWU_F2_WUF12_MASK 0x10u -#define LLWU_F2_WUF12_SHIFT 4 -#define LLWU_F2_WUF13_MASK 0x20u -#define LLWU_F2_WUF13_SHIFT 5 -#define LLWU_F2_WUF14_MASK 0x40u -#define LLWU_F2_WUF14_SHIFT 6 -#define LLWU_F2_WUF15_MASK 0x80u -#define LLWU_F2_WUF15_SHIFT 7 -/* F3 Bit Fields */ -#define LLWU_F3_MWUF0_MASK 0x1u -#define LLWU_F3_MWUF0_SHIFT 0 -#define LLWU_F3_MWUF1_MASK 0x2u -#define LLWU_F3_MWUF1_SHIFT 1 -#define LLWU_F3_MWUF2_MASK 0x4u -#define LLWU_F3_MWUF2_SHIFT 2 -#define LLWU_F3_MWUF3_MASK 0x8u -#define LLWU_F3_MWUF3_SHIFT 3 -#define LLWU_F3_MWUF4_MASK 0x10u -#define LLWU_F3_MWUF4_SHIFT 4 -#define LLWU_F3_MWUF5_MASK 0x20u -#define LLWU_F3_MWUF5_SHIFT 5 -#define LLWU_F3_MWUF6_MASK 0x40u -#define LLWU_F3_MWUF6_SHIFT 6 -#define LLWU_F3_MWUF7_MASK 0x80u -#define LLWU_F3_MWUF7_SHIFT 7 -/* FILT1 Bit Fields */ -#define LLWU_FILT1_FILTSEL_MASK 0xFu -#define LLWU_FILT1_FILTSEL_SHIFT 0 -#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK) -#define LLWU_FILT1_FILTE_MASK 0x60u -#define LLWU_FILT1_FILTE_SHIFT 5 -#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK) -#define LLWU_FILT1_FILTF_MASK 0x80u -#define LLWU_FILT1_FILTF_SHIFT 7 -/* FILT2 Bit Fields */ -#define LLWU_FILT2_FILTSEL_MASK 0xFu -#define LLWU_FILT2_FILTSEL_SHIFT 0 -#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK) -#define LLWU_FILT2_FILTE_MASK 0x60u -#define LLWU_FILT2_FILTE_SHIFT 5 -#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK) -#define LLWU_FILT2_FILTF_MASK 0x80u -#define LLWU_FILT2_FILTF_SHIFT 7 -/* RST Bit Fields */ -#define LLWU_RST_RSTFILT_MASK 0x1u -#define LLWU_RST_RSTFILT_SHIFT 0 -#define LLWU_RST_LLRSTE_MASK 0x2u -#define LLWU_RST_LLRSTE_SHIFT 1 - -/** - * @} - */ /* end of group LLWU_Register_Masks */ - - -/* LLWU - Peripheral instance base addresses */ -/** Peripheral LLWU base address */ -#define LLWU_BASE (0x4007C000u) -/** Peripheral LLWU base pointer */ -#define LLWU ((LLWU_Type *)LLWU_BASE) - -/** - * @} - */ /* end of group LLWU_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- LPTMR Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer - * @{ - */ - -/** LPTMR - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ - __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ - __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ - __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ -} LPTMR_Type; - -/* ---------------------------------------------------------------------------- - -- LPTMR Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup LPTMR_Register_Masks LPTMR Register Masks - * @{ - */ - -/* CSR Bit Fields */ -#define LPTMR_CSR_TEN_MASK 0x1u -#define LPTMR_CSR_TEN_SHIFT 0 -#define LPTMR_CSR_TMS_MASK 0x2u -#define LPTMR_CSR_TMS_SHIFT 1 -#define LPTMR_CSR_TFC_MASK 0x4u -#define LPTMR_CSR_TFC_SHIFT 2 -#define LPTMR_CSR_TPP_MASK 0x8u -#define LPTMR_CSR_TPP_SHIFT 3 -#define LPTMR_CSR_TPS_MASK 0x30u -#define LPTMR_CSR_TPS_SHIFT 4 -#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK) -#define LPTMR_CSR_TIE_MASK 0x40u -#define LPTMR_CSR_TIE_SHIFT 6 -#define LPTMR_CSR_TCF_MASK 0x80u -#define LPTMR_CSR_TCF_SHIFT 7 -/* PSR Bit Fields */ -#define LPTMR_PSR_PCS_MASK 0x3u -#define LPTMR_PSR_PCS_SHIFT 0 -#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK) -#define LPTMR_PSR_PBYP_MASK 0x4u -#define LPTMR_PSR_PBYP_SHIFT 2 -#define LPTMR_PSR_PRESCALE_MASK 0x78u -#define LPTMR_PSR_PRESCALE_SHIFT 3 -#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK) -/* CMR Bit Fields */ -#define LPTMR_CMR_COMPARE_MASK 0xFFFFu -#define LPTMR_CMR_COMPARE_SHIFT 0 -#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK) -/* CNR Bit Fields */ -#define LPTMR_CNR_COUNTER_MASK 0xFFFFu -#define LPTMR_CNR_COUNTER_SHIFT 0 -#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK) - -/** - * @} - */ /* end of group LPTMR_Register_Masks */ - - -/* LPTMR - Peripheral instance base addresses */ -/** Peripheral LPTMR0 base address */ -#define LPTMR0_BASE (0x40040000u) -/** Peripheral LPTMR0 base pointer */ -#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) - -/** - * @} - */ /* end of group LPTMR_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MCG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer - * @{ - */ - -/** MCG - Register Layout Typedef */ -typedef struct { - __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ - __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ - __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ - __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ - __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ - __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ - __I uint8_t S; /**< MCG Status Register, offset: 0x6 */ - uint8_t RESERVED_0[1]; - __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ - uint8_t RESERVED_1[1]; - __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ - __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ - __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ - __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ -} MCG_Type; - -/* ---------------------------------------------------------------------------- - -- MCG Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup MCG_Register_Masks MCG Register Masks - * @{ - */ - -/* C1 Bit Fields */ -#define MCG_C1_IREFSTEN_MASK 0x1u -#define MCG_C1_IREFSTEN_SHIFT 0 -#define MCG_C1_IRCLKEN_MASK 0x2u -#define MCG_C1_IRCLKEN_SHIFT 1 -#define MCG_C1_IREFS_MASK 0x4u -#define MCG_C1_IREFS_SHIFT 2 -#define MCG_C1_FRDIV_MASK 0x38u -#define MCG_C1_FRDIV_SHIFT 3 -#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK) -#define MCG_C1_CLKS_MASK 0xC0u -#define MCG_C1_CLKS_SHIFT 6 -#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK) -/* C2 Bit Fields */ -#define MCG_C2_IRCS_MASK 0x1u -#define MCG_C2_IRCS_SHIFT 0 -#define MCG_C2_LP_MASK 0x2u -#define MCG_C2_LP_SHIFT 1 -#define MCG_C2_EREFS0_MASK 0x4u -#define MCG_C2_EREFS0_SHIFT 2 -#define MCG_C2_HGO0_MASK 0x8u -#define MCG_C2_HGO0_SHIFT 3 -#define MCG_C2_RANGE0_MASK 0x30u -#define MCG_C2_RANGE0_SHIFT 4 -#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK) -#define MCG_C2_LOCRE0_MASK 0x80u -#define MCG_C2_LOCRE0_SHIFT 7 -/* C3 Bit Fields */ -#define MCG_C3_SCTRIM_MASK 0xFFu -#define MCG_C3_SCTRIM_SHIFT 0 -#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK) -/* C4 Bit Fields */ -#define MCG_C4_SCFTRIM_MASK 0x1u -#define MCG_C4_SCFTRIM_SHIFT 0 -#define MCG_C4_FCTRIM_MASK 0x1Eu -#define MCG_C4_FCTRIM_SHIFT 1 -#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK) -#define MCG_C4_DRST_DRS_MASK 0x60u -#define MCG_C4_DRST_DRS_SHIFT 5 -#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK) -#define MCG_C4_DMX32_MASK 0x80u -#define MCG_C4_DMX32_SHIFT 7 -/* C5 Bit Fields */ -#define MCG_C5_PRDIV0_MASK 0x1Fu -#define MCG_C5_PRDIV0_SHIFT 0 -#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK) -#define MCG_C5_PLLSTEN0_MASK 0x20u -#define MCG_C5_PLLSTEN0_SHIFT 5 -#define MCG_C5_PLLCLKEN0_MASK 0x40u -#define MCG_C5_PLLCLKEN0_SHIFT 6 -/* C6 Bit Fields */ -#define MCG_C6_VDIV0_MASK 0x1Fu -#define MCG_C6_VDIV0_SHIFT 0 -#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK) -#define MCG_C6_CME0_MASK 0x20u -#define MCG_C6_CME0_SHIFT 5 -#define MCG_C6_PLLS_MASK 0x40u -#define MCG_C6_PLLS_SHIFT 6 -#define MCG_C6_LOLIE0_MASK 0x80u -#define MCG_C6_LOLIE0_SHIFT 7 -/* S Bit Fields */ -#define MCG_S_IRCST_MASK 0x1u -#define MCG_S_IRCST_SHIFT 0 -#define MCG_S_OSCINIT0_MASK 0x2u -#define MCG_S_OSCINIT0_SHIFT 1 -#define MCG_S_CLKST_MASK 0xCu -#define MCG_S_CLKST_SHIFT 2 -#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK) -#define MCG_S_IREFST_MASK 0x10u -#define MCG_S_IREFST_SHIFT 4 -#define MCG_S_PLLST_MASK 0x20u -#define MCG_S_PLLST_SHIFT 5 -#define MCG_S_LOCK0_MASK 0x40u -#define MCG_S_LOCK0_SHIFT 6 -#define MCG_S_LOLS0_MASK 0x80u -#define MCG_S_LOLS0_SHIFT 7 -/* SC Bit Fields */ -#define MCG_SC_LOCS0_MASK 0x1u -#define MCG_SC_LOCS0_SHIFT 0 -#define MCG_SC_FCRDIV_MASK 0xEu -#define MCG_SC_FCRDIV_SHIFT 1 -#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK) -#define MCG_SC_FLTPRSRV_MASK 0x10u -#define MCG_SC_FLTPRSRV_SHIFT 4 -#define MCG_SC_ATMF_MASK 0x20u -#define MCG_SC_ATMF_SHIFT 5 -#define MCG_SC_ATMS_MASK 0x40u -#define MCG_SC_ATMS_SHIFT 6 -#define MCG_SC_ATME_MASK 0x80u -#define MCG_SC_ATME_SHIFT 7 -/* ATCVH Bit Fields */ -#define MCG_ATCVH_ATCVH_MASK 0xFFu -#define MCG_ATCVH_ATCVH_SHIFT 0 -#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK) -/* ATCVL Bit Fields */ -#define MCG_ATCVL_ATCVL_MASK 0xFFu -#define MCG_ATCVL_ATCVL_SHIFT 0 -#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK) -/* C7 Bit Fields */ -#define MCG_C7_OSCSEL_MASK 0x1u -#define MCG_C7_OSCSEL_SHIFT 0 -/* C8 Bit Fields */ -#define MCG_C8_LOCS1_MASK 0x1u -#define MCG_C8_LOCS1_SHIFT 0 -#define MCG_C8_CME1_MASK 0x20u -#define MCG_C8_CME1_SHIFT 5 -#define MCG_C8_LOLRE_MASK 0x40u -#define MCG_C8_LOLRE_SHIFT 6 -#define MCG_C8_LOCRE1_MASK 0x80u -#define MCG_C8_LOCRE1_SHIFT 7 - -/** - * @} - */ /* end of group MCG_Register_Masks */ - - -/* MCG - Peripheral instance base addresses */ -/** Peripheral MCG base address */ -#define MCG_BASE (0x40064000u) -/** Peripheral MCG base pointer */ -#define MCG ((MCG_Type *)MCG_BASE) - -/** - * @} - */ /* end of group MCG_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- NV Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer - * @{ - */ - -/** NV - Register Layout Typedef */ -typedef struct { - __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ - __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ - __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ - __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ - __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ - __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ - __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ - __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ - __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ - __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ - __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ - __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ - __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ - __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ - __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */ - __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */ -} NV_Type; - -/* ---------------------------------------------------------------------------- - -- NV Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup NV_Register_Masks NV Register Masks - * @{ - */ - -/* BACKKEY3 Bit Fields */ -#define NV_BACKKEY3_KEY_MASK 0xFFu -#define NV_BACKKEY3_KEY_SHIFT 0 -#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK) -/* BACKKEY2 Bit Fields */ -#define NV_BACKKEY2_KEY_MASK 0xFFu -#define NV_BACKKEY2_KEY_SHIFT 0 -#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK) -/* BACKKEY1 Bit Fields */ -#define NV_BACKKEY1_KEY_MASK 0xFFu -#define NV_BACKKEY1_KEY_SHIFT 0 -#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK) -/* BACKKEY0 Bit Fields */ -#define NV_BACKKEY0_KEY_MASK 0xFFu -#define NV_BACKKEY0_KEY_SHIFT 0 -#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK) -/* BACKKEY7 Bit Fields */ -#define NV_BACKKEY7_KEY_MASK 0xFFu -#define NV_BACKKEY7_KEY_SHIFT 0 -#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK) -/* BACKKEY6 Bit Fields */ -#define NV_BACKKEY6_KEY_MASK 0xFFu -#define NV_BACKKEY6_KEY_SHIFT 0 -#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK) -/* BACKKEY5 Bit Fields */ -#define NV_BACKKEY5_KEY_MASK 0xFFu -#define NV_BACKKEY5_KEY_SHIFT 0 -#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK) -/* BACKKEY4 Bit Fields */ -#define NV_BACKKEY4_KEY_MASK 0xFFu -#define NV_BACKKEY4_KEY_SHIFT 0 -#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK) -/* FPROT3 Bit Fields */ -#define NV_FPROT3_PROT_MASK 0xFFu -#define NV_FPROT3_PROT_SHIFT 0 -#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK) -/* FPROT2 Bit Fields */ -#define NV_FPROT2_PROT_MASK 0xFFu -#define NV_FPROT2_PROT_SHIFT 0 -#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK) -/* FPROT1 Bit Fields */ -#define NV_FPROT1_PROT_MASK 0xFFu -#define NV_FPROT1_PROT_SHIFT 0 -#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK) -/* FPROT0 Bit Fields */ -#define NV_FPROT0_PROT_MASK 0xFFu -#define NV_FPROT0_PROT_SHIFT 0 -#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK) -/* FSEC Bit Fields */ -#define NV_FSEC_SEC_MASK 0x3u -#define NV_FSEC_SEC_SHIFT 0 -#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK) -#define NV_FSEC_FSLACC_MASK 0xCu -#define NV_FSEC_FSLACC_SHIFT 2 -#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK) -#define NV_FSEC_MEEN_MASK 0x30u -#define NV_FSEC_MEEN_SHIFT 4 -#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK) -#define NV_FSEC_KEYEN_MASK 0xC0u -#define NV_FSEC_KEYEN_SHIFT 6 -#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK) -/* FOPT Bit Fields */ -#define NV_FOPT_LPBOOT_MASK 0x1u -#define NV_FOPT_LPBOOT_SHIFT 0 -#define NV_FOPT_EZPORT_DIS_MASK 0x2u -#define NV_FOPT_EZPORT_DIS_SHIFT 1 -/* FEPROT Bit Fields */ -#define NV_FEPROT_EPROT_MASK 0xFFu -#define NV_FEPROT_EPROT_SHIFT 0 -#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK) -/* FDPROT Bit Fields */ -#define NV_FDPROT_DPROT_MASK 0xFFu -#define NV_FDPROT_DPROT_SHIFT 0 -#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK) - -/** - * @} - */ /* end of group NV_Register_Masks */ - - -/* NV - Peripheral instance base addresses */ -/** Peripheral FTFL_FlashConfig base address */ -#define FTFL_FlashConfig_BASE (0x400u) -/** Peripheral FTFL_FlashConfig base pointer */ -#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE) - -/** - * @} - */ /* end of group NV_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- OSC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer - * @{ - */ - -/** OSC - Register Layout Typedef */ -typedef struct { - __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ -} OSC_Type; - -/* ---------------------------------------------------------------------------- - -- OSC Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup OSC_Register_Masks OSC Register Masks - * @{ - */ - -/* CR Bit Fields */ -#define OSC_CR_SC16P_MASK 0x1u -#define OSC_CR_SC16P_SHIFT 0 -#define OSC_CR_SC8P_MASK 0x2u -#define OSC_CR_SC8P_SHIFT 1 -#define OSC_CR_SC4P_MASK 0x4u -#define OSC_CR_SC4P_SHIFT 2 -#define OSC_CR_SC2P_MASK 0x8u -#define OSC_CR_SC2P_SHIFT 3 -#define OSC_CR_EREFSTEN_MASK 0x20u -#define OSC_CR_EREFSTEN_SHIFT 5 -#define OSC_CR_ERCLKEN_MASK 0x80u -#define OSC_CR_ERCLKEN_SHIFT 7 - -/** - * @} - */ /* end of group OSC_Register_Masks */ - - -/* OSC - Peripheral instance base addresses */ -/** Peripheral OSC0 base address */ -#define OSC0_BASE (0x40065000u) -/** Peripheral OSC0 base pointer */ -#define OSC0 ((OSC_Type *)OSC0_BASE) - -/** - * @} - */ /* end of group OSC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PDB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer - * @{ - */ - -/** PDB - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */ - __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */ - __I uint32_t CNT; /**< Counter Register, offset: 0x8 */ - __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */ - struct { /* offset: 0x10, array step: 0x10 */ - __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */ - __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */ - __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */ - } CH[1]; - uint8_t RESERVED_0[368]; - __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */ - __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */ -} PDB_Type; - -/* ---------------------------------------------------------------------------- - -- PDB Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup PDB_Register_Masks PDB Register Masks - * @{ - */ - -/* SC Bit Fields */ -#define PDB_SC_LDOK_MASK 0x1u -#define PDB_SC_LDOK_SHIFT 0 -#define PDB_SC_CONT_MASK 0x2u -#define PDB_SC_CONT_SHIFT 1 -#define PDB_SC_MULT_MASK 0xCu -#define PDB_SC_MULT_SHIFT 2 -#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK) -#define PDB_SC_PDBIE_MASK 0x20u -#define PDB_SC_PDBIE_SHIFT 5 -#define PDB_SC_PDBIF_MASK 0x40u -#define PDB_SC_PDBIF_SHIFT 6 -#define PDB_SC_PDBEN_MASK 0x80u -#define PDB_SC_PDBEN_SHIFT 7 -#define PDB_SC_TRGSEL_MASK 0xF00u -#define PDB_SC_TRGSEL_SHIFT 8 -#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK) -#define PDB_SC_PRESCALER_MASK 0x7000u -#define PDB_SC_PRESCALER_SHIFT 12 -#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK) -#define PDB_SC_DMAEN_MASK 0x8000u -#define PDB_SC_DMAEN_SHIFT 15 -#define PDB_SC_SWTRIG_MASK 0x10000u -#define PDB_SC_SWTRIG_SHIFT 16 -#define PDB_SC_PDBEIE_MASK 0x20000u -#define PDB_SC_PDBEIE_SHIFT 17 -#define PDB_SC_LDMOD_MASK 0xC0000u -#define PDB_SC_LDMOD_SHIFT 18 -#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK) -/* MOD Bit Fields */ -#define PDB_MOD_MOD_MASK 0xFFFFu -#define PDB_MOD_MOD_SHIFT 0 -#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK) -/* CNT Bit Fields */ -#define PDB_CNT_CNT_MASK 0xFFFFu -#define PDB_CNT_CNT_SHIFT 0 -#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK) -/* IDLY Bit Fields */ -#define PDB_IDLY_IDLY_MASK 0xFFFFu -#define PDB_IDLY_IDLY_SHIFT 0 -#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK) -/* C1 Bit Fields */ -#define PDB_C1_EN_MASK 0xFFu -#define PDB_C1_EN_SHIFT 0 -#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK) -#define PDB_C1_TOS_MASK 0xFF00u -#define PDB_C1_TOS_SHIFT 8 -#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK) -#define PDB_C1_BB_MASK 0xFF0000u -#define PDB_C1_BB_SHIFT 16 -#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK) -/* S Bit Fields */ -#define PDB_S_ERR_MASK 0xFFu -#define PDB_S_ERR_SHIFT 0 -#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK) -#define PDB_S_CF_MASK 0xFF0000u -#define PDB_S_CF_SHIFT 16 -#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK) -/* DLY Bit Fields */ -#define PDB_DLY_DLY_MASK 0xFFFFu -#define PDB_DLY_DLY_SHIFT 0 -#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK) -/* POEN Bit Fields */ -#define PDB_POEN_POEN_MASK 0xFFu -#define PDB_POEN_POEN_SHIFT 0 -#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK) -/* PODLY Bit Fields */ -#define PDB_PODLY_DLY2_MASK 0xFFFFu -#define PDB_PODLY_DLY2_SHIFT 0 -#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK) -#define PDB_PODLY_DLY1_MASK 0xFFFF0000u -#define PDB_PODLY_DLY1_SHIFT 16 -#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK) - -/** - * @} - */ /* end of group PDB_Register_Masks */ - - -/* PDB - Peripheral instance base addresses */ -/** Peripheral PDB0 base address */ -#define PDB0_BASE (0x40036000u) -/** Peripheral PDB0 base pointer */ -#define PDB0 ((PDB_Type *)PDB0_BASE) - -/** - * @} - */ /* end of group PDB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PIT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer - * @{ - */ - -/** PIT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ - uint8_t RESERVED_0[252]; - struct { /* offset: 0x100, array step: 0x10 */ - __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ - __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ - __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ - __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ - } CHANNEL[4]; -} PIT_Type; - -/* ---------------------------------------------------------------------------- - -- PIT Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup PIT_Register_Masks PIT Register Masks - * @{ - */ - -/* MCR Bit Fields */ -#define PIT_MCR_FRZ_MASK 0x1u -#define PIT_MCR_FRZ_SHIFT 0 -#define PIT_MCR_MDIS_MASK 0x2u -#define PIT_MCR_MDIS_SHIFT 1 -/* LDVAL Bit Fields */ -#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu -#define PIT_LDVAL_TSV_SHIFT 0 -#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK) -/* CVAL Bit Fields */ -#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu -#define PIT_CVAL_TVL_SHIFT 0 -#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK) -/* TCTRL Bit Fields */ -#define PIT_TCTRL_TEN_MASK 0x1u -#define PIT_TCTRL_TEN_SHIFT 0 -#define PIT_TCTRL_TIE_MASK 0x2u -#define PIT_TCTRL_TIE_SHIFT 1 -/* TFLG Bit Fields */ -#define PIT_TFLG_TIF_MASK 0x1u -#define PIT_TFLG_TIF_SHIFT 0 - -/** - * @} - */ /* end of group PIT_Register_Masks */ - - -/* PIT - Peripheral instance base addresses */ -/** Peripheral PIT base address */ -#define PIT_BASE (0x40037000u) -/** Peripheral PIT base pointer */ -#define PIT ((PIT_Type *)PIT_BASE) - -/** - * @} - */ /* end of group PIT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer - * @{ - */ - -/** PMC - Register Layout Typedef */ -typedef struct { - __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */ - __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */ - __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */ -} PMC_Type; - -/* ---------------------------------------------------------------------------- - -- PMC Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup PMC_Register_Masks PMC Register Masks - * @{ - */ - -/* LVDSC1 Bit Fields */ -#define PMC_LVDSC1_LVDV_MASK 0x3u -#define PMC_LVDSC1_LVDV_SHIFT 0 -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) -#define PMC_LVDSC1_LVDRE_MASK 0x10u -#define PMC_LVDSC1_LVDRE_SHIFT 4 -#define PMC_LVDSC1_LVDIE_MASK 0x20u -#define PMC_LVDSC1_LVDIE_SHIFT 5 -#define PMC_LVDSC1_LVDACK_MASK 0x40u -#define PMC_LVDSC1_LVDACK_SHIFT 6 -#define PMC_LVDSC1_LVDF_MASK 0x80u -#define PMC_LVDSC1_LVDF_SHIFT 7 -/* LVDSC2 Bit Fields */ -#define PMC_LVDSC2_LVWV_MASK 0x3u -#define PMC_LVDSC2_LVWV_SHIFT 0 -#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) -#define PMC_LVDSC2_LVWIE_MASK 0x20u -#define PMC_LVDSC2_LVWIE_SHIFT 5 -#define PMC_LVDSC2_LVWACK_MASK 0x40u -#define PMC_LVDSC2_LVWACK_SHIFT 6 -#define PMC_LVDSC2_LVWF_MASK 0x80u -#define PMC_LVDSC2_LVWF_SHIFT 7 -/* REGSC Bit Fields */ -#define PMC_REGSC_BGBE_MASK 0x1u -#define PMC_REGSC_BGBE_SHIFT 0 -#define PMC_REGSC_REGONS_MASK 0x4u -#define PMC_REGSC_REGONS_SHIFT 2 -#define PMC_REGSC_ACKISO_MASK 0x8u -#define PMC_REGSC_ACKISO_SHIFT 3 - -/** - * @} - */ /* end of group PMC_Register_Masks */ - - -/* PMC - Peripheral instance base addresses */ -/** Peripheral PMC base address */ -#define PMC_BASE (0x4007D000u) -/** Peripheral PMC base pointer */ -#define PMC ((PMC_Type *)PMC_BASE) - -/** - * @} - */ /* end of group PMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PORT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer - * @{ - */ - -/** PORT - Register Layout Typedef */ -typedef struct { - __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ - __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ - __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ - uint8_t RESERVED_0[24]; - __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ - uint8_t RESERVED_1[28]; - __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ - __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ - __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ -} PORT_Type; - -/* ---------------------------------------------------------------------------- - -- PORT Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup PORT_Register_Masks PORT Register Masks - * @{ - */ - -/* PCR Bit Fields */ -#define PORT_PCR_PS_MASK 0x1u -#define PORT_PCR_PS_SHIFT 0 -#define PORT_PCR_PE_MASK 0x2u -#define PORT_PCR_PE_SHIFT 1 -#define PORT_PCR_SRE_MASK 0x4u -#define PORT_PCR_SRE_SHIFT 2 -#define PORT_PCR_PFE_MASK 0x10u -#define PORT_PCR_PFE_SHIFT 4 -#define PORT_PCR_ODE_MASK 0x20u -#define PORT_PCR_ODE_SHIFT 5 -#define PORT_PCR_DSE_MASK 0x40u -#define PORT_PCR_DSE_SHIFT 6 -#define PORT_PCR_MUX_MASK 0x700u -#define PORT_PCR_MUX_SHIFT 8 -#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK) -#define PORT_PCR_LK_MASK 0x8000u -#define PORT_PCR_LK_SHIFT 15 -#define PORT_PCR_IRQC_MASK 0xF0000u -#define PORT_PCR_IRQC_SHIFT 16 -#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK) -#define PORT_PCR_ISF_MASK 0x1000000u -#define PORT_PCR_ISF_SHIFT 24 -/* GPCLR Bit Fields */ -#define PORT_GPCLR_GPWD_MASK 0xFFFFu -#define PORT_GPCLR_GPWD_SHIFT 0 -#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK) -#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u -#define PORT_GPCLR_GPWE_SHIFT 16 -#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK) -/* GPCHR Bit Fields */ -#define PORT_GPCHR_GPWD_MASK 0xFFFFu -#define PORT_GPCHR_GPWD_SHIFT 0 -#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK) -#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u -#define PORT_GPCHR_GPWE_SHIFT 16 -#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK) -/* ISFR Bit Fields */ -#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu -#define PORT_ISFR_ISF_SHIFT 0 -#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK) -/* DFER Bit Fields */ -#define PORT_DFER_DFE_MASK 0xFFFFFFFFu -#define PORT_DFER_DFE_SHIFT 0 -#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK) -/* DFCR Bit Fields */ -#define PORT_DFCR_CS_MASK 0x1u -#define PORT_DFCR_CS_SHIFT 0 -/* DFWR Bit Fields */ -#define PORT_DFWR_FILT_MASK 0x1Fu -#define PORT_DFWR_FILT_SHIFT 0 -#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK) - -/** - * @} - */ /* end of group PORT_Register_Masks */ - - -/* PORT - Peripheral instance base addresses */ -/** Peripheral PORTA base address */ -#define PORTA_BASE (0x40049000u) -/** Peripheral PORTA base pointer */ -#define PORTA ((PORT_Type *)PORTA_BASE) -/** Peripheral PORTB base address */ -#define PORTB_BASE (0x4004A000u) -/** Peripheral PORTB base pointer */ -#define PORTB ((PORT_Type *)PORTB_BASE) -/** Peripheral PORTC base address */ -#define PORTC_BASE (0x4004B000u) -/** Peripheral PORTC base pointer */ -#define PORTC ((PORT_Type *)PORTC_BASE) -/** Peripheral PORTD base address */ -#define PORTD_BASE (0x4004C000u) -/** Peripheral PORTD base pointer */ -#define PORTD ((PORT_Type *)PORTD_BASE) -/** Peripheral PORTE base address */ -#define PORTE_BASE (0x4004D000u) -/** Peripheral PORTE base pointer */ -#define PORTE ((PORT_Type *)PORTE_BASE) - -/** - * @} - */ /* end of group PORT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RCM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer - * @{ - */ - -/** RCM - Register Layout Typedef */ -typedef struct { - __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ - __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ - uint8_t RESERVED_0[2]; - __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */ - __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */ - uint8_t RESERVED_1[1]; - __I uint8_t MR; /**< Mode Register, offset: 0x7 */ -} RCM_Type; - -/* ---------------------------------------------------------------------------- - -- RCM Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup RCM_Register_Masks RCM Register Masks - * @{ - */ - -/* SRS0 Bit Fields */ -#define RCM_SRS0_WAKEUP_MASK 0x1u -#define RCM_SRS0_WAKEUP_SHIFT 0 -#define RCM_SRS0_LVD_MASK 0x2u -#define RCM_SRS0_LVD_SHIFT 1 -#define RCM_SRS0_LOC_MASK 0x4u -#define RCM_SRS0_LOC_SHIFT 2 -#define RCM_SRS0_LOL_MASK 0x8u -#define RCM_SRS0_LOL_SHIFT 3 -#define RCM_SRS0_WDOG_MASK 0x20u -#define RCM_SRS0_WDOG_SHIFT 5 -#define RCM_SRS0_PIN_MASK 0x40u -#define RCM_SRS0_PIN_SHIFT 6 -#define RCM_SRS0_POR_MASK 0x80u -#define RCM_SRS0_POR_SHIFT 7 -/* SRS1 Bit Fields */ -#define RCM_SRS1_JTAG_MASK 0x1u -#define RCM_SRS1_JTAG_SHIFT 0 -#define RCM_SRS1_LOCKUP_MASK 0x2u -#define RCM_SRS1_LOCKUP_SHIFT 1 -#define RCM_SRS1_SW_MASK 0x4u -#define RCM_SRS1_SW_SHIFT 2 -#define RCM_SRS1_MDM_AP_MASK 0x8u -#define RCM_SRS1_MDM_AP_SHIFT 3 -#define RCM_SRS1_EZPT_MASK 0x10u -#define RCM_SRS1_EZPT_SHIFT 4 -#define RCM_SRS1_SACKERR_MASK 0x20u -#define RCM_SRS1_SACKERR_SHIFT 5 -/* RPFC Bit Fields */ -#define RCM_RPFC_RSTFLTSRW_MASK 0x3u -#define RCM_RPFC_RSTFLTSRW_SHIFT 0 -#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK) -#define RCM_RPFC_RSTFLTSS_MASK 0x4u -#define RCM_RPFC_RSTFLTSS_SHIFT 2 -/* RPFW Bit Fields */ -#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu -#define RCM_RPFW_RSTFLTSEL_SHIFT 0 -#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK) -/* MR Bit Fields */ -#define RCM_MR_EZP_MS_MASK 0x2u -#define RCM_MR_EZP_MS_SHIFT 1 - -/** - * @} - */ /* end of group RCM_Register_Masks */ - - -/* RCM - Peripheral instance base addresses */ -/** Peripheral RCM base address */ -#define RCM_BASE (0x4007F000u) -/** Peripheral RCM base pointer */ -#define RCM ((RCM_Type *)RCM_BASE) - -/** - * @} - */ /* end of group RCM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RFSYS Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer - * @{ - */ - -/** RFSYS - Register Layout Typedef */ -typedef struct { - __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ -} RFSYS_Type; - -/* ---------------------------------------------------------------------------- - -- RFSYS Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup RFSYS_Register_Masks RFSYS Register Masks - * @{ - */ - -/* REG Bit Fields */ -#define RFSYS_REG_LL_MASK 0xFFu -#define RFSYS_REG_LL_SHIFT 0 -#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK) -#define RFSYS_REG_LH_MASK 0xFF00u -#define RFSYS_REG_LH_SHIFT 8 -#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK) -#define RFSYS_REG_HL_MASK 0xFF0000u -#define RFSYS_REG_HL_SHIFT 16 -#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK) -#define RFSYS_REG_HH_MASK 0xFF000000u -#define RFSYS_REG_HH_SHIFT 24 -#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK) - -/** - * @} - */ /* end of group RFSYS_Register_Masks */ - - -/* RFSYS - Peripheral instance base addresses */ -/** Peripheral RFSYS base address */ -#define RFSYS_BASE (0x40041000u) -/** Peripheral RFSYS base pointer */ -#define RFSYS ((RFSYS_Type *)RFSYS_BASE) - -/** - * @} - */ /* end of group RFSYS_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RFVBAT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer - * @{ - */ - -/** RFVBAT - Register Layout Typedef */ -typedef struct { - __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */ -} RFVBAT_Type; - -/* ---------------------------------------------------------------------------- - -- RFVBAT Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks - * @{ - */ - -/* REG Bit Fields */ -#define RFVBAT_REG_LL_MASK 0xFFu -#define RFVBAT_REG_LL_SHIFT 0 -#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK) -#define RFVBAT_REG_LH_MASK 0xFF00u -#define RFVBAT_REG_LH_SHIFT 8 -#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK) -#define RFVBAT_REG_HL_MASK 0xFF0000u -#define RFVBAT_REG_HL_SHIFT 16 -#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK) -#define RFVBAT_REG_HH_MASK 0xFF000000u -#define RFVBAT_REG_HH_SHIFT 24 -#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK) - -/** - * @} - */ /* end of group RFVBAT_Register_Masks */ - - -/* RFVBAT - Peripheral instance base addresses */ -/** Peripheral RFVBAT base address */ -#define RFVBAT_BASE (0x4003E000u) -/** Peripheral RFVBAT base pointer */ -#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE) - -/** - * @} - */ /* end of group RFVBAT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ - __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ - __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ - __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ - __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ - __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ - __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ - __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ - uint8_t RESERVED_0[2016]; - __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ - __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/* TSR Bit Fields */ -#define RTC_TSR_TSR_MASK 0xFFFFFFFFu -#define RTC_TSR_TSR_SHIFT 0 -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK) -/* TPR Bit Fields */ -#define RTC_TPR_TPR_MASK 0xFFFFu -#define RTC_TPR_TPR_SHIFT 0 -#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK) -/* TAR Bit Fields */ -#define RTC_TAR_TAR_MASK 0xFFFFFFFFu -#define RTC_TAR_TAR_SHIFT 0 -#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK) -/* TCR Bit Fields */ -#define RTC_TCR_TCR_MASK 0xFFu -#define RTC_TCR_TCR_SHIFT 0 -#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK) -#define RTC_TCR_CIR_MASK 0xFF00u -#define RTC_TCR_CIR_SHIFT 8 -#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK) -#define RTC_TCR_TCV_MASK 0xFF0000u -#define RTC_TCR_TCV_SHIFT 16 -#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK) -#define RTC_TCR_CIC_MASK 0xFF000000u -#define RTC_TCR_CIC_SHIFT 24 -#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK) -/* CR Bit Fields */ -#define RTC_CR_SWR_MASK 0x1u -#define RTC_CR_SWR_SHIFT 0 -#define RTC_CR_WPE_MASK 0x2u -#define RTC_CR_WPE_SHIFT 1 -#define RTC_CR_SUP_MASK 0x4u -#define RTC_CR_SUP_SHIFT 2 -#define RTC_CR_UM_MASK 0x8u -#define RTC_CR_UM_SHIFT 3 -#define RTC_CR_OSCE_MASK 0x100u -#define RTC_CR_OSCE_SHIFT 8 -#define RTC_CR_CLKO_MASK 0x200u -#define RTC_CR_CLKO_SHIFT 9 -#define RTC_CR_SC16P_MASK 0x400u -#define RTC_CR_SC16P_SHIFT 10 -#define RTC_CR_SC8P_MASK 0x800u -#define RTC_CR_SC8P_SHIFT 11 -#define RTC_CR_SC4P_MASK 0x1000u -#define RTC_CR_SC4P_SHIFT 12 -#define RTC_CR_SC2P_MASK 0x2000u -#define RTC_CR_SC2P_SHIFT 13 -/* SR Bit Fields */ -#define RTC_SR_TIF_MASK 0x1u -#define RTC_SR_TIF_SHIFT 0 -#define RTC_SR_TOF_MASK 0x2u -#define RTC_SR_TOF_SHIFT 1 -#define RTC_SR_TAF_MASK 0x4u -#define RTC_SR_TAF_SHIFT 2 -#define RTC_SR_TCE_MASK 0x10u -#define RTC_SR_TCE_SHIFT 4 -/* LR Bit Fields */ -#define RTC_LR_TCL_MASK 0x8u -#define RTC_LR_TCL_SHIFT 3 -#define RTC_LR_CRL_MASK 0x10u -#define RTC_LR_CRL_SHIFT 4 -#define RTC_LR_SRL_MASK 0x20u -#define RTC_LR_SRL_SHIFT 5 -#define RTC_LR_LRL_MASK 0x40u -#define RTC_LR_LRL_SHIFT 6 -/* IER Bit Fields */ -#define RTC_IER_TIIE_MASK 0x1u -#define RTC_IER_TIIE_SHIFT 0 -#define RTC_IER_TOIE_MASK 0x2u -#define RTC_IER_TOIE_SHIFT 1 -#define RTC_IER_TAIE_MASK 0x4u -#define RTC_IER_TAIE_SHIFT 2 -#define RTC_IER_TSIE_MASK 0x10u -#define RTC_IER_TSIE_SHIFT 4 -/* WAR Bit Fields */ -#define RTC_WAR_TSRW_MASK 0x1u -#define RTC_WAR_TSRW_SHIFT 0 -#define RTC_WAR_TPRW_MASK 0x2u -#define RTC_WAR_TPRW_SHIFT 1 -#define RTC_WAR_TARW_MASK 0x4u -#define RTC_WAR_TARW_SHIFT 2 -#define RTC_WAR_TCRW_MASK 0x8u -#define RTC_WAR_TCRW_SHIFT 3 -#define RTC_WAR_CRW_MASK 0x10u -#define RTC_WAR_CRW_SHIFT 4 -#define RTC_WAR_SRW_MASK 0x20u -#define RTC_WAR_SRW_SHIFT 5 -#define RTC_WAR_LRW_MASK 0x40u -#define RTC_WAR_LRW_SHIFT 6 -#define RTC_WAR_IERW_MASK 0x80u -#define RTC_WAR_IERW_SHIFT 7 -/* RAR Bit Fields */ -#define RTC_RAR_TSRR_MASK 0x1u -#define RTC_RAR_TSRR_SHIFT 0 -#define RTC_RAR_TPRR_MASK 0x2u -#define RTC_RAR_TPRR_SHIFT 1 -#define RTC_RAR_TARR_MASK 0x4u -#define RTC_RAR_TARR_SHIFT 2 -#define RTC_RAR_TCRR_MASK 0x8u -#define RTC_RAR_TCRR_SHIFT 3 -#define RTC_RAR_CRR_MASK 0x10u -#define RTC_RAR_CRR_SHIFT 4 -#define RTC_RAR_SRR_MASK 0x20u -#define RTC_RAR_SRR_SHIFT 5 -#define RTC_RAR_LRR_MASK 0x40u -#define RTC_RAR_LRR_SHIFT 6 -#define RTC_RAR_IERR_MASK 0x80u -#define RTC_RAR_IERR_SHIFT 7 - -/** - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -/** Peripheral RTC base address */ -#define RTC_BASE (0x4003D000u) -/** Peripheral RTC base pointer */ -#define RTC ((RTC_Type *)RTC_BASE) - -/** - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SIM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer - * @{ - */ - -/** SIM - Register Layout Typedef */ -typedef struct { - __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ - __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ - uint8_t RESERVED_0[4092]; - __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ - uint8_t RESERVED_1[4]; - __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ - __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ - uint8_t RESERVED_2[4]; - __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ - uint8_t RESERVED_3[8]; - __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ - uint8_t RESERVED_4[12]; - __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ - __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ - __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ - __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ - __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ - __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */ - __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ - __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ - __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */ - __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ - __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ - __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ -} SIM_Type; - -/* ---------------------------------------------------------------------------- - -- SIM Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup SIM_Register_Masks SIM Register Masks - * @{ - */ - -/* SOPT1 Bit Fields */ -#define SIM_SOPT1_RAMSIZE_MASK 0xF000u -#define SIM_SOPT1_RAMSIZE_SHIFT 12 -#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK) -#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u -#define SIM_SOPT1_OSC32KSEL_SHIFT 18 -#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK) -#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u -#define SIM_SOPT1_USBVSTBY_SHIFT 29 -#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u -#define SIM_SOPT1_USBSSTBY_SHIFT 30 -#define SIM_SOPT1_USBREGEN_MASK 0x80000000u -#define SIM_SOPT1_USBREGEN_SHIFT 31 -/* SOPT1CFG Bit Fields */ -#define SIM_SOPT1CFG_URWE_MASK 0x1000000u -#define SIM_SOPT1CFG_URWE_SHIFT 24 -#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u -#define SIM_SOPT1CFG_UVSWE_SHIFT 25 -#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u -#define SIM_SOPT1CFG_USSWE_SHIFT 26 -/* SOPT2 Bit Fields */ -#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u -#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4 -#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u -#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 -#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK) -#define SIM_SOPT2_PTD7PAD_MASK 0x800u -#define SIM_SOPT2_PTD7PAD_SHIFT 11 -#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u -#define SIM_SOPT2_TRACECLKSEL_SHIFT 12 -#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u -#define SIM_SOPT2_PLLFLLSEL_SHIFT 16 -#define SIM_SOPT2_USBSRC_MASK 0x40000u -#define SIM_SOPT2_USBSRC_SHIFT 18 -/* SOPT4 Bit Fields */ -#define SIM_SOPT4_FTM0FLT0_MASK 0x1u -#define SIM_SOPT4_FTM0FLT0_SHIFT 0 -#define SIM_SOPT4_FTM0FLT1_MASK 0x2u -#define SIM_SOPT4_FTM0FLT1_SHIFT 1 -#define SIM_SOPT4_FTM1FLT0_MASK 0x10u -#define SIM_SOPT4_FTM1FLT0_SHIFT 4 -#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u -#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18 -#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK) -#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u -#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24 -#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u -#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25 -#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u -#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28 -/* SOPT5 Bit Fields */ -#define SIM_SOPT5_UART0TXSRC_MASK 0x1u -#define SIM_SOPT5_UART0TXSRC_SHIFT 0 -#define SIM_SOPT5_UART0RXSRC_MASK 0xCu -#define SIM_SOPT5_UART0RXSRC_SHIFT 2 -#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK) -#define SIM_SOPT5_UART1TXSRC_MASK 0x10u -#define SIM_SOPT5_UART1TXSRC_SHIFT 4 -#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u -#define SIM_SOPT5_UART1RXSRC_SHIFT 6 -#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK) -/* SOPT7 Bit Fields */ -#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu -#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 -#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK) -#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u -#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4 -#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u -#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7 -/* SDID Bit Fields */ -#define SIM_SDID_PINID_MASK 0xFu -#define SIM_SDID_PINID_SHIFT 0 -#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK) -#define SIM_SDID_FAMID_MASK 0x70u -#define SIM_SDID_FAMID_SHIFT 4 -#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK) -#define SIM_SDID_REVID_MASK 0xF000u -#define SIM_SDID_REVID_SHIFT 12 -#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK) -/* SCGC4 Bit Fields */ -#define SIM_SCGC4_EWM_MASK 0x2u -#define SIM_SCGC4_EWM_SHIFT 1 -#define SIM_SCGC4_CMT_MASK 0x4u -#define SIM_SCGC4_CMT_SHIFT 2 -#define SIM_SCGC4_I2C0_MASK 0x40u -#define SIM_SCGC4_I2C0_SHIFT 6 -#define SIM_SCGC4_UART0_MASK 0x400u -#define SIM_SCGC4_UART0_SHIFT 10 -#define SIM_SCGC4_UART1_MASK 0x800u -#define SIM_SCGC4_UART1_SHIFT 11 -#define SIM_SCGC4_UART2_MASK 0x1000u -#define SIM_SCGC4_UART2_SHIFT 12 -#define SIM_SCGC4_USBOTG_MASK 0x40000u -#define SIM_SCGC4_USBOTG_SHIFT 18 -#define SIM_SCGC4_CMP_MASK 0x80000u -#define SIM_SCGC4_CMP_SHIFT 19 -#define SIM_SCGC4_VREF_MASK 0x100000u -#define SIM_SCGC4_VREF_SHIFT 20 -/* SCGC5 Bit Fields */ -#define SIM_SCGC5_LPTIMER_MASK 0x1u -#define SIM_SCGC5_LPTIMER_SHIFT 0 -#define SIM_SCGC5_TSI_MASK 0x20u -#define SIM_SCGC5_TSI_SHIFT 5 -#define SIM_SCGC5_PORTA_MASK 0x200u -#define SIM_SCGC5_PORTA_SHIFT 9 -#define SIM_SCGC5_PORTB_MASK 0x400u -#define SIM_SCGC5_PORTB_SHIFT 10 -#define SIM_SCGC5_PORTC_MASK 0x800u -#define SIM_SCGC5_PORTC_SHIFT 11 -#define SIM_SCGC5_PORTD_MASK 0x1000u -#define SIM_SCGC5_PORTD_SHIFT 12 -#define SIM_SCGC5_PORTE_MASK 0x2000u -#define SIM_SCGC5_PORTE_SHIFT 13 -/* SCGC6 Bit Fields */ -#define SIM_SCGC6_FTFL_MASK 0x1u -#define SIM_SCGC6_FTFL_SHIFT 0 -#define SIM_SCGC6_DMAMUX_MASK 0x2u -#define SIM_SCGC6_DMAMUX_SHIFT 1 -#define SIM_SCGC6_SPI0_MASK 0x1000u -#define SIM_SCGC6_SPI0_SHIFT 12 -#define SIM_SCGC6_I2S_MASK 0x8000u -#define SIM_SCGC6_I2S_SHIFT 15 -#define SIM_SCGC6_CRC_MASK 0x40000u -#define SIM_SCGC6_CRC_SHIFT 18 -#define SIM_SCGC6_USBDCD_MASK 0x200000u -#define SIM_SCGC6_USBDCD_SHIFT 21 -#define SIM_SCGC6_PDB_MASK 0x400000u -#define SIM_SCGC6_PDB_SHIFT 22 -#define SIM_SCGC6_PIT_MASK 0x800000u -#define SIM_SCGC6_PIT_SHIFT 23 -#define SIM_SCGC6_FTM0_MASK 0x1000000u -#define SIM_SCGC6_FTM0_SHIFT 24 -#define SIM_SCGC6_FTM1_MASK 0x2000000u -#define SIM_SCGC6_FTM1_SHIFT 25 -#define SIM_SCGC6_ADC0_MASK 0x8000000u -#define SIM_SCGC6_ADC0_SHIFT 27 -#define SIM_SCGC6_RTC_MASK 0x20000000u -#define SIM_SCGC6_RTC_SHIFT 29 -/* SCGC7 Bit Fields */ -#define SIM_SCGC7_DMA_MASK 0x2u -#define SIM_SCGC7_DMA_SHIFT 1 -/* CLKDIV1 Bit Fields */ -#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u -#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 -#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK) -#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u -#define SIM_CLKDIV1_OUTDIV2_SHIFT 24 -#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK) -#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u -#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 -#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK) -/* CLKDIV2 Bit Fields */ -#define SIM_CLKDIV2_USBFRAC_MASK 0x1u -#define SIM_CLKDIV2_USBFRAC_SHIFT 0 -#define SIM_CLKDIV2_USBDIV_MASK 0xEu -#define SIM_CLKDIV2_USBDIV_SHIFT 1 -#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK) -/* FCFG1 Bit Fields */ -#define SIM_FCFG1_FLASHDIS_MASK 0x1u -#define SIM_FCFG1_FLASHDIS_SHIFT 0 -#define SIM_FCFG1_FLASHDOZE_MASK 0x2u -#define SIM_FCFG1_FLASHDOZE_SHIFT 1 -#define SIM_FCFG1_DEPART_MASK 0xF00u -#define SIM_FCFG1_DEPART_SHIFT 8 -#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK) -#define SIM_FCFG1_EESIZE_MASK 0xF0000u -#define SIM_FCFG1_EESIZE_SHIFT 16 -#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK) -#define SIM_FCFG1_PFSIZE_MASK 0xF000000u -#define SIM_FCFG1_PFSIZE_SHIFT 24 -#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK) -#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u -#define SIM_FCFG1_NVMSIZE_SHIFT 28 -#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK) -/* FCFG2 Bit Fields */ -#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u -#define SIM_FCFG2_MAXADDR1_SHIFT 16 -#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK) -#define SIM_FCFG2_PFLSH_MASK 0x800000u -#define SIM_FCFG2_PFLSH_SHIFT 23 -#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u -#define SIM_FCFG2_MAXADDR0_SHIFT 24 -#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK) -/* UIDH Bit Fields */ -#define SIM_UIDH_UID_MASK 0xFFFFFFFFu -#define SIM_UIDH_UID_SHIFT 0 -#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK) -/* UIDMH Bit Fields */ -#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu -#define SIM_UIDMH_UID_SHIFT 0 -#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK) -/* UIDML Bit Fields */ -#define SIM_UIDML_UID_MASK 0xFFFFFFFFu -#define SIM_UIDML_UID_SHIFT 0 -#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK) -/* UIDL Bit Fields */ -#define SIM_UIDL_UID_MASK 0xFFFFFFFFu -#define SIM_UIDL_UID_SHIFT 0 -#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK) - -/** - * @} - */ /* end of group SIM_Register_Masks */ - - -/* SIM - Peripheral instance base addresses */ -/** Peripheral SIM base address */ -#define SIM_BASE (0x40047000u) -/** Peripheral SIM base pointer */ -#define SIM ((SIM_Type *)SIM_BASE) - -/** - * @} - */ /* end of group SIM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer - * @{ - */ - -/** SMC - Register Layout Typedef */ -typedef struct { - __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */ - __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */ - __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */ - __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */ -} SMC_Type; - -/* ---------------------------------------------------------------------------- - -- SMC Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup SMC_Register_Masks SMC Register Masks - * @{ - */ - -/* PMPROT Bit Fields */ -#define SMC_PMPROT_AVLLS_MASK 0x2u -#define SMC_PMPROT_AVLLS_SHIFT 1 -#define SMC_PMPROT_ALLS_MASK 0x8u -#define SMC_PMPROT_ALLS_SHIFT 3 -#define SMC_PMPROT_AVLP_MASK 0x20u -#define SMC_PMPROT_AVLP_SHIFT 5 -/* PMCTRL Bit Fields */ -#define SMC_PMCTRL_STOPM_MASK 0x7u -#define SMC_PMCTRL_STOPM_SHIFT 0 -#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK) -#define SMC_PMCTRL_STOPA_MASK 0x8u -#define SMC_PMCTRL_STOPA_SHIFT 3 -#define SMC_PMCTRL_RUNM_MASK 0x60u -#define SMC_PMCTRL_RUNM_SHIFT 5 -#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK) -#define SMC_PMCTRL_LPWUI_MASK 0x80u -#define SMC_PMCTRL_LPWUI_SHIFT 7 -/* VLLSCTRL Bit Fields */ -#define SMC_VLLSCTRL_VLLSM_MASK 0x7u -#define SMC_VLLSCTRL_VLLSM_SHIFT 0 -#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK) -#define SMC_VLLSCTRL_PORPO_MASK 0x20u -#define SMC_VLLSCTRL_PORPO_SHIFT 5 -/* PMSTAT Bit Fields */ -#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu -#define SMC_PMSTAT_PMSTAT_SHIFT 0 -#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK) - -/** - * @} - */ /* end of group SMC_Register_Masks */ - - -/* SMC - Peripheral instance base addresses */ -/** Peripheral SMC base address */ -#define SMC_BASE (0x4007E000u) -/** Peripheral SMC base pointer */ -#define SMC ((SMC_Type *)SMC_BASE) - -/** - * @} - */ /* end of group SMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */ - uint8_t RESERVED_0[4]; - __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */ - union { /* offset: 0xC */ - __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ - __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ - }; - uint8_t RESERVED_1[24]; - __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */ - __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ - union { /* offset: 0x34 */ - __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */ - __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ - }; - __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */ - __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */ - __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */ - __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */ - __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */ - uint8_t RESERVED_2[48]; - __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */ - __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */ - __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */ - __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/* MCR Bit Fields */ -#define SPI_MCR_HALT_MASK 0x1u -#define SPI_MCR_HALT_SHIFT 0 -#define SPI_MCR_SMPL_PT_MASK 0x300u -#define SPI_MCR_SMPL_PT_SHIFT 8 -#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK) -#define SPI_MCR_CLR_RXF_MASK 0x400u -#define SPI_MCR_CLR_RXF_SHIFT 10 -#define SPI_MCR_CLR_TXF_MASK 0x800u -#define SPI_MCR_CLR_TXF_SHIFT 11 -#define SPI_MCR_DIS_RXF_MASK 0x1000u -#define SPI_MCR_DIS_RXF_SHIFT 12 -#define SPI_MCR_DIS_TXF_MASK 0x2000u -#define SPI_MCR_DIS_TXF_SHIFT 13 -#define SPI_MCR_MDIS_MASK 0x4000u -#define SPI_MCR_MDIS_SHIFT 14 -#define SPI_MCR_DOZE_MASK 0x8000u -#define SPI_MCR_DOZE_SHIFT 15 -#define SPI_MCR_PCSIS_MASK 0x3F0000u -#define SPI_MCR_PCSIS_SHIFT 16 -#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK) -#define SPI_MCR_ROOE_MASK 0x1000000u -#define SPI_MCR_ROOE_SHIFT 24 -#define SPI_MCR_PCSSE_MASK 0x2000000u -#define SPI_MCR_PCSSE_SHIFT 25 -#define SPI_MCR_MTFE_MASK 0x4000000u -#define SPI_MCR_MTFE_SHIFT 26 -#define SPI_MCR_FRZ_MASK 0x8000000u -#define SPI_MCR_FRZ_SHIFT 27 -#define SPI_MCR_DCONF_MASK 0x30000000u -#define SPI_MCR_DCONF_SHIFT 28 -#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK) -#define SPI_MCR_CONT_SCKE_MASK 0x40000000u -#define SPI_MCR_CONT_SCKE_SHIFT 30 -#define SPI_MCR_MSTR_MASK 0x80000000u -#define SPI_MCR_MSTR_SHIFT 31 -/* TCR Bit Fields */ -#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u -#define SPI_TCR_SPI_TCNT_SHIFT 16 -#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK) -/* CTAR Bit Fields */ -#define SPI_CTAR_BR_MASK 0xFu -#define SPI_CTAR_BR_SHIFT 0 -#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK) -#define SPI_CTAR_DT_MASK 0xF0u -#define SPI_CTAR_DT_SHIFT 4 -#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK) -#define SPI_CTAR_ASC_MASK 0xF00u -#define SPI_CTAR_ASC_SHIFT 8 -#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK) -#define SPI_CTAR_CSSCK_MASK 0xF000u -#define SPI_CTAR_CSSCK_SHIFT 12 -#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK) -#define SPI_CTAR_PBR_MASK 0x30000u -#define SPI_CTAR_PBR_SHIFT 16 -#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK) -#define SPI_CTAR_PDT_MASK 0xC0000u -#define SPI_CTAR_PDT_SHIFT 18 -#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK) -#define SPI_CTAR_PASC_MASK 0x300000u -#define SPI_CTAR_PASC_SHIFT 20 -#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK) -#define SPI_CTAR_PCSSCK_MASK 0xC00000u -#define SPI_CTAR_PCSSCK_SHIFT 22 -#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK) -#define SPI_CTAR_LSBFE_MASK 0x1000000u -#define SPI_CTAR_LSBFE_SHIFT 24 -#define SPI_CTAR_CPHA_MASK 0x2000000u -#define SPI_CTAR_CPHA_SHIFT 25 -#define SPI_CTAR_CPOL_MASK 0x4000000u -#define SPI_CTAR_CPOL_SHIFT 26 -#define SPI_CTAR_FMSZ_MASK 0x78000000u -#define SPI_CTAR_FMSZ_SHIFT 27 -#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK) -#define SPI_CTAR_DBR_MASK 0x80000000u -#define SPI_CTAR_DBR_SHIFT 31 -/* CTAR_SLAVE Bit Fields */ -#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u -#define SPI_CTAR_SLAVE_CPHA_SHIFT 25 -#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u -#define SPI_CTAR_SLAVE_CPOL_SHIFT 26 -#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u -#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27 -#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK) -/* SR Bit Fields */ -#define SPI_SR_POPNXTPTR_MASK 0xFu -#define SPI_SR_POPNXTPTR_SHIFT 0 -#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK) -#define SPI_SR_RXCTR_MASK 0xF0u -#define SPI_SR_RXCTR_SHIFT 4 -#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK) -#define SPI_SR_TXNXTPTR_MASK 0xF00u -#define SPI_SR_TXNXTPTR_SHIFT 8 -#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK) -#define SPI_SR_TXCTR_MASK 0xF000u -#define SPI_SR_TXCTR_SHIFT 12 -#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK) -#define SPI_SR_RFDF_MASK 0x20000u -#define SPI_SR_RFDF_SHIFT 17 -#define SPI_SR_RFOF_MASK 0x80000u -#define SPI_SR_RFOF_SHIFT 19 -#define SPI_SR_TFFF_MASK 0x2000000u -#define SPI_SR_TFFF_SHIFT 25 -#define SPI_SR_TFUF_MASK 0x8000000u -#define SPI_SR_TFUF_SHIFT 27 -#define SPI_SR_EOQF_MASK 0x10000000u -#define SPI_SR_EOQF_SHIFT 28 -#define SPI_SR_TXRXS_MASK 0x40000000u -#define SPI_SR_TXRXS_SHIFT 30 -#define SPI_SR_TCF_MASK 0x80000000u -#define SPI_SR_TCF_SHIFT 31 -/* RSER Bit Fields */ -#define SPI_RSER_RFDF_DIRS_MASK 0x10000u -#define SPI_RSER_RFDF_DIRS_SHIFT 16 -#define SPI_RSER_RFDF_RE_MASK 0x20000u -#define SPI_RSER_RFDF_RE_SHIFT 17 -#define SPI_RSER_RFOF_RE_MASK 0x80000u -#define SPI_RSER_RFOF_RE_SHIFT 19 -#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u -#define SPI_RSER_TFFF_DIRS_SHIFT 24 -#define SPI_RSER_TFFF_RE_MASK 0x2000000u -#define SPI_RSER_TFFF_RE_SHIFT 25 -#define SPI_RSER_TFUF_RE_MASK 0x8000000u -#define SPI_RSER_TFUF_RE_SHIFT 27 -#define SPI_RSER_EOQF_RE_MASK 0x10000000u -#define SPI_RSER_EOQF_RE_SHIFT 28 -#define SPI_RSER_TCF_RE_MASK 0x80000000u -#define SPI_RSER_TCF_RE_SHIFT 31 -/* PUSHR Bit Fields */ -#define SPI_PUSHR_TXDATA_MASK 0xFFFFu -#define SPI_PUSHR_TXDATA_SHIFT 0 -#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK) -#define SPI_PUSHR_PCS_MASK 0x3F0000u -#define SPI_PUSHR_PCS_SHIFT 16 -#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK) -#define SPI_PUSHR_CTCNT_MASK 0x4000000u -#define SPI_PUSHR_CTCNT_SHIFT 26 -#define SPI_PUSHR_EOQ_MASK 0x8000000u -#define SPI_PUSHR_EOQ_SHIFT 27 -#define SPI_PUSHR_CTAS_MASK 0x70000000u -#define SPI_PUSHR_CTAS_SHIFT 28 -#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK) -#define SPI_PUSHR_CONT_MASK 0x80000000u -#define SPI_PUSHR_CONT_SHIFT 31 -/* PUSHR_SLAVE Bit Fields */ -#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu -#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0 -#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK) -/* POPR Bit Fields */ -#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu -#define SPI_POPR_RXDATA_SHIFT 0 -#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK) -/* TXFR0 Bit Fields */ -#define SPI_TXFR0_TXDATA_MASK 0xFFFFu -#define SPI_TXFR0_TXDATA_SHIFT 0 -#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK) -#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u -#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16 -#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK) -/* TXFR1 Bit Fields */ -#define SPI_TXFR1_TXDATA_MASK 0xFFFFu -#define SPI_TXFR1_TXDATA_SHIFT 0 -#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK) -#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u -#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16 -#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK) -/* TXFR2 Bit Fields */ -#define SPI_TXFR2_TXDATA_MASK 0xFFFFu -#define SPI_TXFR2_TXDATA_SHIFT 0 -#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK) -#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u -#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16 -#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK) -/* TXFR3 Bit Fields */ -#define SPI_TXFR3_TXDATA_MASK 0xFFFFu -#define SPI_TXFR3_TXDATA_SHIFT 0 -#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK) -#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u -#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16 -#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK) -/* RXFR0 Bit Fields */ -#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu -#define SPI_RXFR0_RXDATA_SHIFT 0 -#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK) -/* RXFR1 Bit Fields */ -#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu -#define SPI_RXFR1_RXDATA_SHIFT 0 -#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK) -/* RXFR2 Bit Fields */ -#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu -#define SPI_RXFR2_RXDATA_SHIFT 0 -#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK) -/* RXFR3 Bit Fields */ -#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu -#define SPI_RXFR3_RXDATA_SHIFT 0 -#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK) - -/** - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -/** Peripheral SPI0 base address */ -#define SPI0_BASE (0x4002C000u) -/** Peripheral SPI0 base pointer */ -#define SPI0 ((SPI_Type *)SPI0_BASE) - -/** - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- TSI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer - * @{ - */ - -/** TSI - Register Layout Typedef */ -typedef struct { - __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */ - __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */ - __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */ - __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */ - uint8_t RESERVED_0[240]; - __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */ - __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */ - __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */ - __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */ - __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */ - __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */ - __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */ - __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */ - __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */ -} TSI_Type; - -/* ---------------------------------------------------------------------------- - -- TSI Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup TSI_Register_Masks TSI Register Masks - * @{ - */ - -/* GENCS Bit Fields */ -#define TSI_GENCS_STPE_MASK 0x1u -#define TSI_GENCS_STPE_SHIFT 0 -#define TSI_GENCS_STM_MASK 0x2u -#define TSI_GENCS_STM_SHIFT 1 -#define TSI_GENCS_ESOR_MASK 0x10u -#define TSI_GENCS_ESOR_SHIFT 4 -#define TSI_GENCS_ERIE_MASK 0x20u -#define TSI_GENCS_ERIE_SHIFT 5 -#define TSI_GENCS_TSIIE_MASK 0x40u -#define TSI_GENCS_TSIIE_SHIFT 6 -#define TSI_GENCS_TSIEN_MASK 0x80u -#define TSI_GENCS_TSIEN_SHIFT 7 -#define TSI_GENCS_SWTS_MASK 0x100u -#define TSI_GENCS_SWTS_SHIFT 8 -#define TSI_GENCS_SCNIP_MASK 0x200u -#define TSI_GENCS_SCNIP_SHIFT 9 -#define TSI_GENCS_OVRF_MASK 0x1000u -#define TSI_GENCS_OVRF_SHIFT 12 -#define TSI_GENCS_EXTERF_MASK 0x2000u -#define TSI_GENCS_EXTERF_SHIFT 13 -#define TSI_GENCS_OUTRGF_MASK 0x4000u -#define TSI_GENCS_OUTRGF_SHIFT 14 -#define TSI_GENCS_EOSF_MASK 0x8000u -#define TSI_GENCS_EOSF_SHIFT 15 -#define TSI_GENCS_PS_MASK 0x70000u -#define TSI_GENCS_PS_SHIFT 16 -#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK) -#define TSI_GENCS_NSCN_MASK 0xF80000u -#define TSI_GENCS_NSCN_SHIFT 19 -#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK) -#define TSI_GENCS_LPSCNITV_MASK 0xF000000u -#define TSI_GENCS_LPSCNITV_SHIFT 24 -#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK) -#define TSI_GENCS_LPCLKS_MASK 0x10000000u -#define TSI_GENCS_LPCLKS_SHIFT 28 -/* SCANC Bit Fields */ -#define TSI_SCANC_AMPSC_MASK 0x7u -#define TSI_SCANC_AMPSC_SHIFT 0 -#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK) -#define TSI_SCANC_AMCLKS_MASK 0x18u -#define TSI_SCANC_AMCLKS_SHIFT 3 -#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK) -#define TSI_SCANC_SMOD_MASK 0xFF00u -#define TSI_SCANC_SMOD_SHIFT 8 -#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK) -#define TSI_SCANC_EXTCHRG_MASK 0xF0000u -#define TSI_SCANC_EXTCHRG_SHIFT 16 -#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK) -#define TSI_SCANC_REFCHRG_MASK 0xF000000u -#define TSI_SCANC_REFCHRG_SHIFT 24 -#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK) -/* PEN Bit Fields */ -#define TSI_PEN_PEN0_MASK 0x1u -#define TSI_PEN_PEN0_SHIFT 0 -#define TSI_PEN_PEN1_MASK 0x2u -#define TSI_PEN_PEN1_SHIFT 1 -#define TSI_PEN_PEN2_MASK 0x4u -#define TSI_PEN_PEN2_SHIFT 2 -#define TSI_PEN_PEN3_MASK 0x8u -#define TSI_PEN_PEN3_SHIFT 3 -#define TSI_PEN_PEN4_MASK 0x10u -#define TSI_PEN_PEN4_SHIFT 4 -#define TSI_PEN_PEN5_MASK 0x20u -#define TSI_PEN_PEN5_SHIFT 5 -#define TSI_PEN_PEN6_MASK 0x40u -#define TSI_PEN_PEN6_SHIFT 6 -#define TSI_PEN_PEN7_MASK 0x80u -#define TSI_PEN_PEN7_SHIFT 7 -#define TSI_PEN_PEN8_MASK 0x100u -#define TSI_PEN_PEN8_SHIFT 8 -#define TSI_PEN_PEN9_MASK 0x200u -#define TSI_PEN_PEN9_SHIFT 9 -#define TSI_PEN_PEN10_MASK 0x400u -#define TSI_PEN_PEN10_SHIFT 10 -#define TSI_PEN_PEN11_MASK 0x800u -#define TSI_PEN_PEN11_SHIFT 11 -#define TSI_PEN_PEN12_MASK 0x1000u -#define TSI_PEN_PEN12_SHIFT 12 -#define TSI_PEN_PEN13_MASK 0x2000u -#define TSI_PEN_PEN13_SHIFT 13 -#define TSI_PEN_PEN14_MASK 0x4000u -#define TSI_PEN_PEN14_SHIFT 14 -#define TSI_PEN_PEN15_MASK 0x8000u -#define TSI_PEN_PEN15_SHIFT 15 -#define TSI_PEN_LPSP_MASK 0xF0000u -#define TSI_PEN_LPSP_SHIFT 16 -#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK) -/* WUCNTR Bit Fields */ -#define TSI_WUCNTR_WUCNT_MASK 0xFFFFu -#define TSI_WUCNTR_WUCNT_SHIFT 0 -#define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK) -/* CNTR1 Bit Fields */ -#define TSI_CNTR1_CTN1_MASK 0xFFFFu -#define TSI_CNTR1_CTN1_SHIFT 0 -#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK) -#define TSI_CNTR1_CTN_MASK 0xFFFF0000u -#define TSI_CNTR1_CTN_SHIFT 16 -#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK) -/* CNTR3 Bit Fields */ -#define TSI_CNTR3_CTN1_MASK 0xFFFFu -#define TSI_CNTR3_CTN1_SHIFT 0 -#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK) -#define TSI_CNTR3_CTN_MASK 0xFFFF0000u -#define TSI_CNTR3_CTN_SHIFT 16 -#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK) -/* CNTR5 Bit Fields */ -#define TSI_CNTR5_CTN1_MASK 0xFFFFu -#define TSI_CNTR5_CTN1_SHIFT 0 -#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK) -#define TSI_CNTR5_CTN_MASK 0xFFFF0000u -#define TSI_CNTR5_CTN_SHIFT 16 -#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK) -/* CNTR7 Bit Fields */ -#define TSI_CNTR7_CTN1_MASK 0xFFFFu -#define TSI_CNTR7_CTN1_SHIFT 0 -#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK) -#define TSI_CNTR7_CTN_MASK 0xFFFF0000u -#define TSI_CNTR7_CTN_SHIFT 16 -#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK) -/* CNTR9 Bit Fields */ -#define TSI_CNTR9_CTN1_MASK 0xFFFFu -#define TSI_CNTR9_CTN1_SHIFT 0 -#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK) -#define TSI_CNTR9_CTN_MASK 0xFFFF0000u -#define TSI_CNTR9_CTN_SHIFT 16 -#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK) -/* CNTR11 Bit Fields */ -#define TSI_CNTR11_CTN1_MASK 0xFFFFu -#define TSI_CNTR11_CTN1_SHIFT 0 -#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK) -#define TSI_CNTR11_CTN_MASK 0xFFFF0000u -#define TSI_CNTR11_CTN_SHIFT 16 -#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK) -/* CNTR13 Bit Fields */ -#define TSI_CNTR13_CTN1_MASK 0xFFFFu -#define TSI_CNTR13_CTN1_SHIFT 0 -#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK) -#define TSI_CNTR13_CTN_MASK 0xFFFF0000u -#define TSI_CNTR13_CTN_SHIFT 16 -#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK) -/* CNTR15 Bit Fields */ -#define TSI_CNTR15_CTN1_MASK 0xFFFFu -#define TSI_CNTR15_CTN1_SHIFT 0 -#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK) -#define TSI_CNTR15_CTN_MASK 0xFFFF0000u -#define TSI_CNTR15_CTN_SHIFT 16 -#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK) -/* THRESHOLD Bit Fields */ -#define TSI_THRESHOLD_HTHH_MASK 0xFFFFu -#define TSI_THRESHOLD_HTHH_SHIFT 0 -#define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK) -#define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u -#define TSI_THRESHOLD_LTHH_SHIFT 16 -#define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK) - -/** - * @} - */ /* end of group TSI_Register_Masks */ - - -/* TSI - Peripheral instance base addresses */ -/** Peripheral TSI0 base address */ -#define TSI0_BASE (0x40045000u) -/** Peripheral TSI0 base pointer */ -#define TSI0 ((TSI_Type *)TSI0_BASE) - -/** - * @} - */ /* end of group TSI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- UART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer - * @{ - */ - -/** UART - Register Layout Typedef */ -typedef struct { - __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */ - __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ - __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ - __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ - __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ - __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ - __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ - __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ - __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ - __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ - __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ - __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ - __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */ - __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */ - __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */ - uint8_t RESERVED_0[1]; - __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */ - __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */ - __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */ - __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */ - __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */ - __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */ - __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */ - uint8_t RESERVED_1[1]; - __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ - __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ - __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ - union { /* offset: 0x1B */ - __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ - __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ - }; - __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ - __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ - __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ - __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ - uint8_t RESERVED_2[1]; - __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */ - __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */ - __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */ - __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */ - __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */ - __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */ - __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */ - __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */ - __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */ - __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */ - __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */ - __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */ - __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */ - __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */ - __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */ - __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */ - __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */ -} UART_Type; - -/* ---------------------------------------------------------------------------- - -- UART Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup UART_Register_Masks UART Register Masks - * @{ - */ - -/* BDH Bit Fields */ -#define UART_BDH_SBR_MASK 0x1Fu -#define UART_BDH_SBR_SHIFT 0 -#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK) -#define UART_BDH_RXEDGIE_MASK 0x40u -#define UART_BDH_RXEDGIE_SHIFT 6 -#define UART_BDH_LBKDIE_MASK 0x80u -#define UART_BDH_LBKDIE_SHIFT 7 -/* BDL Bit Fields */ -#define UART_BDL_SBR_MASK 0xFFu -#define UART_BDL_SBR_SHIFT 0 -#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK) -/* C1 Bit Fields */ -#define UART_C1_PT_MASK 0x1u -#define UART_C1_PT_SHIFT 0 -#define UART_C1_PE_MASK 0x2u -#define UART_C1_PE_SHIFT 1 -#define UART_C1_ILT_MASK 0x4u -#define UART_C1_ILT_SHIFT 2 -#define UART_C1_WAKE_MASK 0x8u -#define UART_C1_WAKE_SHIFT 3 -#define UART_C1_M_MASK 0x10u -#define UART_C1_M_SHIFT 4 -#define UART_C1_RSRC_MASK 0x20u -#define UART_C1_RSRC_SHIFT 5 -#define UART_C1_UARTSWAI_MASK 0x40u -#define UART_C1_UARTSWAI_SHIFT 6 -#define UART_C1_LOOPS_MASK 0x80u -#define UART_C1_LOOPS_SHIFT 7 -/* C2 Bit Fields */ -#define UART_C2_SBK_MASK 0x1u -#define UART_C2_SBK_SHIFT 0 -#define UART_C2_RWU_MASK 0x2u -#define UART_C2_RWU_SHIFT 1 -#define UART_C2_RE_MASK 0x4u -#define UART_C2_RE_SHIFT 2 -#define UART_C2_TE_MASK 0x8u -#define UART_C2_TE_SHIFT 3 -#define UART_C2_ILIE_MASK 0x10u -#define UART_C2_ILIE_SHIFT 4 -#define UART_C2_RIE_MASK 0x20u -#define UART_C2_RIE_SHIFT 5 -#define UART_C2_TCIE_MASK 0x40u -#define UART_C2_TCIE_SHIFT 6 -#define UART_C2_TIE_MASK 0x80u -#define UART_C2_TIE_SHIFT 7 -/* S1 Bit Fields */ -#define UART_S1_PF_MASK 0x1u -#define UART_S1_PF_SHIFT 0 -#define UART_S1_FE_MASK 0x2u -#define UART_S1_FE_SHIFT 1 -#define UART_S1_NF_MASK 0x4u -#define UART_S1_NF_SHIFT 2 -#define UART_S1_OR_MASK 0x8u -#define UART_S1_OR_SHIFT 3 -#define UART_S1_IDLE_MASK 0x10u -#define UART_S1_IDLE_SHIFT 4 -#define UART_S1_RDRF_MASK 0x20u -#define UART_S1_RDRF_SHIFT 5 -#define UART_S1_TC_MASK 0x40u -#define UART_S1_TC_SHIFT 6 -#define UART_S1_TDRE_MASK 0x80u -#define UART_S1_TDRE_SHIFT 7 -/* S2 Bit Fields */ -#define UART_S2_RAF_MASK 0x1u -#define UART_S2_RAF_SHIFT 0 -#define UART_S2_LBKDE_MASK 0x2u -#define UART_S2_LBKDE_SHIFT 1 -#define UART_S2_BRK13_MASK 0x4u -#define UART_S2_BRK13_SHIFT 2 -#define UART_S2_RWUID_MASK 0x8u -#define UART_S2_RWUID_SHIFT 3 -#define UART_S2_RXINV_MASK 0x10u -#define UART_S2_RXINV_SHIFT 4 -#define UART_S2_MSBF_MASK 0x20u -#define UART_S2_MSBF_SHIFT 5 -#define UART_S2_RXEDGIF_MASK 0x40u -#define UART_S2_RXEDGIF_SHIFT 6 -#define UART_S2_LBKDIF_MASK 0x80u -#define UART_S2_LBKDIF_SHIFT 7 -/* C3 Bit Fields */ -#define UART_C3_PEIE_MASK 0x1u -#define UART_C3_PEIE_SHIFT 0 -#define UART_C3_FEIE_MASK 0x2u -#define UART_C3_FEIE_SHIFT 1 -#define UART_C3_NEIE_MASK 0x4u -#define UART_C3_NEIE_SHIFT 2 -#define UART_C3_ORIE_MASK 0x8u -#define UART_C3_ORIE_SHIFT 3 -#define UART_C3_TXINV_MASK 0x10u -#define UART_C3_TXINV_SHIFT 4 -#define UART_C3_TXDIR_MASK 0x20u -#define UART_C3_TXDIR_SHIFT 5 -#define UART_C3_T8_MASK 0x40u -#define UART_C3_T8_SHIFT 6 -#define UART_C3_R8_MASK 0x80u -#define UART_C3_R8_SHIFT 7 -/* D Bit Fields */ -#define UART_D_RT_MASK 0xFFu -#define UART_D_RT_SHIFT 0 -#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK) -/* MA1 Bit Fields */ -#define UART_MA1_MA_MASK 0xFFu -#define UART_MA1_MA_SHIFT 0 -#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK) -/* MA2 Bit Fields */ -#define UART_MA2_MA_MASK 0xFFu -#define UART_MA2_MA_SHIFT 0 -#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK) -/* C4 Bit Fields */ -#define UART_C4_BRFA_MASK 0x1Fu -#define UART_C4_BRFA_SHIFT 0 -#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK) -#define UART_C4_M10_MASK 0x20u -#define UART_C4_M10_SHIFT 5 -#define UART_C4_MAEN2_MASK 0x40u -#define UART_C4_MAEN2_SHIFT 6 -#define UART_C4_MAEN1_MASK 0x80u -#define UART_C4_MAEN1_SHIFT 7 -/* C5 Bit Fields */ -#define UART_C5_RDMAS_MASK 0x20u -#define UART_C5_RDMAS_SHIFT 5 -#define UART_C5_TDMAS_MASK 0x80u -#define UART_C5_TDMAS_SHIFT 7 -/* ED Bit Fields */ -#define UART_ED_PARITYE_MASK 0x40u -#define UART_ED_PARITYE_SHIFT 6 -#define UART_ED_NOISY_MASK 0x80u -#define UART_ED_NOISY_SHIFT 7 -/* MODEM Bit Fields */ -#define UART_MODEM_TXCTSE_MASK 0x1u -#define UART_MODEM_TXCTSE_SHIFT 0 -#define UART_MODEM_TXRTSE_MASK 0x2u -#define UART_MODEM_TXRTSE_SHIFT 1 -#define UART_MODEM_TXRTSPOL_MASK 0x4u -#define UART_MODEM_TXRTSPOL_SHIFT 2 -#define UART_MODEM_RXRTSE_MASK 0x8u -#define UART_MODEM_RXRTSE_SHIFT 3 -/* IR Bit Fields */ -#define UART_IR_TNP_MASK 0x3u -#define UART_IR_TNP_SHIFT 0 -#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK) -#define UART_IR_IREN_MASK 0x4u -#define UART_IR_IREN_SHIFT 2 -/* PFIFO Bit Fields */ -#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u -#define UART_PFIFO_RXFIFOSIZE_SHIFT 0 -#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK) -#define UART_PFIFO_RXFE_MASK 0x8u -#define UART_PFIFO_RXFE_SHIFT 3 -#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u -#define UART_PFIFO_TXFIFOSIZE_SHIFT 4 -#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK) -#define UART_PFIFO_TXFE_MASK 0x80u -#define UART_PFIFO_TXFE_SHIFT 7 -/* CFIFO Bit Fields */ -#define UART_CFIFO_RXUFE_MASK 0x1u -#define UART_CFIFO_RXUFE_SHIFT 0 -#define UART_CFIFO_TXOFE_MASK 0x2u -#define UART_CFIFO_TXOFE_SHIFT 1 -#define UART_CFIFO_RXFLUSH_MASK 0x40u -#define UART_CFIFO_RXFLUSH_SHIFT 6 -#define UART_CFIFO_TXFLUSH_MASK 0x80u -#define UART_CFIFO_TXFLUSH_SHIFT 7 -/* SFIFO Bit Fields */ -#define UART_SFIFO_RXUF_MASK 0x1u -#define UART_SFIFO_RXUF_SHIFT 0 -#define UART_SFIFO_TXOF_MASK 0x2u -#define UART_SFIFO_TXOF_SHIFT 1 -#define UART_SFIFO_RXEMPT_MASK 0x40u -#define UART_SFIFO_RXEMPT_SHIFT 6 -#define UART_SFIFO_TXEMPT_MASK 0x80u -#define UART_SFIFO_TXEMPT_SHIFT 7 -/* TWFIFO Bit Fields */ -#define UART_TWFIFO_TXWATER_MASK 0xFFu -#define UART_TWFIFO_TXWATER_SHIFT 0 -#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK) -/* TCFIFO Bit Fields */ -#define UART_TCFIFO_TXCOUNT_MASK 0xFFu -#define UART_TCFIFO_TXCOUNT_SHIFT 0 -#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK) -/* RWFIFO Bit Fields */ -#define UART_RWFIFO_RXWATER_MASK 0xFFu -#define UART_RWFIFO_RXWATER_SHIFT 0 -#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK) -/* RCFIFO Bit Fields */ -#define UART_RCFIFO_RXCOUNT_MASK 0xFFu -#define UART_RCFIFO_RXCOUNT_SHIFT 0 -#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK) -/* C7816 Bit Fields */ -#define UART_C7816_ISO_7816E_MASK 0x1u -#define UART_C7816_ISO_7816E_SHIFT 0 -#define UART_C7816_TTYPE_MASK 0x2u -#define UART_C7816_TTYPE_SHIFT 1 -#define UART_C7816_INIT_MASK 0x4u -#define UART_C7816_INIT_SHIFT 2 -#define UART_C7816_ANACK_MASK 0x8u -#define UART_C7816_ANACK_SHIFT 3 -#define UART_C7816_ONACK_MASK 0x10u -#define UART_C7816_ONACK_SHIFT 4 -/* IE7816 Bit Fields */ -#define UART_IE7816_RXTE_MASK 0x1u -#define UART_IE7816_RXTE_SHIFT 0 -#define UART_IE7816_TXTE_MASK 0x2u -#define UART_IE7816_TXTE_SHIFT 1 -#define UART_IE7816_GTVE_MASK 0x4u -#define UART_IE7816_GTVE_SHIFT 2 -#define UART_IE7816_INITDE_MASK 0x10u -#define UART_IE7816_INITDE_SHIFT 4 -#define UART_IE7816_BWTE_MASK 0x20u -#define UART_IE7816_BWTE_SHIFT 5 -#define UART_IE7816_CWTE_MASK 0x40u -#define UART_IE7816_CWTE_SHIFT 6 -#define UART_IE7816_WTE_MASK 0x80u -#define UART_IE7816_WTE_SHIFT 7 -/* IS7816 Bit Fields */ -#define UART_IS7816_RXT_MASK 0x1u -#define UART_IS7816_RXT_SHIFT 0 -#define UART_IS7816_TXT_MASK 0x2u -#define UART_IS7816_TXT_SHIFT 1 -#define UART_IS7816_GTV_MASK 0x4u -#define UART_IS7816_GTV_SHIFT 2 -#define UART_IS7816_INITD_MASK 0x10u -#define UART_IS7816_INITD_SHIFT 4 -#define UART_IS7816_BWT_MASK 0x20u -#define UART_IS7816_BWT_SHIFT 5 -#define UART_IS7816_CWT_MASK 0x40u -#define UART_IS7816_CWT_SHIFT 6 -#define UART_IS7816_WT_MASK 0x80u -#define UART_IS7816_WT_SHIFT 7 -/* WP7816_T_TYPE0 Bit Fields */ -#define UART_WP7816_T_TYPE0_WI_MASK 0xFFu -#define UART_WP7816_T_TYPE0_WI_SHIFT 0 -#define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK) -/* WP7816_T_TYPE1 Bit Fields */ -#define UART_WP7816_T_TYPE1_BWI_MASK 0xFu -#define UART_WP7816_T_TYPE1_BWI_SHIFT 0 -#define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK) -#define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u -#define UART_WP7816_T_TYPE1_CWI_SHIFT 4 -#define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK) -/* WN7816 Bit Fields */ -#define UART_WN7816_GTN_MASK 0xFFu -#define UART_WN7816_GTN_SHIFT 0 -#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK) -/* WF7816 Bit Fields */ -#define UART_WF7816_GTFD_MASK 0xFFu -#define UART_WF7816_GTFD_SHIFT 0 -#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK) -/* ET7816 Bit Fields */ -#define UART_ET7816_RXTHRESHOLD_MASK 0xFu -#define UART_ET7816_RXTHRESHOLD_SHIFT 0 -#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK) -#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u -#define UART_ET7816_TXTHRESHOLD_SHIFT 4 -#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK) -/* TL7816 Bit Fields */ -#define UART_TL7816_TLEN_MASK 0xFFu -#define UART_TL7816_TLEN_SHIFT 0 -#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK) -/* C6 Bit Fields */ -#define UART_C6_CP_MASK 0x10u -#define UART_C6_CP_SHIFT 4 -#define UART_C6_CE_MASK 0x20u -#define UART_C6_CE_SHIFT 5 -#define UART_C6_TX709_MASK 0x40u -#define UART_C6_TX709_SHIFT 6 -#define UART_C6_EN709_MASK 0x80u -#define UART_C6_EN709_SHIFT 7 -/* PCTH Bit Fields */ -#define UART_PCTH_PCTH_MASK 0xFFu -#define UART_PCTH_PCTH_SHIFT 0 -#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK) -/* PCTL Bit Fields */ -#define UART_PCTL_PCTL_MASK 0xFFu -#define UART_PCTL_PCTL_SHIFT 0 -#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK) -/* B1T Bit Fields */ -#define UART_B1T_B1T_MASK 0xFFu -#define UART_B1T_B1T_SHIFT 0 -#define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK) -/* SDTH Bit Fields */ -#define UART_SDTH_SDTH_MASK 0xFFu -#define UART_SDTH_SDTH_SHIFT 0 -#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK) -/* SDTL Bit Fields */ -#define UART_SDTL_SDTL_MASK 0xFFu -#define UART_SDTL_SDTL_SHIFT 0 -#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK) -/* PRE Bit Fields */ -#define UART_PRE_PREAMBLE_MASK 0xFFu -#define UART_PRE_PREAMBLE_SHIFT 0 -#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK) -/* TPL Bit Fields */ -#define UART_TPL_TPL_MASK 0xFFu -#define UART_TPL_TPL_SHIFT 0 -#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK) -/* IE Bit Fields */ -#define UART_IE_TXFIE_MASK 0x1u -#define UART_IE_TXFIE_SHIFT 0 -#define UART_IE_PSIE_MASK 0x2u -#define UART_IE_PSIE_SHIFT 1 -#define UART_IE_PCTEIE_MASK 0x4u -#define UART_IE_PCTEIE_SHIFT 2 -#define UART_IE_PTXIE_MASK 0x8u -#define UART_IE_PTXIE_SHIFT 3 -#define UART_IE_PRXIE_MASK 0x10u -#define UART_IE_PRXIE_SHIFT 4 -#define UART_IE_ISDIE_MASK 0x20u -#define UART_IE_ISDIE_SHIFT 5 -#define UART_IE_WBEIE_MASK 0x40u -#define UART_IE_WBEIE_SHIFT 6 -/* WB Bit Fields */ -#define UART_WB_WBASE_MASK 0xFFu -#define UART_WB_WBASE_SHIFT 0 -#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK) -/* S3 Bit Fields */ -#define UART_S3_TXFF_MASK 0x1u -#define UART_S3_TXFF_SHIFT 0 -#define UART_S3_PSF_MASK 0x2u -#define UART_S3_PSF_SHIFT 1 -#define UART_S3_PCTEF_MASK 0x4u -#define UART_S3_PCTEF_SHIFT 2 -#define UART_S3_PTXF_MASK 0x8u -#define UART_S3_PTXF_SHIFT 3 -#define UART_S3_PRXF_MASK 0x10u -#define UART_S3_PRXF_SHIFT 4 -#define UART_S3_ISD_MASK 0x20u -#define UART_S3_ISD_SHIFT 5 -#define UART_S3_WBEF_MASK 0x40u -#define UART_S3_WBEF_SHIFT 6 -#define UART_S3_PEF_MASK 0x80u -#define UART_S3_PEF_SHIFT 7 -/* S4 Bit Fields */ -#define UART_S4_FE_MASK 0x1u -#define UART_S4_FE_SHIFT 0 -#define UART_S4_ILCV_MASK 0x2u -#define UART_S4_ILCV_SHIFT 1 -#define UART_S4_CDET_MASK 0xCu -#define UART_S4_CDET_SHIFT 2 -#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK) -#define UART_S4_INITF_MASK 0x10u -#define UART_S4_INITF_SHIFT 4 -/* RPL Bit Fields */ -#define UART_RPL_RPL_MASK 0xFFu -#define UART_RPL_RPL_SHIFT 0 -#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK) -/* RPREL Bit Fields */ -#define UART_RPREL_RPREL_MASK 0xFFu -#define UART_RPREL_RPREL_SHIFT 0 -#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK) -/* CPW Bit Fields */ -#define UART_CPW_CPW_MASK 0xFFu -#define UART_CPW_CPW_SHIFT 0 -#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK) -/* RIDT Bit Fields */ -#define UART_RIDT_RIDT_MASK 0xFFu -#define UART_RIDT_RIDT_SHIFT 0 -#define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK) -/* TIDT Bit Fields */ -#define UART_TIDT_TIDT_MASK 0xFFu -#define UART_TIDT_TIDT_SHIFT 0 -#define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK) - -/** - * @} - */ /* end of group UART_Register_Masks */ - - -/* UART - Peripheral instance base addresses */ -/** Peripheral UART0 base address */ -#define UART0_BASE (0x4006A000u) -/** Peripheral UART0 base pointer */ -#define UART0 ((UART_Type *)UART0_BASE) -/** Peripheral UART1 base address */ -#define UART1_BASE (0x4006B000u) -/** Peripheral UART1 base pointer */ -#define UART1 ((UART_Type *)UART1_BASE) -/** Peripheral UART2 base address */ -#define UART2_BASE (0x4006C000u) -/** Peripheral UART2 base pointer */ -#define UART2 ((UART_Type *)UART2_BASE) - -/** - * @} - */ /* end of group UART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */ - uint8_t RESERVED_0[3]; - __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */ - uint8_t RESERVED_1[3]; - __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */ - uint8_t RESERVED_2[3]; - __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */ - uint8_t RESERVED_3[3]; - __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */ - uint8_t RESERVED_4[3]; - __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */ - uint8_t RESERVED_5[3]; - __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */ - uint8_t RESERVED_6[3]; - __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */ - uint8_t RESERVED_7[99]; - __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */ - uint8_t RESERVED_8[3]; - __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */ - uint8_t RESERVED_9[3]; - __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */ - uint8_t RESERVED_10[3]; - __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */ - uint8_t RESERVED_11[3]; - __I uint8_t STAT; /**< Status Register, offset: 0x90 */ - uint8_t RESERVED_12[3]; - __IO uint8_t CTL; /**< Control Register, offset: 0x94 */ - uint8_t RESERVED_13[3]; - __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */ - uint8_t RESERVED_14[3]; - __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */ - uint8_t RESERVED_15[3]; - __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ - uint8_t RESERVED_16[3]; - __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ - uint8_t RESERVED_17[3]; - __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */ - uint8_t RESERVED_18[3]; - __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */ - uint8_t RESERVED_19[3]; - __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ - uint8_t RESERVED_20[3]; - __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ - uint8_t RESERVED_21[11]; - struct { /* offset: 0xC0, array step: 0x4 */ - __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_0[3]; - } ENDPOINT[16]; - __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */ - uint8_t RESERVED_22[3]; - __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */ - uint8_t RESERVED_23[3]; - __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */ - uint8_t RESERVED_24[3]; - __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */ - uint8_t RESERVED_25[7]; - __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/* PERID Bit Fields */ -#define USB_PERID_ID_MASK 0x3Fu -#define USB_PERID_ID_SHIFT 0 -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK) -/* IDCOMP Bit Fields */ -#define USB_IDCOMP_NID_MASK 0x3Fu -#define USB_IDCOMP_NID_SHIFT 0 -#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK) -/* REV Bit Fields */ -#define USB_REV_REV_MASK 0xFFu -#define USB_REV_REV_SHIFT 0 -#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK) -/* ADDINFO Bit Fields */ -#define USB_ADDINFO_IEHOST_MASK 0x1u -#define USB_ADDINFO_IEHOST_SHIFT 0 -#define USB_ADDINFO_IRQNUM_MASK 0xF8u -#define USB_ADDINFO_IRQNUM_SHIFT 3 -#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK) -/* OTGISTAT Bit Fields */ -#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u -#define USB_OTGISTAT_AVBUSCHG_SHIFT 0 -#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u -#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2 -#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u -#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3 -#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u -#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5 -#define USB_OTGISTAT_ONEMSEC_MASK 0x40u -#define USB_OTGISTAT_ONEMSEC_SHIFT 6 -#define USB_OTGISTAT_IDCHG_MASK 0x80u -#define USB_OTGISTAT_IDCHG_SHIFT 7 -/* OTGICR Bit Fields */ -#define USB_OTGICR_AVBUSEN_MASK 0x1u -#define USB_OTGICR_AVBUSEN_SHIFT 0 -#define USB_OTGICR_BSESSEN_MASK 0x4u -#define USB_OTGICR_BSESSEN_SHIFT 2 -#define USB_OTGICR_SESSVLDEN_MASK 0x8u -#define USB_OTGICR_SESSVLDEN_SHIFT 3 -#define USB_OTGICR_LINESTATEEN_MASK 0x20u -#define USB_OTGICR_LINESTATEEN_SHIFT 5 -#define USB_OTGICR_ONEMSECEN_MASK 0x40u -#define USB_OTGICR_ONEMSECEN_SHIFT 6 -#define USB_OTGICR_IDEN_MASK 0x80u -#define USB_OTGICR_IDEN_SHIFT 7 -/* OTGSTAT Bit Fields */ -#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u -#define USB_OTGSTAT_AVBUSVLD_SHIFT 0 -#define USB_OTGSTAT_BSESSEND_MASK 0x4u -#define USB_OTGSTAT_BSESSEND_SHIFT 2 -#define USB_OTGSTAT_SESS_VLD_MASK 0x8u -#define USB_OTGSTAT_SESS_VLD_SHIFT 3 -#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u -#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5 -#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u -#define USB_OTGSTAT_ONEMSECEN_SHIFT 6 -#define USB_OTGSTAT_ID_MASK 0x80u -#define USB_OTGSTAT_ID_SHIFT 7 -/* OTGCTL Bit Fields */ -#define USB_OTGCTL_OTGEN_MASK 0x4u -#define USB_OTGCTL_OTGEN_SHIFT 2 -#define USB_OTGCTL_DMLOW_MASK 0x10u -#define USB_OTGCTL_DMLOW_SHIFT 4 -#define USB_OTGCTL_DPLOW_MASK 0x20u -#define USB_OTGCTL_DPLOW_SHIFT 5 -#define USB_OTGCTL_DPHIGH_MASK 0x80u -#define USB_OTGCTL_DPHIGH_SHIFT 7 -/* ISTAT Bit Fields */ -#define USB_ISTAT_USBRST_MASK 0x1u -#define USB_ISTAT_USBRST_SHIFT 0 -#define USB_ISTAT_ERROR_MASK 0x2u -#define USB_ISTAT_ERROR_SHIFT 1 -#define USB_ISTAT_SOFTOK_MASK 0x4u -#define USB_ISTAT_SOFTOK_SHIFT 2 -#define USB_ISTAT_TOKDNE_MASK 0x8u -#define USB_ISTAT_TOKDNE_SHIFT 3 -#define USB_ISTAT_SLEEP_MASK 0x10u -#define USB_ISTAT_SLEEP_SHIFT 4 -#define USB_ISTAT_RESUME_MASK 0x20u -#define USB_ISTAT_RESUME_SHIFT 5 -#define USB_ISTAT_ATTACH_MASK 0x40u -#define USB_ISTAT_ATTACH_SHIFT 6 -#define USB_ISTAT_STALL_MASK 0x80u -#define USB_ISTAT_STALL_SHIFT 7 -/* INTEN Bit Fields */ -#define USB_INTEN_USBRSTEN_MASK 0x1u -#define USB_INTEN_USBRSTEN_SHIFT 0 -#define USB_INTEN_ERROREN_MASK 0x2u -#define USB_INTEN_ERROREN_SHIFT 1 -#define USB_INTEN_SOFTOKEN_MASK 0x4u -#define USB_INTEN_SOFTOKEN_SHIFT 2 -#define USB_INTEN_TOKDNEEN_MASK 0x8u -#define USB_INTEN_TOKDNEEN_SHIFT 3 -#define USB_INTEN_SLEEPEN_MASK 0x10u -#define USB_INTEN_SLEEPEN_SHIFT 4 -#define USB_INTEN_RESUMEEN_MASK 0x20u -#define USB_INTEN_RESUMEEN_SHIFT 5 -#define USB_INTEN_ATTACHEN_MASK 0x40u -#define USB_INTEN_ATTACHEN_SHIFT 6 -#define USB_INTEN_STALLEN_MASK 0x80u -#define USB_INTEN_STALLEN_SHIFT 7 -/* ERRSTAT Bit Fields */ -#define USB_ERRSTAT_PIDERR_MASK 0x1u -#define USB_ERRSTAT_PIDERR_SHIFT 0 -#define USB_ERRSTAT_CRC5EOF_MASK 0x2u -#define USB_ERRSTAT_CRC5EOF_SHIFT 1 -#define USB_ERRSTAT_CRC16_MASK 0x4u -#define USB_ERRSTAT_CRC16_SHIFT 2 -#define USB_ERRSTAT_DFN8_MASK 0x8u -#define USB_ERRSTAT_DFN8_SHIFT 3 -#define USB_ERRSTAT_BTOERR_MASK 0x10u -#define USB_ERRSTAT_BTOERR_SHIFT 4 -#define USB_ERRSTAT_DMAERR_MASK 0x20u -#define USB_ERRSTAT_DMAERR_SHIFT 5 -#define USB_ERRSTAT_BTSERR_MASK 0x80u -#define USB_ERRSTAT_BTSERR_SHIFT 7 -/* ERREN Bit Fields */ -#define USB_ERREN_PIDERREN_MASK 0x1u -#define USB_ERREN_PIDERREN_SHIFT 0 -#define USB_ERREN_CRC5EOFEN_MASK 0x2u -#define USB_ERREN_CRC5EOFEN_SHIFT 1 -#define USB_ERREN_CRC16EN_MASK 0x4u -#define USB_ERREN_CRC16EN_SHIFT 2 -#define USB_ERREN_DFN8EN_MASK 0x8u -#define USB_ERREN_DFN8EN_SHIFT 3 -#define USB_ERREN_BTOERREN_MASK 0x10u -#define USB_ERREN_BTOERREN_SHIFT 4 -#define USB_ERREN_DMAERREN_MASK 0x20u -#define USB_ERREN_DMAERREN_SHIFT 5 -#define USB_ERREN_BTSERREN_MASK 0x80u -#define USB_ERREN_BTSERREN_SHIFT 7 -/* STAT Bit Fields */ -#define USB_STAT_ODD_MASK 0x4u -#define USB_STAT_ODD_SHIFT 2 -#define USB_STAT_TX_MASK 0x8u -#define USB_STAT_TX_SHIFT 3 -#define USB_STAT_ENDP_MASK 0xF0u -#define USB_STAT_ENDP_SHIFT 4 -#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK) -/* CTL Bit Fields */ -#define USB_CTL_USBENSOFEN_MASK 0x1u -#define USB_CTL_USBENSOFEN_SHIFT 0 -#define USB_CTL_ODDRST_MASK 0x2u -#define USB_CTL_ODDRST_SHIFT 1 -#define USB_CTL_RESUME_MASK 0x4u -#define USB_CTL_RESUME_SHIFT 2 -#define USB_CTL_HOSTMODEEN_MASK 0x8u -#define USB_CTL_HOSTMODEEN_SHIFT 3 -#define USB_CTL_RESET_MASK 0x10u -#define USB_CTL_RESET_SHIFT 4 -#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u -#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5 -#define USB_CTL_SE0_MASK 0x40u -#define USB_CTL_SE0_SHIFT 6 -#define USB_CTL_JSTATE_MASK 0x80u -#define USB_CTL_JSTATE_SHIFT 7 -/* ADDR Bit Fields */ -#define USB_ADDR_ADDR_MASK 0x7Fu -#define USB_ADDR_ADDR_SHIFT 0 -#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK) -#define USB_ADDR_LSEN_MASK 0x80u -#define USB_ADDR_LSEN_SHIFT 7 -/* BDTPAGE1 Bit Fields */ -#define USB_BDTPAGE1_BDTBA_MASK 0xFEu -#define USB_BDTPAGE1_BDTBA_SHIFT 1 -#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK) -/* FRMNUML Bit Fields */ -#define USB_FRMNUML_FRM_MASK 0xFFu -#define USB_FRMNUML_FRM_SHIFT 0 -#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK) -/* FRMNUMH Bit Fields */ -#define USB_FRMNUMH_FRM_MASK 0x7u -#define USB_FRMNUMH_FRM_SHIFT 0 -#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK) -/* TOKEN Bit Fields */ -#define USB_TOKEN_TOKENENDPT_MASK 0xFu -#define USB_TOKEN_TOKENENDPT_SHIFT 0 -#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK) -#define USB_TOKEN_TOKENPID_MASK 0xF0u -#define USB_TOKEN_TOKENPID_SHIFT 4 -#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK) -/* SOFTHLD Bit Fields */ -#define USB_SOFTHLD_CNT_MASK 0xFFu -#define USB_SOFTHLD_CNT_SHIFT 0 -#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK) -/* BDTPAGE2 Bit Fields */ -#define USB_BDTPAGE2_BDTBA_MASK 0xFFu -#define USB_BDTPAGE2_BDTBA_SHIFT 0 -#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK) -/* BDTPAGE3 Bit Fields */ -#define USB_BDTPAGE3_BDTBA_MASK 0xFFu -#define USB_BDTPAGE3_BDTBA_SHIFT 0 -#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK) -/* ENDPT Bit Fields */ -#define USB_ENDPT_EPHSHK_MASK 0x1u -#define USB_ENDPT_EPHSHK_SHIFT 0 -#define USB_ENDPT_EPSTALL_MASK 0x2u -#define USB_ENDPT_EPSTALL_SHIFT 1 -#define USB_ENDPT_EPTXEN_MASK 0x4u -#define USB_ENDPT_EPTXEN_SHIFT 2 -#define USB_ENDPT_EPRXEN_MASK 0x8u -#define USB_ENDPT_EPRXEN_SHIFT 3 -#define USB_ENDPT_EPCTLDIS_MASK 0x10u -#define USB_ENDPT_EPCTLDIS_SHIFT 4 -#define USB_ENDPT_RETRYDIS_MASK 0x40u -#define USB_ENDPT_RETRYDIS_SHIFT 6 -#define USB_ENDPT_HOSTWOHUB_MASK 0x80u -#define USB_ENDPT_HOSTWOHUB_SHIFT 7 -/* USBCTRL Bit Fields */ -#define USB_USBCTRL_PDE_MASK 0x40u -#define USB_USBCTRL_PDE_SHIFT 6 -#define USB_USBCTRL_SUSP_MASK 0x80u -#define USB_USBCTRL_SUSP_SHIFT 7 -/* OBSERVE Bit Fields */ -#define USB_OBSERVE_DMPD_MASK 0x10u -#define USB_OBSERVE_DMPD_SHIFT 4 -#define USB_OBSERVE_DPPD_MASK 0x40u -#define USB_OBSERVE_DPPD_SHIFT 6 -#define USB_OBSERVE_DPPU_MASK 0x80u -#define USB_OBSERVE_DPPU_SHIFT 7 -/* CONTROL Bit Fields */ -#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u -#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4 -/* USBTRC0 Bit Fields */ -#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u -#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0 -#define USB_USBTRC0_SYNC_DET_MASK 0x2u -#define USB_USBTRC0_SYNC_DET_SHIFT 1 -#define USB_USBTRC0_USBRESMEN_MASK 0x20u -#define USB_USBTRC0_USBRESMEN_SHIFT 5 -#define USB_USBTRC0_USBRESET_MASK 0x80u -#define USB_USBTRC0_USBRESET_SHIFT 7 -/* USBFRMADJUST Bit Fields */ -#define USB_USBFRMADJUST_ADJ_MASK 0xFFu -#define USB_USBFRMADJUST_ADJ_SHIFT 0 -#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK) - -/** - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -/** Peripheral USB0 base address */ -#define USB0_BASE (0x40072000u) -/** Peripheral USB0 base pointer */ -#define USB0 ((USB_Type *)USB0_BASE) - -/** - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USBDCD Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer - * @{ - */ - -/** USBDCD - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */ - __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */ - __I uint32_t STATUS; /**< Status Register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */ - __IO uint32_t TIMER1; /**< , offset: 0x14 */ - __IO uint32_t TIMER2; /**< , offset: 0x18 */ -} USBDCD_Type; - -/* ---------------------------------------------------------------------------- - -- USBDCD Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup USBDCD_Register_Masks USBDCD Register Masks - * @{ - */ - -/* CONTROL Bit Fields */ -#define USBDCD_CONTROL_IACK_MASK 0x1u -#define USBDCD_CONTROL_IACK_SHIFT 0 -#define USBDCD_CONTROL_IF_MASK 0x100u -#define USBDCD_CONTROL_IF_SHIFT 8 -#define USBDCD_CONTROL_IE_MASK 0x10000u -#define USBDCD_CONTROL_IE_SHIFT 16 -#define USBDCD_CONTROL_START_MASK 0x1000000u -#define USBDCD_CONTROL_START_SHIFT 24 -#define USBDCD_CONTROL_SR_MASK 0x2000000u -#define USBDCD_CONTROL_SR_SHIFT 25 -/* CLOCK Bit Fields */ -#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u -#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0 -#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu -#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2 -#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK) -/* STATUS Bit Fields */ -#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u -#define USBDCD_STATUS_SEQ_RES_SHIFT 16 -#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK) -#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u -#define USBDCD_STATUS_SEQ_STAT_SHIFT 18 -#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK) -#define USBDCD_STATUS_ERR_MASK 0x100000u -#define USBDCD_STATUS_ERR_SHIFT 20 -#define USBDCD_STATUS_TO_MASK 0x200000u -#define USBDCD_STATUS_TO_SHIFT 21 -#define USBDCD_STATUS_ACTIVE_MASK 0x400000u -#define USBDCD_STATUS_ACTIVE_SHIFT 22 -/* TIMER0 Bit Fields */ -#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu -#define USBDCD_TIMER0_TUNITCON_SHIFT 0 -#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK) -#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u -#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16 -#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK) -/* TIMER1 Bit Fields */ -#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu -#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0 -#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK) -#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u -#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16 -#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK) -/* TIMER2 Bit Fields */ -#define USBDCD_TIMER2_CHECK_DM_MASK 0xFu -#define USBDCD_TIMER2_CHECK_DM_SHIFT 0 -#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK) -#define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u -#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16 -#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK) - -/** - * @} - */ /* end of group USBDCD_Register_Masks */ - - -/* USBDCD - Peripheral instance base addresses */ -/** Peripheral USBDCD base address */ -#define USBDCD_BASE (0x40035000u) -/** Peripheral USBDCD base pointer */ -#define USBDCD ((USBDCD_Type *)USBDCD_BASE) - -/** - * @} - */ /* end of group USBDCD_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- VREF Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer - * @{ - */ - -/** VREF - Register Layout Typedef */ -typedef struct { - __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ - __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ -} VREF_Type; - -/* ---------------------------------------------------------------------------- - -- VREF Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup VREF_Register_Masks VREF Register Masks - * @{ - */ - -/* TRM Bit Fields */ -#define VREF_TRM_TRIM_MASK 0x3Fu -#define VREF_TRM_TRIM_SHIFT 0 -#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK) -#define VREF_TRM_CHOPEN_MASK 0x40u -#define VREF_TRM_CHOPEN_SHIFT 6 -/* SC Bit Fields */ -#define VREF_SC_MODE_LV_MASK 0x3u -#define VREF_SC_MODE_LV_SHIFT 0 -#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK) -#define VREF_SC_VREFST_MASK 0x4u -#define VREF_SC_VREFST_SHIFT 2 -#define VREF_SC_REGEN_MASK 0x40u -#define VREF_SC_REGEN_SHIFT 6 -#define VREF_SC_VREFEN_MASK 0x80u -#define VREF_SC_VREFEN_SHIFT 7 - -/** - * @} - */ /* end of group VREF_Register_Masks */ - - -/* VREF - Peripheral instance base addresses */ -/** Peripheral VREF base address */ -#define VREF_BASE (0x40074000u) -/** Peripheral VREF base pointer */ -#define VREF ((VREF_Type *)VREF_BASE) - -/** - * @} - */ /* end of group VREF_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WDOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer - * @{ - */ - -/** WDOG - Register Layout Typedef */ -typedef struct { - __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */ - __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */ - __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */ - __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */ - __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */ - __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */ - __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */ - __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */ - __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */ - __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */ - __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */ - __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */ -} WDOG_Type; - -/* ---------------------------------------------------------------------------- - -- WDOG Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup WDOG_Register_Masks WDOG Register Masks - * @{ - */ - -/* STCTRLH Bit Fields */ -#define WDOG_STCTRLH_WDOGEN_MASK 0x1u -#define WDOG_STCTRLH_WDOGEN_SHIFT 0 -#define WDOG_STCTRLH_CLKSRC_MASK 0x2u -#define WDOG_STCTRLH_CLKSRC_SHIFT 1 -#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u -#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 -#define WDOG_STCTRLH_WINEN_MASK 0x8u -#define WDOG_STCTRLH_WINEN_SHIFT 3 -#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u -#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 -#define WDOG_STCTRLH_DBGEN_MASK 0x20u -#define WDOG_STCTRLH_DBGEN_SHIFT 5 -#define WDOG_STCTRLH_STOPEN_MASK 0x40u -#define WDOG_STCTRLH_STOPEN_SHIFT 6 -#define WDOG_STCTRLH_WAITEN_MASK 0x80u -#define WDOG_STCTRLH_WAITEN_SHIFT 7 -#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u -#define WDOG_STCTRLH_TESTWDOG_SHIFT 10 -#define WDOG_STCTRLH_TESTSEL_MASK 0x800u -#define WDOG_STCTRLH_TESTSEL_SHIFT 11 -#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u -#define WDOG_STCTRLH_BYTESEL_SHIFT 12 -#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK) -#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u -#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14 -/* STCTRLL Bit Fields */ -#define WDOG_STCTRLL_INTFLG_MASK 0x8000u -#define WDOG_STCTRLL_INTFLG_SHIFT 15 -/* TOVALH Bit Fields */ -#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu -#define WDOG_TOVALH_TOVALHIGH_SHIFT 0 -#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK) -/* TOVALL Bit Fields */ -#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu -#define WDOG_TOVALL_TOVALLOW_SHIFT 0 -#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK) -/* WINH Bit Fields */ -#define WDOG_WINH_WINHIGH_MASK 0xFFFFu -#define WDOG_WINH_WINHIGH_SHIFT 0 -#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK) -/* WINL Bit Fields */ -#define WDOG_WINL_WINLOW_MASK 0xFFFFu -#define WDOG_WINL_WINLOW_SHIFT 0 -#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK) -/* REFRESH Bit Fields */ -#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu -#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0 -#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK) -/* UNLOCK Bit Fields */ -#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu -#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0 -#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK) -/* TMROUTH Bit Fields */ -#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu -#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0 -#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK) -/* TMROUTL Bit Fields */ -#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu -#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0 -#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK) -/* RSTCNT Bit Fields */ -#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu -#define WDOG_RSTCNT_RSTCNT_SHIFT 0 -#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK) -/* PRESC Bit Fields */ -#define WDOG_PRESC_PRESCVAL_MASK 0x700u -#define WDOG_PRESC_PRESCVAL_SHIFT 8 -#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK) - -/** - * @} - */ /* end of group WDOG_Register_Masks */ - - -/* WDOG - Peripheral instance base addresses */ -/** Peripheral WDOG base address */ -#define WDOG_BASE (0x40052000u) -/** Peripheral WDOG base pointer */ -#define WDOG ((WDOG_Type *)WDOG_BASE) - -/** - * @} - */ /* end of group WDOG_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma pop -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/** - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Backward Compatibility - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Backward_Compatibility_Symbols Backward Compatibility - * @{ - */ - -/* No backward compatibility issues. */ - -/** - * @} - */ /* end of group Backward_Compatibility_Symbols */ - - -#endif /* #if !defined(MK20D5_H_) */ - -/* MK20D5.h, eof. */
--- a/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,14 +0,0 @@ - -LR_IROM1 0x00000000 0x20000 { ; load region size_region (132k) - ER_IROM1 0x00000000 0x20000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0xF8) = 0xF8 - ; 0x4000 - 0xF8 = 0x3F08 - RW_IRAM1 0x1FFFE0F8 0x3F08 { - .ANY (+RW +ZI) - } -} -
--- a/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,412 +0,0 @@ -;/***************************************************************************** -; * @file: startup_MK20D5.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the -; * MK20D5 -; * @version: 1.0 -; * @date: 2011-12-15 -; * -; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved. -;* -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - - -__initial_sp EQU 0x20002000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt - DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt - DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt - DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt - DCD DMA_Error_IRQHandler ; DMA error interrupt - DCD Reserved21_IRQHandler ; Reserved interrupt 21 - DCD FTFL_IRQHandler ; FTFL interrupt - DCD Read_Collision_IRQHandler ; Read collision interrupt - DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning - DCD LLW_IRQHandler ; Low Leakage Wakeup - DCD Watchdog_IRQHandler ; WDOG interrupt - DCD I2C0_IRQHandler ; I2C0 interrupt - DCD SPI0_IRQHandler ; SPI0 interrupt - DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt - DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt - DCD UART0_LON_IRQHandler ; UART0 LON interrupt - DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt - DCD UART0_ERR_IRQHandler ; UART0 error interrupt - DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt - DCD UART1_ERR_IRQHandler ; UART1 error interrupt - DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt - DCD UART2_ERR_IRQHandler ; UART2 error interrupt - DCD ADC0_IRQHandler ; ADC0 interrupt - DCD CMP0_IRQHandler ; CMP0 interrupt - DCD CMP1_IRQHandler ; CMP1 interrupt - DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt - DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt - DCD CMT_IRQHandler ; CMT interrupt - DCD RTC_IRQHandler ; RTC interrupt - DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt - DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt - DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt - DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt - DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt - DCD PDB0_IRQHandler ; PDB0 interrupt - DCD USB0_IRQHandler ; USB0 interrupt - DCD USBDCD_IRQHandler ; USBDCD interrupt - DCD TSI0_IRQHandler ; TSI0 interrupt - DCD MCG_IRQHandler ; MCG interrupt - DCD LPTimer_IRQHandler ; LPTimer interrupt - DCD PORTA_IRQHandler ; Port A interrupt - DCD PORTB_IRQHandler ; Port B interrupt - DCD PORTC_IRQHandler ; Port C interrupt - DCD PORTD_IRQHandler ; Port D interrupt - DCD PORTE_IRQHandler ; Port E interrupt - DCD SWI_IRQHandler ; Software interrupt -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; <h> Flash Configuration -; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) -; <i> and security information that allows the MCU to restrict acces to the FTFL module. -; <h> Backdoor Comparison Key -; <o0> Backdoor Key 0 <0x0-0xFF:2> -; <o1> Backdoor Key 1 <0x0-0xFF:2> -; <o2> Backdoor Key 2 <0x0-0xFF:2> -; <o3> Backdoor Key 3 <0x0-0xFF:2> -; <o4> Backdoor Key 4 <0x0-0xFF:2> -; <o5> Backdoor Key 5 <0x0-0xFF:2> -; <o6> Backdoor Key 6 <0x0-0xFF:2> -; <o7> Backdoor Key 7 <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; </h> -; <h> Program flash protection bytes (FPROT) -; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; <i> Each bit protects a 1/32 region of the program flash memory. -; <h> FPROT0 -; <i> Program flash protection bytes -; <i> 1/32 - 8/32 region -; <o.0> FPROT0.0 -; <o.1> FPROT0.1 -; <o.2> FPROT0.2 -; <o.3> FPROT0.3 -; <o.4> FPROT0.4 -; <o.5> FPROT0.5 -; <o.6> FPROT0.6 -; <o.7> FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; </h> -; <h> FPROT1 -; <i> Program Flash Region Protect Register 1 -; <i> 9/32 - 16/32 region -; <o.0> FPROT1.0 -; <o.1> FPROT1.1 -; <o.2> FPROT1.2 -; <o.3> FPROT1.3 -; <o.4> FPROT1.4 -; <o.5> FPROT1.5 -; <o.6> FPROT1.6 -; <o.7> FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; </h> -; <h> FPROT2 -; <i> Program Flash Region Protect Register 2 -; <i> 17/32 - 24/32 region -; <o.0> FPROT2.0 -; <o.1> FPROT2.1 -; <o.2> FPROT2.2 -; <o.3> FPROT2.3 -; <o.4> FPROT2.4 -; <o.5> FPROT2.5 -; <o.6> FPROT2.6 -; <o.7> FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; </h> -; <h> FPROT3 -; <i> Program Flash Region Protect Register 3 -; <i> 25/32 - 32/32 region -; <o.0> FPROT3.0 -; <o.1> FPROT3.1 -; <o.2> FPROT3.2 -; <o.3> FPROT3.3 -; <o.4> FPROT3.4 -; <o.5> FPROT3.5 -; <o.6> FPROT3.6 -; <o.7> FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; </h> -; </h> -; <h> Data flash protection byte (FDPROT) -; <i> Each bit protects a 1/8 region of the data flash memory. -; <i> (Program flash only devices: Reserved) -; <o.0> FDPROT.0 -; <o.1> FDPROT.1 -; <o.2> FDPROT.2 -; <o.3> FDPROT.3 -; <o.4> FDPROT.4 -; <o.5> FDPROT.5 -; <o.6> FDPROT.6 -; <o.7> FDPROT.7 -nFDPROT EQU 0x00 -FDPROT EQU nFDPROT:EOR:0xFF -; </h> -; <h> EEPROM protection byte (FEPROT) -; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. -; <i> (Program flash only devices: Reserved) -; <o.0> FEPROT.0 -; <o.1> FEPROT.1 -; <o.2> FEPROT.2 -; <o.3> FEPROT.3 -; <o.4> FEPROT.4 -; <o.5> FEPROT.5 -; <o.6> FEPROT.6 -; <o.7> FEPROT.7 -nFEPROT EQU 0x00 -FEPROT EQU nFEPROT:EOR:0xFF -; </h> -; <h> Flash nonvolatile option byte (FOPT) -; <i> Allows the user to customize the operation of the MCU at boot time. -; <o.0> LPBOOT -; <0=> Low-power boot -; <1=> normal boot -; <o.1> EZPORT_DIS -; <0=> EzPort operation is enabled -; <1=> EzPort operation is disabled -FOPT EQU 0xFF -; </h> -; <h> Flash security byte (FSEC) -; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; <o.0..1> SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; <i> Flash Security -; <i> This bits define the security state of the MCU. -; <o.2..3> FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; <i> Freescale Failure Analysis Access Code -; <i> This bits define the security state of the MCU. -; <o.4..5> MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; <i> Mass Erase Enable Bits -; <i> Enables and disables mass erase capability of the FTFL module -; <o.6..7> KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; <i> Backdoor key Security Enable -; <i> These bits enable and disable backdoor key access to the FTFL module. -FSEC EQU 0xFE -; </h> -; </h> - IF :LNOT::DEF:RAM_TARGET - AREA |.ARM.__at_0x400|, CODE, READONLY - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0, FPROT1, FPROT2, FPROT3 - DCB FSEC, FOPT, FEPROT, FDPROT - ENDIF - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT DMA0_IRQHandler [WEAK] - EXPORT DMA1_IRQHandler [WEAK] - EXPORT DMA2_IRQHandler [WEAK] - EXPORT DMA3_IRQHandler [WEAK] - EXPORT DMA_Error_IRQHandler [WEAK] - EXPORT Reserved21_IRQHandler [WEAK] - EXPORT FTFL_IRQHandler [WEAK] - EXPORT Read_Collision_IRQHandler [WEAK] - EXPORT LVD_LVW_IRQHandler [WEAK] - EXPORT LLW_IRQHandler [WEAK] - EXPORT Watchdog_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT I2S0_Tx_IRQHandler [WEAK] - EXPORT I2S0_Rx_IRQHandler [WEAK] - EXPORT UART0_LON_IRQHandler [WEAK] - EXPORT UART0_RX_TX_IRQHandler [WEAK] - EXPORT UART0_ERR_IRQHandler [WEAK] - EXPORT UART1_RX_TX_IRQHandler [WEAK] - EXPORT UART1_ERR_IRQHandler [WEAK] - EXPORT UART2_RX_TX_IRQHandler [WEAK] - EXPORT UART2_ERR_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT CMP1_IRQHandler [WEAK] - EXPORT FTM0_IRQHandler [WEAK] - EXPORT FTM1_IRQHandler [WEAK] - EXPORT CMT_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT PIT0_IRQHandler [WEAK] - EXPORT PIT1_IRQHandler [WEAK] - EXPORT PIT2_IRQHandler [WEAK] - EXPORT PIT3_IRQHandler [WEAK] - EXPORT PDB0_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT USBDCD_IRQHandler [WEAK] - EXPORT TSI0_IRQHandler [WEAK] - EXPORT MCG_IRQHandler [WEAK] - EXPORT LPTimer_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTB_IRQHandler [WEAK] - EXPORT PORTC_IRQHandler [WEAK] - EXPORT PORTD_IRQHandler [WEAK] - EXPORT PORTE_IRQHandler [WEAK] - EXPORT SWI_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] - -DMA0_IRQHandler -DMA1_IRQHandler -DMA2_IRQHandler -DMA3_IRQHandler -DMA_Error_IRQHandler -Reserved21_IRQHandler -FTFL_IRQHandler -Read_Collision_IRQHandler -LVD_LVW_IRQHandler -LLW_IRQHandler -Watchdog_IRQHandler -I2C0_IRQHandler -SPI0_IRQHandler -I2S0_Tx_IRQHandler -I2S0_Rx_IRQHandler -UART0_LON_IRQHandler -UART0_RX_TX_IRQHandler -UART0_ERR_IRQHandler -UART1_RX_TX_IRQHandler -UART1_ERR_IRQHandler -UART2_RX_TX_IRQHandler -UART2_ERR_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -CMP1_IRQHandler -FTM0_IRQHandler -FTM1_IRQHandler -CMT_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT0_IRQHandler -PIT1_IRQHandler -PIT2_IRQHandler -PIT3_IRQHandler -PDB0_IRQHandler -USB0_IRQHandler -USBDCD_IRQHandler -TSI0_IRQHandler -MCG_IRQHandler -LPTimer_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -SWI_IRQHandler -DefaultISR - - B . - - ENDP - - - ALIGN - END
--- a/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,31 +0,0 @@ -/* mbed Microcontroller Library - stackheap - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * Setup a fixed single stack/heap memory model, - * between the top of the RW/ZI region and the stackpointer - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rt_misc.h> -#include <stdint.h> - -extern char Image$$RW_IRAM1$$ZI$$Limit[]; - -extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { - uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; - uint32_t sp_limit = __current_sp(); - - zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned - - struct __initial_stackheap r; - r.heap_base = zi_limit; - r.heap_limit = sp_limit; - return r; -} - -#ifdef __cplusplus -} -#endif
--- a/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,163 +0,0 @@ -/* - * K20 ARM GCC linker script file - */ - -MEMORY -{ - VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 - FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010 - FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410 - RAM (rwx) : ORIGIN = 0x1FFFE0F8, LENGTH = 16K - 0xF8 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * _reset_init : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .isr_vector : - { - __vector_table = .; - KEEP(*(.vector_table)) - *(.text.Reset_Handler) - *(.text.System_Init) - . = ALIGN(4); - } > VECTORS - - .flash_protect : - { - KEEP(*(.kinetis_flash_config_field)) - . = ALIGN(4); - } > FLASH_PROTECTION - - .text : - { - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -}
--- a/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,259 +0,0 @@ -/* File: startup_MK20D5.s - * Purpose: startup file for Cortex-M4 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.3 - * Date: 08 Feb 2012 - * - * Copyright (c) 2012, ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the ARM Limited nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - .syntax unified - .arch armv7-m - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x400 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0xC00 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long DMA0_IRQHandler /* 0: Watchdog Timer */ - .long DMA1_IRQHandler /* 1: Real Time Clock */ - .long DMA2_IRQHandler /* 2: Timer0 / Timer1 */ - .long DMA3_IRQHandler /* 3: Timer2 / Timer3 */ - .long DMA_Error_IRQHandler /* 4: MCIa */ - .long 0 /* 5: MCIb */ - .long FTFL_IRQHandler /* 6: UART0 - DUT FPGA */ - .long Read_Collision_IRQHandler /* 7: UART1 - DUT FPGA */ - .long LVD_LVW_IRQHandler /* 8: UART2 - DUT FPGA */ - .long LLW_IRQHandler /* 9: UART4 - not connected */ - .long Watchdog_IRQHandler /* 10: AACI / AC97 */ - .long I2C0_IRQHandler /* 11: CLCD Combined Interrupt */ - .long SPI0_IRQHandler /* 12: Ethernet */ - .long I2S0_Tx_IRQHandler /* 13: USB Device */ - .long I2S0_Rx_IRQHandler /* 14: USB Host Controller */ - .long UART0_LON_IRQHandler /* 15: Character LCD */ - .long UART0_RX_TX_IRQHandler /* 16: Flexray */ - .long UART0_ERR_IRQHandler /* 17: CAN */ - .long UART1_RX_TX_IRQHandler /* 18: LIN */ - .long UART1_ERR_IRQHandler /* 19: I2C ADC/DAC */ - .long UART2_RX_TX_IRQHandler /* 20: Reserved */ - .long UART2_ERR_IRQHandler /* 21: Reserved */ - .long ADC0_IRQHandler /* 22: Reserved */ - .long CMP0_IRQHandler /* 23: Reserved */ - .long CMP1_IRQHandler /* 24: Reserved */ - .long FTM0_IRQHandler /* 25: Reserved */ - .long FTM1_IRQHandler /* 26: Reserved */ - .long CMT_IRQHandler /* 27: Reserved */ - .long RTC_IRQHandler /* 28: Reserved - CPU FPGA CLCD */ - .long RTC_Seconds_IRQHandler /* 29: Reserved - CPU FPGA */ - .long PIT0_IRQHandler /* 30: UART3 - CPU FPGA */ - .long PIT1_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ - .long PIT2_IRQHandler - .long PIT3_IRQHandler - .long PDB0_IRQHandler - .long USB0_IRQHandler - .long USBDCD_IRQHandler - .long TSI0_IRQHandler - .long MCG_IRQHandler - .long LPTimer_IRQHandler - .long PORTA_IRQHandler - .long PORTB_IRQHandler - .long PORTC_IRQHandler - .long PORTD_IRQHandler - .long PORTE_IRQHandler - .long SWI_IRQHandler - .size __isr_vector, . - __isr_vector - - .section .text.Reset_Handler - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.Lflash_to_ram_loop: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .Lflash_to_ram_loop - -.Lflash_to_ram_loop_end: - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler MemManage_Handler - def_default_handler BusFault_Handler - def_default_handler UsageFault_Handler - def_default_handler SVC_Handler - def_default_handler DebugMon_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_default_handler DMA0_IRQHandler - def_irq_default_handler DMA1_IRQHandler - def_irq_default_handler DMA2_IRQHandler - def_irq_default_handler DMA3_IRQHandler - def_irq_default_handler DMA_Error_IRQHandler - def_irq_default_handler FTFL_IRQHandler - def_irq_default_handler Read_Collision_IRQHandler - def_irq_default_handler LVD_LVW_IRQHandler - def_irq_default_handler LLW_IRQHandler - def_irq_default_handler Watchdog_IRQHandler - def_irq_default_handler I2C0_IRQHandler - def_irq_default_handler SPI0_IRQHandler - def_irq_default_handler I2S0_Tx_IRQHandler - def_irq_default_handler I2S0_Rx_IRQHandler - def_irq_default_handler UART0_LON_IRQHandler - def_irq_default_handler UART0_RX_TX_IRQHandler - def_irq_default_handler UART0_ERR_IRQHandler - def_irq_default_handler UART1_RX_TX_IRQHandler - def_irq_default_handler UART1_ERR_IRQHandler - def_irq_default_handler UART2_RX_TX_IRQHandler - def_irq_default_handler UART2_ERR_IRQHandler - def_irq_default_handler ADC0_IRQHandler - def_irq_default_handler CMP0_IRQHandler - def_irq_default_handler CMP1_IRQHandler - def_irq_default_handler FTM0_IRQHandler - def_irq_default_handler FTM1_IRQHandler - def_irq_default_handler CMT_IRQHandler - def_irq_default_handler RTC_IRQHandler - def_irq_default_handler RTC_Seconds_IRQHandler - def_irq_default_handler PIT0_IRQHandler - def_irq_default_handler PIT1_IRQHandler - def_irq_default_handler PIT2_IRQHandler - def_irq_default_handler PIT3_IRQHandler - def_irq_default_handler PDB0_IRQHandler - def_irq_default_handler USB0_IRQHandler - def_irq_default_handler USBDCD_IRQHandler - def_irq_default_handler TSI0_IRQHandler - def_irq_default_handler MCG_IRQHandler - def_irq_default_handler LPTimer_IRQHandler - def_irq_default_handler PORTA_IRQHandler - def_irq_default_handler PORTB_IRQHandler - def_irq_default_handler PORTC_IRQHandler - def_irq_default_handler PORTD_IRQHandler - def_irq_default_handler PORTE_IRQHandler - def_irq_default_handler SWI_IRQHandler - def_irq_default_handler DEF_IRQHandler - -/* Flash protection region, placed at 0x400 */ - .text - .thumb - .align 2 - .section .kinetis_flash_config_field,"a",%progbits -kinetis_flash_config: - .long 0xffffffff - .long 0xffffffff - .long 0xffffffff - .long 0xfffffffe - - .end
--- a/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,51 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0001ffff; -define symbol __ICFEDIT_region_NVIC_start__ = 0x1fffe000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x1fffe0f7; -define symbol __ICFEDIT_region_RAM_start__ = 0x1fffe0f8; -define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x800; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __region_RAM2_start__ = 0x20000000; -define symbol __region_RAM2_end__ = 0x20001fff; - -define symbol __FlashConfig_start__ = 0x00000400; -define symbol __FlashConfig_end__ = 0x0000040f; - -define symbol __region_FlexNVM_start__ = 0x10000000; -define symbol __region_FlexNVM_end__ = 0x10007fff; - -define symbol __region_FlexRAM_start__ = 0x14000000; -define symbol __region_FlexRAM_end__ = 0x140007ff; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__] | mem:[from __region_FlexNVM_start__ to __region_FlexNVM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__]; -define region FlexRAM_region = mem:[from __region_FlexRAM_start__ to __region_FlexRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__]; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in FlashConfig_region {section FlashConfig}; - -place in ROM_region { readonly }; - -place in RAM_region { readwrite, block HEAP, block CSTACK }; - -place in FlexRAM_region { section .flex_ram };
--- a/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,271 +0,0 @@ -/************************************************** - * - * Copyright 2010 IAR Systems. All rights reserved. - * - * $Revision: 16 $ - * - **************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:ROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - ; External Interrupts - DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete - DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete - DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete - DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete - DCD DMA_ERR_IRQHandler ; 4: DMA Error Interrupt Channels 0-15 - DCD 0 ; 5: Reserved - DCD FLASH_CC_IRQHandler ; 6: Flash memory command complete - DCD FLASH_RC_IRQHandler ; 7: Flash memory read collision - DCD VLD_IRQHandler ; 8: Low Voltage Detect, Low Voltage Warning - DCD LLWU_IRQHandler ; 9: Low Leakage Wakeup - DCD WDOG_IRQHandler ;10: WDOG interrupt - DCD I2C0_IRQHandler ;11: I2C0 interrupt - DCD SPI0_IRQHandler ;12: SPI 0 interrupt - DCD I2S0_IRQHandler ;13: I2S 0 interrupt - DCD I2S1_IRQHandler ;14: I2S 1 interrupt - DCD UART0_LON_IRQHandler ;15: UART 0 LON intertrupt - DCD UART0_IRQHandler ;16: UART 0 intertrupt - DCD UART0_ERR_IRQHandler ;17: UART 0 error intertrupt - DCD UART1_IRQHandler ;18: UART 1 intertrupt - DCD UART1_ERR_IRQHandler ;19: UART 1 error intertrupt - DCD UART2_IRQHandler ;20: UART 2 intertrupt - DCD UART2_ERR_IRQHandler ;21: UART 2 error intertrupt - DCD ADC0_IRQHandler ;22: ADC 0 interrupt - DCD CMP0_IRQHandler ;23: CMP 0 High-speed comparator interrupt - DCD CMP1_IRQHandler ;24: CMP 1 interrupt - DCD FTM0_IRQHandler ;25: FTM 0 interrupt - DCD FTM1_IRQHandler ;26: FTM 1 interrupt - DCD CMT_IRQHandler ;27: CMT intrrupt - DCD RTC_ALRM_IRQHandler ;28: RTC Alarm interrupt - DCD RTC_SEC_IRQHandler ;29: RTC Sec interrupt - DCD PIT0_IRQHandler ;30: PIT 0 interrupt - DCD PIT1_IRQHandler ;31: PIT 1 interrupt - DCD PIT2_IRQHandler ;32: PIT 2 interrupt - DCD PIT3_IRQHandler ;33: PIT 3 interrupt - DCD PDB_IRQHandler ;34: PDB interrupt - DCD USB_OTG_IRQHandler ;35: USB OTG interrupt - DCD USB_CD_IRQHandler ;36: USB Charger Detect interrupt - DCD TSI_IRQHandler ;37: TSI interrupt - DCD MCG_IRQHandler ;38: MCG interrupt - DCD LPT_IRQHandler ;39: LPT interrupt - DCD PORTA_IRQHandler ;40: PORT A interrupt - DCD PORTB_IRQHandler ;41: PORT B interrupt - DCD PORTC_IRQHandler ;42: PORT C interrupt - DCD PORTD_IRQHandler ;43: PORT D interrupt - DCD PORTE_IRQHandler ;44: PORT E interrupt - DCD SW_IRQHandler ;45: Software initiated interrupt -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;;Flash Configuration -;;16-byte flash configuration field that stores default protection settings (loaded on reset) -;;and security information that allows the MCU to restrict acces to the FTFL module. - -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF - -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0^0xFF - -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1^0xFF - -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2^0xFF - -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3^0xFF - -nFEPROT EQU 0x00 -FEPROT EQU nFEPROT^0xFF - -nFDPROT EQU 0x00 -FDPROT EQU nFDPROT^0xFF - -FOPT EQU 0xFF - -FSEC EQU 0xFE - SECTION FlashConfig:CONST:REORDER:ROOT(2) -Config: - DATA - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0, FPROT1, FPROT2, FPROT3 - DCB FSEC, FOPT, FEPROT, FDPROT -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA2_IRQHandler - PUBWEAK DMA3_IRQHandler - PUBWEAK DMA_ERR_IRQHandler - PUBWEAK FLASH_CC_IRQHandler - PUBWEAK FLASH_RC_IRQHandler - PUBWEAK VLD_IRQHandler - PUBWEAK LLWU_IRQHandler - PUBWEAK WDOG_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK SPI0_IRQHandler - PUBWEAK I2S0_IRQHandler - PUBWEAK I2S1_IRQHandler - PUBWEAK UART0_LON_IRQHandler - PUBWEAK UART0_IRQHandler - PUBWEAK UART0_ERR_IRQHandler - PUBWEAK UART1_IRQHandler - PUBWEAK UART1_ERR_IRQHandler - PUBWEAK UART2_IRQHandler - PUBWEAK UART2_ERR_IRQHandler - PUBWEAK ADC0_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK CMP1_IRQHandler - PUBWEAK FTM0_IRQHandler - PUBWEAK FTM1_IRQHandler - PUBWEAK CMT_IRQHandler - PUBWEAK RTC_ALRM_IRQHandler - PUBWEAK RTC_SEC_IRQHandler - PUBWEAK PIT0_IRQHandler - PUBWEAK PIT1_IRQHandler - PUBWEAK PIT2_IRQHandler - PUBWEAK PIT3_IRQHandler - PUBWEAK PDB_IRQHandler - PUBWEAK USB_OTG_IRQHandler - PUBWEAK USB_CD_IRQHandler - PUBWEAK TSI_IRQHandler - PUBWEAK MCG_IRQHandler - PUBWEAK LPT_IRQHandler - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTB_IRQHandler - PUBWEAK PORTC_IRQHandler - PUBWEAK PORTD_IRQHandler - PUBWEAK PORTE_IRQHandler - PUBWEAK SW_IRQHandler - - SECTION .text:CODE:REORDER:NOROOT(1) - THUMB -NMI_Handler -HardFault_Handler -MemManage_Handler -BusFault_Handler -UsageFault_Handler -SVC_Handler -DebugMon_Handler -PendSV_Handler -SysTick_Handler -DMA0_IRQHandler -DMA1_IRQHandler -DMA2_IRQHandler -DMA3_IRQHandler -DMA_ERR_IRQHandler -FLASH_CC_IRQHandler -FLASH_RC_IRQHandler -VLD_IRQHandler -LLWU_IRQHandler -WDOG_IRQHandler -I2C0_IRQHandler -SPI0_IRQHandler -I2S0_IRQHandler -I2S1_IRQHandler -UART0_LON_IRQHandler -UART0_IRQHandler -UART0_ERR_IRQHandler -UART1_IRQHandler -UART1_ERR_IRQHandler -UART2_IRQHandler -UART2_ERR_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -CMP1_IRQHandler -FTM0_IRQHandler -FTM1_IRQHandler -CMT_IRQHandler -RTC_ALRM_IRQHandler -RTC_SEC_IRQHandler -PIT0_IRQHandler -PIT1_IRQHandler -PIT2_IRQHandler -PIT3_IRQHandler -PDB_IRQHandler -USB_OTG_IRQHandler -USB_CD_IRQHandler -TSI_IRQHandler -MCG_IRQHandler -LPT_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -SW_IRQHandler -Default_Handler - - B Default_Handler - END
--- a/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis.h Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC11U24 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "MK20D5.h" -#include "cmsis_nvic.h" - -#endif
--- a/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis_nvic.c Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,55 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "cmsis_nvic.h" - -#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM -#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - uint32_t i; - - // Copy and switch to dynamic vectors if the first time called - if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { - uint32_t *old_vectors = vectors; - vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; - for (i=0; i<NVIC_NUM_VECTORS; i++) { - vectors[i] = old_vectors[i]; - } - SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; - } - vectors[IRQn + 16] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - return vectors[IRQn + 16]; -}
--- a/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis_nvic.h Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,51 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals -#define NVIC_USER_IRQ_OFFSET 16 - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/system_MK20D5.c Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,278 +0,0 @@ -/* -** ################################################################### -** Compilers: ARM Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011 -** K20P32M50SF0RM Rev. 1, Oct 2011 -** K20P48M50SF0RM Rev. 1, Oct 2011 -** -** Version: rev. 1.0, 2011-12-15 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright: 2011 Freescale Semiconductor, Inc. All Rights Reserved. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2011-12-15) -** Initial version -** -** ################################################################### -*/ - -/** - * @file MK20D5 - * @version 1.0 - * @date 2011-12-15 - * @brief Device specific configuration file for MK20D5 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include <stdint.h> -#include "MK20D5.h" - -#define DISABLE_WDOG 1 - -#define CLOCK_SETUP 1 -/* Predefined clock setups - 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode - Reference clock source for MCG module is the slow internal clock source 32.768kHz - Core clock = 41.94MHz, BusClock = 41.94MHz - 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode - Reference clock source for MCG module is an external crystal 8MHz - Core clock = 48MHz, BusClock = 48MHz - 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode - Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication - Core clock = 8MHz, BusClock = 8MHz -*/ - -/*---------------------------------------------------------------------------- - Define clock source values - *----------------------------------------------------------------------------*/ -#if (CLOCK_SETUP == 0) - #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ - #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ - #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */ -#elif (CLOCK_SETUP == 1) - #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ - #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ - #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ -#elif (CLOCK_SETUP == 2) - #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ - #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ - #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */ -#endif /* (CLOCK_SETUP == 2) */ - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -void SystemInit (void) { -#if (DISABLE_WDOG) - /* Disable the WDOG module */ - /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */ - WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */ - /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */ - WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */ - /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ - WDOG->STCTRLH = (uint16_t)0x01D2u; -#endif /* (DISABLE_WDOG) */ -#if (CLOCK_SETUP == 0) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ - SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ - /* Switch to FEI Mode */ - /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x06u; - /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */ - MCG->C2 = (uint8_t)0x00u; - /* MCG_C4: DMX32=0,DRST_DRS=1 */ - MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u); - /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ - MCG->C5 = (uint8_t)0x00u; - /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ - MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */ - } - while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */ - } -#elif (CLOCK_SETUP == 1) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ - SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ - /* Switch to FBE Mode */ - /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - OSC0->CR = (uint8_t)0x00u; - /* MCG->C7: OSCSEL=0 */ - MCG->C7 = (uint8_t)0x00u; - /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = (uint8_t)0x24u; - /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x9Au; - /* MCG->C4: DMX32=0,DRST_DRS=0 */ - MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; - /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ - MCG->C5 = (uint8_t)0x03u; - /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ - MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ - } -#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ - while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ - } -#endif - while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ - } - /* Switch to PBE Mode */ - /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ - MCG->C5 = (uint8_t)0x03u; - /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */ - MCG->C6 = (uint8_t)0x40u; - while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */ - } - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ - } - /* Switch to PEE Mode */ - /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x1Au; - while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */ - } - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ - } -#elif (CLOCK_SETUP == 2) - /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ - SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ - /* Switch to FBE Mode */ - /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - OSC0->CR = (uint8_t)0x00u; - /* MCG->C7: OSCSEL=0 */ - MCG->C7 = (uint8_t)0x00u; - /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = (uint8_t)0x24u; - /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x9Au; - /* MCG->C4: DMX32=0,DRST_DRS=0 */ - MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; - /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ - MCG->C5 = (uint8_t)0x00u; - /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ - MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ - } -#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ - while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ - } -#endif - while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ - } - /* Switch to BLPE Mode */ - /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = (uint8_t)0x24u; -#endif /* (CLOCK_SETUP == 2) */ -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ - uint8_t Divider; - - if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { - /* Output of FLL or PLL is selected */ - if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { - /* FLL is selected */ - if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { - /* External reference clock is selected */ - if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ - Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ - if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { - MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */ - } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */ - } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ - } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ - /* Select correct multiplier to calculate the MCG output clock */ - switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { - case 0x0u: - MCGOUTClock *= 640u; - break; - case 0x20u: - MCGOUTClock *= 1280u; - break; - case 0x40u: - MCGOUTClock *= 1920u; - break; - case 0x60u: - MCGOUTClock *= 2560u; - break; - case 0x80u: - MCGOUTClock *= 732u; - break; - case 0xA0u: - MCGOUTClock *= 1464u; - break; - case 0xC0u: - MCGOUTClock *= 2197u; - break; - case 0xE0u: - MCGOUTClock *= 2929u; - break; - default: - break; - } - } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ - /* PLL is selected */ - Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); - MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ - Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); - MCGOUTClock *= Divider; /* Calculate the MCG output clock */ - } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { - /* Internal reference clock is selected */ - if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { - MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ - } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ - MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ - } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ - } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { - /* External reference clock is selected */ - if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { - MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ - } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ - MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ - } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ - } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ - /* Reserved value */ - return; - } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ - SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); -}
--- a/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/system_MK20D5.h Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,87 +0,0 @@ -/* -** ################################################################### -** Compilers: ARM Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011 -** K20P32M50SF0RM Rev. 1, Oct 2011 -** K20P48M50SF0RM Rev. 1, Oct 2011 -** -** Version: rev. 2.0, 2012-03-19 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2011-12-15) -** Initial version -** - rev. 2.0 (2012-03-19) -** PDB Peripheral register structure updated. -** DMA Registers and bits for unsupported DMA channels removed. -** -** ################################################################### -*/ - -/** - * @file MK20D5 - * @version 2.0 - * @date 2012-03-19 - * @brief Device specific configuration file for MK20D5 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef SYSTEM_MK20D5_H_ -#define SYSTEM_MK20D5_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include <stdint.h> - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* #if !defined(SYSTEM_MK20D5_H_) */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/MK20D5.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,5836 @@ +/* +** ################################################################### +** Compilers: ARM Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011 +** K20P32M50SF0RM Rev. 1, Oct 2011 +** K20P48M50SF0RM Rev. 1, Oct 2011 +** +** Version: rev. 2.0, 2012-03-19 +** +** Abstract: +** CMSIS Peripheral Access Layer for MK20D5 +** +** Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2011-12-15) +** Initial version +** - rev. 2.0 (2012-03-19) +** PDB Peripheral register structure updated. +** DMA Registers and bits for unsupported DMA channels removed. +** +** ################################################################### +*/ + +/** + * @file MK20D5.h + * @version 2.0 + * @date 2012-03-19 + * @brief CMSIS Peripheral Access Layer for MK20D5 + * + * CMSIS Peripheral Access Layer for MK20D5 + */ + +#if !defined(MK20D5_H_) +#define MK20D5_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0200u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000u + +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +typedef enum IRQn { + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */ + DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */ + DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */ + DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */ + DMA_Error_IRQn = 4, /**< DMA error interrupt */ + Reserved21_IRQn = 5, /**< Reserved interrupt 21 */ + FTFL_IRQn = 6, /**< FTFL interrupt */ + Read_Collision_IRQn = 7, /**< Read collision interrupt */ + LVD_LVW_IRQn = 8, /**< Low Voltage Detect, Low Voltage Warning */ + LLW_IRQn = 9, /**< Low Leakage Wakeup */ + Watchdog_IRQn = 10, /**< WDOG interrupt */ + I2C0_IRQn = 11, /**< I2C0 interrupt */ + SPI0_IRQn = 12, /**< SPI0 interrupt */ + I2S0_Tx_IRQn = 13, /**< I2S0 transmit interrupt */ + I2S0_Rx_IRQn = 14, /**< I2S0 receive interrupt */ + UART0_LON_IRQn = 15, /**< UART0 LON interrupt */ + UART0_RX_TX_IRQn = 16, /**< UART0 receive/transmit interrupt */ + UART0_ERR_IRQn = 17, /**< UART0 error interrupt */ + UART1_RX_TX_IRQn = 18, /**< UART1 receive/transmit interrupt */ + UART1_ERR_IRQn = 19, /**< UART1 error interrupt */ + UART2_RX_TX_IRQn = 20, /**< UART2 receive/transmit interrupt */ + UART2_ERR_IRQn = 21, /**< UART2 error interrupt */ + ADC0_IRQn = 22, /**< ADC0 interrupt */ + CMP0_IRQn = 23, /**< CMP0 interrupt */ + CMP1_IRQn = 24, /**< CMP1 interrupt */ + FTM0_IRQn = 25, /**< FTM0 fault, overflow and channels interrupt */ + FTM1_IRQn = 26, /**< FTM1 fault, overflow and channels interrupt */ + CMT_IRQn = 27, /**< CMT interrupt */ + RTC_IRQn = 28, /**< RTC interrupt */ + RTC_Seconds_IRQn = 29, /**< RTC seconds interrupt */ + PIT0_IRQn = 30, /**< PIT timer channel 0 interrupt */ + PIT1_IRQn = 31, /**< PIT timer channel 1 interrupt */ + PIT2_IRQn = 32, /**< PIT timer channel 2 interrupt */ + PIT3_IRQn = 33, /**< PIT timer channel 3 interrupt */ + PDB0_IRQn = 34, /**< PDB0 interrupt */ + USB0_IRQn = 35, /**< USB0 interrupt */ + USBDCD_IRQn = 36, /**< USBDCD interrupt */ + TSI0_IRQn = 37, /**< TSI0 interrupt */ + MCG_IRQn = 38, /**< MCG interrupt */ + LPTimer_IRQn = 39, /**< LPTimer interrupt */ + PORTA_IRQn = 40, /**< Port A interrupt */ + PORTB_IRQn = 41, /**< Port B interrupt */ + PORTC_IRQn = 42, /**< Port C interrupt */ + PORTD_IRQn = 43, /**< Port D interrupt */ + PORTE_IRQn = 44, /**< Port E interrupt */ + SWI_IRQn = 45 /**< Software interrupt */ +} IRQn_Type; + +/** + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ +#include "system_MK20D5.h" /* Device specific configuration file */ + +/** + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */ + __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */ + __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */ + __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */ + __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */ + __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */ + __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */ + __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */ + __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */ + __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */ + __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */ + __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */ + __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */ + __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */ + __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */ + __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */ + __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */ + __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */ + __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */ + __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */ + __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */ + __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */ + __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* SC1 Bit Fields */ +#define ADC_SC1_ADCH_MASK 0x1Fu +#define ADC_SC1_ADCH_SHIFT 0 +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK) +#define ADC_SC1_DIFF_MASK 0x20u +#define ADC_SC1_DIFF_SHIFT 5 +#define ADC_SC1_AIEN_MASK 0x40u +#define ADC_SC1_AIEN_SHIFT 6 +#define ADC_SC1_COCO_MASK 0x80u +#define ADC_SC1_COCO_SHIFT 7 +/* CFG1 Bit Fields */ +#define ADC_CFG1_ADICLK_MASK 0x3u +#define ADC_CFG1_ADICLK_SHIFT 0 +#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK) +#define ADC_CFG1_MODE_MASK 0xCu +#define ADC_CFG1_MODE_SHIFT 2 +#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK) +#define ADC_CFG1_ADLSMP_MASK 0x10u +#define ADC_CFG1_ADLSMP_SHIFT 4 +#define ADC_CFG1_ADIV_MASK 0x60u +#define ADC_CFG1_ADIV_SHIFT 5 +#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK) +#define ADC_CFG1_ADLPC_MASK 0x80u +#define ADC_CFG1_ADLPC_SHIFT 7 +/* CFG2 Bit Fields */ +#define ADC_CFG2_ADLSTS_MASK 0x3u +#define ADC_CFG2_ADLSTS_SHIFT 0 +#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK) +#define ADC_CFG2_ADHSC_MASK 0x4u +#define ADC_CFG2_ADHSC_SHIFT 2 +#define ADC_CFG2_ADACKEN_MASK 0x8u +#define ADC_CFG2_ADACKEN_SHIFT 3 +#define ADC_CFG2_MUXSEL_MASK 0x10u +#define ADC_CFG2_MUXSEL_SHIFT 4 +/* R Bit Fields */ +#define ADC_R_D_MASK 0xFFFFu +#define ADC_R_D_SHIFT 0 +#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK) +/* CV1 Bit Fields */ +#define ADC_CV1_CV_MASK 0xFFFFu +#define ADC_CV1_CV_SHIFT 0 +#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK) +/* CV2 Bit Fields */ +#define ADC_CV2_CV_MASK 0xFFFFu +#define ADC_CV2_CV_SHIFT 0 +#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK) +/* SC2 Bit Fields */ +#define ADC_SC2_REFSEL_MASK 0x3u +#define ADC_SC2_REFSEL_SHIFT 0 +#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK) +#define ADC_SC2_DMAEN_MASK 0x4u +#define ADC_SC2_DMAEN_SHIFT 2 +#define ADC_SC2_ACREN_MASK 0x8u +#define ADC_SC2_ACREN_SHIFT 3 +#define ADC_SC2_ACFGT_MASK 0x10u +#define ADC_SC2_ACFGT_SHIFT 4 +#define ADC_SC2_ACFE_MASK 0x20u +#define ADC_SC2_ACFE_SHIFT 5 +#define ADC_SC2_ADTRG_MASK 0x40u +#define ADC_SC2_ADTRG_SHIFT 6 +#define ADC_SC2_ADACT_MASK 0x80u +#define ADC_SC2_ADACT_SHIFT 7 +/* SC3 Bit Fields */ +#define ADC_SC3_AVGS_MASK 0x3u +#define ADC_SC3_AVGS_SHIFT 0 +#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK) +#define ADC_SC3_AVGE_MASK 0x4u +#define ADC_SC3_AVGE_SHIFT 2 +#define ADC_SC3_ADCO_MASK 0x8u +#define ADC_SC3_ADCO_SHIFT 3 +#define ADC_SC3_CALF_MASK 0x40u +#define ADC_SC3_CALF_SHIFT 6 +#define ADC_SC3_CAL_MASK 0x80u +#define ADC_SC3_CAL_SHIFT 7 +/* OFS Bit Fields */ +#define ADC_OFS_OFS_MASK 0xFFFFu +#define ADC_OFS_OFS_SHIFT 0 +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK) +/* PG Bit Fields */ +#define ADC_PG_PG_MASK 0xFFFFu +#define ADC_PG_PG_SHIFT 0 +#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK) +/* MG Bit Fields */ +#define ADC_MG_MG_MASK 0xFFFFu +#define ADC_MG_MG_SHIFT 0 +#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK) +/* CLPD Bit Fields */ +#define ADC_CLPD_CLPD_MASK 0x3Fu +#define ADC_CLPD_CLPD_SHIFT 0 +#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK) +/* CLPS Bit Fields */ +#define ADC_CLPS_CLPS_MASK 0x3Fu +#define ADC_CLPS_CLPS_SHIFT 0 +#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK) +/* CLP4 Bit Fields */ +#define ADC_CLP4_CLP4_MASK 0x3FFu +#define ADC_CLP4_CLP4_SHIFT 0 +#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK) +/* CLP3 Bit Fields */ +#define ADC_CLP3_CLP3_MASK 0x1FFu +#define ADC_CLP3_CLP3_SHIFT 0 +#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK) +/* CLP2 Bit Fields */ +#define ADC_CLP2_CLP2_MASK 0xFFu +#define ADC_CLP2_CLP2_SHIFT 0 +#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK) +/* CLP1 Bit Fields */ +#define ADC_CLP1_CLP1_MASK 0x7Fu +#define ADC_CLP1_CLP1_SHIFT 0 +#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK) +/* CLP0 Bit Fields */ +#define ADC_CLP0_CLP0_MASK 0x3Fu +#define ADC_CLP0_CLP0_SHIFT 0 +#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK) +/* CLMD Bit Fields */ +#define ADC_CLMD_CLMD_MASK 0x3Fu +#define ADC_CLMD_CLMD_SHIFT 0 +#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK) +/* CLMS Bit Fields */ +#define ADC_CLMS_CLMS_MASK 0x3Fu +#define ADC_CLMS_CLMS_SHIFT 0 +#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK) +/* CLM4 Bit Fields */ +#define ADC_CLM4_CLM4_MASK 0x3FFu +#define ADC_CLM4_CLM4_SHIFT 0 +#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK) +/* CLM3 Bit Fields */ +#define ADC_CLM3_CLM3_MASK 0x1FFu +#define ADC_CLM3_CLM3_SHIFT 0 +#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK) +/* CLM2 Bit Fields */ +#define ADC_CLM2_CLM2_MASK 0xFFu +#define ADC_CLM2_CLM2_SHIFT 0 +#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK) +/* CLM1 Bit Fields */ +#define ADC_CLM1_CLM1_MASK 0x7Fu +#define ADC_CLM1_CLM1_SHIFT 0 +#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK) +/* CLM0 Bit Fields */ +#define ADC_CLM0_CLM0_MASK 0x3Fu +#define ADC_CLM0_CLM0_SHIFT 0 +#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK) + +/** + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x4003B000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) + +/** + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer + * @{ + */ + +/** CMP - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ + __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ + __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ + __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ + __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ + __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ +} CMP_Type; + +/* ---------------------------------------------------------------------------- + -- CMP Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CMP_Register_Masks CMP Register Masks + * @{ + */ + +/* CR0 Bit Fields */ +#define CMP_CR0_HYSTCTR_MASK 0x3u +#define CMP_CR0_HYSTCTR_SHIFT 0 +#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK) +#define CMP_CR0_FILTER_CNT_MASK 0x70u +#define CMP_CR0_FILTER_CNT_SHIFT 4 +#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK) +/* CR1 Bit Fields */ +#define CMP_CR1_EN_MASK 0x1u +#define CMP_CR1_EN_SHIFT 0 +#define CMP_CR1_OPE_MASK 0x2u +#define CMP_CR1_OPE_SHIFT 1 +#define CMP_CR1_COS_MASK 0x4u +#define CMP_CR1_COS_SHIFT 2 +#define CMP_CR1_INV_MASK 0x8u +#define CMP_CR1_INV_SHIFT 3 +#define CMP_CR1_PMODE_MASK 0x10u +#define CMP_CR1_PMODE_SHIFT 4 +#define CMP_CR1_WE_MASK 0x40u +#define CMP_CR1_WE_SHIFT 6 +#define CMP_CR1_SE_MASK 0x80u +#define CMP_CR1_SE_SHIFT 7 +/* FPR Bit Fields */ +#define CMP_FPR_FILT_PER_MASK 0xFFu +#define CMP_FPR_FILT_PER_SHIFT 0 +#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK) +/* SCR Bit Fields */ +#define CMP_SCR_COUT_MASK 0x1u +#define CMP_SCR_COUT_SHIFT 0 +#define CMP_SCR_CFF_MASK 0x2u +#define CMP_SCR_CFF_SHIFT 1 +#define CMP_SCR_CFR_MASK 0x4u +#define CMP_SCR_CFR_SHIFT 2 +#define CMP_SCR_IEF_MASK 0x8u +#define CMP_SCR_IEF_SHIFT 3 +#define CMP_SCR_IER_MASK 0x10u +#define CMP_SCR_IER_SHIFT 4 +#define CMP_SCR_DMAEN_MASK 0x40u +#define CMP_SCR_DMAEN_SHIFT 6 +/* DACCR Bit Fields */ +#define CMP_DACCR_VOSEL_MASK 0x3Fu +#define CMP_DACCR_VOSEL_SHIFT 0 +#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK) +#define CMP_DACCR_VRSEL_MASK 0x40u +#define CMP_DACCR_VRSEL_SHIFT 6 +#define CMP_DACCR_DACEN_MASK 0x80u +#define CMP_DACCR_DACEN_SHIFT 7 +/* MUXCR Bit Fields */ +#define CMP_MUXCR_MSEL_MASK 0x7u +#define CMP_MUXCR_MSEL_SHIFT 0 +#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK) +#define CMP_MUXCR_PSEL_MASK 0x38u +#define CMP_MUXCR_PSEL_SHIFT 3 +#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK) + +/** + * @} + */ /* end of group CMP_Register_Masks */ + + +/* CMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x40073000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((CMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x40073008u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((CMP_Type *)CMP1_BASE) + +/** + * @} + */ /* end of group CMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer + * @{ + */ + +/** CMT - Register Layout Typedef */ +typedef struct { + __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */ + __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */ + __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */ + __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */ + __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */ + __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */ + __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */ + __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */ + __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */ + __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */ + __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */ + __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */ +} CMT_Type; + +/* ---------------------------------------------------------------------------- + -- CMT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CMT_Register_Masks CMT Register Masks + * @{ + */ + +/* CGH1 Bit Fields */ +#define CMT_CGH1_PH_MASK 0xFFu +#define CMT_CGH1_PH_SHIFT 0 +#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK) +/* CGL1 Bit Fields */ +#define CMT_CGL1_PL_MASK 0xFFu +#define CMT_CGL1_PL_SHIFT 0 +#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK) +/* CGH2 Bit Fields */ +#define CMT_CGH2_SH_MASK 0xFFu +#define CMT_CGH2_SH_SHIFT 0 +#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK) +/* CGL2 Bit Fields */ +#define CMT_CGL2_SL_MASK 0xFFu +#define CMT_CGL2_SL_SHIFT 0 +#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK) +/* OC Bit Fields */ +#define CMT_OC_IROPEN_MASK 0x20u +#define CMT_OC_IROPEN_SHIFT 5 +#define CMT_OC_CMTPOL_MASK 0x40u +#define CMT_OC_CMTPOL_SHIFT 6 +#define CMT_OC_IROL_MASK 0x80u +#define CMT_OC_IROL_SHIFT 7 +/* MSC Bit Fields */ +#define CMT_MSC_MCGEN_MASK 0x1u +#define CMT_MSC_MCGEN_SHIFT 0 +#define CMT_MSC_EOCIE_MASK 0x2u +#define CMT_MSC_EOCIE_SHIFT 1 +#define CMT_MSC_FSK_MASK 0x4u +#define CMT_MSC_FSK_SHIFT 2 +#define CMT_MSC_BASE_MASK 0x8u +#define CMT_MSC_BASE_SHIFT 3 +#define CMT_MSC_EXSPC_MASK 0x10u +#define CMT_MSC_EXSPC_SHIFT 4 +#define CMT_MSC_CMTDIV_MASK 0x60u +#define CMT_MSC_CMTDIV_SHIFT 5 +#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK) +#define CMT_MSC_EOCF_MASK 0x80u +#define CMT_MSC_EOCF_SHIFT 7 +/* CMD1 Bit Fields */ +#define CMT_CMD1_MB_MASK 0xFFu +#define CMT_CMD1_MB_SHIFT 0 +#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK) +/* CMD2 Bit Fields */ +#define CMT_CMD2_MB_MASK 0xFFu +#define CMT_CMD2_MB_SHIFT 0 +#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK) +/* CMD3 Bit Fields */ +#define CMT_CMD3_SB_MASK 0xFFu +#define CMT_CMD3_SB_SHIFT 0 +#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK) +/* CMD4 Bit Fields */ +#define CMT_CMD4_SB_MASK 0xFFu +#define CMT_CMD4_SB_SHIFT 0 +#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK) +/* PPS Bit Fields */ +#define CMT_PPS_PPSDIV_MASK 0xFu +#define CMT_PPS_PPSDIV_SHIFT 0 +#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK) +/* DMA Bit Fields */ +#define CMT_DMA_DMA_MASK 0x1u +#define CMT_DMA_DMA_SHIFT 0 + +/** + * @} + */ /* end of group CMT_Register_Masks */ + + +/* CMT - Peripheral instance base addresses */ +/** Peripheral CMT base address */ +#define CMT_BASE (0x40062000u) +/** Peripheral CMT base pointer */ +#define CMT ((CMT_Type *)CMT_BASE) + +/** + * @} + */ /* end of group CMT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */ + __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */ + } ACCESS16BIT; + __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */ + __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */ + __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */ + __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */ + } ACCESS8BIT; + }; + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ + __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ + } GPOLY_ACCESS16BIT; + __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ + __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ + __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ + __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ + } GPOLY_ACCESS8BIT; + }; + union { /* offset: 0x8 */ + __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */ + struct { /* offset: 0x8 */ + uint8_t RESERVED_0[3]; + __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ + } CTRL_ACCESS8BIT; + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/* CRCL Bit Fields */ +#define CRC_CRCL_CRCL_MASK 0xFFFFu +#define CRC_CRCL_CRCL_SHIFT 0 +#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK) +/* CRCH Bit Fields */ +#define CRC_CRCH_CRCH_MASK 0xFFFFu +#define CRC_CRCH_CRCH_SHIFT 0 +#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK) +/* CRC Bit Fields */ +#define CRC_CRC_LL_MASK 0xFFu +#define CRC_CRC_LL_SHIFT 0 +#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK) +#define CRC_CRC_LU_MASK 0xFF00u +#define CRC_CRC_LU_SHIFT 8 +#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK) +#define CRC_CRC_HL_MASK 0xFF0000u +#define CRC_CRC_HL_SHIFT 16 +#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK) +#define CRC_CRC_HU_MASK 0xFF000000u +#define CRC_CRC_HU_SHIFT 24 +#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK) +/* CRCLL Bit Fields */ +#define CRC_CRCLL_CRCLL_MASK 0xFFu +#define CRC_CRCLL_CRCLL_SHIFT 0 +#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK) +/* CRCLU Bit Fields */ +#define CRC_CRCLU_CRCLU_MASK 0xFFu +#define CRC_CRCLU_CRCLU_SHIFT 0 +#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK) +/* CRCHL Bit Fields */ +#define CRC_CRCHL_CRCHL_MASK 0xFFu +#define CRC_CRCHL_CRCHL_SHIFT 0 +#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK) +/* CRCHU Bit Fields */ +#define CRC_CRCHU_CRCHU_MASK 0xFFu +#define CRC_CRCHU_CRCHU_SHIFT 0 +#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK) +/* GPOLYL Bit Fields */ +#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu +#define CRC_GPOLYL_GPOLYL_SHIFT 0 +#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK) +/* GPOLYH Bit Fields */ +#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu +#define CRC_GPOLYH_GPOLYH_SHIFT 0 +#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK) +/* GPOLY Bit Fields */ +#define CRC_GPOLY_LOW_MASK 0xFFFFu +#define CRC_GPOLY_LOW_SHIFT 0 +#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK) +#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u +#define CRC_GPOLY_HIGH_SHIFT 16 +#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK) +/* GPOLYLL Bit Fields */ +#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu +#define CRC_GPOLYLL_GPOLYLL_SHIFT 0 +#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK) +/* GPOLYLU Bit Fields */ +#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu +#define CRC_GPOLYLU_GPOLYLU_SHIFT 0 +#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK) +/* GPOLYHL Bit Fields */ +#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu +#define CRC_GPOLYHL_GPOLYHL_SHIFT 0 +#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK) +/* GPOLYHU Bit Fields */ +#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu +#define CRC_GPOLYHU_GPOLYHU_SHIFT 0 +#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK) +/* CTRL Bit Fields */ +#define CRC_CTRL_TCRC_MASK 0x1000000u +#define CRC_CTRL_TCRC_SHIFT 24 +#define CRC_CTRL_WAS_MASK 0x2000000u +#define CRC_CTRL_WAS_SHIFT 25 +#define CRC_CTRL_FXOR_MASK 0x4000000u +#define CRC_CTRL_FXOR_SHIFT 26 +#define CRC_CTRL_TOTR_MASK 0x30000000u +#define CRC_CTRL_TOTR_SHIFT 28 +#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK) +#define CRC_CTRL_TOT_MASK 0xC0000000u +#define CRC_CTRL_TOT_SHIFT 30 +#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK) +/* CTRLHU Bit Fields */ +#define CRC_CTRLHU_TCRC_MASK 0x1u +#define CRC_CTRLHU_TCRC_SHIFT 0 +#define CRC_CTRLHU_WAS_MASK 0x2u +#define CRC_CTRLHU_WAS_SHIFT 1 +#define CRC_CTRLHU_FXOR_MASK 0x4u +#define CRC_CTRLHU_FXOR_SHIFT 2 +#define CRC_CTRLHU_TOTR_MASK 0x30u +#define CRC_CTRLHU_TOTR_SHIFT 4 +#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK) +#define CRC_CTRLHU_TOT_MASK 0xC0u +#define CRC_CTRLHU_TOT_SHIFT 6 +#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK) + +/** + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC base address */ +#define CRC_BASE (0x40032000u) +/** Peripheral CRC base pointer */ +#define CRC0 ((CRC_Type *)CRC_BASE) + +/** + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control Register, offset: 0x0 */ + __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ + uint8_t RESERVED_1[4]; + __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ + __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ + __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ + __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ + __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ + __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ + __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ + __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ + __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ + uint8_t RESERVED_2[4]; + __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ + uint8_t RESERVED_4[4]; + __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ + uint8_t RESERVED_5[200]; + __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ + __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ + __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ + __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ + uint8_t RESERVED_6[3836]; + struct { /* offset: 0x1000, array step: 0x20 */ + __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ + __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ + __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ + union { /* offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */ + }; + __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ + __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ + __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ + union { /* offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ + }; + __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ + __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ + union { /* offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ + }; + } TCD[4]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define DMA_CR_EDBG_MASK 0x2u +#define DMA_CR_EDBG_SHIFT 1 +#define DMA_CR_ERCA_MASK 0x4u +#define DMA_CR_ERCA_SHIFT 2 +#define DMA_CR_HOE_MASK 0x10u +#define DMA_CR_HOE_SHIFT 4 +#define DMA_CR_HALT_MASK 0x20u +#define DMA_CR_HALT_SHIFT 5 +#define DMA_CR_CLM_MASK 0x40u +#define DMA_CR_CLM_SHIFT 6 +#define DMA_CR_EMLM_MASK 0x80u +#define DMA_CR_EMLM_SHIFT 7 +#define DMA_CR_ECX_MASK 0x10000u +#define DMA_CR_ECX_SHIFT 16 +#define DMA_CR_CX_MASK 0x20000u +#define DMA_CR_CX_SHIFT 17 +/* ES Bit Fields */ +#define DMA_ES_DBE_MASK 0x1u +#define DMA_ES_DBE_SHIFT 0 +#define DMA_ES_SBE_MASK 0x2u +#define DMA_ES_SBE_SHIFT 1 +#define DMA_ES_SGE_MASK 0x4u +#define DMA_ES_SGE_SHIFT 2 +#define DMA_ES_NCE_MASK 0x8u +#define DMA_ES_NCE_SHIFT 3 +#define DMA_ES_DOE_MASK 0x10u +#define DMA_ES_DOE_SHIFT 4 +#define DMA_ES_DAE_MASK 0x20u +#define DMA_ES_DAE_SHIFT 5 +#define DMA_ES_SOE_MASK 0x40u +#define DMA_ES_SOE_SHIFT 6 +#define DMA_ES_SAE_MASK 0x80u +#define DMA_ES_SAE_SHIFT 7 +#define DMA_ES_ERRCHN_MASK 0xF00u +#define DMA_ES_ERRCHN_SHIFT 8 +#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK) +#define DMA_ES_CPE_MASK 0x4000u +#define DMA_ES_CPE_SHIFT 14 +#define DMA_ES_ECX_MASK 0x10000u +#define DMA_ES_ECX_SHIFT 16 +#define DMA_ES_VLD_MASK 0x80000000u +#define DMA_ES_VLD_SHIFT 31 +/* ERQ Bit Fields */ +#define DMA_ERQ_ERQ0_MASK 0x1u +#define DMA_ERQ_ERQ0_SHIFT 0 +#define DMA_ERQ_ERQ1_MASK 0x2u +#define DMA_ERQ_ERQ1_SHIFT 1 +#define DMA_ERQ_ERQ2_MASK 0x4u +#define DMA_ERQ_ERQ2_SHIFT 2 +#define DMA_ERQ_ERQ3_MASK 0x8u +#define DMA_ERQ_ERQ3_SHIFT 3 +/* EEI Bit Fields */ +#define DMA_EEI_EEI0_MASK 0x1u +#define DMA_EEI_EEI0_SHIFT 0 +#define DMA_EEI_EEI1_MASK 0x2u +#define DMA_EEI_EEI1_SHIFT 1 +#define DMA_EEI_EEI2_MASK 0x4u +#define DMA_EEI_EEI2_SHIFT 2 +#define DMA_EEI_EEI3_MASK 0x8u +#define DMA_EEI_EEI3_SHIFT 3 +/* CEEI Bit Fields */ +#define DMA_CEEI_CEEI_MASK 0xFu +#define DMA_CEEI_CEEI_SHIFT 0 +#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK) +#define DMA_CEEI_CAEE_MASK 0x40u +#define DMA_CEEI_CAEE_SHIFT 6 +#define DMA_CEEI_NOP_MASK 0x80u +#define DMA_CEEI_NOP_SHIFT 7 +/* SEEI Bit Fields */ +#define DMA_SEEI_SEEI_MASK 0xFu +#define DMA_SEEI_SEEI_SHIFT 0 +#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK) +#define DMA_SEEI_SAEE_MASK 0x40u +#define DMA_SEEI_SAEE_SHIFT 6 +#define DMA_SEEI_NOP_MASK 0x80u +#define DMA_SEEI_NOP_SHIFT 7 +/* CERQ Bit Fields */ +#define DMA_CERQ_CERQ_MASK 0xFu +#define DMA_CERQ_CERQ_SHIFT 0 +#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK) +#define DMA_CERQ_CAER_MASK 0x40u +#define DMA_CERQ_CAER_SHIFT 6 +#define DMA_CERQ_NOP_MASK 0x80u +#define DMA_CERQ_NOP_SHIFT 7 +/* SERQ Bit Fields */ +#define DMA_SERQ_SERQ_MASK 0xFu +#define DMA_SERQ_SERQ_SHIFT 0 +#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK) +#define DMA_SERQ_SAER_MASK 0x40u +#define DMA_SERQ_SAER_SHIFT 6 +#define DMA_SERQ_NOP_MASK 0x80u +#define DMA_SERQ_NOP_SHIFT 7 +/* CDNE Bit Fields */ +#define DMA_CDNE_CDNE_MASK 0xFu +#define DMA_CDNE_CDNE_SHIFT 0 +#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK) +#define DMA_CDNE_CADN_MASK 0x40u +#define DMA_CDNE_CADN_SHIFT 6 +#define DMA_CDNE_NOP_MASK 0x80u +#define DMA_CDNE_NOP_SHIFT 7 +/* SSRT Bit Fields */ +#define DMA_SSRT_SSRT_MASK 0xFu +#define DMA_SSRT_SSRT_SHIFT 0 +#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK) +#define DMA_SSRT_SAST_MASK 0x40u +#define DMA_SSRT_SAST_SHIFT 6 +#define DMA_SSRT_NOP_MASK 0x80u +#define DMA_SSRT_NOP_SHIFT 7 +/* CERR Bit Fields */ +#define DMA_CERR_CERR_MASK 0xFu +#define DMA_CERR_CERR_SHIFT 0 +#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK) +#define DMA_CERR_CAEI_MASK 0x40u +#define DMA_CERR_CAEI_SHIFT 6 +#define DMA_CERR_NOP_MASK 0x80u +#define DMA_CERR_NOP_SHIFT 7 +/* CINT Bit Fields */ +#define DMA_CINT_CINT_MASK 0xFu +#define DMA_CINT_CINT_SHIFT 0 +#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK) +#define DMA_CINT_CAIR_MASK 0x40u +#define DMA_CINT_CAIR_SHIFT 6 +#define DMA_CINT_NOP_MASK 0x80u +#define DMA_CINT_NOP_SHIFT 7 +/* INT Bit Fields */ +#define DMA_INT_INT0_MASK 0x1u +#define DMA_INT_INT0_SHIFT 0 +#define DMA_INT_INT1_MASK 0x2u +#define DMA_INT_INT1_SHIFT 1 +#define DMA_INT_INT2_MASK 0x4u +#define DMA_INT_INT2_SHIFT 2 +#define DMA_INT_INT3_MASK 0x8u +#define DMA_INT_INT3_SHIFT 3 +/* ERR Bit Fields */ +#define DMA_ERR_ERR0_MASK 0x1u +#define DMA_ERR_ERR0_SHIFT 0 +#define DMA_ERR_ERR1_MASK 0x2u +#define DMA_ERR_ERR1_SHIFT 1 +#define DMA_ERR_ERR2_MASK 0x4u +#define DMA_ERR_ERR2_SHIFT 2 +#define DMA_ERR_ERR3_MASK 0x8u +#define DMA_ERR_ERR3_SHIFT 3 +/* HRS Bit Fields */ +#define DMA_HRS_HRS0_MASK 0x1u +#define DMA_HRS_HRS0_SHIFT 0 +#define DMA_HRS_HRS1_MASK 0x2u +#define DMA_HRS_HRS1_SHIFT 1 +#define DMA_HRS_HRS2_MASK 0x4u +#define DMA_HRS_HRS2_SHIFT 2 +#define DMA_HRS_HRS3_MASK 0x8u +#define DMA_HRS_HRS3_SHIFT 3 +/* DCHPRI3 Bit Fields */ +#define DMA_DCHPRI3_CHPRI_MASK 0xFu +#define DMA_DCHPRI3_CHPRI_SHIFT 0 +#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK) +#define DMA_DCHPRI3_DPA_MASK 0x40u +#define DMA_DCHPRI3_DPA_SHIFT 6 +#define DMA_DCHPRI3_ECP_MASK 0x80u +#define DMA_DCHPRI3_ECP_SHIFT 7 +/* DCHPRI2 Bit Fields */ +#define DMA_DCHPRI2_CHPRI_MASK 0xFu +#define DMA_DCHPRI2_CHPRI_SHIFT 0 +#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK) +#define DMA_DCHPRI2_DPA_MASK 0x40u +#define DMA_DCHPRI2_DPA_SHIFT 6 +#define DMA_DCHPRI2_ECP_MASK 0x80u +#define DMA_DCHPRI2_ECP_SHIFT 7 +/* DCHPRI1 Bit Fields */ +#define DMA_DCHPRI1_CHPRI_MASK 0xFu +#define DMA_DCHPRI1_CHPRI_SHIFT 0 +#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK) +#define DMA_DCHPRI1_DPA_MASK 0x40u +#define DMA_DCHPRI1_DPA_SHIFT 6 +#define DMA_DCHPRI1_ECP_MASK 0x80u +#define DMA_DCHPRI1_ECP_SHIFT 7 +/* DCHPRI0 Bit Fields */ +#define DMA_DCHPRI0_CHPRI_MASK 0xFu +#define DMA_DCHPRI0_CHPRI_SHIFT 0 +#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK) +#define DMA_DCHPRI0_DPA_MASK 0x40u +#define DMA_DCHPRI0_DPA_SHIFT 6 +#define DMA_DCHPRI0_ECP_MASK 0x80u +#define DMA_DCHPRI0_ECP_SHIFT 7 +/* SADDR Bit Fields */ +#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu +#define DMA_SADDR_SADDR_SHIFT 0 +#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK) +/* SOFF Bit Fields */ +#define DMA_SOFF_SOFF_MASK 0xFFFFu +#define DMA_SOFF_SOFF_SHIFT 0 +#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK) +/* ATTR Bit Fields */ +#define DMA_ATTR_DSIZE_MASK 0x7u +#define DMA_ATTR_DSIZE_SHIFT 0 +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK) +#define DMA_ATTR_DMOD_MASK 0xF8u +#define DMA_ATTR_DMOD_SHIFT 3 +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK) +#define DMA_ATTR_SSIZE_MASK 0x700u +#define DMA_ATTR_SSIZE_SHIFT 8 +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK) +#define DMA_ATTR_SMOD_MASK 0xF800u +#define DMA_ATTR_SMOD_SHIFT 11 +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK) +/* NBYTES_MLNO Bit Fields */ +#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu +#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0 +#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK) +/* NBYTES_MLOFFNO Bit Fields */ +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu +#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0 +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK) +#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u +#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30 +#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u +#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31 +/* NBYTES_MLOFFYES Bit Fields */ +#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu +#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0 +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK) +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u +#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10 +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK) +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u +#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30 +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u +#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31 +/* SLAST Bit Fields */ +#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu +#define DMA_SLAST_SLAST_SHIFT 0 +#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK) +/* DADDR Bit Fields */ +#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu +#define DMA_DADDR_DADDR_SHIFT 0 +#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK) +/* DOFF Bit Fields */ +#define DMA_DOFF_DOFF_MASK 0xFFFFu +#define DMA_DOFF_DOFF_SHIFT 0 +#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK) +/* CITER_ELINKNO Bit Fields */ +#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu +#define DMA_CITER_ELINKNO_CITER_SHIFT 0 +#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK) +#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u +#define DMA_CITER_ELINKNO_ELINK_SHIFT 15 +/* CITER_ELINKYES Bit Fields */ +#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu +#define DMA_CITER_ELINKYES_CITER_SHIFT 0 +#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK) +#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u +#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9 +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK) +#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u +#define DMA_CITER_ELINKYES_ELINK_SHIFT 15 +/* DLAST_SGA Bit Fields */ +#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu +#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0 +#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK) +/* CSR Bit Fields */ +#define DMA_CSR_START_MASK 0x1u +#define DMA_CSR_START_SHIFT 0 +#define DMA_CSR_INTMAJOR_MASK 0x2u +#define DMA_CSR_INTMAJOR_SHIFT 1 +#define DMA_CSR_INTHALF_MASK 0x4u +#define DMA_CSR_INTHALF_SHIFT 2 +#define DMA_CSR_DREQ_MASK 0x8u +#define DMA_CSR_DREQ_SHIFT 3 +#define DMA_CSR_ESG_MASK 0x10u +#define DMA_CSR_ESG_SHIFT 4 +#define DMA_CSR_MAJORELINK_MASK 0x20u +#define DMA_CSR_MAJORELINK_SHIFT 5 +#define DMA_CSR_ACTIVE_MASK 0x40u +#define DMA_CSR_ACTIVE_SHIFT 6 +#define DMA_CSR_DONE_MASK 0x80u +#define DMA_CSR_DONE_SHIFT 7 +#define DMA_CSR_MAJORLINKCH_MASK 0xF00u +#define DMA_CSR_MAJORLINKCH_SHIFT 8 +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK) +#define DMA_CSR_BWC_MASK 0xC000u +#define DMA_CSR_BWC_SHIFT 14 +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK) +/* BITER_ELINKNO Bit Fields */ +#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu +#define DMA_BITER_ELINKNO_BITER_SHIFT 0 +#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK) +#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u +#define DMA_BITER_ELINKNO_ELINK_SHIFT 15 +/* BITER_ELINKYES Bit Fields */ +#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu +#define DMA_BITER_ELINKYES_BITER_SHIFT 0 +#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK) +#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u +#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9 +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK) +#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u +#define DMA_BITER_ELINKYES_ELINK_SHIFT 15 + +/** + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA base address */ +#define DMA_BASE (0x40008000u) +/** Peripheral DMA base pointer */ +#define DMA0 ((DMA_Type *)DMA_BASE) + +/** + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer + * @{ + */ + +/** DMAMUX - Register Layout Typedef */ +typedef struct { + __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */ +} DMAMUX_Type; + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/* CHCFG Bit Fields */ +#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu +#define DMAMUX_CHCFG_SOURCE_SHIFT 0 +#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK) +#define DMAMUX_CHCFG_TRIG_MASK 0x40u +#define DMAMUX_CHCFG_TRIG_SHIFT 6 +#define DMAMUX_CHCFG_ENBL_MASK 0x80u +#define DMAMUX_CHCFG_ENBL_SHIFT 7 + +/** + * @} + */ /* end of group DMAMUX_Register_Masks */ + + +/* DMAMUX - Peripheral instance base addresses */ +/** Peripheral DMAMUX base address */ +#define DMAMUX_BASE (0x40021000u) +/** Peripheral DMAMUX base pointer */ +#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) + +/** + * @} + */ /* end of group DMAMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer + * @{ + */ + +/** EWM - Register Layout Typedef */ +typedef struct { + __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ + __O uint8_t SERV; /**< Service Register, offset: 0x1 */ + __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ + __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ +} EWM_Type; + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define EWM_CTRL_EWMEN_MASK 0x1u +#define EWM_CTRL_EWMEN_SHIFT 0 +#define EWM_CTRL_ASSIN_MASK 0x2u +#define EWM_CTRL_ASSIN_SHIFT 1 +#define EWM_CTRL_INEN_MASK 0x4u +#define EWM_CTRL_INEN_SHIFT 2 +#define EWM_CTRL_INTEN_MASK 0x8u +#define EWM_CTRL_INTEN_SHIFT 3 +/* SERV Bit Fields */ +#define EWM_SERV_SERVICE_MASK 0xFFu +#define EWM_SERV_SERVICE_SHIFT 0 +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK) +/* CMPL Bit Fields */ +#define EWM_CMPL_COMPAREL_MASK 0xFFu +#define EWM_CMPL_COMPAREL_SHIFT 0 +#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK) +/* CMPH Bit Fields */ +#define EWM_CMPH_COMPAREH_MASK 0xFFu +#define EWM_CMPH_COMPAREH_SHIFT 0 +#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK) + +/** + * @} + */ /* end of group EWM_Register_Masks */ + + +/* EWM - Peripheral instance base addresses */ +/** Peripheral EWM base address */ +#define EWM_BASE (0x40061000u) +/** Peripheral EWM base pointer */ +#define EWM ((EWM_Type *)EWM_BASE) + +/** + * @} + */ /* end of group EWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer + * @{ + */ + +/** FMC - Register Layout Typedef */ +typedef struct { + __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */ + __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */ + uint8_t RESERVED_0[248]; + struct { /* offset: 0x100, array step: 0x20 */ + __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */ + uint8_t RESERVED_0[24]; + } TAG_WAY[4]; + uint8_t RESERVED_1[132]; + struct { /* offset: 0x204, array step: 0x8 */ + __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */ + uint8_t RESERVED_0[4]; + } DATAW0S[2]; + uint8_t RESERVED_2[48]; + struct { /* offset: 0x244, array step: 0x8 */ + __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */ + uint8_t RESERVED_0[4]; + } DATAW1S[2]; + uint8_t RESERVED_3[48]; + struct { /* offset: 0x284, array step: 0x8 */ + __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */ + uint8_t RESERVED_0[4]; + } DATAW2S[2]; + uint8_t RESERVED_4[48]; + struct { /* offset: 0x2C4, array step: 0x8 */ + __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */ + uint8_t RESERVED_0[4]; + } DATAW3S[2]; +} FMC_Type; + +/* ---------------------------------------------------------------------------- + -- FMC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FMC_Register_Masks FMC Register Masks + * @{ + */ + +/* PFAPR Bit Fields */ +#define FMC_PFAPR_M0AP_MASK 0x3u +#define FMC_PFAPR_M0AP_SHIFT 0 +#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK) +#define FMC_PFAPR_M1AP_MASK 0xCu +#define FMC_PFAPR_M1AP_SHIFT 2 +#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK) +#define FMC_PFAPR_M2AP_MASK 0x30u +#define FMC_PFAPR_M2AP_SHIFT 4 +#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK) +#define FMC_PFAPR_M3AP_MASK 0xC0u +#define FMC_PFAPR_M3AP_SHIFT 6 +#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK) +#define FMC_PFAPR_M0PFD_MASK 0x10000u +#define FMC_PFAPR_M0PFD_SHIFT 16 +#define FMC_PFAPR_M1PFD_MASK 0x20000u +#define FMC_PFAPR_M1PFD_SHIFT 17 +#define FMC_PFAPR_M2PFD_MASK 0x40000u +#define FMC_PFAPR_M2PFD_SHIFT 18 +#define FMC_PFAPR_M3PFD_MASK 0x80000u +#define FMC_PFAPR_M3PFD_SHIFT 19 +/* PFB0CR Bit Fields */ +#define FMC_PFB0CR_B0SEBE_MASK 0x1u +#define FMC_PFB0CR_B0SEBE_SHIFT 0 +#define FMC_PFB0CR_B0IPE_MASK 0x2u +#define FMC_PFB0CR_B0IPE_SHIFT 1 +#define FMC_PFB0CR_B0DPE_MASK 0x4u +#define FMC_PFB0CR_B0DPE_SHIFT 2 +#define FMC_PFB0CR_B0ICE_MASK 0x8u +#define FMC_PFB0CR_B0ICE_SHIFT 3 +#define FMC_PFB0CR_B0DCE_MASK 0x10u +#define FMC_PFB0CR_B0DCE_SHIFT 4 +#define FMC_PFB0CR_CRC_MASK 0xE0u +#define FMC_PFB0CR_CRC_SHIFT 5 +#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK) +#define FMC_PFB0CR_B0MW_MASK 0x60000u +#define FMC_PFB0CR_B0MW_SHIFT 17 +#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK) +#define FMC_PFB0CR_S_B_INV_MASK 0x80000u +#define FMC_PFB0CR_S_B_INV_SHIFT 19 +#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u +#define FMC_PFB0CR_CINV_WAY_SHIFT 20 +#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK) +#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u +#define FMC_PFB0CR_CLCK_WAY_SHIFT 24 +#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK) +#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u +#define FMC_PFB0CR_B0RWSC_SHIFT 28 +#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK) +/* TAGVD Bit Fields */ +#define FMC_TAGVD_valid_MASK 0x1u +#define FMC_TAGVD_valid_SHIFT 0 +#define FMC_TAGVD_tag_MASK 0x7FFC0u +#define FMC_TAGVD_tag_SHIFT 6 +#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK) +/* DATAW0S Bit Fields */ +#define FMC_DATAW0S_data_MASK 0xFFFFFFFFu +#define FMC_DATAW0S_data_SHIFT 0 +#define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK) +/* DATAW1S Bit Fields */ +#define FMC_DATAW1S_data_MASK 0xFFFFFFFFu +#define FMC_DATAW1S_data_SHIFT 0 +#define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK) +/* DATAW2S Bit Fields */ +#define FMC_DATAW2S_data_MASK 0xFFFFFFFFu +#define FMC_DATAW2S_data_SHIFT 0 +#define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK) +/* DATAW3S Bit Fields */ +#define FMC_DATAW3S_data_MASK 0xFFFFFFFFu +#define FMC_DATAW3S_data_SHIFT 0 +#define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK) + +/** + * @} + */ /* end of group FMC_Register_Masks */ + + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC base address */ +#define FMC_BASE (0x4001F000u) +/** Peripheral FMC base pointer */ +#define FMC ((FMC_Type *)FMC_BASE) + +/** + * @} + */ /* end of group FMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FTFL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer + * @{ + */ + +/** FTFL - Register Layout Typedef */ +typedef struct { + __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ + __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ + __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ + __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ + __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ + __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ + __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ + __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ + __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ + __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ + __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ + __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ + __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ + __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ + __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ + __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ + __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ + __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ + __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ + uint8_t RESERVED_0[2]; + __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */ + __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */ +} FTFL_Type; + +/* ---------------------------------------------------------------------------- + -- FTFL Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTFL_Register_Masks FTFL Register Masks + * @{ + */ + +/* FSTAT Bit Fields */ +#define FTFL_FSTAT_MGSTAT0_MASK 0x1u +#define FTFL_FSTAT_MGSTAT0_SHIFT 0 +#define FTFL_FSTAT_FPVIOL_MASK 0x10u +#define FTFL_FSTAT_FPVIOL_SHIFT 4 +#define FTFL_FSTAT_ACCERR_MASK 0x20u +#define FTFL_FSTAT_ACCERR_SHIFT 5 +#define FTFL_FSTAT_RDCOLERR_MASK 0x40u +#define FTFL_FSTAT_RDCOLERR_SHIFT 6 +#define FTFL_FSTAT_CCIF_MASK 0x80u +#define FTFL_FSTAT_CCIF_SHIFT 7 +/* FCNFG Bit Fields */ +#define FTFL_FCNFG_EEERDY_MASK 0x1u +#define FTFL_FCNFG_EEERDY_SHIFT 0 +#define FTFL_FCNFG_RAMRDY_MASK 0x2u +#define FTFL_FCNFG_RAMRDY_SHIFT 1 +#define FTFL_FCNFG_PFLSH_MASK 0x4u +#define FTFL_FCNFG_PFLSH_SHIFT 2 +#define FTFL_FCNFG_ERSSUSP_MASK 0x10u +#define FTFL_FCNFG_ERSSUSP_SHIFT 4 +#define FTFL_FCNFG_ERSAREQ_MASK 0x20u +#define FTFL_FCNFG_ERSAREQ_SHIFT 5 +#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u +#define FTFL_FCNFG_RDCOLLIE_SHIFT 6 +#define FTFL_FCNFG_CCIE_MASK 0x80u +#define FTFL_FCNFG_CCIE_SHIFT 7 +/* FSEC Bit Fields */ +#define FTFL_FSEC_SEC_MASK 0x3u +#define FTFL_FSEC_SEC_SHIFT 0 +#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK) +#define FTFL_FSEC_FSLACC_MASK 0xCu +#define FTFL_FSEC_FSLACC_SHIFT 2 +#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK) +#define FTFL_FSEC_MEEN_MASK 0x30u +#define FTFL_FSEC_MEEN_SHIFT 4 +#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK) +#define FTFL_FSEC_KEYEN_MASK 0xC0u +#define FTFL_FSEC_KEYEN_SHIFT 6 +#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK) +/* FOPT Bit Fields */ +#define FTFL_FOPT_OPT_MASK 0xFFu +#define FTFL_FOPT_OPT_SHIFT 0 +#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK) +/* FCCOB3 Bit Fields */ +#define FTFL_FCCOB3_CCOBn_MASK 0xFFu +#define FTFL_FCCOB3_CCOBn_SHIFT 0 +#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK) +/* FCCOB2 Bit Fields */ +#define FTFL_FCCOB2_CCOBn_MASK 0xFFu +#define FTFL_FCCOB2_CCOBn_SHIFT 0 +#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK) +/* FCCOB1 Bit Fields */ +#define FTFL_FCCOB1_CCOBn_MASK 0xFFu +#define FTFL_FCCOB1_CCOBn_SHIFT 0 +#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK) +/* FCCOB0 Bit Fields */ +#define FTFL_FCCOB0_CCOBn_MASK 0xFFu +#define FTFL_FCCOB0_CCOBn_SHIFT 0 +#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK) +/* FCCOB7 Bit Fields */ +#define FTFL_FCCOB7_CCOBn_MASK 0xFFu +#define FTFL_FCCOB7_CCOBn_SHIFT 0 +#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK) +/* FCCOB6 Bit Fields */ +#define FTFL_FCCOB6_CCOBn_MASK 0xFFu +#define FTFL_FCCOB6_CCOBn_SHIFT 0 +#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK) +/* FCCOB5 Bit Fields */ +#define FTFL_FCCOB5_CCOBn_MASK 0xFFu +#define FTFL_FCCOB5_CCOBn_SHIFT 0 +#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK) +/* FCCOB4 Bit Fields */ +#define FTFL_FCCOB4_CCOBn_MASK 0xFFu +#define FTFL_FCCOB4_CCOBn_SHIFT 0 +#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK) +/* FCCOBB Bit Fields */ +#define FTFL_FCCOBB_CCOBn_MASK 0xFFu +#define FTFL_FCCOBB_CCOBn_SHIFT 0 +#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK) +/* FCCOBA Bit Fields */ +#define FTFL_FCCOBA_CCOBn_MASK 0xFFu +#define FTFL_FCCOBA_CCOBn_SHIFT 0 +#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK) +/* FCCOB9 Bit Fields */ +#define FTFL_FCCOB9_CCOBn_MASK 0xFFu +#define FTFL_FCCOB9_CCOBn_SHIFT 0 +#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK) +/* FCCOB8 Bit Fields */ +#define FTFL_FCCOB8_CCOBn_MASK 0xFFu +#define FTFL_FCCOB8_CCOBn_SHIFT 0 +#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK) +/* FPROT3 Bit Fields */ +#define FTFL_FPROT3_PROT_MASK 0xFFu +#define FTFL_FPROT3_PROT_SHIFT 0 +#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK) +/* FPROT2 Bit Fields */ +#define FTFL_FPROT2_PROT_MASK 0xFFu +#define FTFL_FPROT2_PROT_SHIFT 0 +#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK) +/* FPROT1 Bit Fields */ +#define FTFL_FPROT1_PROT_MASK 0xFFu +#define FTFL_FPROT1_PROT_SHIFT 0 +#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK) +/* FPROT0 Bit Fields */ +#define FTFL_FPROT0_PROT_MASK 0xFFu +#define FTFL_FPROT0_PROT_SHIFT 0 +#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK) +/* FEPROT Bit Fields */ +#define FTFL_FEPROT_EPROT_MASK 0xFFu +#define FTFL_FEPROT_EPROT_SHIFT 0 +#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK) +/* FDPROT Bit Fields */ +#define FTFL_FDPROT_DPROT_MASK 0xFFu +#define FTFL_FDPROT_DPROT_SHIFT 0 +#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK) + +/** + * @} + */ /* end of group FTFL_Register_Masks */ + + +/* FTFL - Peripheral instance base addresses */ +/** Peripheral FTFL base address */ +#define FTFL_BASE (0x40020000u) +/** Peripheral FTFL base pointer */ +#define FTFL ((FTFL_Type *)FTFL_BASE) + +/** + * @} + */ /* end of group FTFL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FTM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer + * @{ + */ + +/** FTM - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ + __IO uint32_t CNT; /**< Counter, offset: 0x4 */ + __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ + struct { /* offset: 0xC, array step: 0x8 */ + __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ + __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ + } CONTROLS[8]; + __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ + __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ + __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ + __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ + __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */ + __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ + __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */ + __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ + __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ + __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ + __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ + __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ + __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ + __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */ + __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ + __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ + __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ + __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ + __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ + __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ +} FTM_Type; + +/* ---------------------------------------------------------------------------- + -- FTM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTM_Register_Masks FTM Register Masks + * @{ + */ + +/* SC Bit Fields */ +#define FTM_SC_PS_MASK 0x7u +#define FTM_SC_PS_SHIFT 0 +#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK) +#define FTM_SC_CLKS_MASK 0x18u +#define FTM_SC_CLKS_SHIFT 3 +#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK) +#define FTM_SC_CPWMS_MASK 0x20u +#define FTM_SC_CPWMS_SHIFT 5 +#define FTM_SC_TOIE_MASK 0x40u +#define FTM_SC_TOIE_SHIFT 6 +#define FTM_SC_TOF_MASK 0x80u +#define FTM_SC_TOF_SHIFT 7 +/* CNT Bit Fields */ +#define FTM_CNT_COUNT_MASK 0xFFFFu +#define FTM_CNT_COUNT_SHIFT 0 +#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK) +/* MOD Bit Fields */ +#define FTM_MOD_MOD_MASK 0xFFFFu +#define FTM_MOD_MOD_SHIFT 0 +#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK) +/* CnSC Bit Fields */ +#define FTM_CnSC_DMA_MASK 0x1u +#define FTM_CnSC_DMA_SHIFT 0 +#define FTM_CnSC_ELSA_MASK 0x4u +#define FTM_CnSC_ELSA_SHIFT 2 +#define FTM_CnSC_ELSB_MASK 0x8u +#define FTM_CnSC_ELSB_SHIFT 3 +#define FTM_CnSC_MSA_MASK 0x10u +#define FTM_CnSC_MSA_SHIFT 4 +#define FTM_CnSC_MSB_MASK 0x20u +#define FTM_CnSC_MSB_SHIFT 5 +#define FTM_CnSC_CHIE_MASK 0x40u +#define FTM_CnSC_CHIE_SHIFT 6 +#define FTM_CnSC_CHF_MASK 0x80u +#define FTM_CnSC_CHF_SHIFT 7 +/* CnV Bit Fields */ +#define FTM_CnV_VAL_MASK 0xFFFFu +#define FTM_CnV_VAL_SHIFT 0 +#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK) +/* CNTIN Bit Fields */ +#define FTM_CNTIN_INIT_MASK 0xFFFFu +#define FTM_CNTIN_INIT_SHIFT 0 +#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK) +/* STATUS Bit Fields */ +#define FTM_STATUS_CH0F_MASK 0x1u +#define FTM_STATUS_CH0F_SHIFT 0 +#define FTM_STATUS_CH1F_MASK 0x2u +#define FTM_STATUS_CH1F_SHIFT 1 +#define FTM_STATUS_CH2F_MASK 0x4u +#define FTM_STATUS_CH2F_SHIFT 2 +#define FTM_STATUS_CH3F_MASK 0x8u +#define FTM_STATUS_CH3F_SHIFT 3 +#define FTM_STATUS_CH4F_MASK 0x10u +#define FTM_STATUS_CH4F_SHIFT 4 +#define FTM_STATUS_CH5F_MASK 0x20u +#define FTM_STATUS_CH5F_SHIFT 5 +#define FTM_STATUS_CH6F_MASK 0x40u +#define FTM_STATUS_CH6F_SHIFT 6 +#define FTM_STATUS_CH7F_MASK 0x80u +#define FTM_STATUS_CH7F_SHIFT 7 +/* MODE Bit Fields */ +#define FTM_MODE_FTMEN_MASK 0x1u +#define FTM_MODE_FTMEN_SHIFT 0 +#define FTM_MODE_INIT_MASK 0x2u +#define FTM_MODE_INIT_SHIFT 1 +#define FTM_MODE_WPDIS_MASK 0x4u +#define FTM_MODE_WPDIS_SHIFT 2 +#define FTM_MODE_PWMSYNC_MASK 0x8u +#define FTM_MODE_PWMSYNC_SHIFT 3 +#define FTM_MODE_CAPTEST_MASK 0x10u +#define FTM_MODE_CAPTEST_SHIFT 4 +#define FTM_MODE_FAULTM_MASK 0x60u +#define FTM_MODE_FAULTM_SHIFT 5 +#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK) +#define FTM_MODE_FAULTIE_MASK 0x80u +#define FTM_MODE_FAULTIE_SHIFT 7 +/* SYNC Bit Fields */ +#define FTM_SYNC_CNTMIN_MASK 0x1u +#define FTM_SYNC_CNTMIN_SHIFT 0 +#define FTM_SYNC_CNTMAX_MASK 0x2u +#define FTM_SYNC_CNTMAX_SHIFT 1 +#define FTM_SYNC_REINIT_MASK 0x4u +#define FTM_SYNC_REINIT_SHIFT 2 +#define FTM_SYNC_SYNCHOM_MASK 0x8u +#define FTM_SYNC_SYNCHOM_SHIFT 3 +#define FTM_SYNC_TRIG0_MASK 0x10u +#define FTM_SYNC_TRIG0_SHIFT 4 +#define FTM_SYNC_TRIG1_MASK 0x20u +#define FTM_SYNC_TRIG1_SHIFT 5 +#define FTM_SYNC_TRIG2_MASK 0x40u +#define FTM_SYNC_TRIG2_SHIFT 6 +#define FTM_SYNC_SWSYNC_MASK 0x80u +#define FTM_SYNC_SWSYNC_SHIFT 7 +/* OUTINIT Bit Fields */ +#define FTM_OUTINIT_CH0OI_MASK 0x1u +#define FTM_OUTINIT_CH0OI_SHIFT 0 +#define FTM_OUTINIT_CH1OI_MASK 0x2u +#define FTM_OUTINIT_CH1OI_SHIFT 1 +#define FTM_OUTINIT_CH2OI_MASK 0x4u +#define FTM_OUTINIT_CH2OI_SHIFT 2 +#define FTM_OUTINIT_CH3OI_MASK 0x8u +#define FTM_OUTINIT_CH3OI_SHIFT 3 +#define FTM_OUTINIT_CH4OI_MASK 0x10u +#define FTM_OUTINIT_CH4OI_SHIFT 4 +#define FTM_OUTINIT_CH5OI_MASK 0x20u +#define FTM_OUTINIT_CH5OI_SHIFT 5 +#define FTM_OUTINIT_CH6OI_MASK 0x40u +#define FTM_OUTINIT_CH6OI_SHIFT 6 +#define FTM_OUTINIT_CH7OI_MASK 0x80u +#define FTM_OUTINIT_CH7OI_SHIFT 7 +/* OUTMASK Bit Fields */ +#define FTM_OUTMASK_CH0OM_MASK 0x1u +#define FTM_OUTMASK_CH0OM_SHIFT 0 +#define FTM_OUTMASK_CH1OM_MASK 0x2u +#define FTM_OUTMASK_CH1OM_SHIFT 1 +#define FTM_OUTMASK_CH2OM_MASK 0x4u +#define FTM_OUTMASK_CH2OM_SHIFT 2 +#define FTM_OUTMASK_CH3OM_MASK 0x8u +#define FTM_OUTMASK_CH3OM_SHIFT 3 +#define FTM_OUTMASK_CH4OM_MASK 0x10u +#define FTM_OUTMASK_CH4OM_SHIFT 4 +#define FTM_OUTMASK_CH5OM_MASK 0x20u +#define FTM_OUTMASK_CH5OM_SHIFT 5 +#define FTM_OUTMASK_CH6OM_MASK 0x40u +#define FTM_OUTMASK_CH6OM_SHIFT 6 +#define FTM_OUTMASK_CH7OM_MASK 0x80u +#define FTM_OUTMASK_CH7OM_SHIFT 7 +/* COMBINE Bit Fields */ +#define FTM_COMBINE_COMBINE0_MASK 0x1u +#define FTM_COMBINE_COMBINE0_SHIFT 0 +#define FTM_COMBINE_COMP0_MASK 0x2u +#define FTM_COMBINE_COMP0_SHIFT 1 +#define FTM_COMBINE_DECAPEN0_MASK 0x4u +#define FTM_COMBINE_DECAPEN0_SHIFT 2 +#define FTM_COMBINE_DECAP0_MASK 0x8u +#define FTM_COMBINE_DECAP0_SHIFT 3 +#define FTM_COMBINE_DTEN0_MASK 0x10u +#define FTM_COMBINE_DTEN0_SHIFT 4 +#define FTM_COMBINE_SYNCEN0_MASK 0x20u +#define FTM_COMBINE_SYNCEN0_SHIFT 5 +#define FTM_COMBINE_FAULTEN0_MASK 0x40u +#define FTM_COMBINE_FAULTEN0_SHIFT 6 +#define FTM_COMBINE_COMBINE1_MASK 0x100u +#define FTM_COMBINE_COMBINE1_SHIFT 8 +#define FTM_COMBINE_COMP1_MASK 0x200u +#define FTM_COMBINE_COMP1_SHIFT 9 +#define FTM_COMBINE_DECAPEN1_MASK 0x400u +#define FTM_COMBINE_DECAPEN1_SHIFT 10 +#define FTM_COMBINE_DECAP1_MASK 0x800u +#define FTM_COMBINE_DECAP1_SHIFT 11 +#define FTM_COMBINE_DTEN1_MASK 0x1000u +#define FTM_COMBINE_DTEN1_SHIFT 12 +#define FTM_COMBINE_SYNCEN1_MASK 0x2000u +#define FTM_COMBINE_SYNCEN1_SHIFT 13 +#define FTM_COMBINE_FAULTEN1_MASK 0x4000u +#define FTM_COMBINE_FAULTEN1_SHIFT 14 +#define FTM_COMBINE_COMBINE2_MASK 0x10000u +#define FTM_COMBINE_COMBINE2_SHIFT 16 +#define FTM_COMBINE_COMP2_MASK 0x20000u +#define FTM_COMBINE_COMP2_SHIFT 17 +#define FTM_COMBINE_DECAPEN2_MASK 0x40000u +#define FTM_COMBINE_DECAPEN2_SHIFT 18 +#define FTM_COMBINE_DECAP2_MASK 0x80000u +#define FTM_COMBINE_DECAP2_SHIFT 19 +#define FTM_COMBINE_DTEN2_MASK 0x100000u +#define FTM_COMBINE_DTEN2_SHIFT 20 +#define FTM_COMBINE_SYNCEN2_MASK 0x200000u +#define FTM_COMBINE_SYNCEN2_SHIFT 21 +#define FTM_COMBINE_FAULTEN2_MASK 0x400000u +#define FTM_COMBINE_FAULTEN2_SHIFT 22 +#define FTM_COMBINE_COMBINE3_MASK 0x1000000u +#define FTM_COMBINE_COMBINE3_SHIFT 24 +#define FTM_COMBINE_COMP3_MASK 0x2000000u +#define FTM_COMBINE_COMP3_SHIFT 25 +#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u +#define FTM_COMBINE_DECAPEN3_SHIFT 26 +#define FTM_COMBINE_DECAP3_MASK 0x8000000u +#define FTM_COMBINE_DECAP3_SHIFT 27 +#define FTM_COMBINE_DTEN3_MASK 0x10000000u +#define FTM_COMBINE_DTEN3_SHIFT 28 +#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u +#define FTM_COMBINE_SYNCEN3_SHIFT 29 +#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u +#define FTM_COMBINE_FAULTEN3_SHIFT 30 +/* DEADTIME Bit Fields */ +#define FTM_DEADTIME_DTVAL_MASK 0x3Fu +#define FTM_DEADTIME_DTVAL_SHIFT 0 +#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK) +#define FTM_DEADTIME_DTPS_MASK 0xC0u +#define FTM_DEADTIME_DTPS_SHIFT 6 +#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK) +/* EXTTRIG Bit Fields */ +#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u +#define FTM_EXTTRIG_CH2TRIG_SHIFT 0 +#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u +#define FTM_EXTTRIG_CH3TRIG_SHIFT 1 +#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u +#define FTM_EXTTRIG_CH4TRIG_SHIFT 2 +#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u +#define FTM_EXTTRIG_CH5TRIG_SHIFT 3 +#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u +#define FTM_EXTTRIG_CH0TRIG_SHIFT 4 +#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u +#define FTM_EXTTRIG_CH1TRIG_SHIFT 5 +#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u +#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6 +#define FTM_EXTTRIG_TRIGF_MASK 0x80u +#define FTM_EXTTRIG_TRIGF_SHIFT 7 +/* POL Bit Fields */ +#define FTM_POL_POL0_MASK 0x1u +#define FTM_POL_POL0_SHIFT 0 +#define FTM_POL_POL1_MASK 0x2u +#define FTM_POL_POL1_SHIFT 1 +#define FTM_POL_POL2_MASK 0x4u +#define FTM_POL_POL2_SHIFT 2 +#define FTM_POL_POL3_MASK 0x8u +#define FTM_POL_POL3_SHIFT 3 +#define FTM_POL_POL4_MASK 0x10u +#define FTM_POL_POL4_SHIFT 4 +#define FTM_POL_POL5_MASK 0x20u +#define FTM_POL_POL5_SHIFT 5 +#define FTM_POL_POL6_MASK 0x40u +#define FTM_POL_POL6_SHIFT 6 +#define FTM_POL_POL7_MASK 0x80u +#define FTM_POL_POL7_SHIFT 7 +/* FMS Bit Fields */ +#define FTM_FMS_FAULTF0_MASK 0x1u +#define FTM_FMS_FAULTF0_SHIFT 0 +#define FTM_FMS_FAULTF1_MASK 0x2u +#define FTM_FMS_FAULTF1_SHIFT 1 +#define FTM_FMS_FAULTF2_MASK 0x4u +#define FTM_FMS_FAULTF2_SHIFT 2 +#define FTM_FMS_FAULTF3_MASK 0x8u +#define FTM_FMS_FAULTF3_SHIFT 3 +#define FTM_FMS_FAULTIN_MASK 0x20u +#define FTM_FMS_FAULTIN_SHIFT 5 +#define FTM_FMS_WPEN_MASK 0x40u +#define FTM_FMS_WPEN_SHIFT 6 +#define FTM_FMS_FAULTF_MASK 0x80u +#define FTM_FMS_FAULTF_SHIFT 7 +/* FILTER Bit Fields */ +#define FTM_FILTER_CH0FVAL_MASK 0xFu +#define FTM_FILTER_CH0FVAL_SHIFT 0 +#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK) +#define FTM_FILTER_CH1FVAL_MASK 0xF0u +#define FTM_FILTER_CH1FVAL_SHIFT 4 +#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK) +#define FTM_FILTER_CH2FVAL_MASK 0xF00u +#define FTM_FILTER_CH2FVAL_SHIFT 8 +#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK) +#define FTM_FILTER_CH3FVAL_MASK 0xF000u +#define FTM_FILTER_CH3FVAL_SHIFT 12 +#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK) +/* FLTCTRL Bit Fields */ +#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u +#define FTM_FLTCTRL_FAULT0EN_SHIFT 0 +#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u +#define FTM_FLTCTRL_FAULT1EN_SHIFT 1 +#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u +#define FTM_FLTCTRL_FAULT2EN_SHIFT 2 +#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u +#define FTM_FLTCTRL_FAULT3EN_SHIFT 3 +#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u +#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4 +#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u +#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5 +#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u +#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6 +#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u +#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7 +#define FTM_FLTCTRL_FFVAL_MASK 0xF00u +#define FTM_FLTCTRL_FFVAL_SHIFT 8 +#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK) +/* QDCTRL Bit Fields */ +#define FTM_QDCTRL_QUADEN_MASK 0x1u +#define FTM_QDCTRL_QUADEN_SHIFT 0 +#define FTM_QDCTRL_TOFDIR_MASK 0x2u +#define FTM_QDCTRL_TOFDIR_SHIFT 1 +#define FTM_QDCTRL_QUADIR_MASK 0x4u +#define FTM_QDCTRL_QUADIR_SHIFT 2 +#define FTM_QDCTRL_QUADMODE_MASK 0x8u +#define FTM_QDCTRL_QUADMODE_SHIFT 3 +#define FTM_QDCTRL_PHBPOL_MASK 0x10u +#define FTM_QDCTRL_PHBPOL_SHIFT 4 +#define FTM_QDCTRL_PHAPOL_MASK 0x20u +#define FTM_QDCTRL_PHAPOL_SHIFT 5 +#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u +#define FTM_QDCTRL_PHBFLTREN_SHIFT 6 +#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u +#define FTM_QDCTRL_PHAFLTREN_SHIFT 7 +/* CONF Bit Fields */ +#define FTM_CONF_NUMTOF_MASK 0x1Fu +#define FTM_CONF_NUMTOF_SHIFT 0 +#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK) +#define FTM_CONF_BDMMODE_MASK 0xC0u +#define FTM_CONF_BDMMODE_SHIFT 6 +#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK) +#define FTM_CONF_GTBEEN_MASK 0x200u +#define FTM_CONF_GTBEEN_SHIFT 9 +#define FTM_CONF_GTBEOUT_MASK 0x400u +#define FTM_CONF_GTBEOUT_SHIFT 10 +/* FLTPOL Bit Fields */ +#define FTM_FLTPOL_FLT0POL_MASK 0x1u +#define FTM_FLTPOL_FLT0POL_SHIFT 0 +#define FTM_FLTPOL_FLT1POL_MASK 0x2u +#define FTM_FLTPOL_FLT1POL_SHIFT 1 +#define FTM_FLTPOL_FLT2POL_MASK 0x4u +#define FTM_FLTPOL_FLT2POL_SHIFT 2 +#define FTM_FLTPOL_FLT3POL_MASK 0x8u +#define FTM_FLTPOL_FLT3POL_SHIFT 3 +/* SYNCONF Bit Fields */ +#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u +#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0 +#define FTM_SYNCONF_CNTINC_MASK 0x4u +#define FTM_SYNCONF_CNTINC_SHIFT 2 +#define FTM_SYNCONF_INVC_MASK 0x10u +#define FTM_SYNCONF_INVC_SHIFT 4 +#define FTM_SYNCONF_SWOC_MASK 0x20u +#define FTM_SYNCONF_SWOC_SHIFT 5 +#define FTM_SYNCONF_SYNCMODE_MASK 0x80u +#define FTM_SYNCONF_SYNCMODE_SHIFT 7 +#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u +#define FTM_SYNCONF_SWRSTCNT_SHIFT 8 +#define FTM_SYNCONF_SWWRBUF_MASK 0x200u +#define FTM_SYNCONF_SWWRBUF_SHIFT 9 +#define FTM_SYNCONF_SWOM_MASK 0x400u +#define FTM_SYNCONF_SWOM_SHIFT 10 +#define FTM_SYNCONF_SWINVC_MASK 0x800u +#define FTM_SYNCONF_SWINVC_SHIFT 11 +#define FTM_SYNCONF_SWSOC_MASK 0x1000u +#define FTM_SYNCONF_SWSOC_SHIFT 12 +#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u +#define FTM_SYNCONF_HWRSTCNT_SHIFT 16 +#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u +#define FTM_SYNCONF_HWWRBUF_SHIFT 17 +#define FTM_SYNCONF_HWOM_MASK 0x40000u +#define FTM_SYNCONF_HWOM_SHIFT 18 +#define FTM_SYNCONF_HWINVC_MASK 0x80000u +#define FTM_SYNCONF_HWINVC_SHIFT 19 +#define FTM_SYNCONF_HWSOC_MASK 0x100000u +#define FTM_SYNCONF_HWSOC_SHIFT 20 +/* INVCTRL Bit Fields */ +#define FTM_INVCTRL_INV0EN_MASK 0x1u +#define FTM_INVCTRL_INV0EN_SHIFT 0 +#define FTM_INVCTRL_INV1EN_MASK 0x2u +#define FTM_INVCTRL_INV1EN_SHIFT 1 +#define FTM_INVCTRL_INV2EN_MASK 0x4u +#define FTM_INVCTRL_INV2EN_SHIFT 2 +#define FTM_INVCTRL_INV3EN_MASK 0x8u +#define FTM_INVCTRL_INV3EN_SHIFT 3 +/* SWOCTRL Bit Fields */ +#define FTM_SWOCTRL_CH0OC_MASK 0x1u +#define FTM_SWOCTRL_CH0OC_SHIFT 0 +#define FTM_SWOCTRL_CH1OC_MASK 0x2u +#define FTM_SWOCTRL_CH1OC_SHIFT 1 +#define FTM_SWOCTRL_CH2OC_MASK 0x4u +#define FTM_SWOCTRL_CH2OC_SHIFT 2 +#define FTM_SWOCTRL_CH3OC_MASK 0x8u +#define FTM_SWOCTRL_CH3OC_SHIFT 3 +#define FTM_SWOCTRL_CH4OC_MASK 0x10u +#define FTM_SWOCTRL_CH4OC_SHIFT 4 +#define FTM_SWOCTRL_CH5OC_MASK 0x20u +#define FTM_SWOCTRL_CH5OC_SHIFT 5 +#define FTM_SWOCTRL_CH6OC_MASK 0x40u +#define FTM_SWOCTRL_CH6OC_SHIFT 6 +#define FTM_SWOCTRL_CH7OC_MASK 0x80u +#define FTM_SWOCTRL_CH7OC_SHIFT 7 +#define FTM_SWOCTRL_CH0OCV_MASK 0x100u +#define FTM_SWOCTRL_CH0OCV_SHIFT 8 +#define FTM_SWOCTRL_CH1OCV_MASK 0x200u +#define FTM_SWOCTRL_CH1OCV_SHIFT 9 +#define FTM_SWOCTRL_CH2OCV_MASK 0x400u +#define FTM_SWOCTRL_CH2OCV_SHIFT 10 +#define FTM_SWOCTRL_CH3OCV_MASK 0x800u +#define FTM_SWOCTRL_CH3OCV_SHIFT 11 +#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u +#define FTM_SWOCTRL_CH4OCV_SHIFT 12 +#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u +#define FTM_SWOCTRL_CH5OCV_SHIFT 13 +#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u +#define FTM_SWOCTRL_CH6OCV_SHIFT 14 +#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u +#define FTM_SWOCTRL_CH7OCV_SHIFT 15 +/* PWMLOAD Bit Fields */ +#define FTM_PWMLOAD_CH0SEL_MASK 0x1u +#define FTM_PWMLOAD_CH0SEL_SHIFT 0 +#define FTM_PWMLOAD_CH1SEL_MASK 0x2u +#define FTM_PWMLOAD_CH1SEL_SHIFT 1 +#define FTM_PWMLOAD_CH2SEL_MASK 0x4u +#define FTM_PWMLOAD_CH2SEL_SHIFT 2 +#define FTM_PWMLOAD_CH3SEL_MASK 0x8u +#define FTM_PWMLOAD_CH3SEL_SHIFT 3 +#define FTM_PWMLOAD_CH4SEL_MASK 0x10u +#define FTM_PWMLOAD_CH4SEL_SHIFT 4 +#define FTM_PWMLOAD_CH5SEL_MASK 0x20u +#define FTM_PWMLOAD_CH5SEL_SHIFT 5 +#define FTM_PWMLOAD_CH6SEL_MASK 0x40u +#define FTM_PWMLOAD_CH6SEL_SHIFT 6 +#define FTM_PWMLOAD_CH7SEL_MASK 0x80u +#define FTM_PWMLOAD_CH7SEL_SHIFT 7 +#define FTM_PWMLOAD_LDOK_MASK 0x200u +#define FTM_PWMLOAD_LDOK_SHIFT 9 + +/** + * @} + */ /* end of group FTM_Register_Masks */ + + +/* FTM - Peripheral instance base addresses */ +/** Peripheral FTM0 base address */ +#define FTM0_BASE (0x40038000u) +/** Peripheral FTM0 base pointer */ +#define FTM0 ((FTM_Type *)FTM0_BASE) +/** Peripheral FTM1 base address */ +#define FTM1_BASE (0x40039000u) +/** Peripheral FTM1 base pointer */ +#define FTM1 ((FTM_Type *)FTM1_BASE) + +/** + * @} + */ /* end of group FTM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ + __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ + __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ + __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ + __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ + __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/* PDOR Bit Fields */ +#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu +#define GPIO_PDOR_PDO_SHIFT 0 +#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK) +/* PSOR Bit Fields */ +#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu +#define GPIO_PSOR_PTSO_SHIFT 0 +#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK) +/* PCOR Bit Fields */ +#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu +#define GPIO_PCOR_PTCO_SHIFT 0 +#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK) +/* PTOR Bit Fields */ +#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu +#define GPIO_PTOR_PTTO_SHIFT 0 +#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK) +/* PDIR Bit Fields */ +#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu +#define GPIO_PDIR_PDI_SHIFT 0 +#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK) +/* PDDR Bit Fields */ +#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu +#define GPIO_PDDR_PDD_SHIFT 0 +#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK) + +/** + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral PTA base address */ +#define PTA_BASE (0x400FF000u) +/** Peripheral PTA base pointer */ +#define PTA ((GPIO_Type *)PTA_BASE) +/** Peripheral PTB base address */ +#define PTB_BASE (0x400FF040u) +/** Peripheral PTB base pointer */ +#define PTB ((GPIO_Type *)PTB_BASE) +/** Peripheral PTC base address */ +#define PTC_BASE (0x400FF080u) +/** Peripheral PTC base pointer */ +#define PTC ((GPIO_Type *)PTC_BASE) +/** Peripheral PTD base address */ +#define PTD_BASE (0x400FF0C0u) +/** Peripheral PTD base pointer */ +#define PTD ((GPIO_Type *)PTD_BASE) +/** Peripheral PTE base address */ +#define PTE_BASE (0x400FF100u) +/** Peripheral PTE base pointer */ +#define PTE ((GPIO_Type *)PTE_BASE) + +/** + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ + __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ + __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ + __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */ + __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ + __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ + __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ + __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ + __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ + __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ + __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ + __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/* A1 Bit Fields */ +#define I2C_A1_AD_MASK 0xFEu +#define I2C_A1_AD_SHIFT 1 +#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK) +/* F Bit Fields */ +#define I2C_F_ICR_MASK 0x3Fu +#define I2C_F_ICR_SHIFT 0 +#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK) +#define I2C_F_MULT_MASK 0xC0u +#define I2C_F_MULT_SHIFT 6 +#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK) +/* C1 Bit Fields */ +#define I2C_C1_DMAEN_MASK 0x1u +#define I2C_C1_DMAEN_SHIFT 0 +#define I2C_C1_WUEN_MASK 0x2u +#define I2C_C1_WUEN_SHIFT 1 +#define I2C_C1_RSTA_MASK 0x4u +#define I2C_C1_RSTA_SHIFT 2 +#define I2C_C1_TXAK_MASK 0x8u +#define I2C_C1_TXAK_SHIFT 3 +#define I2C_C1_TX_MASK 0x10u +#define I2C_C1_TX_SHIFT 4 +#define I2C_C1_MST_MASK 0x20u +#define I2C_C1_MST_SHIFT 5 +#define I2C_C1_IICIE_MASK 0x40u +#define I2C_C1_IICIE_SHIFT 6 +#define I2C_C1_IICEN_MASK 0x80u +#define I2C_C1_IICEN_SHIFT 7 +/* S Bit Fields */ +#define I2C_S_RXAK_MASK 0x1u +#define I2C_S_RXAK_SHIFT 0 +#define I2C_S_IICIF_MASK 0x2u +#define I2C_S_IICIF_SHIFT 1 +#define I2C_S_SRW_MASK 0x4u +#define I2C_S_SRW_SHIFT 2 +#define I2C_S_RAM_MASK 0x8u +#define I2C_S_RAM_SHIFT 3 +#define I2C_S_ARBL_MASK 0x10u +#define I2C_S_ARBL_SHIFT 4 +#define I2C_S_BUSY_MASK 0x20u +#define I2C_S_BUSY_SHIFT 5 +#define I2C_S_IAAS_MASK 0x40u +#define I2C_S_IAAS_SHIFT 6 +#define I2C_S_TCF_MASK 0x80u +#define I2C_S_TCF_SHIFT 7 +/* D Bit Fields */ +#define I2C_D_DATA_MASK 0xFFu +#define I2C_D_DATA_SHIFT 0 +#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK) +/* C2 Bit Fields */ +#define I2C_C2_AD_MASK 0x7u +#define I2C_C2_AD_SHIFT 0 +#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK) +#define I2C_C2_RMEN_MASK 0x8u +#define I2C_C2_RMEN_SHIFT 3 +#define I2C_C2_SBRC_MASK 0x10u +#define I2C_C2_SBRC_SHIFT 4 +#define I2C_C2_HDRS_MASK 0x20u +#define I2C_C2_HDRS_SHIFT 5 +#define I2C_C2_ADEXT_MASK 0x40u +#define I2C_C2_ADEXT_SHIFT 6 +#define I2C_C2_GCAEN_MASK 0x80u +#define I2C_C2_GCAEN_SHIFT 7 +/* FLT Bit Fields */ +#define I2C_FLT_FLT_MASK 0x1Fu +#define I2C_FLT_FLT_SHIFT 0 +#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK) +/* RA Bit Fields */ +#define I2C_RA_RAD_MASK 0xFEu +#define I2C_RA_RAD_SHIFT 1 +#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK) +/* SMB Bit Fields */ +#define I2C_SMB_SHTF2IE_MASK 0x1u +#define I2C_SMB_SHTF2IE_SHIFT 0 +#define I2C_SMB_SHTF2_MASK 0x2u +#define I2C_SMB_SHTF2_SHIFT 1 +#define I2C_SMB_SHTF1_MASK 0x4u +#define I2C_SMB_SHTF1_SHIFT 2 +#define I2C_SMB_SLTF_MASK 0x8u +#define I2C_SMB_SLTF_SHIFT 3 +#define I2C_SMB_TCKSEL_MASK 0x10u +#define I2C_SMB_TCKSEL_SHIFT 4 +#define I2C_SMB_SIICAEN_MASK 0x20u +#define I2C_SMB_SIICAEN_SHIFT 5 +#define I2C_SMB_ALERTEN_MASK 0x40u +#define I2C_SMB_ALERTEN_SHIFT 6 +#define I2C_SMB_FACK_MASK 0x80u +#define I2C_SMB_FACK_SHIFT 7 +/* A2 Bit Fields */ +#define I2C_A2_SAD_MASK 0xFEu +#define I2C_A2_SAD_SHIFT 1 +#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK) +/* SLTH Bit Fields */ +#define I2C_SLTH_SSLT_MASK 0xFFu +#define I2C_SLTH_SSLT_SHIFT 0 +#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK) +/* SLTL Bit Fields */ +#define I2C_SLTL_SSLT_MASK 0xFFu +#define I2C_SLTL_SSLT_SHIFT 0 +#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK) + +/** + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C0 base address */ +#define I2C0_BASE (0x40066000u) +/** Peripheral I2C0 base pointer */ +#define I2C0 ((I2C_Type *)I2C0_BASE) + +/** + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[24]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_3[28]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ + uint8_t RESERVED_4[8]; + __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_5[24]; + __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_6[24]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ + uint8_t RESERVED_7[28]; + __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ + __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/* TCSR Bit Fields */ +#define I2S_TCSR_FRDE_MASK 0x1u +#define I2S_TCSR_FRDE_SHIFT 0 +#define I2S_TCSR_FWDE_MASK 0x2u +#define I2S_TCSR_FWDE_SHIFT 1 +#define I2S_TCSR_FRIE_MASK 0x100u +#define I2S_TCSR_FRIE_SHIFT 8 +#define I2S_TCSR_FWIE_MASK 0x200u +#define I2S_TCSR_FWIE_SHIFT 9 +#define I2S_TCSR_FEIE_MASK 0x400u +#define I2S_TCSR_FEIE_SHIFT 10 +#define I2S_TCSR_SEIE_MASK 0x800u +#define I2S_TCSR_SEIE_SHIFT 11 +#define I2S_TCSR_WSIE_MASK 0x1000u +#define I2S_TCSR_WSIE_SHIFT 12 +#define I2S_TCSR_FRF_MASK 0x10000u +#define I2S_TCSR_FRF_SHIFT 16 +#define I2S_TCSR_FWF_MASK 0x20000u +#define I2S_TCSR_FWF_SHIFT 17 +#define I2S_TCSR_FEF_MASK 0x40000u +#define I2S_TCSR_FEF_SHIFT 18 +#define I2S_TCSR_SEF_MASK 0x80000u +#define I2S_TCSR_SEF_SHIFT 19 +#define I2S_TCSR_WSF_MASK 0x100000u +#define I2S_TCSR_WSF_SHIFT 20 +#define I2S_TCSR_SR_MASK 0x1000000u +#define I2S_TCSR_SR_SHIFT 24 +#define I2S_TCSR_FR_MASK 0x2000000u +#define I2S_TCSR_FR_SHIFT 25 +#define I2S_TCSR_BCE_MASK 0x10000000u +#define I2S_TCSR_BCE_SHIFT 28 +#define I2S_TCSR_DBGE_MASK 0x20000000u +#define I2S_TCSR_DBGE_SHIFT 29 +#define I2S_TCSR_STOPE_MASK 0x40000000u +#define I2S_TCSR_STOPE_SHIFT 30 +#define I2S_TCSR_TE_MASK 0x80000000u +#define I2S_TCSR_TE_SHIFT 31 +/* TCR1 Bit Fields */ +#define I2S_TCR1_TFW_MASK 0x7u +#define I2S_TCR1_TFW_SHIFT 0 +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK) +/* TCR2 Bit Fields */ +#define I2S_TCR2_DIV_MASK 0xFFu +#define I2S_TCR2_DIV_SHIFT 0 +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK 0x1000000u +#define I2S_TCR2_BCD_SHIFT 24 +#define I2S_TCR2_BCP_MASK 0x2000000u +#define I2S_TCR2_BCP_SHIFT 25 +#define I2S_TCR2_MSEL_MASK 0xC000000u +#define I2S_TCR2_MSEL_SHIFT 26 +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK 0x10000000u +#define I2S_TCR2_BCI_SHIFT 28 +#define I2S_TCR2_BCS_MASK 0x20000000u +#define I2S_TCR2_BCS_SHIFT 29 +#define I2S_TCR2_SYNC_MASK 0xC0000000u +#define I2S_TCR2_SYNC_SHIFT 30 +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK) +/* TCR3 Bit Fields */ +#define I2S_TCR3_WDFL_MASK 0x1Fu +#define I2S_TCR3_WDFL_SHIFT 0 +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK 0x30000u +#define I2S_TCR3_TCE_SHIFT 16 +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK) +/* TCR4 Bit Fields */ +#define I2S_TCR4_FSD_MASK 0x1u +#define I2S_TCR4_FSD_SHIFT 0 +#define I2S_TCR4_FSP_MASK 0x2u +#define I2S_TCR4_FSP_SHIFT 1 +#define I2S_TCR4_FSE_MASK 0x8u +#define I2S_TCR4_FSE_SHIFT 3 +#define I2S_TCR4_MF_MASK 0x10u +#define I2S_TCR4_MF_SHIFT 4 +#define I2S_TCR4_SYWD_MASK 0x1F00u +#define I2S_TCR4_SYWD_SHIFT 8 +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK 0x1F0000u +#define I2S_TCR4_FRSZ_SHIFT 16 +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK) +/* TCR5 Bit Fields */ +#define I2S_TCR5_FBT_MASK 0x1F00u +#define I2S_TCR5_FBT_SHIFT 8 +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK 0x1F0000u +#define I2S_TCR5_W0W_SHIFT 16 +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK 0x1F000000u +#define I2S_TCR5_WNW_SHIFT 24 +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK) +/* TDR Bit Fields */ +#define I2S_TDR_TDR_MASK 0xFFFFFFFFu +#define I2S_TDR_TDR_SHIFT 0 +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK) +/* TFR Bit Fields */ +#define I2S_TFR_RFP_MASK 0xFu +#define I2S_TFR_RFP_SHIFT 0 +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK 0xF0000u +#define I2S_TFR_WFP_SHIFT 16 +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK) +/* TMR Bit Fields */ +#define I2S_TMR_TWM_MASK 0xFFFFFFFFu +#define I2S_TMR_TWM_SHIFT 0 +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK) +/* RCSR Bit Fields */ +#define I2S_RCSR_FRDE_MASK 0x1u +#define I2S_RCSR_FRDE_SHIFT 0 +#define I2S_RCSR_FWDE_MASK 0x2u +#define I2S_RCSR_FWDE_SHIFT 1 +#define I2S_RCSR_FRIE_MASK 0x100u +#define I2S_RCSR_FRIE_SHIFT 8 +#define I2S_RCSR_FWIE_MASK 0x200u +#define I2S_RCSR_FWIE_SHIFT 9 +#define I2S_RCSR_FEIE_MASK 0x400u +#define I2S_RCSR_FEIE_SHIFT 10 +#define I2S_RCSR_SEIE_MASK 0x800u +#define I2S_RCSR_SEIE_SHIFT 11 +#define I2S_RCSR_WSIE_MASK 0x1000u +#define I2S_RCSR_WSIE_SHIFT 12 +#define I2S_RCSR_FRF_MASK 0x10000u +#define I2S_RCSR_FRF_SHIFT 16 +#define I2S_RCSR_FWF_MASK 0x20000u +#define I2S_RCSR_FWF_SHIFT 17 +#define I2S_RCSR_FEF_MASK 0x40000u +#define I2S_RCSR_FEF_SHIFT 18 +#define I2S_RCSR_SEF_MASK 0x80000u +#define I2S_RCSR_SEF_SHIFT 19 +#define I2S_RCSR_WSF_MASK 0x100000u +#define I2S_RCSR_WSF_SHIFT 20 +#define I2S_RCSR_SR_MASK 0x1000000u +#define I2S_RCSR_SR_SHIFT 24 +#define I2S_RCSR_FR_MASK 0x2000000u +#define I2S_RCSR_FR_SHIFT 25 +#define I2S_RCSR_BCE_MASK 0x10000000u +#define I2S_RCSR_BCE_SHIFT 28 +#define I2S_RCSR_DBGE_MASK 0x20000000u +#define I2S_RCSR_DBGE_SHIFT 29 +#define I2S_RCSR_STOPE_MASK 0x40000000u +#define I2S_RCSR_STOPE_SHIFT 30 +#define I2S_RCSR_RE_MASK 0x80000000u +#define I2S_RCSR_RE_SHIFT 31 +/* RCR1 Bit Fields */ +#define I2S_RCR1_RFW_MASK 0x7u +#define I2S_RCR1_RFW_SHIFT 0 +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK) +/* RCR2 Bit Fields */ +#define I2S_RCR2_DIV_MASK 0xFFu +#define I2S_RCR2_DIV_SHIFT 0 +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK 0x1000000u +#define I2S_RCR2_BCD_SHIFT 24 +#define I2S_RCR2_BCP_MASK 0x2000000u +#define I2S_RCR2_BCP_SHIFT 25 +#define I2S_RCR2_MSEL_MASK 0xC000000u +#define I2S_RCR2_MSEL_SHIFT 26 +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK 0x10000000u +#define I2S_RCR2_BCI_SHIFT 28 +#define I2S_RCR2_BCS_MASK 0x20000000u +#define I2S_RCR2_BCS_SHIFT 29 +#define I2S_RCR2_SYNC_MASK 0xC0000000u +#define I2S_RCR2_SYNC_SHIFT 30 +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK) +/* RCR3 Bit Fields */ +#define I2S_RCR3_WDFL_MASK 0x1Fu +#define I2S_RCR3_WDFL_SHIFT 0 +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK 0x30000u +#define I2S_RCR3_RCE_SHIFT 16 +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK) +/* RCR4 Bit Fields */ +#define I2S_RCR4_FSD_MASK 0x1u +#define I2S_RCR4_FSD_SHIFT 0 +#define I2S_RCR4_FSP_MASK 0x2u +#define I2S_RCR4_FSP_SHIFT 1 +#define I2S_RCR4_FSE_MASK 0x8u +#define I2S_RCR4_FSE_SHIFT 3 +#define I2S_RCR4_MF_MASK 0x10u +#define I2S_RCR4_MF_SHIFT 4 +#define I2S_RCR4_SYWD_MASK 0x1F00u +#define I2S_RCR4_SYWD_SHIFT 8 +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK 0x1F0000u +#define I2S_RCR4_FRSZ_SHIFT 16 +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK) +/* RCR5 Bit Fields */ +#define I2S_RCR5_FBT_MASK 0x1F00u +#define I2S_RCR5_FBT_SHIFT 8 +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK 0x1F0000u +#define I2S_RCR5_W0W_SHIFT 16 +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK 0x1F000000u +#define I2S_RCR5_WNW_SHIFT 24 +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK) +/* RDR Bit Fields */ +#define I2S_RDR_RDR_MASK 0xFFFFFFFFu +#define I2S_RDR_RDR_SHIFT 0 +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK) +/* RFR Bit Fields */ +#define I2S_RFR_RFP_MASK 0xFu +#define I2S_RFR_RFP_SHIFT 0 +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK) +#define I2S_RFR_WFP_MASK 0xF0000u +#define I2S_RFR_WFP_SHIFT 16 +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK) +/* RMR Bit Fields */ +#define I2S_RMR_RWM_MASK 0xFFFFFFFFu +#define I2S_RMR_RWM_SHIFT 0 +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK) +/* MCR Bit Fields */ +#define I2S_MCR_MICS_MASK 0x3000000u +#define I2S_MCR_MICS_SHIFT 24 +#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK) +#define I2S_MCR_MOE_MASK 0x40000000u +#define I2S_MCR_MOE_SHIFT 30 +#define I2S_MCR_DUF_MASK 0x80000000u +#define I2S_MCR_DUF_SHIFT 31 +/* MDR Bit Fields */ +#define I2S_MDR_DIVIDE_MASK 0xFFFu +#define I2S_MDR_DIVIDE_SHIFT 0 +#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK) +#define I2S_MDR_FRACT_MASK 0xFF000u +#define I2S_MDR_FRACT_SHIFT 12 +#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK) + +/** + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S0 base address */ +#define I2S0_BASE (0x4002F000u) +/** Peripheral I2S0 base pointer */ +#define I2S0 ((I2S_Type *)I2S0_BASE) + +/** + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LLWU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer + * @{ + */ + +/** LLWU - Register Layout Typedef */ +typedef struct { + __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */ + __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */ + __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */ + __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */ + __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */ + __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */ + __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */ + __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */ + __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */ + __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */ + __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */ +} LLWU_Type; + +/* ---------------------------------------------------------------------------- + -- LLWU Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LLWU_Register_Masks LLWU Register Masks + * @{ + */ + +/* PE1 Bit Fields */ +#define LLWU_PE1_WUPE0_MASK 0x3u +#define LLWU_PE1_WUPE0_SHIFT 0 +#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK) +#define LLWU_PE1_WUPE1_MASK 0xCu +#define LLWU_PE1_WUPE1_SHIFT 2 +#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK) +#define LLWU_PE1_WUPE2_MASK 0x30u +#define LLWU_PE1_WUPE2_SHIFT 4 +#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK) +#define LLWU_PE1_WUPE3_MASK 0xC0u +#define LLWU_PE1_WUPE3_SHIFT 6 +#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK) +/* PE2 Bit Fields */ +#define LLWU_PE2_WUPE4_MASK 0x3u +#define LLWU_PE2_WUPE4_SHIFT 0 +#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK) +#define LLWU_PE2_WUPE5_MASK 0xCu +#define LLWU_PE2_WUPE5_SHIFT 2 +#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK) +#define LLWU_PE2_WUPE6_MASK 0x30u +#define LLWU_PE2_WUPE6_SHIFT 4 +#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK) +#define LLWU_PE2_WUPE7_MASK 0xC0u +#define LLWU_PE2_WUPE7_SHIFT 6 +#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK) +/* PE3 Bit Fields */ +#define LLWU_PE3_WUPE8_MASK 0x3u +#define LLWU_PE3_WUPE8_SHIFT 0 +#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK) +#define LLWU_PE3_WUPE9_MASK 0xCu +#define LLWU_PE3_WUPE9_SHIFT 2 +#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK) +#define LLWU_PE3_WUPE10_MASK 0x30u +#define LLWU_PE3_WUPE10_SHIFT 4 +#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK) +#define LLWU_PE3_WUPE11_MASK 0xC0u +#define LLWU_PE3_WUPE11_SHIFT 6 +#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK) +/* PE4 Bit Fields */ +#define LLWU_PE4_WUPE12_MASK 0x3u +#define LLWU_PE4_WUPE12_SHIFT 0 +#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK) +#define LLWU_PE4_WUPE13_MASK 0xCu +#define LLWU_PE4_WUPE13_SHIFT 2 +#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK) +#define LLWU_PE4_WUPE14_MASK 0x30u +#define LLWU_PE4_WUPE14_SHIFT 4 +#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK) +#define LLWU_PE4_WUPE15_MASK 0xC0u +#define LLWU_PE4_WUPE15_SHIFT 6 +#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK) +/* ME Bit Fields */ +#define LLWU_ME_WUME0_MASK 0x1u +#define LLWU_ME_WUME0_SHIFT 0 +#define LLWU_ME_WUME1_MASK 0x2u +#define LLWU_ME_WUME1_SHIFT 1 +#define LLWU_ME_WUME2_MASK 0x4u +#define LLWU_ME_WUME2_SHIFT 2 +#define LLWU_ME_WUME3_MASK 0x8u +#define LLWU_ME_WUME3_SHIFT 3 +#define LLWU_ME_WUME4_MASK 0x10u +#define LLWU_ME_WUME4_SHIFT 4 +#define LLWU_ME_WUME5_MASK 0x20u +#define LLWU_ME_WUME5_SHIFT 5 +#define LLWU_ME_WUME6_MASK 0x40u +#define LLWU_ME_WUME6_SHIFT 6 +#define LLWU_ME_WUME7_MASK 0x80u +#define LLWU_ME_WUME7_SHIFT 7 +/* F1 Bit Fields */ +#define LLWU_F1_WUF0_MASK 0x1u +#define LLWU_F1_WUF0_SHIFT 0 +#define LLWU_F1_WUF1_MASK 0x2u +#define LLWU_F1_WUF1_SHIFT 1 +#define LLWU_F1_WUF2_MASK 0x4u +#define LLWU_F1_WUF2_SHIFT 2 +#define LLWU_F1_WUF3_MASK 0x8u +#define LLWU_F1_WUF3_SHIFT 3 +#define LLWU_F1_WUF4_MASK 0x10u +#define LLWU_F1_WUF4_SHIFT 4 +#define LLWU_F1_WUF5_MASK 0x20u +#define LLWU_F1_WUF5_SHIFT 5 +#define LLWU_F1_WUF6_MASK 0x40u +#define LLWU_F1_WUF6_SHIFT 6 +#define LLWU_F1_WUF7_MASK 0x80u +#define LLWU_F1_WUF7_SHIFT 7 +/* F2 Bit Fields */ +#define LLWU_F2_WUF8_MASK 0x1u +#define LLWU_F2_WUF8_SHIFT 0 +#define LLWU_F2_WUF9_MASK 0x2u +#define LLWU_F2_WUF9_SHIFT 1 +#define LLWU_F2_WUF10_MASK 0x4u +#define LLWU_F2_WUF10_SHIFT 2 +#define LLWU_F2_WUF11_MASK 0x8u +#define LLWU_F2_WUF11_SHIFT 3 +#define LLWU_F2_WUF12_MASK 0x10u +#define LLWU_F2_WUF12_SHIFT 4 +#define LLWU_F2_WUF13_MASK 0x20u +#define LLWU_F2_WUF13_SHIFT 5 +#define LLWU_F2_WUF14_MASK 0x40u +#define LLWU_F2_WUF14_SHIFT 6 +#define LLWU_F2_WUF15_MASK 0x80u +#define LLWU_F2_WUF15_SHIFT 7 +/* F3 Bit Fields */ +#define LLWU_F3_MWUF0_MASK 0x1u +#define LLWU_F3_MWUF0_SHIFT 0 +#define LLWU_F3_MWUF1_MASK 0x2u +#define LLWU_F3_MWUF1_SHIFT 1 +#define LLWU_F3_MWUF2_MASK 0x4u +#define LLWU_F3_MWUF2_SHIFT 2 +#define LLWU_F3_MWUF3_MASK 0x8u +#define LLWU_F3_MWUF3_SHIFT 3 +#define LLWU_F3_MWUF4_MASK 0x10u +#define LLWU_F3_MWUF4_SHIFT 4 +#define LLWU_F3_MWUF5_MASK 0x20u +#define LLWU_F3_MWUF5_SHIFT 5 +#define LLWU_F3_MWUF6_MASK 0x40u +#define LLWU_F3_MWUF6_SHIFT 6 +#define LLWU_F3_MWUF7_MASK 0x80u +#define LLWU_F3_MWUF7_SHIFT 7 +/* FILT1 Bit Fields */ +#define LLWU_FILT1_FILTSEL_MASK 0xFu +#define LLWU_FILT1_FILTSEL_SHIFT 0 +#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK) +#define LLWU_FILT1_FILTE_MASK 0x60u +#define LLWU_FILT1_FILTE_SHIFT 5 +#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK) +#define LLWU_FILT1_FILTF_MASK 0x80u +#define LLWU_FILT1_FILTF_SHIFT 7 +/* FILT2 Bit Fields */ +#define LLWU_FILT2_FILTSEL_MASK 0xFu +#define LLWU_FILT2_FILTSEL_SHIFT 0 +#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK) +#define LLWU_FILT2_FILTE_MASK 0x60u +#define LLWU_FILT2_FILTE_SHIFT 5 +#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK) +#define LLWU_FILT2_FILTF_MASK 0x80u +#define LLWU_FILT2_FILTF_SHIFT 7 +/* RST Bit Fields */ +#define LLWU_RST_RSTFILT_MASK 0x1u +#define LLWU_RST_RSTFILT_SHIFT 0 +#define LLWU_RST_LLRSTE_MASK 0x2u +#define LLWU_RST_LLRSTE_SHIFT 1 + +/** + * @} + */ /* end of group LLWU_Register_Masks */ + + +/* LLWU - Peripheral instance base addresses */ +/** Peripheral LLWU base address */ +#define LLWU_BASE (0x4007C000u) +/** Peripheral LLWU base pointer */ +#define LLWU ((LLWU_Type *)LLWU_BASE) + +/** + * @} + */ /* end of group LLWU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer + * @{ + */ + +/** LPTMR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ + __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ + __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ + __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ +} LPTMR_Type; + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/* CSR Bit Fields */ +#define LPTMR_CSR_TEN_MASK 0x1u +#define LPTMR_CSR_TEN_SHIFT 0 +#define LPTMR_CSR_TMS_MASK 0x2u +#define LPTMR_CSR_TMS_SHIFT 1 +#define LPTMR_CSR_TFC_MASK 0x4u +#define LPTMR_CSR_TFC_SHIFT 2 +#define LPTMR_CSR_TPP_MASK 0x8u +#define LPTMR_CSR_TPP_SHIFT 3 +#define LPTMR_CSR_TPS_MASK 0x30u +#define LPTMR_CSR_TPS_SHIFT 4 +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK) +#define LPTMR_CSR_TIE_MASK 0x40u +#define LPTMR_CSR_TIE_SHIFT 6 +#define LPTMR_CSR_TCF_MASK 0x80u +#define LPTMR_CSR_TCF_SHIFT 7 +/* PSR Bit Fields */ +#define LPTMR_PSR_PCS_MASK 0x3u +#define LPTMR_PSR_PCS_SHIFT 0 +#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK) +#define LPTMR_PSR_PBYP_MASK 0x4u +#define LPTMR_PSR_PBYP_SHIFT 2 +#define LPTMR_PSR_PRESCALE_MASK 0x78u +#define LPTMR_PSR_PRESCALE_SHIFT 3 +#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK) +/* CMR Bit Fields */ +#define LPTMR_CMR_COMPARE_MASK 0xFFFFu +#define LPTMR_CMR_COMPARE_SHIFT 0 +#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK) +/* CNR Bit Fields */ +#define LPTMR_CNR_COUNTER_MASK 0xFFFFu +#define LPTMR_CNR_COUNTER_SHIFT 0 +#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK) + +/** + * @} + */ /* end of group LPTMR_Register_Masks */ + + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x40040000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + +/** + * @} + */ /* end of group LPTMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MCG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer + * @{ + */ + +/** MCG - Register Layout Typedef */ +typedef struct { + __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ + __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ + __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ + __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ + __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ + __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ + __I uint8_t S; /**< MCG Status Register, offset: 0x6 */ + uint8_t RESERVED_0[1]; + __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ + uint8_t RESERVED_1[1]; + __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ + __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ + __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ + __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ +} MCG_Type; + +/* ---------------------------------------------------------------------------- + -- MCG Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup MCG_Register_Masks MCG Register Masks + * @{ + */ + +/* C1 Bit Fields */ +#define MCG_C1_IREFSTEN_MASK 0x1u +#define MCG_C1_IREFSTEN_SHIFT 0 +#define MCG_C1_IRCLKEN_MASK 0x2u +#define MCG_C1_IRCLKEN_SHIFT 1 +#define MCG_C1_IREFS_MASK 0x4u +#define MCG_C1_IREFS_SHIFT 2 +#define MCG_C1_FRDIV_MASK 0x38u +#define MCG_C1_FRDIV_SHIFT 3 +#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK) +#define MCG_C1_CLKS_MASK 0xC0u +#define MCG_C1_CLKS_SHIFT 6 +#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK) +/* C2 Bit Fields */ +#define MCG_C2_IRCS_MASK 0x1u +#define MCG_C2_IRCS_SHIFT 0 +#define MCG_C2_LP_MASK 0x2u +#define MCG_C2_LP_SHIFT 1 +#define MCG_C2_EREFS0_MASK 0x4u +#define MCG_C2_EREFS0_SHIFT 2 +#define MCG_C2_HGO0_MASK 0x8u +#define MCG_C2_HGO0_SHIFT 3 +#define MCG_C2_RANGE0_MASK 0x30u +#define MCG_C2_RANGE0_SHIFT 4 +#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK) +#define MCG_C2_LOCRE0_MASK 0x80u +#define MCG_C2_LOCRE0_SHIFT 7 +/* C3 Bit Fields */ +#define MCG_C3_SCTRIM_MASK 0xFFu +#define MCG_C3_SCTRIM_SHIFT 0 +#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK) +/* C4 Bit Fields */ +#define MCG_C4_SCFTRIM_MASK 0x1u +#define MCG_C4_SCFTRIM_SHIFT 0 +#define MCG_C4_FCTRIM_MASK 0x1Eu +#define MCG_C4_FCTRIM_SHIFT 1 +#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK) +#define MCG_C4_DRST_DRS_MASK 0x60u +#define MCG_C4_DRST_DRS_SHIFT 5 +#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK) +#define MCG_C4_DMX32_MASK 0x80u +#define MCG_C4_DMX32_SHIFT 7 +/* C5 Bit Fields */ +#define MCG_C5_PRDIV0_MASK 0x1Fu +#define MCG_C5_PRDIV0_SHIFT 0 +#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK) +#define MCG_C5_PLLSTEN0_MASK 0x20u +#define MCG_C5_PLLSTEN0_SHIFT 5 +#define MCG_C5_PLLCLKEN0_MASK 0x40u +#define MCG_C5_PLLCLKEN0_SHIFT 6 +/* C6 Bit Fields */ +#define MCG_C6_VDIV0_MASK 0x1Fu +#define MCG_C6_VDIV0_SHIFT 0 +#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK) +#define MCG_C6_CME0_MASK 0x20u +#define MCG_C6_CME0_SHIFT 5 +#define MCG_C6_PLLS_MASK 0x40u +#define MCG_C6_PLLS_SHIFT 6 +#define MCG_C6_LOLIE0_MASK 0x80u +#define MCG_C6_LOLIE0_SHIFT 7 +/* S Bit Fields */ +#define MCG_S_IRCST_MASK 0x1u +#define MCG_S_IRCST_SHIFT 0 +#define MCG_S_OSCINIT0_MASK 0x2u +#define MCG_S_OSCINIT0_SHIFT 1 +#define MCG_S_CLKST_MASK 0xCu +#define MCG_S_CLKST_SHIFT 2 +#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK) +#define MCG_S_IREFST_MASK 0x10u +#define MCG_S_IREFST_SHIFT 4 +#define MCG_S_PLLST_MASK 0x20u +#define MCG_S_PLLST_SHIFT 5 +#define MCG_S_LOCK0_MASK 0x40u +#define MCG_S_LOCK0_SHIFT 6 +#define MCG_S_LOLS0_MASK 0x80u +#define MCG_S_LOLS0_SHIFT 7 +/* SC Bit Fields */ +#define MCG_SC_LOCS0_MASK 0x1u +#define MCG_SC_LOCS0_SHIFT 0 +#define MCG_SC_FCRDIV_MASK 0xEu +#define MCG_SC_FCRDIV_SHIFT 1 +#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK) +#define MCG_SC_FLTPRSRV_MASK 0x10u +#define MCG_SC_FLTPRSRV_SHIFT 4 +#define MCG_SC_ATMF_MASK 0x20u +#define MCG_SC_ATMF_SHIFT 5 +#define MCG_SC_ATMS_MASK 0x40u +#define MCG_SC_ATMS_SHIFT 6 +#define MCG_SC_ATME_MASK 0x80u +#define MCG_SC_ATME_SHIFT 7 +/* ATCVH Bit Fields */ +#define MCG_ATCVH_ATCVH_MASK 0xFFu +#define MCG_ATCVH_ATCVH_SHIFT 0 +#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK) +/* ATCVL Bit Fields */ +#define MCG_ATCVL_ATCVL_MASK 0xFFu +#define MCG_ATCVL_ATCVL_SHIFT 0 +#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK) +/* C7 Bit Fields */ +#define MCG_C7_OSCSEL_MASK 0x1u +#define MCG_C7_OSCSEL_SHIFT 0 +/* C8 Bit Fields */ +#define MCG_C8_LOCS1_MASK 0x1u +#define MCG_C8_LOCS1_SHIFT 0 +#define MCG_C8_CME1_MASK 0x20u +#define MCG_C8_CME1_SHIFT 5 +#define MCG_C8_LOLRE_MASK 0x40u +#define MCG_C8_LOLRE_SHIFT 6 +#define MCG_C8_LOCRE1_MASK 0x80u +#define MCG_C8_LOCRE1_SHIFT 7 + +/** + * @} + */ /* end of group MCG_Register_Masks */ + + +/* MCG - Peripheral instance base addresses */ +/** Peripheral MCG base address */ +#define MCG_BASE (0x40064000u) +/** Peripheral MCG base pointer */ +#define MCG ((MCG_Type *)MCG_BASE) + +/** + * @} + */ /* end of group MCG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- NV Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer + * @{ + */ + +/** NV - Register Layout Typedef */ +typedef struct { + __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ + __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ + __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ + __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ + __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ + __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ + __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ + __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ + __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ + __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ + __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ + __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ + __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ + __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ + __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */ + __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */ +} NV_Type; + +/* ---------------------------------------------------------------------------- + -- NV Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup NV_Register_Masks NV Register Masks + * @{ + */ + +/* BACKKEY3 Bit Fields */ +#define NV_BACKKEY3_KEY_MASK 0xFFu +#define NV_BACKKEY3_KEY_SHIFT 0 +#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK) +/* BACKKEY2 Bit Fields */ +#define NV_BACKKEY2_KEY_MASK 0xFFu +#define NV_BACKKEY2_KEY_SHIFT 0 +#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK) +/* BACKKEY1 Bit Fields */ +#define NV_BACKKEY1_KEY_MASK 0xFFu +#define NV_BACKKEY1_KEY_SHIFT 0 +#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK) +/* BACKKEY0 Bit Fields */ +#define NV_BACKKEY0_KEY_MASK 0xFFu +#define NV_BACKKEY0_KEY_SHIFT 0 +#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK) +/* BACKKEY7 Bit Fields */ +#define NV_BACKKEY7_KEY_MASK 0xFFu +#define NV_BACKKEY7_KEY_SHIFT 0 +#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK) +/* BACKKEY6 Bit Fields */ +#define NV_BACKKEY6_KEY_MASK 0xFFu +#define NV_BACKKEY6_KEY_SHIFT 0 +#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK) +/* BACKKEY5 Bit Fields */ +#define NV_BACKKEY5_KEY_MASK 0xFFu +#define NV_BACKKEY5_KEY_SHIFT 0 +#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK) +/* BACKKEY4 Bit Fields */ +#define NV_BACKKEY4_KEY_MASK 0xFFu +#define NV_BACKKEY4_KEY_SHIFT 0 +#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK) +/* FPROT3 Bit Fields */ +#define NV_FPROT3_PROT_MASK 0xFFu +#define NV_FPROT3_PROT_SHIFT 0 +#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK) +/* FPROT2 Bit Fields */ +#define NV_FPROT2_PROT_MASK 0xFFu +#define NV_FPROT2_PROT_SHIFT 0 +#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK) +/* FPROT1 Bit Fields */ +#define NV_FPROT1_PROT_MASK 0xFFu +#define NV_FPROT1_PROT_SHIFT 0 +#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK) +/* FPROT0 Bit Fields */ +#define NV_FPROT0_PROT_MASK 0xFFu +#define NV_FPROT0_PROT_SHIFT 0 +#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK) +/* FSEC Bit Fields */ +#define NV_FSEC_SEC_MASK 0x3u +#define NV_FSEC_SEC_SHIFT 0 +#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK) +#define NV_FSEC_FSLACC_MASK 0xCu +#define NV_FSEC_FSLACC_SHIFT 2 +#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK) +#define NV_FSEC_MEEN_MASK 0x30u +#define NV_FSEC_MEEN_SHIFT 4 +#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK) +#define NV_FSEC_KEYEN_MASK 0xC0u +#define NV_FSEC_KEYEN_SHIFT 6 +#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK) +/* FOPT Bit Fields */ +#define NV_FOPT_LPBOOT_MASK 0x1u +#define NV_FOPT_LPBOOT_SHIFT 0 +#define NV_FOPT_EZPORT_DIS_MASK 0x2u +#define NV_FOPT_EZPORT_DIS_SHIFT 1 +/* FEPROT Bit Fields */ +#define NV_FEPROT_EPROT_MASK 0xFFu +#define NV_FEPROT_EPROT_SHIFT 0 +#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK) +/* FDPROT Bit Fields */ +#define NV_FDPROT_DPROT_MASK 0xFFu +#define NV_FDPROT_DPROT_SHIFT 0 +#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK) + +/** + * @} + */ /* end of group NV_Register_Masks */ + + +/* NV - Peripheral instance base addresses */ +/** Peripheral FTFL_FlashConfig base address */ +#define FTFL_FlashConfig_BASE (0x400u) +/** Peripheral FTFL_FlashConfig base pointer */ +#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE) + +/** + * @} + */ /* end of group NV_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer + * @{ + */ + +/** OSC - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ +} OSC_Type; + +/* ---------------------------------------------------------------------------- + -- OSC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup OSC_Register_Masks OSC Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define OSC_CR_SC16P_MASK 0x1u +#define OSC_CR_SC16P_SHIFT 0 +#define OSC_CR_SC8P_MASK 0x2u +#define OSC_CR_SC8P_SHIFT 1 +#define OSC_CR_SC4P_MASK 0x4u +#define OSC_CR_SC4P_SHIFT 2 +#define OSC_CR_SC2P_MASK 0x8u +#define OSC_CR_SC2P_SHIFT 3 +#define OSC_CR_EREFSTEN_MASK 0x20u +#define OSC_CR_EREFSTEN_SHIFT 5 +#define OSC_CR_ERCLKEN_MASK 0x80u +#define OSC_CR_ERCLKEN_SHIFT 7 + +/** + * @} + */ /* end of group OSC_Register_Masks */ + + +/* OSC - Peripheral instance base addresses */ +/** Peripheral OSC0 base address */ +#define OSC0_BASE (0x40065000u) +/** Peripheral OSC0 base pointer */ +#define OSC0 ((OSC_Type *)OSC0_BASE) + +/** + * @} + */ /* end of group OSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PDB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer + * @{ + */ + +/** PDB - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */ + __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */ + __I uint32_t CNT; /**< Counter Register, offset: 0x8 */ + __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */ + struct { /* offset: 0x10, array step: 0x10 */ + __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */ + __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */ + __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */ + } CH[1]; + uint8_t RESERVED_0[368]; + __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */ + __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */ +} PDB_Type; + +/* ---------------------------------------------------------------------------- + -- PDB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PDB_Register_Masks PDB Register Masks + * @{ + */ + +/* SC Bit Fields */ +#define PDB_SC_LDOK_MASK 0x1u +#define PDB_SC_LDOK_SHIFT 0 +#define PDB_SC_CONT_MASK 0x2u +#define PDB_SC_CONT_SHIFT 1 +#define PDB_SC_MULT_MASK 0xCu +#define PDB_SC_MULT_SHIFT 2 +#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK) +#define PDB_SC_PDBIE_MASK 0x20u +#define PDB_SC_PDBIE_SHIFT 5 +#define PDB_SC_PDBIF_MASK 0x40u +#define PDB_SC_PDBIF_SHIFT 6 +#define PDB_SC_PDBEN_MASK 0x80u +#define PDB_SC_PDBEN_SHIFT 7 +#define PDB_SC_TRGSEL_MASK 0xF00u +#define PDB_SC_TRGSEL_SHIFT 8 +#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK) +#define PDB_SC_PRESCALER_MASK 0x7000u +#define PDB_SC_PRESCALER_SHIFT 12 +#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK) +#define PDB_SC_DMAEN_MASK 0x8000u +#define PDB_SC_DMAEN_SHIFT 15 +#define PDB_SC_SWTRIG_MASK 0x10000u +#define PDB_SC_SWTRIG_SHIFT 16 +#define PDB_SC_PDBEIE_MASK 0x20000u +#define PDB_SC_PDBEIE_SHIFT 17 +#define PDB_SC_LDMOD_MASK 0xC0000u +#define PDB_SC_LDMOD_SHIFT 18 +#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK) +/* MOD Bit Fields */ +#define PDB_MOD_MOD_MASK 0xFFFFu +#define PDB_MOD_MOD_SHIFT 0 +#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK) +/* CNT Bit Fields */ +#define PDB_CNT_CNT_MASK 0xFFFFu +#define PDB_CNT_CNT_SHIFT 0 +#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK) +/* IDLY Bit Fields */ +#define PDB_IDLY_IDLY_MASK 0xFFFFu +#define PDB_IDLY_IDLY_SHIFT 0 +#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK) +/* C1 Bit Fields */ +#define PDB_C1_EN_MASK 0xFFu +#define PDB_C1_EN_SHIFT 0 +#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK) +#define PDB_C1_TOS_MASK 0xFF00u +#define PDB_C1_TOS_SHIFT 8 +#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK) +#define PDB_C1_BB_MASK 0xFF0000u +#define PDB_C1_BB_SHIFT 16 +#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK) +/* S Bit Fields */ +#define PDB_S_ERR_MASK 0xFFu +#define PDB_S_ERR_SHIFT 0 +#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK) +#define PDB_S_CF_MASK 0xFF0000u +#define PDB_S_CF_SHIFT 16 +#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK) +/* DLY Bit Fields */ +#define PDB_DLY_DLY_MASK 0xFFFFu +#define PDB_DLY_DLY_SHIFT 0 +#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK) +/* POEN Bit Fields */ +#define PDB_POEN_POEN_MASK 0xFFu +#define PDB_POEN_POEN_SHIFT 0 +#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK) +/* PODLY Bit Fields */ +#define PDB_PODLY_DLY2_MASK 0xFFFFu +#define PDB_PODLY_DLY2_SHIFT 0 +#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK) +#define PDB_PODLY_DLY1_MASK 0xFFFF0000u +#define PDB_PODLY_DLY1_SHIFT 16 +#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK) + +/** + * @} + */ /* end of group PDB_Register_Masks */ + + +/* PDB - Peripheral instance base addresses */ +/** Peripheral PDB0 base address */ +#define PDB0_BASE (0x40036000u) +/** Peripheral PDB0 base pointer */ +#define PDB0 ((PDB_Type *)PDB0_BASE) + +/** + * @} + */ /* end of group PDB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer + * @{ + */ + +/** PIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ + uint8_t RESERVED_0[252]; + struct { /* offset: 0x100, array step: 0x10 */ + __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ + __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ + __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ + __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ + } CHANNEL[4]; +} PIT_Type; + +/* ---------------------------------------------------------------------------- + -- PIT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PIT_Register_Masks PIT Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define PIT_MCR_FRZ_MASK 0x1u +#define PIT_MCR_FRZ_SHIFT 0 +#define PIT_MCR_MDIS_MASK 0x2u +#define PIT_MCR_MDIS_SHIFT 1 +/* LDVAL Bit Fields */ +#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu +#define PIT_LDVAL_TSV_SHIFT 0 +#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK) +/* CVAL Bit Fields */ +#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu +#define PIT_CVAL_TVL_SHIFT 0 +#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK) +/* TCTRL Bit Fields */ +#define PIT_TCTRL_TEN_MASK 0x1u +#define PIT_TCTRL_TEN_SHIFT 0 +#define PIT_TCTRL_TIE_MASK 0x2u +#define PIT_TCTRL_TIE_SHIFT 1 +/* TFLG Bit Fields */ +#define PIT_TFLG_TIF_MASK 0x1u +#define PIT_TFLG_TIF_SHIFT 0 + +/** + * @} + */ /* end of group PIT_Register_Masks */ + + +/* PIT - Peripheral instance base addresses */ +/** Peripheral PIT base address */ +#define PIT_BASE (0x40037000u) +/** Peripheral PIT base pointer */ +#define PIT ((PIT_Type *)PIT_BASE) + +/** + * @} + */ /* end of group PIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer + * @{ + */ + +/** PMC - Register Layout Typedef */ +typedef struct { + __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */ + __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */ + __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */ +} PMC_Type; + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/* LVDSC1 Bit Fields */ +#define PMC_LVDSC1_LVDV_MASK 0x3u +#define PMC_LVDSC1_LVDV_SHIFT 0 +#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) +#define PMC_LVDSC1_LVDRE_MASK 0x10u +#define PMC_LVDSC1_LVDRE_SHIFT 4 +#define PMC_LVDSC1_LVDIE_MASK 0x20u +#define PMC_LVDSC1_LVDIE_SHIFT 5 +#define PMC_LVDSC1_LVDACK_MASK 0x40u +#define PMC_LVDSC1_LVDACK_SHIFT 6 +#define PMC_LVDSC1_LVDF_MASK 0x80u +#define PMC_LVDSC1_LVDF_SHIFT 7 +/* LVDSC2 Bit Fields */ +#define PMC_LVDSC2_LVWV_MASK 0x3u +#define PMC_LVDSC2_LVWV_SHIFT 0 +#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) +#define PMC_LVDSC2_LVWIE_MASK 0x20u +#define PMC_LVDSC2_LVWIE_SHIFT 5 +#define PMC_LVDSC2_LVWACK_MASK 0x40u +#define PMC_LVDSC2_LVWACK_SHIFT 6 +#define PMC_LVDSC2_LVWF_MASK 0x80u +#define PMC_LVDSC2_LVWF_SHIFT 7 +/* REGSC Bit Fields */ +#define PMC_REGSC_BGBE_MASK 0x1u +#define PMC_REGSC_BGBE_SHIFT 0 +#define PMC_REGSC_REGONS_MASK 0x4u +#define PMC_REGSC_REGONS_SHIFT 2 +#define PMC_REGSC_ACKISO_MASK 0x8u +#define PMC_REGSC_ACKISO_SHIFT 3 + +/** + * @} + */ /* end of group PMC_Register_Masks */ + + +/* PMC - Peripheral instance base addresses */ +/** Peripheral PMC base address */ +#define PMC_BASE (0x4007D000u) +/** Peripheral PMC base pointer */ +#define PMC ((PMC_Type *)PMC_BASE) + +/** + * @} + */ /* end of group PMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PORT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer + * @{ + */ + +/** PORT - Register Layout Typedef */ +typedef struct { + __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ + __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ + __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ + uint8_t RESERVED_0[24]; + __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ + uint8_t RESERVED_1[28]; + __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ + __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ + __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ +} PORT_Type; + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/* PCR Bit Fields */ +#define PORT_PCR_PS_MASK 0x1u +#define PORT_PCR_PS_SHIFT 0 +#define PORT_PCR_PE_MASK 0x2u +#define PORT_PCR_PE_SHIFT 1 +#define PORT_PCR_SRE_MASK 0x4u +#define PORT_PCR_SRE_SHIFT 2 +#define PORT_PCR_PFE_MASK 0x10u +#define PORT_PCR_PFE_SHIFT 4 +#define PORT_PCR_ODE_MASK 0x20u +#define PORT_PCR_ODE_SHIFT 5 +#define PORT_PCR_DSE_MASK 0x40u +#define PORT_PCR_DSE_SHIFT 6 +#define PORT_PCR_MUX_MASK 0x700u +#define PORT_PCR_MUX_SHIFT 8 +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK) +#define PORT_PCR_LK_MASK 0x8000u +#define PORT_PCR_LK_SHIFT 15 +#define PORT_PCR_IRQC_MASK 0xF0000u +#define PORT_PCR_IRQC_SHIFT 16 +#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK) +#define PORT_PCR_ISF_MASK 0x1000000u +#define PORT_PCR_ISF_SHIFT 24 +/* GPCLR Bit Fields */ +#define PORT_GPCLR_GPWD_MASK 0xFFFFu +#define PORT_GPCLR_GPWD_SHIFT 0 +#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK) +#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u +#define PORT_GPCLR_GPWE_SHIFT 16 +#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK) +/* GPCHR Bit Fields */ +#define PORT_GPCHR_GPWD_MASK 0xFFFFu +#define PORT_GPCHR_GPWD_SHIFT 0 +#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK) +#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u +#define PORT_GPCHR_GPWE_SHIFT 16 +#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK) +/* ISFR Bit Fields */ +#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu +#define PORT_ISFR_ISF_SHIFT 0 +#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK) +/* DFER Bit Fields */ +#define PORT_DFER_DFE_MASK 0xFFFFFFFFu +#define PORT_DFER_DFE_SHIFT 0 +#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK) +/* DFCR Bit Fields */ +#define PORT_DFCR_CS_MASK 0x1u +#define PORT_DFCR_CS_SHIFT 0 +/* DFWR Bit Fields */ +#define PORT_DFWR_FILT_MASK 0x1Fu +#define PORT_DFWR_FILT_SHIFT 0 +#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK) + +/** + * @} + */ /* end of group PORT_Register_Masks */ + + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORTA base address */ +#define PORTA_BASE (0x40049000u) +/** Peripheral PORTA base pointer */ +#define PORTA ((PORT_Type *)PORTA_BASE) +/** Peripheral PORTB base address */ +#define PORTB_BASE (0x4004A000u) +/** Peripheral PORTB base pointer */ +#define PORTB ((PORT_Type *)PORTB_BASE) +/** Peripheral PORTC base address */ +#define PORTC_BASE (0x4004B000u) +/** Peripheral PORTC base pointer */ +#define PORTC ((PORT_Type *)PORTC_BASE) +/** Peripheral PORTD base address */ +#define PORTD_BASE (0x4004C000u) +/** Peripheral PORTD base pointer */ +#define PORTD ((PORT_Type *)PORTD_BASE) +/** Peripheral PORTE base address */ +#define PORTE_BASE (0x4004D000u) +/** Peripheral PORTE base pointer */ +#define PORTE ((PORT_Type *)PORTE_BASE) + +/** + * @} + */ /* end of group PORT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer + * @{ + */ + +/** RCM - Register Layout Typedef */ +typedef struct { + __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ + __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ + uint8_t RESERVED_0[2]; + __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */ + __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */ + uint8_t RESERVED_1[1]; + __I uint8_t MR; /**< Mode Register, offset: 0x7 */ +} RCM_Type; + +/* ---------------------------------------------------------------------------- + -- RCM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RCM_Register_Masks RCM Register Masks + * @{ + */ + +/* SRS0 Bit Fields */ +#define RCM_SRS0_WAKEUP_MASK 0x1u +#define RCM_SRS0_WAKEUP_SHIFT 0 +#define RCM_SRS0_LVD_MASK 0x2u +#define RCM_SRS0_LVD_SHIFT 1 +#define RCM_SRS0_LOC_MASK 0x4u +#define RCM_SRS0_LOC_SHIFT 2 +#define RCM_SRS0_LOL_MASK 0x8u +#define RCM_SRS0_LOL_SHIFT 3 +#define RCM_SRS0_WDOG_MASK 0x20u +#define RCM_SRS0_WDOG_SHIFT 5 +#define RCM_SRS0_PIN_MASK 0x40u +#define RCM_SRS0_PIN_SHIFT 6 +#define RCM_SRS0_POR_MASK 0x80u +#define RCM_SRS0_POR_SHIFT 7 +/* SRS1 Bit Fields */ +#define RCM_SRS1_JTAG_MASK 0x1u +#define RCM_SRS1_JTAG_SHIFT 0 +#define RCM_SRS1_LOCKUP_MASK 0x2u +#define RCM_SRS1_LOCKUP_SHIFT 1 +#define RCM_SRS1_SW_MASK 0x4u +#define RCM_SRS1_SW_SHIFT 2 +#define RCM_SRS1_MDM_AP_MASK 0x8u +#define RCM_SRS1_MDM_AP_SHIFT 3 +#define RCM_SRS1_EZPT_MASK 0x10u +#define RCM_SRS1_EZPT_SHIFT 4 +#define RCM_SRS1_SACKERR_MASK 0x20u +#define RCM_SRS1_SACKERR_SHIFT 5 +/* RPFC Bit Fields */ +#define RCM_RPFC_RSTFLTSRW_MASK 0x3u +#define RCM_RPFC_RSTFLTSRW_SHIFT 0 +#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK) +#define RCM_RPFC_RSTFLTSS_MASK 0x4u +#define RCM_RPFC_RSTFLTSS_SHIFT 2 +/* RPFW Bit Fields */ +#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu +#define RCM_RPFW_RSTFLTSEL_SHIFT 0 +#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK) +/* MR Bit Fields */ +#define RCM_MR_EZP_MS_MASK 0x2u +#define RCM_MR_EZP_MS_SHIFT 1 + +/** + * @} + */ /* end of group RCM_Register_Masks */ + + +/* RCM - Peripheral instance base addresses */ +/** Peripheral RCM base address */ +#define RCM_BASE (0x4007F000u) +/** Peripheral RCM base pointer */ +#define RCM ((RCM_Type *)RCM_BASE) + +/** + * @} + */ /* end of group RCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RFSYS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer + * @{ + */ + +/** RFSYS - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ +} RFSYS_Type; + +/* ---------------------------------------------------------------------------- + -- RFSYS Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RFSYS_Register_Masks RFSYS Register Masks + * @{ + */ + +/* REG Bit Fields */ +#define RFSYS_REG_LL_MASK 0xFFu +#define RFSYS_REG_LL_SHIFT 0 +#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK) +#define RFSYS_REG_LH_MASK 0xFF00u +#define RFSYS_REG_LH_SHIFT 8 +#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK) +#define RFSYS_REG_HL_MASK 0xFF0000u +#define RFSYS_REG_HL_SHIFT 16 +#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK) +#define RFSYS_REG_HH_MASK 0xFF000000u +#define RFSYS_REG_HH_SHIFT 24 +#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK) + +/** + * @} + */ /* end of group RFSYS_Register_Masks */ + + +/* RFSYS - Peripheral instance base addresses */ +/** Peripheral RFSYS base address */ +#define RFSYS_BASE (0x40041000u) +/** Peripheral RFSYS base pointer */ +#define RFSYS ((RFSYS_Type *)RFSYS_BASE) + +/** + * @} + */ /* end of group RFSYS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RFVBAT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer + * @{ + */ + +/** RFVBAT - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */ +} RFVBAT_Type; + +/* ---------------------------------------------------------------------------- + -- RFVBAT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks + * @{ + */ + +/* REG Bit Fields */ +#define RFVBAT_REG_LL_MASK 0xFFu +#define RFVBAT_REG_LL_SHIFT 0 +#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK) +#define RFVBAT_REG_LH_MASK 0xFF00u +#define RFVBAT_REG_LH_SHIFT 8 +#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK) +#define RFVBAT_REG_HL_MASK 0xFF0000u +#define RFVBAT_REG_HL_SHIFT 16 +#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK) +#define RFVBAT_REG_HH_MASK 0xFF000000u +#define RFVBAT_REG_HH_SHIFT 24 +#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK) + +/** + * @} + */ /* end of group RFVBAT_Register_Masks */ + + +/* RFVBAT - Peripheral instance base addresses */ +/** Peripheral RFVBAT base address */ +#define RFVBAT_BASE (0x4003E000u) +/** Peripheral RFVBAT base pointer */ +#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE) + +/** + * @} + */ /* end of group RFVBAT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ + __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ + __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ + __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ + __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ + __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ + __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ + __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ + uint8_t RESERVED_0[2016]; + __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ + __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/* TSR Bit Fields */ +#define RTC_TSR_TSR_MASK 0xFFFFFFFFu +#define RTC_TSR_TSR_SHIFT 0 +#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK) +/* TPR Bit Fields */ +#define RTC_TPR_TPR_MASK 0xFFFFu +#define RTC_TPR_TPR_SHIFT 0 +#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK) +/* TAR Bit Fields */ +#define RTC_TAR_TAR_MASK 0xFFFFFFFFu +#define RTC_TAR_TAR_SHIFT 0 +#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK) +/* TCR Bit Fields */ +#define RTC_TCR_TCR_MASK 0xFFu +#define RTC_TCR_TCR_SHIFT 0 +#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK) +#define RTC_TCR_CIR_MASK 0xFF00u +#define RTC_TCR_CIR_SHIFT 8 +#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK) +#define RTC_TCR_TCV_MASK 0xFF0000u +#define RTC_TCR_TCV_SHIFT 16 +#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK) +#define RTC_TCR_CIC_MASK 0xFF000000u +#define RTC_TCR_CIC_SHIFT 24 +#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK) +/* CR Bit Fields */ +#define RTC_CR_SWR_MASK 0x1u +#define RTC_CR_SWR_SHIFT 0 +#define RTC_CR_WPE_MASK 0x2u +#define RTC_CR_WPE_SHIFT 1 +#define RTC_CR_SUP_MASK 0x4u +#define RTC_CR_SUP_SHIFT 2 +#define RTC_CR_UM_MASK 0x8u +#define RTC_CR_UM_SHIFT 3 +#define RTC_CR_OSCE_MASK 0x100u +#define RTC_CR_OSCE_SHIFT 8 +#define RTC_CR_CLKO_MASK 0x200u +#define RTC_CR_CLKO_SHIFT 9 +#define RTC_CR_SC16P_MASK 0x400u +#define RTC_CR_SC16P_SHIFT 10 +#define RTC_CR_SC8P_MASK 0x800u +#define RTC_CR_SC8P_SHIFT 11 +#define RTC_CR_SC4P_MASK 0x1000u +#define RTC_CR_SC4P_SHIFT 12 +#define RTC_CR_SC2P_MASK 0x2000u +#define RTC_CR_SC2P_SHIFT 13 +/* SR Bit Fields */ +#define RTC_SR_TIF_MASK 0x1u +#define RTC_SR_TIF_SHIFT 0 +#define RTC_SR_TOF_MASK 0x2u +#define RTC_SR_TOF_SHIFT 1 +#define RTC_SR_TAF_MASK 0x4u +#define RTC_SR_TAF_SHIFT 2 +#define RTC_SR_TCE_MASK 0x10u +#define RTC_SR_TCE_SHIFT 4 +/* LR Bit Fields */ +#define RTC_LR_TCL_MASK 0x8u +#define RTC_LR_TCL_SHIFT 3 +#define RTC_LR_CRL_MASK 0x10u +#define RTC_LR_CRL_SHIFT 4 +#define RTC_LR_SRL_MASK 0x20u +#define RTC_LR_SRL_SHIFT 5 +#define RTC_LR_LRL_MASK 0x40u +#define RTC_LR_LRL_SHIFT 6 +/* IER Bit Fields */ +#define RTC_IER_TIIE_MASK 0x1u +#define RTC_IER_TIIE_SHIFT 0 +#define RTC_IER_TOIE_MASK 0x2u +#define RTC_IER_TOIE_SHIFT 1 +#define RTC_IER_TAIE_MASK 0x4u +#define RTC_IER_TAIE_SHIFT 2 +#define RTC_IER_TSIE_MASK 0x10u +#define RTC_IER_TSIE_SHIFT 4 +/* WAR Bit Fields */ +#define RTC_WAR_TSRW_MASK 0x1u +#define RTC_WAR_TSRW_SHIFT 0 +#define RTC_WAR_TPRW_MASK 0x2u +#define RTC_WAR_TPRW_SHIFT 1 +#define RTC_WAR_TARW_MASK 0x4u +#define RTC_WAR_TARW_SHIFT 2 +#define RTC_WAR_TCRW_MASK 0x8u +#define RTC_WAR_TCRW_SHIFT 3 +#define RTC_WAR_CRW_MASK 0x10u +#define RTC_WAR_CRW_SHIFT 4 +#define RTC_WAR_SRW_MASK 0x20u +#define RTC_WAR_SRW_SHIFT 5 +#define RTC_WAR_LRW_MASK 0x40u +#define RTC_WAR_LRW_SHIFT 6 +#define RTC_WAR_IERW_MASK 0x80u +#define RTC_WAR_IERW_SHIFT 7 +/* RAR Bit Fields */ +#define RTC_RAR_TSRR_MASK 0x1u +#define RTC_RAR_TSRR_SHIFT 0 +#define RTC_RAR_TPRR_MASK 0x2u +#define RTC_RAR_TPRR_SHIFT 1 +#define RTC_RAR_TARR_MASK 0x4u +#define RTC_RAR_TARR_SHIFT 2 +#define RTC_RAR_TCRR_MASK 0x8u +#define RTC_RAR_TCRR_SHIFT 3 +#define RTC_RAR_CRR_MASK 0x10u +#define RTC_RAR_CRR_SHIFT 4 +#define RTC_RAR_SRR_MASK 0x20u +#define RTC_RAR_SRR_SHIFT 5 +#define RTC_RAR_LRR_MASK 0x40u +#define RTC_RAR_LRR_SHIFT 6 +#define RTC_RAR_IERR_MASK 0x80u +#define RTC_RAR_IERR_SHIFT 7 + +/** + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC base address */ +#define RTC_BASE (0x4003D000u) +/** Peripheral RTC base pointer */ +#define RTC ((RTC_Type *)RTC_BASE) + +/** + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer + * @{ + */ + +/** SIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ + __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ + uint8_t RESERVED_0[4092]; + __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ + __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ + uint8_t RESERVED_3[8]; + __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ + __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ + __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ + __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ + __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ + __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */ + __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ + __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ + __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */ + __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ + __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ + __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ +} SIM_Type; + +/* ---------------------------------------------------------------------------- + -- SIM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SIM_Register_Masks SIM Register Masks + * @{ + */ + +/* SOPT1 Bit Fields */ +#define SIM_SOPT1_RAMSIZE_MASK 0xF000u +#define SIM_SOPT1_RAMSIZE_SHIFT 12 +#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK) +#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 +#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK) +#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u +#define SIM_SOPT1_USBVSTBY_SHIFT 29 +#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u +#define SIM_SOPT1_USBSSTBY_SHIFT 30 +#define SIM_SOPT1_USBREGEN_MASK 0x80000000u +#define SIM_SOPT1_USBREGEN_SHIFT 31 +/* SOPT1CFG Bit Fields */ +#define SIM_SOPT1CFG_URWE_MASK 0x1000000u +#define SIM_SOPT1CFG_URWE_SHIFT 24 +#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u +#define SIM_SOPT1CFG_UVSWE_SHIFT 25 +#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u +#define SIM_SOPT1CFG_USSWE_SHIFT 26 +/* SOPT2 Bit Fields */ +#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u +#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4 +#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 +#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK) +#define SIM_SOPT2_PTD7PAD_MASK 0x800u +#define SIM_SOPT2_PTD7PAD_SHIFT 11 +#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u +#define SIM_SOPT2_TRACECLKSEL_SHIFT 12 +#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u +#define SIM_SOPT2_PLLFLLSEL_SHIFT 16 +#define SIM_SOPT2_USBSRC_MASK 0x40000u +#define SIM_SOPT2_USBSRC_SHIFT 18 +/* SOPT4 Bit Fields */ +#define SIM_SOPT4_FTM0FLT0_MASK 0x1u +#define SIM_SOPT4_FTM0FLT0_SHIFT 0 +#define SIM_SOPT4_FTM0FLT1_MASK 0x2u +#define SIM_SOPT4_FTM0FLT1_SHIFT 1 +#define SIM_SOPT4_FTM1FLT0_MASK 0x10u +#define SIM_SOPT4_FTM1FLT0_SHIFT 4 +#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u +#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18 +#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK) +#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u +#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24 +#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u +#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25 +#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u +#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28 +/* SOPT5 Bit Fields */ +#define SIM_SOPT5_UART0TXSRC_MASK 0x1u +#define SIM_SOPT5_UART0TXSRC_SHIFT 0 +#define SIM_SOPT5_UART0RXSRC_MASK 0xCu +#define SIM_SOPT5_UART0RXSRC_SHIFT 2 +#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK) +#define SIM_SOPT5_UART1TXSRC_MASK 0x10u +#define SIM_SOPT5_UART1TXSRC_SHIFT 4 +#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u +#define SIM_SOPT5_UART1RXSRC_SHIFT 6 +#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK) +/* SOPT7 Bit Fields */ +#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu +#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 +#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK) +#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u +#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4 +#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u +#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7 +/* SDID Bit Fields */ +#define SIM_SDID_PINID_MASK 0xFu +#define SIM_SDID_PINID_SHIFT 0 +#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK) +#define SIM_SDID_FAMID_MASK 0x70u +#define SIM_SDID_FAMID_SHIFT 4 +#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK) +#define SIM_SDID_REVID_MASK 0xF000u +#define SIM_SDID_REVID_SHIFT 12 +#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK) +/* SCGC4 Bit Fields */ +#define SIM_SCGC4_EWM_MASK 0x2u +#define SIM_SCGC4_EWM_SHIFT 1 +#define SIM_SCGC4_CMT_MASK 0x4u +#define SIM_SCGC4_CMT_SHIFT 2 +#define SIM_SCGC4_I2C0_MASK 0x40u +#define SIM_SCGC4_I2C0_SHIFT 6 +#define SIM_SCGC4_UART0_MASK 0x400u +#define SIM_SCGC4_UART0_SHIFT 10 +#define SIM_SCGC4_UART1_MASK 0x800u +#define SIM_SCGC4_UART1_SHIFT 11 +#define SIM_SCGC4_UART2_MASK 0x1000u +#define SIM_SCGC4_UART2_SHIFT 12 +#define SIM_SCGC4_USBOTG_MASK 0x40000u +#define SIM_SCGC4_USBOTG_SHIFT 18 +#define SIM_SCGC4_CMP_MASK 0x80000u +#define SIM_SCGC4_CMP_SHIFT 19 +#define SIM_SCGC4_VREF_MASK 0x100000u +#define SIM_SCGC4_VREF_SHIFT 20 +/* SCGC5 Bit Fields */ +#define SIM_SCGC5_LPTIMER_MASK 0x1u +#define SIM_SCGC5_LPTIMER_SHIFT 0 +#define SIM_SCGC5_TSI_MASK 0x20u +#define SIM_SCGC5_TSI_SHIFT 5 +#define SIM_SCGC5_PORTA_MASK 0x200u +#define SIM_SCGC5_PORTA_SHIFT 9 +#define SIM_SCGC5_PORTB_MASK 0x400u +#define SIM_SCGC5_PORTB_SHIFT 10 +#define SIM_SCGC5_PORTC_MASK 0x800u +#define SIM_SCGC5_PORTC_SHIFT 11 +#define SIM_SCGC5_PORTD_MASK 0x1000u +#define SIM_SCGC5_PORTD_SHIFT 12 +#define SIM_SCGC5_PORTE_MASK 0x2000u +#define SIM_SCGC5_PORTE_SHIFT 13 +/* SCGC6 Bit Fields */ +#define SIM_SCGC6_FTFL_MASK 0x1u +#define SIM_SCGC6_FTFL_SHIFT 0 +#define SIM_SCGC6_DMAMUX_MASK 0x2u +#define SIM_SCGC6_DMAMUX_SHIFT 1 +#define SIM_SCGC6_SPI0_MASK 0x1000u +#define SIM_SCGC6_SPI0_SHIFT 12 +#define SIM_SCGC6_I2S_MASK 0x8000u +#define SIM_SCGC6_I2S_SHIFT 15 +#define SIM_SCGC6_CRC_MASK 0x40000u +#define SIM_SCGC6_CRC_SHIFT 18 +#define SIM_SCGC6_USBDCD_MASK 0x200000u +#define SIM_SCGC6_USBDCD_SHIFT 21 +#define SIM_SCGC6_PDB_MASK 0x400000u +#define SIM_SCGC6_PDB_SHIFT 22 +#define SIM_SCGC6_PIT_MASK 0x800000u +#define SIM_SCGC6_PIT_SHIFT 23 +#define SIM_SCGC6_FTM0_MASK 0x1000000u +#define SIM_SCGC6_FTM0_SHIFT 24 +#define SIM_SCGC6_FTM1_MASK 0x2000000u +#define SIM_SCGC6_FTM1_SHIFT 25 +#define SIM_SCGC6_ADC0_MASK 0x8000000u +#define SIM_SCGC6_ADC0_SHIFT 27 +#define SIM_SCGC6_RTC_MASK 0x20000000u +#define SIM_SCGC6_RTC_SHIFT 29 +/* SCGC7 Bit Fields */ +#define SIM_SCGC7_DMA_MASK 0x2u +#define SIM_SCGC7_DMA_SHIFT 1 +/* CLKDIV1 Bit Fields */ +#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 +#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK) +#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u +#define SIM_CLKDIV1_OUTDIV2_SHIFT 24 +#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK) +#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 +#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK) +/* CLKDIV2 Bit Fields */ +#define SIM_CLKDIV2_USBFRAC_MASK 0x1u +#define SIM_CLKDIV2_USBFRAC_SHIFT 0 +#define SIM_CLKDIV2_USBDIV_MASK 0xEu +#define SIM_CLKDIV2_USBDIV_SHIFT 1 +#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK) +/* FCFG1 Bit Fields */ +#define SIM_FCFG1_FLASHDIS_MASK 0x1u +#define SIM_FCFG1_FLASHDIS_SHIFT 0 +#define SIM_FCFG1_FLASHDOZE_MASK 0x2u +#define SIM_FCFG1_FLASHDOZE_SHIFT 1 +#define SIM_FCFG1_DEPART_MASK 0xF00u +#define SIM_FCFG1_DEPART_SHIFT 8 +#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK) +#define SIM_FCFG1_EESIZE_MASK 0xF0000u +#define SIM_FCFG1_EESIZE_SHIFT 16 +#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK) +#define SIM_FCFG1_PFSIZE_MASK 0xF000000u +#define SIM_FCFG1_PFSIZE_SHIFT 24 +#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK) +#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u +#define SIM_FCFG1_NVMSIZE_SHIFT 28 +#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK) +/* FCFG2 Bit Fields */ +#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u +#define SIM_FCFG2_MAXADDR1_SHIFT 16 +#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK) +#define SIM_FCFG2_PFLSH_MASK 0x800000u +#define SIM_FCFG2_PFLSH_SHIFT 23 +#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u +#define SIM_FCFG2_MAXADDR0_SHIFT 24 +#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK) +/* UIDH Bit Fields */ +#define SIM_UIDH_UID_MASK 0xFFFFFFFFu +#define SIM_UIDH_UID_SHIFT 0 +#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK) +/* UIDMH Bit Fields */ +#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu +#define SIM_UIDMH_UID_SHIFT 0 +#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK) +/* UIDML Bit Fields */ +#define SIM_UIDML_UID_MASK 0xFFFFFFFFu +#define SIM_UIDML_UID_SHIFT 0 +#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK) +/* UIDL Bit Fields */ +#define SIM_UIDL_UID_MASK 0xFFFFFFFFu +#define SIM_UIDL_UID_SHIFT 0 +#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK) + +/** + * @} + */ /* end of group SIM_Register_Masks */ + + +/* SIM - Peripheral instance base addresses */ +/** Peripheral SIM base address */ +#define SIM_BASE (0x40047000u) +/** Peripheral SIM base pointer */ +#define SIM ((SIM_Type *)SIM_BASE) + +/** + * @} + */ /* end of group SIM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer + * @{ + */ + +/** SMC - Register Layout Typedef */ +typedef struct { + __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */ + __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */ + __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */ + __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */ +} SMC_Type; + +/* ---------------------------------------------------------------------------- + -- SMC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SMC_Register_Masks SMC Register Masks + * @{ + */ + +/* PMPROT Bit Fields */ +#define SMC_PMPROT_AVLLS_MASK 0x2u +#define SMC_PMPROT_AVLLS_SHIFT 1 +#define SMC_PMPROT_ALLS_MASK 0x8u +#define SMC_PMPROT_ALLS_SHIFT 3 +#define SMC_PMPROT_AVLP_MASK 0x20u +#define SMC_PMPROT_AVLP_SHIFT 5 +/* PMCTRL Bit Fields */ +#define SMC_PMCTRL_STOPM_MASK 0x7u +#define SMC_PMCTRL_STOPM_SHIFT 0 +#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK) +#define SMC_PMCTRL_STOPA_MASK 0x8u +#define SMC_PMCTRL_STOPA_SHIFT 3 +#define SMC_PMCTRL_RUNM_MASK 0x60u +#define SMC_PMCTRL_RUNM_SHIFT 5 +#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK) +#define SMC_PMCTRL_LPWUI_MASK 0x80u +#define SMC_PMCTRL_LPWUI_SHIFT 7 +/* VLLSCTRL Bit Fields */ +#define SMC_VLLSCTRL_VLLSM_MASK 0x7u +#define SMC_VLLSCTRL_VLLSM_SHIFT 0 +#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK) +#define SMC_VLLSCTRL_PORPO_MASK 0x20u +#define SMC_VLLSCTRL_PORPO_SHIFT 5 +/* PMSTAT Bit Fields */ +#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu +#define SMC_PMSTAT_PMSTAT_SHIFT 0 +#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK) + +/** + * @} + */ /* end of group SMC_Register_Masks */ + + +/* SMC - Peripheral instance base addresses */ +/** Peripheral SMC base address */ +#define SMC_BASE (0x4007E000u) +/** Peripheral SMC base pointer */ +#define SMC ((SMC_Type *)SMC_BASE) + +/** + * @} + */ /* end of group SMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */ + union { /* offset: 0xC */ + __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ + __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ + }; + uint8_t RESERVED_1[24]; + __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */ + __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ + union { /* offset: 0x34 */ + __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */ + __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ + }; + __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */ + __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */ + __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */ + __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */ + __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */ + uint8_t RESERVED_2[48]; + __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */ + __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */ + __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */ + __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define SPI_MCR_HALT_MASK 0x1u +#define SPI_MCR_HALT_SHIFT 0 +#define SPI_MCR_SMPL_PT_MASK 0x300u +#define SPI_MCR_SMPL_PT_SHIFT 8 +#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK) +#define SPI_MCR_CLR_RXF_MASK 0x400u +#define SPI_MCR_CLR_RXF_SHIFT 10 +#define SPI_MCR_CLR_TXF_MASK 0x800u +#define SPI_MCR_CLR_TXF_SHIFT 11 +#define SPI_MCR_DIS_RXF_MASK 0x1000u +#define SPI_MCR_DIS_RXF_SHIFT 12 +#define SPI_MCR_DIS_TXF_MASK 0x2000u +#define SPI_MCR_DIS_TXF_SHIFT 13 +#define SPI_MCR_MDIS_MASK 0x4000u +#define SPI_MCR_MDIS_SHIFT 14 +#define SPI_MCR_DOZE_MASK 0x8000u +#define SPI_MCR_DOZE_SHIFT 15 +#define SPI_MCR_PCSIS_MASK 0x3F0000u +#define SPI_MCR_PCSIS_SHIFT 16 +#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK) +#define SPI_MCR_ROOE_MASK 0x1000000u +#define SPI_MCR_ROOE_SHIFT 24 +#define SPI_MCR_PCSSE_MASK 0x2000000u +#define SPI_MCR_PCSSE_SHIFT 25 +#define SPI_MCR_MTFE_MASK 0x4000000u +#define SPI_MCR_MTFE_SHIFT 26 +#define SPI_MCR_FRZ_MASK 0x8000000u +#define SPI_MCR_FRZ_SHIFT 27 +#define SPI_MCR_DCONF_MASK 0x30000000u +#define SPI_MCR_DCONF_SHIFT 28 +#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK) +#define SPI_MCR_CONT_SCKE_MASK 0x40000000u +#define SPI_MCR_CONT_SCKE_SHIFT 30 +#define SPI_MCR_MSTR_MASK 0x80000000u +#define SPI_MCR_MSTR_SHIFT 31 +/* TCR Bit Fields */ +#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u +#define SPI_TCR_SPI_TCNT_SHIFT 16 +#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK) +/* CTAR Bit Fields */ +#define SPI_CTAR_BR_MASK 0xFu +#define SPI_CTAR_BR_SHIFT 0 +#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK) +#define SPI_CTAR_DT_MASK 0xF0u +#define SPI_CTAR_DT_SHIFT 4 +#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK) +#define SPI_CTAR_ASC_MASK 0xF00u +#define SPI_CTAR_ASC_SHIFT 8 +#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK) +#define SPI_CTAR_CSSCK_MASK 0xF000u +#define SPI_CTAR_CSSCK_SHIFT 12 +#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK) +#define SPI_CTAR_PBR_MASK 0x30000u +#define SPI_CTAR_PBR_SHIFT 16 +#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK) +#define SPI_CTAR_PDT_MASK 0xC0000u +#define SPI_CTAR_PDT_SHIFT 18 +#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK) +#define SPI_CTAR_PASC_MASK 0x300000u +#define SPI_CTAR_PASC_SHIFT 20 +#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK) +#define SPI_CTAR_PCSSCK_MASK 0xC00000u +#define SPI_CTAR_PCSSCK_SHIFT 22 +#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK) +#define SPI_CTAR_LSBFE_MASK 0x1000000u +#define SPI_CTAR_LSBFE_SHIFT 24 +#define SPI_CTAR_CPHA_MASK 0x2000000u +#define SPI_CTAR_CPHA_SHIFT 25 +#define SPI_CTAR_CPOL_MASK 0x4000000u +#define SPI_CTAR_CPOL_SHIFT 26 +#define SPI_CTAR_FMSZ_MASK 0x78000000u +#define SPI_CTAR_FMSZ_SHIFT 27 +#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK) +#define SPI_CTAR_DBR_MASK 0x80000000u +#define SPI_CTAR_DBR_SHIFT 31 +/* CTAR_SLAVE Bit Fields */ +#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u +#define SPI_CTAR_SLAVE_CPHA_SHIFT 25 +#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u +#define SPI_CTAR_SLAVE_CPOL_SHIFT 26 +#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u +#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27 +#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK) +/* SR Bit Fields */ +#define SPI_SR_POPNXTPTR_MASK 0xFu +#define SPI_SR_POPNXTPTR_SHIFT 0 +#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK) +#define SPI_SR_RXCTR_MASK 0xF0u +#define SPI_SR_RXCTR_SHIFT 4 +#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK) +#define SPI_SR_TXNXTPTR_MASK 0xF00u +#define SPI_SR_TXNXTPTR_SHIFT 8 +#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK) +#define SPI_SR_TXCTR_MASK 0xF000u +#define SPI_SR_TXCTR_SHIFT 12 +#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK) +#define SPI_SR_RFDF_MASK 0x20000u +#define SPI_SR_RFDF_SHIFT 17 +#define SPI_SR_RFOF_MASK 0x80000u +#define SPI_SR_RFOF_SHIFT 19 +#define SPI_SR_TFFF_MASK 0x2000000u +#define SPI_SR_TFFF_SHIFT 25 +#define SPI_SR_TFUF_MASK 0x8000000u +#define SPI_SR_TFUF_SHIFT 27 +#define SPI_SR_EOQF_MASK 0x10000000u +#define SPI_SR_EOQF_SHIFT 28 +#define SPI_SR_TXRXS_MASK 0x40000000u +#define SPI_SR_TXRXS_SHIFT 30 +#define SPI_SR_TCF_MASK 0x80000000u +#define SPI_SR_TCF_SHIFT 31 +/* RSER Bit Fields */ +#define SPI_RSER_RFDF_DIRS_MASK 0x10000u +#define SPI_RSER_RFDF_DIRS_SHIFT 16 +#define SPI_RSER_RFDF_RE_MASK 0x20000u +#define SPI_RSER_RFDF_RE_SHIFT 17 +#define SPI_RSER_RFOF_RE_MASK 0x80000u +#define SPI_RSER_RFOF_RE_SHIFT 19 +#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u +#define SPI_RSER_TFFF_DIRS_SHIFT 24 +#define SPI_RSER_TFFF_RE_MASK 0x2000000u +#define SPI_RSER_TFFF_RE_SHIFT 25 +#define SPI_RSER_TFUF_RE_MASK 0x8000000u +#define SPI_RSER_TFUF_RE_SHIFT 27 +#define SPI_RSER_EOQF_RE_MASK 0x10000000u +#define SPI_RSER_EOQF_RE_SHIFT 28 +#define SPI_RSER_TCF_RE_MASK 0x80000000u +#define SPI_RSER_TCF_RE_SHIFT 31 +/* PUSHR Bit Fields */ +#define SPI_PUSHR_TXDATA_MASK 0xFFFFu +#define SPI_PUSHR_TXDATA_SHIFT 0 +#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK) +#define SPI_PUSHR_PCS_MASK 0x3F0000u +#define SPI_PUSHR_PCS_SHIFT 16 +#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK) +#define SPI_PUSHR_CTCNT_MASK 0x4000000u +#define SPI_PUSHR_CTCNT_SHIFT 26 +#define SPI_PUSHR_EOQ_MASK 0x8000000u +#define SPI_PUSHR_EOQ_SHIFT 27 +#define SPI_PUSHR_CTAS_MASK 0x70000000u +#define SPI_PUSHR_CTAS_SHIFT 28 +#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK) +#define SPI_PUSHR_CONT_MASK 0x80000000u +#define SPI_PUSHR_CONT_SHIFT 31 +/* PUSHR_SLAVE Bit Fields */ +#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu +#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0 +#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK) +/* POPR Bit Fields */ +#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu +#define SPI_POPR_RXDATA_SHIFT 0 +#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK) +/* TXFR0 Bit Fields */ +#define SPI_TXFR0_TXDATA_MASK 0xFFFFu +#define SPI_TXFR0_TXDATA_SHIFT 0 +#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK) +#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u +#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16 +#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK) +/* TXFR1 Bit Fields */ +#define SPI_TXFR1_TXDATA_MASK 0xFFFFu +#define SPI_TXFR1_TXDATA_SHIFT 0 +#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK) +#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u +#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16 +#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK) +/* TXFR2 Bit Fields */ +#define SPI_TXFR2_TXDATA_MASK 0xFFFFu +#define SPI_TXFR2_TXDATA_SHIFT 0 +#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK) +#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u +#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16 +#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK) +/* TXFR3 Bit Fields */ +#define SPI_TXFR3_TXDATA_MASK 0xFFFFu +#define SPI_TXFR3_TXDATA_SHIFT 0 +#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK) +#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u +#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16 +#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK) +/* RXFR0 Bit Fields */ +#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu +#define SPI_RXFR0_RXDATA_SHIFT 0 +#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK) +/* RXFR1 Bit Fields */ +#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu +#define SPI_RXFR1_RXDATA_SHIFT 0 +#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK) +/* RXFR2 Bit Fields */ +#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu +#define SPI_RXFR2_RXDATA_SHIFT 0 +#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK) +/* RXFR3 Bit Fields */ +#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu +#define SPI_RXFR3_RXDATA_SHIFT 0 +#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK) + +/** + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +/** Peripheral SPI0 base address */ +#define SPI0_BASE (0x4002C000u) +/** Peripheral SPI0 base pointer */ +#define SPI0 ((SPI_Type *)SPI0_BASE) + +/** + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TSI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer + * @{ + */ + +/** TSI - Register Layout Typedef */ +typedef struct { + __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */ + __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */ + __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */ + __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */ + uint8_t RESERVED_0[240]; + __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */ + __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */ + __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */ + __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */ + __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */ + __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */ + __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */ + __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */ + __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */ +} TSI_Type; + +/* ---------------------------------------------------------------------------- + -- TSI Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup TSI_Register_Masks TSI Register Masks + * @{ + */ + +/* GENCS Bit Fields */ +#define TSI_GENCS_STPE_MASK 0x1u +#define TSI_GENCS_STPE_SHIFT 0 +#define TSI_GENCS_STM_MASK 0x2u +#define TSI_GENCS_STM_SHIFT 1 +#define TSI_GENCS_ESOR_MASK 0x10u +#define TSI_GENCS_ESOR_SHIFT 4 +#define TSI_GENCS_ERIE_MASK 0x20u +#define TSI_GENCS_ERIE_SHIFT 5 +#define TSI_GENCS_TSIIE_MASK 0x40u +#define TSI_GENCS_TSIIE_SHIFT 6 +#define TSI_GENCS_TSIEN_MASK 0x80u +#define TSI_GENCS_TSIEN_SHIFT 7 +#define TSI_GENCS_SWTS_MASK 0x100u +#define TSI_GENCS_SWTS_SHIFT 8 +#define TSI_GENCS_SCNIP_MASK 0x200u +#define TSI_GENCS_SCNIP_SHIFT 9 +#define TSI_GENCS_OVRF_MASK 0x1000u +#define TSI_GENCS_OVRF_SHIFT 12 +#define TSI_GENCS_EXTERF_MASK 0x2000u +#define TSI_GENCS_EXTERF_SHIFT 13 +#define TSI_GENCS_OUTRGF_MASK 0x4000u +#define TSI_GENCS_OUTRGF_SHIFT 14 +#define TSI_GENCS_EOSF_MASK 0x8000u +#define TSI_GENCS_EOSF_SHIFT 15 +#define TSI_GENCS_PS_MASK 0x70000u +#define TSI_GENCS_PS_SHIFT 16 +#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK) +#define TSI_GENCS_NSCN_MASK 0xF80000u +#define TSI_GENCS_NSCN_SHIFT 19 +#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK) +#define TSI_GENCS_LPSCNITV_MASK 0xF000000u +#define TSI_GENCS_LPSCNITV_SHIFT 24 +#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK) +#define TSI_GENCS_LPCLKS_MASK 0x10000000u +#define TSI_GENCS_LPCLKS_SHIFT 28 +/* SCANC Bit Fields */ +#define TSI_SCANC_AMPSC_MASK 0x7u +#define TSI_SCANC_AMPSC_SHIFT 0 +#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK) +#define TSI_SCANC_AMCLKS_MASK 0x18u +#define TSI_SCANC_AMCLKS_SHIFT 3 +#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK) +#define TSI_SCANC_SMOD_MASK 0xFF00u +#define TSI_SCANC_SMOD_SHIFT 8 +#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK) +#define TSI_SCANC_EXTCHRG_MASK 0xF0000u +#define TSI_SCANC_EXTCHRG_SHIFT 16 +#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK) +#define TSI_SCANC_REFCHRG_MASK 0xF000000u +#define TSI_SCANC_REFCHRG_SHIFT 24 +#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK) +/* PEN Bit Fields */ +#define TSI_PEN_PEN0_MASK 0x1u +#define TSI_PEN_PEN0_SHIFT 0 +#define TSI_PEN_PEN1_MASK 0x2u +#define TSI_PEN_PEN1_SHIFT 1 +#define TSI_PEN_PEN2_MASK 0x4u +#define TSI_PEN_PEN2_SHIFT 2 +#define TSI_PEN_PEN3_MASK 0x8u +#define TSI_PEN_PEN3_SHIFT 3 +#define TSI_PEN_PEN4_MASK 0x10u +#define TSI_PEN_PEN4_SHIFT 4 +#define TSI_PEN_PEN5_MASK 0x20u +#define TSI_PEN_PEN5_SHIFT 5 +#define TSI_PEN_PEN6_MASK 0x40u +#define TSI_PEN_PEN6_SHIFT 6 +#define TSI_PEN_PEN7_MASK 0x80u +#define TSI_PEN_PEN7_SHIFT 7 +#define TSI_PEN_PEN8_MASK 0x100u +#define TSI_PEN_PEN8_SHIFT 8 +#define TSI_PEN_PEN9_MASK 0x200u +#define TSI_PEN_PEN9_SHIFT 9 +#define TSI_PEN_PEN10_MASK 0x400u +#define TSI_PEN_PEN10_SHIFT 10 +#define TSI_PEN_PEN11_MASK 0x800u +#define TSI_PEN_PEN11_SHIFT 11 +#define TSI_PEN_PEN12_MASK 0x1000u +#define TSI_PEN_PEN12_SHIFT 12 +#define TSI_PEN_PEN13_MASK 0x2000u +#define TSI_PEN_PEN13_SHIFT 13 +#define TSI_PEN_PEN14_MASK 0x4000u +#define TSI_PEN_PEN14_SHIFT 14 +#define TSI_PEN_PEN15_MASK 0x8000u +#define TSI_PEN_PEN15_SHIFT 15 +#define TSI_PEN_LPSP_MASK 0xF0000u +#define TSI_PEN_LPSP_SHIFT 16 +#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK) +/* WUCNTR Bit Fields */ +#define TSI_WUCNTR_WUCNT_MASK 0xFFFFu +#define TSI_WUCNTR_WUCNT_SHIFT 0 +#define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK) +/* CNTR1 Bit Fields */ +#define TSI_CNTR1_CTN1_MASK 0xFFFFu +#define TSI_CNTR1_CTN1_SHIFT 0 +#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK) +#define TSI_CNTR1_CTN_MASK 0xFFFF0000u +#define TSI_CNTR1_CTN_SHIFT 16 +#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK) +/* CNTR3 Bit Fields */ +#define TSI_CNTR3_CTN1_MASK 0xFFFFu +#define TSI_CNTR3_CTN1_SHIFT 0 +#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK) +#define TSI_CNTR3_CTN_MASK 0xFFFF0000u +#define TSI_CNTR3_CTN_SHIFT 16 +#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK) +/* CNTR5 Bit Fields */ +#define TSI_CNTR5_CTN1_MASK 0xFFFFu +#define TSI_CNTR5_CTN1_SHIFT 0 +#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK) +#define TSI_CNTR5_CTN_MASK 0xFFFF0000u +#define TSI_CNTR5_CTN_SHIFT 16 +#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK) +/* CNTR7 Bit Fields */ +#define TSI_CNTR7_CTN1_MASK 0xFFFFu +#define TSI_CNTR7_CTN1_SHIFT 0 +#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK) +#define TSI_CNTR7_CTN_MASK 0xFFFF0000u +#define TSI_CNTR7_CTN_SHIFT 16 +#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK) +/* CNTR9 Bit Fields */ +#define TSI_CNTR9_CTN1_MASK 0xFFFFu +#define TSI_CNTR9_CTN1_SHIFT 0 +#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK) +#define TSI_CNTR9_CTN_MASK 0xFFFF0000u +#define TSI_CNTR9_CTN_SHIFT 16 +#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK) +/* CNTR11 Bit Fields */ +#define TSI_CNTR11_CTN1_MASK 0xFFFFu +#define TSI_CNTR11_CTN1_SHIFT 0 +#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK) +#define TSI_CNTR11_CTN_MASK 0xFFFF0000u +#define TSI_CNTR11_CTN_SHIFT 16 +#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK) +/* CNTR13 Bit Fields */ +#define TSI_CNTR13_CTN1_MASK 0xFFFFu +#define TSI_CNTR13_CTN1_SHIFT 0 +#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK) +#define TSI_CNTR13_CTN_MASK 0xFFFF0000u +#define TSI_CNTR13_CTN_SHIFT 16 +#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK) +/* CNTR15 Bit Fields */ +#define TSI_CNTR15_CTN1_MASK 0xFFFFu +#define TSI_CNTR15_CTN1_SHIFT 0 +#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK) +#define TSI_CNTR15_CTN_MASK 0xFFFF0000u +#define TSI_CNTR15_CTN_SHIFT 16 +#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK) +/* THRESHOLD Bit Fields */ +#define TSI_THRESHOLD_HTHH_MASK 0xFFFFu +#define TSI_THRESHOLD_HTHH_SHIFT 0 +#define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK) +#define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u +#define TSI_THRESHOLD_LTHH_SHIFT 16 +#define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK) + +/** + * @} + */ /* end of group TSI_Register_Masks */ + + +/* TSI - Peripheral instance base addresses */ +/** Peripheral TSI0 base address */ +#define TSI0_BASE (0x40045000u) +/** Peripheral TSI0 base pointer */ +#define TSI0 ((TSI_Type *)TSI0_BASE) + +/** + * @} + */ /* end of group TSI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer + * @{ + */ + +/** UART - Register Layout Typedef */ +typedef struct { + __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */ + __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ + __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ + __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ + __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ + __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ + __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ + __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ + __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ + __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ + __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ + __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ + __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */ + __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */ + __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */ + uint8_t RESERVED_0[1]; + __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */ + __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */ + __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */ + __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */ + __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */ + __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */ + __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */ + uint8_t RESERVED_1[1]; + __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ + __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ + __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ + union { /* offset: 0x1B */ + __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ + __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ + }; + __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ + __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ + __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ + __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ + uint8_t RESERVED_2[1]; + __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */ + __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */ + __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */ + __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */ + __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */ + __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */ + __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */ + __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */ + __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */ + __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */ + __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */ + __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */ + __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */ + __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */ + __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */ + __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */ + __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */ +} UART_Type; + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/* BDH Bit Fields */ +#define UART_BDH_SBR_MASK 0x1Fu +#define UART_BDH_SBR_SHIFT 0 +#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK) +#define UART_BDH_RXEDGIE_MASK 0x40u +#define UART_BDH_RXEDGIE_SHIFT 6 +#define UART_BDH_LBKDIE_MASK 0x80u +#define UART_BDH_LBKDIE_SHIFT 7 +/* BDL Bit Fields */ +#define UART_BDL_SBR_MASK 0xFFu +#define UART_BDL_SBR_SHIFT 0 +#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK) +/* C1 Bit Fields */ +#define UART_C1_PT_MASK 0x1u +#define UART_C1_PT_SHIFT 0 +#define UART_C1_PE_MASK 0x2u +#define UART_C1_PE_SHIFT 1 +#define UART_C1_ILT_MASK 0x4u +#define UART_C1_ILT_SHIFT 2 +#define UART_C1_WAKE_MASK 0x8u +#define UART_C1_WAKE_SHIFT 3 +#define UART_C1_M_MASK 0x10u +#define UART_C1_M_SHIFT 4 +#define UART_C1_RSRC_MASK 0x20u +#define UART_C1_RSRC_SHIFT 5 +#define UART_C1_UARTSWAI_MASK 0x40u +#define UART_C1_UARTSWAI_SHIFT 6 +#define UART_C1_LOOPS_MASK 0x80u +#define UART_C1_LOOPS_SHIFT 7 +/* C2 Bit Fields */ +#define UART_C2_SBK_MASK 0x1u +#define UART_C2_SBK_SHIFT 0 +#define UART_C2_RWU_MASK 0x2u +#define UART_C2_RWU_SHIFT 1 +#define UART_C2_RE_MASK 0x4u +#define UART_C2_RE_SHIFT 2 +#define UART_C2_TE_MASK 0x8u +#define UART_C2_TE_SHIFT 3 +#define UART_C2_ILIE_MASK 0x10u +#define UART_C2_ILIE_SHIFT 4 +#define UART_C2_RIE_MASK 0x20u +#define UART_C2_RIE_SHIFT 5 +#define UART_C2_TCIE_MASK 0x40u +#define UART_C2_TCIE_SHIFT 6 +#define UART_C2_TIE_MASK 0x80u +#define UART_C2_TIE_SHIFT 7 +/* S1 Bit Fields */ +#define UART_S1_PF_MASK 0x1u +#define UART_S1_PF_SHIFT 0 +#define UART_S1_FE_MASK 0x2u +#define UART_S1_FE_SHIFT 1 +#define UART_S1_NF_MASK 0x4u +#define UART_S1_NF_SHIFT 2 +#define UART_S1_OR_MASK 0x8u +#define UART_S1_OR_SHIFT 3 +#define UART_S1_IDLE_MASK 0x10u +#define UART_S1_IDLE_SHIFT 4 +#define UART_S1_RDRF_MASK 0x20u +#define UART_S1_RDRF_SHIFT 5 +#define UART_S1_TC_MASK 0x40u +#define UART_S1_TC_SHIFT 6 +#define UART_S1_TDRE_MASK 0x80u +#define UART_S1_TDRE_SHIFT 7 +/* S2 Bit Fields */ +#define UART_S2_RAF_MASK 0x1u +#define UART_S2_RAF_SHIFT 0 +#define UART_S2_LBKDE_MASK 0x2u +#define UART_S2_LBKDE_SHIFT 1 +#define UART_S2_BRK13_MASK 0x4u +#define UART_S2_BRK13_SHIFT 2 +#define UART_S2_RWUID_MASK 0x8u +#define UART_S2_RWUID_SHIFT 3 +#define UART_S2_RXINV_MASK 0x10u +#define UART_S2_RXINV_SHIFT 4 +#define UART_S2_MSBF_MASK 0x20u +#define UART_S2_MSBF_SHIFT 5 +#define UART_S2_RXEDGIF_MASK 0x40u +#define UART_S2_RXEDGIF_SHIFT 6 +#define UART_S2_LBKDIF_MASK 0x80u +#define UART_S2_LBKDIF_SHIFT 7 +/* C3 Bit Fields */ +#define UART_C3_PEIE_MASK 0x1u +#define UART_C3_PEIE_SHIFT 0 +#define UART_C3_FEIE_MASK 0x2u +#define UART_C3_FEIE_SHIFT 1 +#define UART_C3_NEIE_MASK 0x4u +#define UART_C3_NEIE_SHIFT 2 +#define UART_C3_ORIE_MASK 0x8u +#define UART_C3_ORIE_SHIFT 3 +#define UART_C3_TXINV_MASK 0x10u +#define UART_C3_TXINV_SHIFT 4 +#define UART_C3_TXDIR_MASK 0x20u +#define UART_C3_TXDIR_SHIFT 5 +#define UART_C3_T8_MASK 0x40u +#define UART_C3_T8_SHIFT 6 +#define UART_C3_R8_MASK 0x80u +#define UART_C3_R8_SHIFT 7 +/* D Bit Fields */ +#define UART_D_RT_MASK 0xFFu +#define UART_D_RT_SHIFT 0 +#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK) +/* MA1 Bit Fields */ +#define UART_MA1_MA_MASK 0xFFu +#define UART_MA1_MA_SHIFT 0 +#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK) +/* MA2 Bit Fields */ +#define UART_MA2_MA_MASK 0xFFu +#define UART_MA2_MA_SHIFT 0 +#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK) +/* C4 Bit Fields */ +#define UART_C4_BRFA_MASK 0x1Fu +#define UART_C4_BRFA_SHIFT 0 +#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK) +#define UART_C4_M10_MASK 0x20u +#define UART_C4_M10_SHIFT 5 +#define UART_C4_MAEN2_MASK 0x40u +#define UART_C4_MAEN2_SHIFT 6 +#define UART_C4_MAEN1_MASK 0x80u +#define UART_C4_MAEN1_SHIFT 7 +/* C5 Bit Fields */ +#define UART_C5_RDMAS_MASK 0x20u +#define UART_C5_RDMAS_SHIFT 5 +#define UART_C5_TDMAS_MASK 0x80u +#define UART_C5_TDMAS_SHIFT 7 +/* ED Bit Fields */ +#define UART_ED_PARITYE_MASK 0x40u +#define UART_ED_PARITYE_SHIFT 6 +#define UART_ED_NOISY_MASK 0x80u +#define UART_ED_NOISY_SHIFT 7 +/* MODEM Bit Fields */ +#define UART_MODEM_TXCTSE_MASK 0x1u +#define UART_MODEM_TXCTSE_SHIFT 0 +#define UART_MODEM_TXRTSE_MASK 0x2u +#define UART_MODEM_TXRTSE_SHIFT 1 +#define UART_MODEM_TXRTSPOL_MASK 0x4u +#define UART_MODEM_TXRTSPOL_SHIFT 2 +#define UART_MODEM_RXRTSE_MASK 0x8u +#define UART_MODEM_RXRTSE_SHIFT 3 +/* IR Bit Fields */ +#define UART_IR_TNP_MASK 0x3u +#define UART_IR_TNP_SHIFT 0 +#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK) +#define UART_IR_IREN_MASK 0x4u +#define UART_IR_IREN_SHIFT 2 +/* PFIFO Bit Fields */ +#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u +#define UART_PFIFO_RXFIFOSIZE_SHIFT 0 +#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK) +#define UART_PFIFO_RXFE_MASK 0x8u +#define UART_PFIFO_RXFE_SHIFT 3 +#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u +#define UART_PFIFO_TXFIFOSIZE_SHIFT 4 +#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK) +#define UART_PFIFO_TXFE_MASK 0x80u +#define UART_PFIFO_TXFE_SHIFT 7 +/* CFIFO Bit Fields */ +#define UART_CFIFO_RXUFE_MASK 0x1u +#define UART_CFIFO_RXUFE_SHIFT 0 +#define UART_CFIFO_TXOFE_MASK 0x2u +#define UART_CFIFO_TXOFE_SHIFT 1 +#define UART_CFIFO_RXFLUSH_MASK 0x40u +#define UART_CFIFO_RXFLUSH_SHIFT 6 +#define UART_CFIFO_TXFLUSH_MASK 0x80u +#define UART_CFIFO_TXFLUSH_SHIFT 7 +/* SFIFO Bit Fields */ +#define UART_SFIFO_RXUF_MASK 0x1u +#define UART_SFIFO_RXUF_SHIFT 0 +#define UART_SFIFO_TXOF_MASK 0x2u +#define UART_SFIFO_TXOF_SHIFT 1 +#define UART_SFIFO_RXEMPT_MASK 0x40u +#define UART_SFIFO_RXEMPT_SHIFT 6 +#define UART_SFIFO_TXEMPT_MASK 0x80u +#define UART_SFIFO_TXEMPT_SHIFT 7 +/* TWFIFO Bit Fields */ +#define UART_TWFIFO_TXWATER_MASK 0xFFu +#define UART_TWFIFO_TXWATER_SHIFT 0 +#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK) +/* TCFIFO Bit Fields */ +#define UART_TCFIFO_TXCOUNT_MASK 0xFFu +#define UART_TCFIFO_TXCOUNT_SHIFT 0 +#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK) +/* RWFIFO Bit Fields */ +#define UART_RWFIFO_RXWATER_MASK 0xFFu +#define UART_RWFIFO_RXWATER_SHIFT 0 +#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK) +/* RCFIFO Bit Fields */ +#define UART_RCFIFO_RXCOUNT_MASK 0xFFu +#define UART_RCFIFO_RXCOUNT_SHIFT 0 +#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK) +/* C7816 Bit Fields */ +#define UART_C7816_ISO_7816E_MASK 0x1u +#define UART_C7816_ISO_7816E_SHIFT 0 +#define UART_C7816_TTYPE_MASK 0x2u +#define UART_C7816_TTYPE_SHIFT 1 +#define UART_C7816_INIT_MASK 0x4u +#define UART_C7816_INIT_SHIFT 2 +#define UART_C7816_ANACK_MASK 0x8u +#define UART_C7816_ANACK_SHIFT 3 +#define UART_C7816_ONACK_MASK 0x10u +#define UART_C7816_ONACK_SHIFT 4 +/* IE7816 Bit Fields */ +#define UART_IE7816_RXTE_MASK 0x1u +#define UART_IE7816_RXTE_SHIFT 0 +#define UART_IE7816_TXTE_MASK 0x2u +#define UART_IE7816_TXTE_SHIFT 1 +#define UART_IE7816_GTVE_MASK 0x4u +#define UART_IE7816_GTVE_SHIFT 2 +#define UART_IE7816_INITDE_MASK 0x10u +#define UART_IE7816_INITDE_SHIFT 4 +#define UART_IE7816_BWTE_MASK 0x20u +#define UART_IE7816_BWTE_SHIFT 5 +#define UART_IE7816_CWTE_MASK 0x40u +#define UART_IE7816_CWTE_SHIFT 6 +#define UART_IE7816_WTE_MASK 0x80u +#define UART_IE7816_WTE_SHIFT 7 +/* IS7816 Bit Fields */ +#define UART_IS7816_RXT_MASK 0x1u +#define UART_IS7816_RXT_SHIFT 0 +#define UART_IS7816_TXT_MASK 0x2u +#define UART_IS7816_TXT_SHIFT 1 +#define UART_IS7816_GTV_MASK 0x4u +#define UART_IS7816_GTV_SHIFT 2 +#define UART_IS7816_INITD_MASK 0x10u +#define UART_IS7816_INITD_SHIFT 4 +#define UART_IS7816_BWT_MASK 0x20u +#define UART_IS7816_BWT_SHIFT 5 +#define UART_IS7816_CWT_MASK 0x40u +#define UART_IS7816_CWT_SHIFT 6 +#define UART_IS7816_WT_MASK 0x80u +#define UART_IS7816_WT_SHIFT 7 +/* WP7816_T_TYPE0 Bit Fields */ +#define UART_WP7816_T_TYPE0_WI_MASK 0xFFu +#define UART_WP7816_T_TYPE0_WI_SHIFT 0 +#define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK) +/* WP7816_T_TYPE1 Bit Fields */ +#define UART_WP7816_T_TYPE1_BWI_MASK 0xFu +#define UART_WP7816_T_TYPE1_BWI_SHIFT 0 +#define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK) +#define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u +#define UART_WP7816_T_TYPE1_CWI_SHIFT 4 +#define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK) +/* WN7816 Bit Fields */ +#define UART_WN7816_GTN_MASK 0xFFu +#define UART_WN7816_GTN_SHIFT 0 +#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK) +/* WF7816 Bit Fields */ +#define UART_WF7816_GTFD_MASK 0xFFu +#define UART_WF7816_GTFD_SHIFT 0 +#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK) +/* ET7816 Bit Fields */ +#define UART_ET7816_RXTHRESHOLD_MASK 0xFu +#define UART_ET7816_RXTHRESHOLD_SHIFT 0 +#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK) +#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u +#define UART_ET7816_TXTHRESHOLD_SHIFT 4 +#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK) +/* TL7816 Bit Fields */ +#define UART_TL7816_TLEN_MASK 0xFFu +#define UART_TL7816_TLEN_SHIFT 0 +#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK) +/* C6 Bit Fields */ +#define UART_C6_CP_MASK 0x10u +#define UART_C6_CP_SHIFT 4 +#define UART_C6_CE_MASK 0x20u +#define UART_C6_CE_SHIFT 5 +#define UART_C6_TX709_MASK 0x40u +#define UART_C6_TX709_SHIFT 6 +#define UART_C6_EN709_MASK 0x80u +#define UART_C6_EN709_SHIFT 7 +/* PCTH Bit Fields */ +#define UART_PCTH_PCTH_MASK 0xFFu +#define UART_PCTH_PCTH_SHIFT 0 +#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK) +/* PCTL Bit Fields */ +#define UART_PCTL_PCTL_MASK 0xFFu +#define UART_PCTL_PCTL_SHIFT 0 +#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK) +/* B1T Bit Fields */ +#define UART_B1T_B1T_MASK 0xFFu +#define UART_B1T_B1T_SHIFT 0 +#define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK) +/* SDTH Bit Fields */ +#define UART_SDTH_SDTH_MASK 0xFFu +#define UART_SDTH_SDTH_SHIFT 0 +#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK) +/* SDTL Bit Fields */ +#define UART_SDTL_SDTL_MASK 0xFFu +#define UART_SDTL_SDTL_SHIFT 0 +#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK) +/* PRE Bit Fields */ +#define UART_PRE_PREAMBLE_MASK 0xFFu +#define UART_PRE_PREAMBLE_SHIFT 0 +#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK) +/* TPL Bit Fields */ +#define UART_TPL_TPL_MASK 0xFFu +#define UART_TPL_TPL_SHIFT 0 +#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK) +/* IE Bit Fields */ +#define UART_IE_TXFIE_MASK 0x1u +#define UART_IE_TXFIE_SHIFT 0 +#define UART_IE_PSIE_MASK 0x2u +#define UART_IE_PSIE_SHIFT 1 +#define UART_IE_PCTEIE_MASK 0x4u +#define UART_IE_PCTEIE_SHIFT 2 +#define UART_IE_PTXIE_MASK 0x8u +#define UART_IE_PTXIE_SHIFT 3 +#define UART_IE_PRXIE_MASK 0x10u +#define UART_IE_PRXIE_SHIFT 4 +#define UART_IE_ISDIE_MASK 0x20u +#define UART_IE_ISDIE_SHIFT 5 +#define UART_IE_WBEIE_MASK 0x40u +#define UART_IE_WBEIE_SHIFT 6 +/* WB Bit Fields */ +#define UART_WB_WBASE_MASK 0xFFu +#define UART_WB_WBASE_SHIFT 0 +#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK) +/* S3 Bit Fields */ +#define UART_S3_TXFF_MASK 0x1u +#define UART_S3_TXFF_SHIFT 0 +#define UART_S3_PSF_MASK 0x2u +#define UART_S3_PSF_SHIFT 1 +#define UART_S3_PCTEF_MASK 0x4u +#define UART_S3_PCTEF_SHIFT 2 +#define UART_S3_PTXF_MASK 0x8u +#define UART_S3_PTXF_SHIFT 3 +#define UART_S3_PRXF_MASK 0x10u +#define UART_S3_PRXF_SHIFT 4 +#define UART_S3_ISD_MASK 0x20u +#define UART_S3_ISD_SHIFT 5 +#define UART_S3_WBEF_MASK 0x40u +#define UART_S3_WBEF_SHIFT 6 +#define UART_S3_PEF_MASK 0x80u +#define UART_S3_PEF_SHIFT 7 +/* S4 Bit Fields */ +#define UART_S4_FE_MASK 0x1u +#define UART_S4_FE_SHIFT 0 +#define UART_S4_ILCV_MASK 0x2u +#define UART_S4_ILCV_SHIFT 1 +#define UART_S4_CDET_MASK 0xCu +#define UART_S4_CDET_SHIFT 2 +#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK) +#define UART_S4_INITF_MASK 0x10u +#define UART_S4_INITF_SHIFT 4 +/* RPL Bit Fields */ +#define UART_RPL_RPL_MASK 0xFFu +#define UART_RPL_RPL_SHIFT 0 +#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK) +/* RPREL Bit Fields */ +#define UART_RPREL_RPREL_MASK 0xFFu +#define UART_RPREL_RPREL_SHIFT 0 +#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK) +/* CPW Bit Fields */ +#define UART_CPW_CPW_MASK 0xFFu +#define UART_CPW_CPW_SHIFT 0 +#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK) +/* RIDT Bit Fields */ +#define UART_RIDT_RIDT_MASK 0xFFu +#define UART_RIDT_RIDT_SHIFT 0 +#define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK) +/* TIDT Bit Fields */ +#define UART_TIDT_TIDT_MASK 0xFFu +#define UART_TIDT_TIDT_SHIFT 0 +#define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK) + +/** + * @} + */ /* end of group UART_Register_Masks */ + + +/* UART - Peripheral instance base addresses */ +/** Peripheral UART0 base address */ +#define UART0_BASE (0x4006A000u) +/** Peripheral UART0 base pointer */ +#define UART0 ((UART_Type *)UART0_BASE) +/** Peripheral UART1 base address */ +#define UART1_BASE (0x4006B000u) +/** Peripheral UART1 base pointer */ +#define UART1 ((UART_Type *)UART1_BASE) +/** Peripheral UART2 base address */ +#define UART2_BASE (0x4006C000u) +/** Peripheral UART2 base pointer */ +#define UART2 ((UART_Type *)UART2_BASE) + +/** + * @} + */ /* end of group UART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */ + uint8_t RESERVED_0[3]; + __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */ + uint8_t RESERVED_1[3]; + __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */ + uint8_t RESERVED_2[3]; + __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */ + uint8_t RESERVED_3[3]; + __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */ + uint8_t RESERVED_4[3]; + __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */ + uint8_t RESERVED_5[3]; + __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */ + uint8_t RESERVED_6[3]; + __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */ + uint8_t RESERVED_7[99]; + __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */ + uint8_t RESERVED_8[3]; + __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */ + uint8_t RESERVED_9[3]; + __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */ + uint8_t RESERVED_10[3]; + __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */ + uint8_t RESERVED_11[3]; + __I uint8_t STAT; /**< Status Register, offset: 0x90 */ + uint8_t RESERVED_12[3]; + __IO uint8_t CTL; /**< Control Register, offset: 0x94 */ + uint8_t RESERVED_13[3]; + __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */ + uint8_t RESERVED_14[3]; + __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */ + uint8_t RESERVED_15[3]; + __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ + uint8_t RESERVED_16[3]; + __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ + uint8_t RESERVED_17[3]; + __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */ + uint8_t RESERVED_18[3]; + __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */ + uint8_t RESERVED_19[3]; + __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ + uint8_t RESERVED_20[3]; + __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ + uint8_t RESERVED_21[11]; + struct { /* offset: 0xC0, array step: 0x4 */ + __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_0[3]; + } ENDPOINT[16]; + __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */ + uint8_t RESERVED_22[3]; + __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */ + uint8_t RESERVED_23[3]; + __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */ + uint8_t RESERVED_24[3]; + __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */ + uint8_t RESERVED_25[7]; + __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/* PERID Bit Fields */ +#define USB_PERID_ID_MASK 0x3Fu +#define USB_PERID_ID_SHIFT 0 +#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK) +/* IDCOMP Bit Fields */ +#define USB_IDCOMP_NID_MASK 0x3Fu +#define USB_IDCOMP_NID_SHIFT 0 +#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK) +/* REV Bit Fields */ +#define USB_REV_REV_MASK 0xFFu +#define USB_REV_REV_SHIFT 0 +#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK) +/* ADDINFO Bit Fields */ +#define USB_ADDINFO_IEHOST_MASK 0x1u +#define USB_ADDINFO_IEHOST_SHIFT 0 +#define USB_ADDINFO_IRQNUM_MASK 0xF8u +#define USB_ADDINFO_IRQNUM_SHIFT 3 +#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK) +/* OTGISTAT Bit Fields */ +#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u +#define USB_OTGISTAT_AVBUSCHG_SHIFT 0 +#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u +#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2 +#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u +#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3 +#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u +#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5 +#define USB_OTGISTAT_ONEMSEC_MASK 0x40u +#define USB_OTGISTAT_ONEMSEC_SHIFT 6 +#define USB_OTGISTAT_IDCHG_MASK 0x80u +#define USB_OTGISTAT_IDCHG_SHIFT 7 +/* OTGICR Bit Fields */ +#define USB_OTGICR_AVBUSEN_MASK 0x1u +#define USB_OTGICR_AVBUSEN_SHIFT 0 +#define USB_OTGICR_BSESSEN_MASK 0x4u +#define USB_OTGICR_BSESSEN_SHIFT 2 +#define USB_OTGICR_SESSVLDEN_MASK 0x8u +#define USB_OTGICR_SESSVLDEN_SHIFT 3 +#define USB_OTGICR_LINESTATEEN_MASK 0x20u +#define USB_OTGICR_LINESTATEEN_SHIFT 5 +#define USB_OTGICR_ONEMSECEN_MASK 0x40u +#define USB_OTGICR_ONEMSECEN_SHIFT 6 +#define USB_OTGICR_IDEN_MASK 0x80u +#define USB_OTGICR_IDEN_SHIFT 7 +/* OTGSTAT Bit Fields */ +#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u +#define USB_OTGSTAT_AVBUSVLD_SHIFT 0 +#define USB_OTGSTAT_BSESSEND_MASK 0x4u +#define USB_OTGSTAT_BSESSEND_SHIFT 2 +#define USB_OTGSTAT_SESS_VLD_MASK 0x8u +#define USB_OTGSTAT_SESS_VLD_SHIFT 3 +#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u +#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5 +#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u +#define USB_OTGSTAT_ONEMSECEN_SHIFT 6 +#define USB_OTGSTAT_ID_MASK 0x80u +#define USB_OTGSTAT_ID_SHIFT 7 +/* OTGCTL Bit Fields */ +#define USB_OTGCTL_OTGEN_MASK 0x4u +#define USB_OTGCTL_OTGEN_SHIFT 2 +#define USB_OTGCTL_DMLOW_MASK 0x10u +#define USB_OTGCTL_DMLOW_SHIFT 4 +#define USB_OTGCTL_DPLOW_MASK 0x20u +#define USB_OTGCTL_DPLOW_SHIFT 5 +#define USB_OTGCTL_DPHIGH_MASK 0x80u +#define USB_OTGCTL_DPHIGH_SHIFT 7 +/* ISTAT Bit Fields */ +#define USB_ISTAT_USBRST_MASK 0x1u +#define USB_ISTAT_USBRST_SHIFT 0 +#define USB_ISTAT_ERROR_MASK 0x2u +#define USB_ISTAT_ERROR_SHIFT 1 +#define USB_ISTAT_SOFTOK_MASK 0x4u +#define USB_ISTAT_SOFTOK_SHIFT 2 +#define USB_ISTAT_TOKDNE_MASK 0x8u +#define USB_ISTAT_TOKDNE_SHIFT 3 +#define USB_ISTAT_SLEEP_MASK 0x10u +#define USB_ISTAT_SLEEP_SHIFT 4 +#define USB_ISTAT_RESUME_MASK 0x20u +#define USB_ISTAT_RESUME_SHIFT 5 +#define USB_ISTAT_ATTACH_MASK 0x40u +#define USB_ISTAT_ATTACH_SHIFT 6 +#define USB_ISTAT_STALL_MASK 0x80u +#define USB_ISTAT_STALL_SHIFT 7 +/* INTEN Bit Fields */ +#define USB_INTEN_USBRSTEN_MASK 0x1u +#define USB_INTEN_USBRSTEN_SHIFT 0 +#define USB_INTEN_ERROREN_MASK 0x2u +#define USB_INTEN_ERROREN_SHIFT 1 +#define USB_INTEN_SOFTOKEN_MASK 0x4u +#define USB_INTEN_SOFTOKEN_SHIFT 2 +#define USB_INTEN_TOKDNEEN_MASK 0x8u +#define USB_INTEN_TOKDNEEN_SHIFT 3 +#define USB_INTEN_SLEEPEN_MASK 0x10u +#define USB_INTEN_SLEEPEN_SHIFT 4 +#define USB_INTEN_RESUMEEN_MASK 0x20u +#define USB_INTEN_RESUMEEN_SHIFT 5 +#define USB_INTEN_ATTACHEN_MASK 0x40u +#define USB_INTEN_ATTACHEN_SHIFT 6 +#define USB_INTEN_STALLEN_MASK 0x80u +#define USB_INTEN_STALLEN_SHIFT 7 +/* ERRSTAT Bit Fields */ +#define USB_ERRSTAT_PIDERR_MASK 0x1u +#define USB_ERRSTAT_PIDERR_SHIFT 0 +#define USB_ERRSTAT_CRC5EOF_MASK 0x2u +#define USB_ERRSTAT_CRC5EOF_SHIFT 1 +#define USB_ERRSTAT_CRC16_MASK 0x4u +#define USB_ERRSTAT_CRC16_SHIFT 2 +#define USB_ERRSTAT_DFN8_MASK 0x8u +#define USB_ERRSTAT_DFN8_SHIFT 3 +#define USB_ERRSTAT_BTOERR_MASK 0x10u +#define USB_ERRSTAT_BTOERR_SHIFT 4 +#define USB_ERRSTAT_DMAERR_MASK 0x20u +#define USB_ERRSTAT_DMAERR_SHIFT 5 +#define USB_ERRSTAT_BTSERR_MASK 0x80u +#define USB_ERRSTAT_BTSERR_SHIFT 7 +/* ERREN Bit Fields */ +#define USB_ERREN_PIDERREN_MASK 0x1u +#define USB_ERREN_PIDERREN_SHIFT 0 +#define USB_ERREN_CRC5EOFEN_MASK 0x2u +#define USB_ERREN_CRC5EOFEN_SHIFT 1 +#define USB_ERREN_CRC16EN_MASK 0x4u +#define USB_ERREN_CRC16EN_SHIFT 2 +#define USB_ERREN_DFN8EN_MASK 0x8u +#define USB_ERREN_DFN8EN_SHIFT 3 +#define USB_ERREN_BTOERREN_MASK 0x10u +#define USB_ERREN_BTOERREN_SHIFT 4 +#define USB_ERREN_DMAERREN_MASK 0x20u +#define USB_ERREN_DMAERREN_SHIFT 5 +#define USB_ERREN_BTSERREN_MASK 0x80u +#define USB_ERREN_BTSERREN_SHIFT 7 +/* STAT Bit Fields */ +#define USB_STAT_ODD_MASK 0x4u +#define USB_STAT_ODD_SHIFT 2 +#define USB_STAT_TX_MASK 0x8u +#define USB_STAT_TX_SHIFT 3 +#define USB_STAT_ENDP_MASK 0xF0u +#define USB_STAT_ENDP_SHIFT 4 +#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK) +/* CTL Bit Fields */ +#define USB_CTL_USBENSOFEN_MASK 0x1u +#define USB_CTL_USBENSOFEN_SHIFT 0 +#define USB_CTL_ODDRST_MASK 0x2u +#define USB_CTL_ODDRST_SHIFT 1 +#define USB_CTL_RESUME_MASK 0x4u +#define USB_CTL_RESUME_SHIFT 2 +#define USB_CTL_HOSTMODEEN_MASK 0x8u +#define USB_CTL_HOSTMODEEN_SHIFT 3 +#define USB_CTL_RESET_MASK 0x10u +#define USB_CTL_RESET_SHIFT 4 +#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u +#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5 +#define USB_CTL_SE0_MASK 0x40u +#define USB_CTL_SE0_SHIFT 6 +#define USB_CTL_JSTATE_MASK 0x80u +#define USB_CTL_JSTATE_SHIFT 7 +/* ADDR Bit Fields */ +#define USB_ADDR_ADDR_MASK 0x7Fu +#define USB_ADDR_ADDR_SHIFT 0 +#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK) +#define USB_ADDR_LSEN_MASK 0x80u +#define USB_ADDR_LSEN_SHIFT 7 +/* BDTPAGE1 Bit Fields */ +#define USB_BDTPAGE1_BDTBA_MASK 0xFEu +#define USB_BDTPAGE1_BDTBA_SHIFT 1 +#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK) +/* FRMNUML Bit Fields */ +#define USB_FRMNUML_FRM_MASK 0xFFu +#define USB_FRMNUML_FRM_SHIFT 0 +#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK) +/* FRMNUMH Bit Fields */ +#define USB_FRMNUMH_FRM_MASK 0x7u +#define USB_FRMNUMH_FRM_SHIFT 0 +#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK) +/* TOKEN Bit Fields */ +#define USB_TOKEN_TOKENENDPT_MASK 0xFu +#define USB_TOKEN_TOKENENDPT_SHIFT 0 +#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK) +#define USB_TOKEN_TOKENPID_MASK 0xF0u +#define USB_TOKEN_TOKENPID_SHIFT 4 +#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK) +/* SOFTHLD Bit Fields */ +#define USB_SOFTHLD_CNT_MASK 0xFFu +#define USB_SOFTHLD_CNT_SHIFT 0 +#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK) +/* BDTPAGE2 Bit Fields */ +#define USB_BDTPAGE2_BDTBA_MASK 0xFFu +#define USB_BDTPAGE2_BDTBA_SHIFT 0 +#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK) +/* BDTPAGE3 Bit Fields */ +#define USB_BDTPAGE3_BDTBA_MASK 0xFFu +#define USB_BDTPAGE3_BDTBA_SHIFT 0 +#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK) +/* ENDPT Bit Fields */ +#define USB_ENDPT_EPHSHK_MASK 0x1u +#define USB_ENDPT_EPHSHK_SHIFT 0 +#define USB_ENDPT_EPSTALL_MASK 0x2u +#define USB_ENDPT_EPSTALL_SHIFT 1 +#define USB_ENDPT_EPTXEN_MASK 0x4u +#define USB_ENDPT_EPTXEN_SHIFT 2 +#define USB_ENDPT_EPRXEN_MASK 0x8u +#define USB_ENDPT_EPRXEN_SHIFT 3 +#define USB_ENDPT_EPCTLDIS_MASK 0x10u +#define USB_ENDPT_EPCTLDIS_SHIFT 4 +#define USB_ENDPT_RETRYDIS_MASK 0x40u +#define USB_ENDPT_RETRYDIS_SHIFT 6 +#define USB_ENDPT_HOSTWOHUB_MASK 0x80u +#define USB_ENDPT_HOSTWOHUB_SHIFT 7 +/* USBCTRL Bit Fields */ +#define USB_USBCTRL_PDE_MASK 0x40u +#define USB_USBCTRL_PDE_SHIFT 6 +#define USB_USBCTRL_SUSP_MASK 0x80u +#define USB_USBCTRL_SUSP_SHIFT 7 +/* OBSERVE Bit Fields */ +#define USB_OBSERVE_DMPD_MASK 0x10u +#define USB_OBSERVE_DMPD_SHIFT 4 +#define USB_OBSERVE_DPPD_MASK 0x40u +#define USB_OBSERVE_DPPD_SHIFT 6 +#define USB_OBSERVE_DPPU_MASK 0x80u +#define USB_OBSERVE_DPPU_SHIFT 7 +/* CONTROL Bit Fields */ +#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u +#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4 +/* USBTRC0 Bit Fields */ +#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u +#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0 +#define USB_USBTRC0_SYNC_DET_MASK 0x2u +#define USB_USBTRC0_SYNC_DET_SHIFT 1 +#define USB_USBTRC0_USBRESMEN_MASK 0x20u +#define USB_USBTRC0_USBRESMEN_SHIFT 5 +#define USB_USBTRC0_USBRESET_MASK 0x80u +#define USB_USBTRC0_USBRESET_SHIFT 7 +/* USBFRMADJUST Bit Fields */ +#define USB_USBFRMADJUST_ADJ_MASK 0xFFu +#define USB_USBFRMADJUST_ADJ_SHIFT 0 +#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK) + +/** + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x40072000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) + +/** + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBDCD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer + * @{ + */ + +/** USBDCD - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */ + __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */ + __I uint32_t STATUS; /**< Status Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */ + __IO uint32_t TIMER1; /**< , offset: 0x14 */ + __IO uint32_t TIMER2; /**< , offset: 0x18 */ +} USBDCD_Type; + +/* ---------------------------------------------------------------------------- + -- USBDCD Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup USBDCD_Register_Masks USBDCD Register Masks + * @{ + */ + +/* CONTROL Bit Fields */ +#define USBDCD_CONTROL_IACK_MASK 0x1u +#define USBDCD_CONTROL_IACK_SHIFT 0 +#define USBDCD_CONTROL_IF_MASK 0x100u +#define USBDCD_CONTROL_IF_SHIFT 8 +#define USBDCD_CONTROL_IE_MASK 0x10000u +#define USBDCD_CONTROL_IE_SHIFT 16 +#define USBDCD_CONTROL_START_MASK 0x1000000u +#define USBDCD_CONTROL_START_SHIFT 24 +#define USBDCD_CONTROL_SR_MASK 0x2000000u +#define USBDCD_CONTROL_SR_SHIFT 25 +/* CLOCK Bit Fields */ +#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u +#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0 +#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu +#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2 +#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK) +/* STATUS Bit Fields */ +#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u +#define USBDCD_STATUS_SEQ_RES_SHIFT 16 +#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK) +#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u +#define USBDCD_STATUS_SEQ_STAT_SHIFT 18 +#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK) +#define USBDCD_STATUS_ERR_MASK 0x100000u +#define USBDCD_STATUS_ERR_SHIFT 20 +#define USBDCD_STATUS_TO_MASK 0x200000u +#define USBDCD_STATUS_TO_SHIFT 21 +#define USBDCD_STATUS_ACTIVE_MASK 0x400000u +#define USBDCD_STATUS_ACTIVE_SHIFT 22 +/* TIMER0 Bit Fields */ +#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu +#define USBDCD_TIMER0_TUNITCON_SHIFT 0 +#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK) +#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u +#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16 +#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK) +/* TIMER1 Bit Fields */ +#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu +#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0 +#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK) +#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u +#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16 +#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK) +/* TIMER2 Bit Fields */ +#define USBDCD_TIMER2_CHECK_DM_MASK 0xFu +#define USBDCD_TIMER2_CHECK_DM_SHIFT 0 +#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK) +#define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u +#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16 +#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK) + +/** + * @} + */ /* end of group USBDCD_Register_Masks */ + + +/* USBDCD - Peripheral instance base addresses */ +/** Peripheral USBDCD base address */ +#define USBDCD_BASE (0x40035000u) +/** Peripheral USBDCD base pointer */ +#define USBDCD ((USBDCD_Type *)USBDCD_BASE) + +/** + * @} + */ /* end of group USBDCD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- VREF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer + * @{ + */ + +/** VREF - Register Layout Typedef */ +typedef struct { + __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ + __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ +} VREF_Type; + +/* ---------------------------------------------------------------------------- + -- VREF Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup VREF_Register_Masks VREF Register Masks + * @{ + */ + +/* TRM Bit Fields */ +#define VREF_TRM_TRIM_MASK 0x3Fu +#define VREF_TRM_TRIM_SHIFT 0 +#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK) +#define VREF_TRM_CHOPEN_MASK 0x40u +#define VREF_TRM_CHOPEN_SHIFT 6 +/* SC Bit Fields */ +#define VREF_SC_MODE_LV_MASK 0x3u +#define VREF_SC_MODE_LV_SHIFT 0 +#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK) +#define VREF_SC_VREFST_MASK 0x4u +#define VREF_SC_VREFST_SHIFT 2 +#define VREF_SC_REGEN_MASK 0x40u +#define VREF_SC_REGEN_SHIFT 6 +#define VREF_SC_VREFEN_MASK 0x80u +#define VREF_SC_VREFEN_SHIFT 7 + +/** + * @} + */ /* end of group VREF_Register_Masks */ + + +/* VREF - Peripheral instance base addresses */ +/** Peripheral VREF base address */ +#define VREF_BASE (0x40074000u) +/** Peripheral VREF base pointer */ +#define VREF ((VREF_Type *)VREF_BASE) + +/** + * @} + */ /* end of group VREF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */ + __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */ + __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */ + __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */ + __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */ + __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */ + __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */ + __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */ + __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */ + __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */ + __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */ + __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/* STCTRLH Bit Fields */ +#define WDOG_STCTRLH_WDOGEN_MASK 0x1u +#define WDOG_STCTRLH_WDOGEN_SHIFT 0 +#define WDOG_STCTRLH_CLKSRC_MASK 0x2u +#define WDOG_STCTRLH_CLKSRC_SHIFT 1 +#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u +#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 +#define WDOG_STCTRLH_WINEN_MASK 0x8u +#define WDOG_STCTRLH_WINEN_SHIFT 3 +#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u +#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 +#define WDOG_STCTRLH_DBGEN_MASK 0x20u +#define WDOG_STCTRLH_DBGEN_SHIFT 5 +#define WDOG_STCTRLH_STOPEN_MASK 0x40u +#define WDOG_STCTRLH_STOPEN_SHIFT 6 +#define WDOG_STCTRLH_WAITEN_MASK 0x80u +#define WDOG_STCTRLH_WAITEN_SHIFT 7 +#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u +#define WDOG_STCTRLH_TESTWDOG_SHIFT 10 +#define WDOG_STCTRLH_TESTSEL_MASK 0x800u +#define WDOG_STCTRLH_TESTSEL_SHIFT 11 +#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u +#define WDOG_STCTRLH_BYTESEL_SHIFT 12 +#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK) +#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u +#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14 +/* STCTRLL Bit Fields */ +#define WDOG_STCTRLL_INTFLG_MASK 0x8000u +#define WDOG_STCTRLL_INTFLG_SHIFT 15 +/* TOVALH Bit Fields */ +#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu +#define WDOG_TOVALH_TOVALHIGH_SHIFT 0 +#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK) +/* TOVALL Bit Fields */ +#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu +#define WDOG_TOVALL_TOVALLOW_SHIFT 0 +#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK) +/* WINH Bit Fields */ +#define WDOG_WINH_WINHIGH_MASK 0xFFFFu +#define WDOG_WINH_WINHIGH_SHIFT 0 +#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK) +/* WINL Bit Fields */ +#define WDOG_WINL_WINLOW_MASK 0xFFFFu +#define WDOG_WINL_WINLOW_SHIFT 0 +#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK) +/* REFRESH Bit Fields */ +#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu +#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0 +#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK) +/* UNLOCK Bit Fields */ +#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu +#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0 +#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK) +/* TMROUTH Bit Fields */ +#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu +#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0 +#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK) +/* TMROUTL Bit Fields */ +#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu +#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0 +#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK) +/* RSTCNT Bit Fields */ +#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu +#define WDOG_RSTCNT_RSTCNT_SHIFT 0 +#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK) +/* PRESC Bit Fields */ +#define WDOG_PRESC_PRESCVAL_MASK 0x700u +#define WDOG_PRESC_PRESCVAL_SHIFT 8 +#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK) + +/** + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG base address */ +#define WDOG_BASE (0x40052000u) +/** Peripheral WDOG base pointer */ +#define WDOG ((WDOG_Type *)WDOG_BASE) + +/** + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__CWCC__) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/** + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Backward Compatibility + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Backward_Compatibility_Symbols Backward Compatibility + * @{ + */ + +/* No backward compatibility issues. */ + +/** + * @} + */ /* end of group Backward_Compatibility_Symbols */ + + +#endif /* #if !defined(MK20D5_H_) */ + +/* MK20D5.h, eof. */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,14 @@ + +LR_IROM1 0x00000000 0x20000 { ; load region size_region (132k) + ER_IROM1 0x00000000 0x20000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0xF8) = 0xF8 + ; 0x4000 - 0xF8 = 0x3F08 + RW_IRAM1 0x1FFFE0F8 0x3F08 { + .ANY (+RW +ZI) + } +} +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,412 @@ +;/***************************************************************************** +; * @file: startup_MK20D5.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the +; * MK20D5 +; * @version: 1.0 +; * @date: 2011-12-15 +; * +; * Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved. +;* +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + +__initial_sp EQU 0x20002000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt + DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt + DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt + DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt + DCD DMA_Error_IRQHandler ; DMA error interrupt + DCD Reserved21_IRQHandler ; Reserved interrupt 21 + DCD FTFL_IRQHandler ; FTFL interrupt + DCD Read_Collision_IRQHandler ; Read collision interrupt + DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning + DCD LLW_IRQHandler ; Low Leakage Wakeup + DCD Watchdog_IRQHandler ; WDOG interrupt + DCD I2C0_IRQHandler ; I2C0 interrupt + DCD SPI0_IRQHandler ; SPI0 interrupt + DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt + DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt + DCD UART0_LON_IRQHandler ; UART0 LON interrupt + DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt + DCD UART0_ERR_IRQHandler ; UART0 error interrupt + DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt + DCD UART1_ERR_IRQHandler ; UART1 error interrupt + DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt + DCD UART2_ERR_IRQHandler ; UART2 error interrupt + DCD ADC0_IRQHandler ; ADC0 interrupt + DCD CMP0_IRQHandler ; CMP0 interrupt + DCD CMP1_IRQHandler ; CMP1 interrupt + DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt + DCD CMT_IRQHandler ; CMT interrupt + DCD RTC_IRQHandler ; RTC interrupt + DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt + DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt + DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt + DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt + DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt + DCD PDB0_IRQHandler ; PDB0 interrupt + DCD USB0_IRQHandler ; USB0 interrupt + DCD USBDCD_IRQHandler ; USBDCD interrupt + DCD TSI0_IRQHandler ; TSI0 interrupt + DCD MCG_IRQHandler ; MCG interrupt + DCD LPTimer_IRQHandler ; LPTimer interrupt + DCD PORTA_IRQHandler ; Port A interrupt + DCD PORTB_IRQHandler ; Port B interrupt + DCD PORTC_IRQHandler ; Port C interrupt + DCD PORTD_IRQHandler ; Port D interrupt + DCD PORTE_IRQHandler ; Port E interrupt + DCD SWI_IRQHandler ; Software interrupt +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; <h> Flash Configuration +; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) +; <i> and security information that allows the MCU to restrict acces to the FTFL module. +; <h> Backdoor Comparison Key +; <o0> Backdoor Key 0 <0x0-0xFF:2> +; <o1> Backdoor Key 1 <0x0-0xFF:2> +; <o2> Backdoor Key 2 <0x0-0xFF:2> +; <o3> Backdoor Key 3 <0x0-0xFF:2> +; <o4> Backdoor Key 4 <0x0-0xFF:2> +; <o5> Backdoor Key 5 <0x0-0xFF:2> +; <o6> Backdoor Key 6 <0x0-0xFF:2> +; <o7> Backdoor Key 7 <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; </h> +; <h> Program flash protection bytes (FPROT) +; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; <i> Each bit protects a 1/32 region of the program flash memory. +; <h> FPROT0 +; <i> Program flash protection bytes +; <i> 1/32 - 8/32 region +; <o.0> FPROT0.0 +; <o.1> FPROT0.1 +; <o.2> FPROT0.2 +; <o.3> FPROT0.3 +; <o.4> FPROT0.4 +; <o.5> FPROT0.5 +; <o.6> FPROT0.6 +; <o.7> FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; </h> +; <h> FPROT1 +; <i> Program Flash Region Protect Register 1 +; <i> 9/32 - 16/32 region +; <o.0> FPROT1.0 +; <o.1> FPROT1.1 +; <o.2> FPROT1.2 +; <o.3> FPROT1.3 +; <o.4> FPROT1.4 +; <o.5> FPROT1.5 +; <o.6> FPROT1.6 +; <o.7> FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; </h> +; <h> FPROT2 +; <i> Program Flash Region Protect Register 2 +; <i> 17/32 - 24/32 region +; <o.0> FPROT2.0 +; <o.1> FPROT2.1 +; <o.2> FPROT2.2 +; <o.3> FPROT2.3 +; <o.4> FPROT2.4 +; <o.5> FPROT2.5 +; <o.6> FPROT2.6 +; <o.7> FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; </h> +; <h> FPROT3 +; <i> Program Flash Region Protect Register 3 +; <i> 25/32 - 32/32 region +; <o.0> FPROT3.0 +; <o.1> FPROT3.1 +; <o.2> FPROT3.2 +; <o.3> FPROT3.3 +; <o.4> FPROT3.4 +; <o.5> FPROT3.5 +; <o.6> FPROT3.6 +; <o.7> FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; </h> +; </h> +; <h> Data flash protection byte (FDPROT) +; <i> Each bit protects a 1/8 region of the data flash memory. +; <i> (Program flash only devices: Reserved) +; <o.0> FDPROT.0 +; <o.1> FDPROT.1 +; <o.2> FDPROT.2 +; <o.3> FDPROT.3 +; <o.4> FDPROT.4 +; <o.5> FDPROT.5 +; <o.6> FDPROT.6 +; <o.7> FDPROT.7 +nFDPROT EQU 0x00 +FDPROT EQU nFDPROT:EOR:0xFF +; </h> +; <h> EEPROM protection byte (FEPROT) +; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. +; <i> (Program flash only devices: Reserved) +; <o.0> FEPROT.0 +; <o.1> FEPROT.1 +; <o.2> FEPROT.2 +; <o.3> FEPROT.3 +; <o.4> FEPROT.4 +; <o.5> FEPROT.5 +; <o.6> FEPROT.6 +; <o.7> FEPROT.7 +nFEPROT EQU 0x00 +FEPROT EQU nFEPROT:EOR:0xFF +; </h> +; <h> Flash nonvolatile option byte (FOPT) +; <i> Allows the user to customize the operation of the MCU at boot time. +; <o.0> LPBOOT +; <0=> Low-power boot +; <1=> normal boot +; <o.1> EZPORT_DIS +; <0=> EzPort operation is enabled +; <1=> EzPort operation is disabled +FOPT EQU 0xFF +; </h> +; <h> Flash security byte (FSEC) +; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; <o.0..1> SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; <i> Flash Security +; <i> This bits define the security state of the MCU. +; <o.2..3> FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; <i> Freescale Failure Analysis Access Code +; <i> This bits define the security state of the MCU. +; <o.4..5> MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; <i> Mass Erase Enable Bits +; <i> Enables and disables mass erase capability of the FTFL module +; <o.6..7> KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; <i> Backdoor key Security Enable +; <i> These bits enable and disable backdoor key access to the FTFL module. +FSEC EQU 0xFE +; </h> +; </h> + IF :LNOT::DEF:RAM_TARGET + AREA |.ARM.__at_0x400|, CODE, READONLY + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0, FPROT1, FPROT2, FPROT3 + DCB FSEC, FOPT, FEPROT, FDPROT + ENDIF + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DMA0_IRQHandler [WEAK] + EXPORT DMA1_IRQHandler [WEAK] + EXPORT DMA2_IRQHandler [WEAK] + EXPORT DMA3_IRQHandler [WEAK] + EXPORT DMA_Error_IRQHandler [WEAK] + EXPORT Reserved21_IRQHandler [WEAK] + EXPORT FTFL_IRQHandler [WEAK] + EXPORT Read_Collision_IRQHandler [WEAK] + EXPORT LVD_LVW_IRQHandler [WEAK] + EXPORT LLW_IRQHandler [WEAK] + EXPORT Watchdog_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT I2S0_Tx_IRQHandler [WEAK] + EXPORT I2S0_Rx_IRQHandler [WEAK] + EXPORT UART0_LON_IRQHandler [WEAK] + EXPORT UART0_RX_TX_IRQHandler [WEAK] + EXPORT UART0_ERR_IRQHandler [WEAK] + EXPORT UART1_RX_TX_IRQHandler [WEAK] + EXPORT UART1_ERR_IRQHandler [WEAK] + EXPORT UART2_RX_TX_IRQHandler [WEAK] + EXPORT UART2_ERR_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT FTM0_IRQHandler [WEAK] + EXPORT FTM1_IRQHandler [WEAK] + EXPORT CMT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT0_IRQHandler [WEAK] + EXPORT PIT1_IRQHandler [WEAK] + EXPORT PIT2_IRQHandler [WEAK] + EXPORT PIT3_IRQHandler [WEAK] + EXPORT PDB0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT USBDCD_IRQHandler [WEAK] + EXPORT TSI0_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT LPTimer_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_IRQHandler [WEAK] + EXPORT PORTD_IRQHandler [WEAK] + EXPORT PORTE_IRQHandler [WEAK] + EXPORT SWI_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] + +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +DMA_Error_IRQHandler +Reserved21_IRQHandler +FTFL_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +LLW_IRQHandler +Watchdog_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +I2S0_Tx_IRQHandler +I2S0_Rx_IRQHandler +UART0_LON_IRQHandler +UART0_RX_TX_IRQHandler +UART0_ERR_IRQHandler +UART1_RX_TX_IRQHandler +UART1_ERR_IRQHandler +UART2_RX_TX_IRQHandler +UART2_ERR_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +CMT_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +USBDCD_IRQHandler +TSI0_IRQHandler +MCG_IRQHandler +LPTimer_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +DefaultISR + + B . + + ENDP + + + ALIGN + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2015 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rt_misc.h> +#include <stdint.h> + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,163 @@ +/* + * K20 ARM GCC linker script file + */ + +MEMORY +{ + VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010 + FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410 + RAM (rwx) : ORIGIN = 0x1FFFE0F8, LENGTH = 16K - 0xF8 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * _reset_init : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .isr_vector : + { + __vector_table = .; + KEEP(*(.vector_table)) + *(.text.Reset_Handler) + *(.text.System_Init) + . = ALIGN(4); + } > VECTORS + + .flash_protect : + { + KEEP(*(.kinetis_flash_config_field)) + . = ALIGN(4); + } > FLASH_PROTECTION + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5..s Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,259 @@ +/* File: startup_MK20D5.s + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.3 + * Date: 08 Feb 2012 + * + * Copyright (c) 2015, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x400 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0xC00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long DMA0_IRQHandler /* 0: Watchdog Timer */ + .long DMA1_IRQHandler /* 1: Real Time Clock */ + .long DMA2_IRQHandler /* 2: Timer0 / Timer1 */ + .long DMA3_IRQHandler /* 3: Timer2 / Timer3 */ + .long DMA_Error_IRQHandler /* 4: MCIa */ + .long 0 /* 5: MCIb */ + .long FTFL_IRQHandler /* 6: UART0 - DUT FPGA */ + .long Read_Collision_IRQHandler /* 7: UART1 - DUT FPGA */ + .long LVD_LVW_IRQHandler /* 8: UART2 - DUT FPGA */ + .long LLW_IRQHandler /* 9: UART4 - not connected */ + .long Watchdog_IRQHandler /* 10: AACI / AC97 */ + .long I2C0_IRQHandler /* 11: CLCD Combined Interrupt */ + .long SPI0_IRQHandler /* 12: Ethernet */ + .long I2S0_Tx_IRQHandler /* 13: USB Device */ + .long I2S0_Rx_IRQHandler /* 14: USB Host Controller */ + .long UART0_LON_IRQHandler /* 15: Character LCD */ + .long UART0_RX_TX_IRQHandler /* 16: Flexray */ + .long UART0_ERR_IRQHandler /* 17: CAN */ + .long UART1_RX_TX_IRQHandler /* 18: LIN */ + .long UART1_ERR_IRQHandler /* 19: I2C ADC/DAC */ + .long UART2_RX_TX_IRQHandler /* 20: Reserved */ + .long UART2_ERR_IRQHandler /* 21: Reserved */ + .long ADC0_IRQHandler /* 22: Reserved */ + .long CMP0_IRQHandler /* 23: Reserved */ + .long CMP1_IRQHandler /* 24: Reserved */ + .long FTM0_IRQHandler /* 25: Reserved */ + .long FTM1_IRQHandler /* 26: Reserved */ + .long CMT_IRQHandler /* 27: Reserved */ + .long RTC_IRQHandler /* 28: Reserved - CPU FPGA CLCD */ + .long RTC_Seconds_IRQHandler /* 29: Reserved - CPU FPGA */ + .long PIT0_IRQHandler /* 30: UART3 - CPU FPGA */ + .long PIT1_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ + .long PIT2_IRQHandler + .long PIT3_IRQHandler + .long PDB0_IRQHandler + .long USB0_IRQHandler + .long USBDCD_IRQHandler + .long TSI0_IRQHandler + .long MCG_IRQHandler + .long LPTimer_IRQHandler + .long PORTA_IRQHandler + .long PORTB_IRQHandler + .long PORTC_IRQHandler + .long PORTD_IRQHandler + .long PORTE_IRQHandler + .long SWI_IRQHandler + .size __isr_vector, . - __isr_vector + + .section .text.Reset_Handler + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.Lflash_to_ram_loop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .Lflash_to_ram_loop + +.Lflash_to_ram_loop_end: + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_default_handler DMA0_IRQHandler + def_irq_default_handler DMA1_IRQHandler + def_irq_default_handler DMA2_IRQHandler + def_irq_default_handler DMA3_IRQHandler + def_irq_default_handler DMA_Error_IRQHandler + def_irq_default_handler FTFL_IRQHandler + def_irq_default_handler Read_Collision_IRQHandler + def_irq_default_handler LVD_LVW_IRQHandler + def_irq_default_handler LLW_IRQHandler + def_irq_default_handler Watchdog_IRQHandler + def_irq_default_handler I2C0_IRQHandler + def_irq_default_handler SPI0_IRQHandler + def_irq_default_handler I2S0_Tx_IRQHandler + def_irq_default_handler I2S0_Rx_IRQHandler + def_irq_default_handler UART0_LON_IRQHandler + def_irq_default_handler UART0_RX_TX_IRQHandler + def_irq_default_handler UART0_ERR_IRQHandler + def_irq_default_handler UART1_RX_TX_IRQHandler + def_irq_default_handler UART1_ERR_IRQHandler + def_irq_default_handler UART2_RX_TX_IRQHandler + def_irq_default_handler UART2_ERR_IRQHandler + def_irq_default_handler ADC0_IRQHandler + def_irq_default_handler CMP0_IRQHandler + def_irq_default_handler CMP1_IRQHandler + def_irq_default_handler FTM0_IRQHandler + def_irq_default_handler FTM1_IRQHandler + def_irq_default_handler CMT_IRQHandler + def_irq_default_handler RTC_IRQHandler + def_irq_default_handler RTC_Seconds_IRQHandler + def_irq_default_handler PIT0_IRQHandler + def_irq_default_handler PIT1_IRQHandler + def_irq_default_handler PIT2_IRQHandler + def_irq_default_handler PIT3_IRQHandler + def_irq_default_handler PDB0_IRQHandler + def_irq_default_handler USB0_IRQHandler + def_irq_default_handler USBDCD_IRQHandler + def_irq_default_handler TSI0_IRQHandler + def_irq_default_handler MCG_IRQHandler + def_irq_default_handler LPTimer_IRQHandler + def_irq_default_handler PORTA_IRQHandler + def_irq_default_handler PORTB_IRQHandler + def_irq_default_handler PORTC_IRQHandler + def_irq_default_handler PORTD_IRQHandler + def_irq_default_handler PORTE_IRQHandler + def_irq_default_handler SWI_IRQHandler + def_irq_default_handler DEF_IRQHandler + +/* Flash protection region, placed at 0x400 */ + .text + .thumb + .align 2 + .section .kinetis_flash_config_field,"a",%progbits +kinetis_flash_config: + .long 0xffffffff + .long 0xffffffff + .long 0xffffffff + .long 0xfffffffe + + .end
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,51 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0001ffff; +define symbol __ICFEDIT_region_NVIC_start__ = 0x1fffe000; +define symbol __ICFEDIT_region_NVIC_end__ = 0x1fffe0f7; +define symbol __ICFEDIT_region_RAM_start__ = 0x1fffe0f8; +define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_RAM2_start__ = 0x20000000; +define symbol __region_RAM2_end__ = 0x20001fff; + +define symbol __FlashConfig_start__ = 0x00000400; +define symbol __FlashConfig_end__ = 0x0000040f; + +define symbol __region_FlexNVM_start__ = 0x10000000; +define symbol __region_FlexNVM_end__ = 0x10007fff; + +define symbol __region_FlexRAM_start__ = 0x14000000; +define symbol __region_FlexRAM_end__ = 0x140007ff; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__] | mem:[from __region_FlexNVM_start__ to __region_FlexNVM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__]; +define region FlexRAM_region = mem:[from __region_FlexRAM_start__ to __region_FlexRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__]; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in FlashConfig_region {section FlashConfig}; + +place in ROM_region { readonly }; + +place in RAM_region { readwrite, block HEAP, block CSTACK }; + +place in FlexRAM_region { section .flex_ram };
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,271 @@ +/************************************************** + * + * Copyright 2010 IAR Systems. All rights reserved. + * + * $Revision: 16 $ + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:ROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + ; External Interrupts + DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete + DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete + DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete + DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete + DCD DMA_ERR_IRQHandler ; 4: DMA Error Interrupt Channels 0-15 + DCD 0 ; 5: Reserved + DCD FLASH_CC_IRQHandler ; 6: Flash memory command complete + DCD FLASH_RC_IRQHandler ; 7: Flash memory read collision + DCD VLD_IRQHandler ; 8: Low Voltage Detect, Low Voltage Warning + DCD LLWU_IRQHandler ; 9: Low Leakage Wakeup + DCD WDOG_IRQHandler ;10: WDOG interrupt + DCD I2C0_IRQHandler ;11: I2C0 interrupt + DCD SPI0_IRQHandler ;12: SPI 0 interrupt + DCD I2S0_IRQHandler ;13: I2S 0 interrupt + DCD I2S1_IRQHandler ;14: I2S 1 interrupt + DCD UART0_LON_IRQHandler ;15: UART 0 LON intertrupt + DCD UART0_IRQHandler ;16: UART 0 intertrupt + DCD UART0_ERR_IRQHandler ;17: UART 0 error intertrupt + DCD UART1_IRQHandler ;18: UART 1 intertrupt + DCD UART1_ERR_IRQHandler ;19: UART 1 error intertrupt + DCD UART2_IRQHandler ;20: UART 2 intertrupt + DCD UART2_ERR_IRQHandler ;21: UART 2 error intertrupt + DCD ADC0_IRQHandler ;22: ADC 0 interrupt + DCD CMP0_IRQHandler ;23: CMP 0 High-speed comparator interrupt + DCD CMP1_IRQHandler ;24: CMP 1 interrupt + DCD FTM0_IRQHandler ;25: FTM 0 interrupt + DCD FTM1_IRQHandler ;26: FTM 1 interrupt + DCD CMT_IRQHandler ;27: CMT intrrupt + DCD RTC_ALRM_IRQHandler ;28: RTC Alarm interrupt + DCD RTC_SEC_IRQHandler ;29: RTC Sec interrupt + DCD PIT0_IRQHandler ;30: PIT 0 interrupt + DCD PIT1_IRQHandler ;31: PIT 1 interrupt + DCD PIT2_IRQHandler ;32: PIT 2 interrupt + DCD PIT3_IRQHandler ;33: PIT 3 interrupt + DCD PDB_IRQHandler ;34: PDB interrupt + DCD USB_OTG_IRQHandler ;35: USB OTG interrupt + DCD USB_CD_IRQHandler ;36: USB Charger Detect interrupt + DCD TSI_IRQHandler ;37: TSI interrupt + DCD MCG_IRQHandler ;38: MCG interrupt + DCD LPT_IRQHandler ;39: LPT interrupt + DCD PORTA_IRQHandler ;40: PORT A interrupt + DCD PORTB_IRQHandler ;41: PORT B interrupt + DCD PORTC_IRQHandler ;42: PORT C interrupt + DCD PORTD_IRQHandler ;43: PORT D interrupt + DCD PORTE_IRQHandler ;44: PORT E interrupt + DCD SW_IRQHandler ;45: Software initiated interrupt +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;;Flash Configuration +;;16-byte flash configuration field that stores default protection settings (loaded on reset) +;;and security information that allows the MCU to restrict acces to the FTFL module. + +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF + +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0^0xFF + +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1^0xFF + +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2^0xFF + +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3^0xFF + +nFEPROT EQU 0x00 +FEPROT EQU nFEPROT^0xFF + +nFDPROT EQU 0x00 +FDPROT EQU nFDPROT^0xFF + +FOPT EQU 0xFF + +FSEC EQU 0xFE + SECTION FlashConfig:CONST:REORDER:ROOT(2) +Config: + DATA + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0, FPROT1, FPROT2, FPROT3 + DCB FSEC, FOPT, FEPROT, FDPROT +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA_ERR_IRQHandler + PUBWEAK FLASH_CC_IRQHandler + PUBWEAK FLASH_RC_IRQHandler + PUBWEAK VLD_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK WDOG_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK I2S0_IRQHandler + PUBWEAK I2S1_IRQHandler + PUBWEAK UART0_LON_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART0_ERR_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART1_ERR_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK UART2_ERR_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK CMP1_IRQHandler + PUBWEAK FTM0_IRQHandler + PUBWEAK FTM1_IRQHandler + PUBWEAK CMT_IRQHandler + PUBWEAK RTC_ALRM_IRQHandler + PUBWEAK RTC_SEC_IRQHandler + PUBWEAK PIT0_IRQHandler + PUBWEAK PIT1_IRQHandler + PUBWEAK PIT2_IRQHandler + PUBWEAK PIT3_IRQHandler + PUBWEAK PDB_IRQHandler + PUBWEAK USB_OTG_IRQHandler + PUBWEAK USB_CD_IRQHandler + PUBWEAK TSI_IRQHandler + PUBWEAK MCG_IRQHandler + PUBWEAK LPT_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTB_IRQHandler + PUBWEAK PORTC_IRQHandler + PUBWEAK PORTD_IRQHandler + PUBWEAK PORTE_IRQHandler + PUBWEAK SW_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB +NMI_Handler +HardFault_Handler +MemManage_Handler +BusFault_Handler +UsageFault_Handler +SVC_Handler +DebugMon_Handler +PendSV_Handler +SysTick_Handler +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +DMA_ERR_IRQHandler +FLASH_CC_IRQHandler +FLASH_RC_IRQHandler +VLD_IRQHandler +LLWU_IRQHandler +WDOG_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +I2S0_IRQHandler +I2S1_IRQHandler +UART0_LON_IRQHandler +UART0_IRQHandler +UART0_ERR_IRQHandler +UART1_IRQHandler +UART1_ERR_IRQHandler +UART2_IRQHandler +UART2_ERR_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +CMT_IRQHandler +RTC_ALRM_IRQHandler +RTC_SEC_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB_IRQHandler +USB_OTG_IRQHandler +USB_CD_IRQHandler +TSI_IRQHandler +MCG_IRQHandler +LPT_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SW_IRQHandler +Default_Handler + + B Default_Handler + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2015 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC11U24 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "MK20D5.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; i<NVIC_NUM_VECTORS; i++) { + vectors[i] = old_vectors[i]; + } + SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + 16] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + 16]; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,278 @@ +/* +** ################################################################### +** Compilers: ARM Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011 +** K20P32M50SF0RM Rev. 1, Oct 2011 +** K20P48M50SF0RM Rev. 1, Oct 2011 +** +** Version: rev. 1.0, 2011-12-15 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2011-12-15) +** Initial version +** +** ################################################################### +*/ + +/** + * @file MK20D5 + * @version 1.0 + * @date 2011-12-15 + * @brief Device specific configuration file for MK20D5 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include <stdint.h> +#include "MK20D5.h" + +#define DISABLE_WDOG 1 + +#define CLOCK_SETUP 1 +/* Predefined clock setups + 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode + Reference clock source for MCG module is the slow internal clock source 32.768kHz + Core clock = 41.94MHz, BusClock = 41.94MHz + 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode + Reference clock source for MCG module is an external crystal 8MHz + Core clock = 48MHz, BusClock = 48MHz + 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode + Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication + Core clock = 8MHz, BusClock = 8MHz +*/ + +/*---------------------------------------------------------------------------- + Define clock source values + *----------------------------------------------------------------------------*/ +#if (CLOCK_SETUP == 0) + #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */ +#elif (CLOCK_SETUP == 1) + #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#elif (CLOCK_SETUP == 2) + #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */ +#endif /* (CLOCK_SETUP == 2) */ + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { +#if (DISABLE_WDOG) + /* Disable the WDOG module */ + /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */ + WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */ + /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */ + WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */ + /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ + WDOG->STCTRLH = (uint16_t)0x01D2u; +#endif /* (DISABLE_WDOG) */ +#if (CLOCK_SETUP == 0) + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* Switch to FEI Mode */ + /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x06u; + /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x00u; + /* MCG_C4: DMX32=0,DRST_DRS=1 */ + MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u); + /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ + MCG->C5 = (uint8_t)0x00u; + /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x00u; + while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */ + } + while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */ + } +#elif (CLOCK_SETUP == 1) + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* Switch to FBE Mode */ + /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + OSC0->CR = (uint8_t)0x00u; + /* MCG->C7: OSCSEL=0 */ + MCG->C7 = (uint8_t)0x00u; + /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x24u; + /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x9Au; + /* MCG->C4: DMX32=0,DRST_DRS=0 */ + MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; + /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = (uint8_t)0x03u; + /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x00u; + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ + } +#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ + while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ + } +#endif + while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ + } + /* Switch to PBE Mode */ + /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = (uint8_t)0x03u; + /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x40u; + while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */ + } + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ + } + /* Switch to PEE Mode */ + /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x1Au; + while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */ + } + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ + } +#elif (CLOCK_SETUP == 2) + /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* Switch to FBE Mode */ + /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + OSC0->CR = (uint8_t)0x00u; + /* MCG->C7: OSCSEL=0 */ + MCG->C7 = (uint8_t)0x00u; + /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x24u; + /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x9Au; + /* MCG->C4: DMX32=0,DRST_DRS=0 */ + MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; + /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ + MCG->C5 = (uint8_t)0x00u; + /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x00u; + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ + } +#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ + while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ + } +#endif + while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ + } + /* Switch to BLPE Mode */ + /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x24u; +#endif /* (CLOCK_SETUP == 2) */ +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ + uint8_t Divider; + + if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { + /* Output of FLL or PLL is selected */ + if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { + /* FLL is selected */ + if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { + /* External reference clock is selected */ + if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ + if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { + MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */ + } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */ + } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ + } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ + /* Select correct multiplier to calculate the MCG output clock */ + switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { + case 0x0u: + MCGOUTClock *= 640u; + break; + case 0x20u: + MCGOUTClock *= 1280u; + break; + case 0x40u: + MCGOUTClock *= 1920u; + break; + case 0x60u: + MCGOUTClock *= 2560u; + break; + case 0x80u: + MCGOUTClock *= 732u; + break; + case 0xA0u: + MCGOUTClock *= 1464u; + break; + case 0xC0u: + MCGOUTClock *= 2197u; + break; + case 0xE0u: + MCGOUTClock *= 2929u; + break; + default: + break; + } + } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ + /* PLL is selected */ + Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); + MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ + Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); + MCGOUTClock *= Divider; /* Calculate the MCG output clock */ + } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { + /* Internal reference clock is selected */ + if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ + } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ + MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ + } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { + /* External reference clock is selected */ + if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ + /* Reserved value */ + return; + } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ + SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,87 @@ +/* +** ################################################################### +** Compilers: ARM Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011 +** K20P32M50SF0RM Rev. 1, Oct 2011 +** K20P48M50SF0RM Rev. 1, Oct 2011 +** +** Version: rev. 2.0, 2012-03-19 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2011-12-15) +** Initial version +** - rev. 2.0 (2012-03-19) +** PDB Peripheral register structure updated. +** DMA Registers and bits for unsupported DMA channels removed. +** +** ################################################################### +*/ + +/** + * @file MK20D5 + * @version 2.0 + * @date 2012-03-19 + * @brief Device specific configuration file for MK20D5 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef SYSTEM_MK20D5_H_ +#define SYSTEM_MK20D5_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* #if !defined(SYSTEM_MK20D5_H_) */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,6032 @@ +/* +** ################################################################### +** Processors: MK20DX64VLH7 +** MK20DX128VLH7 +** MK20DX256VLH7 +** MK20DX64VLK7 +** MK20DX128VLK7 +** MK20DX256VLK7 +** MK20DX128VLL7 +** MK20DX256VLL7 +** MK20DX64VMB7 +** MK20DX128VMB7 +** MK20DX256VMB7 +** MK20DX128VML7 +** MK20DX256VML7 +** +** Compilers: ARM Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: Kxx (P1 silicon) Sub-Family Reference Manual Rev. 0, draft A Oct 2011 +** Version: rev. 1.0, 2012-01-15 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2012-01-15) +** Initial public version. +** +** ################################################################### +*/ + +/** + * @file MK20DX256.h + * @version 2.0 + * @date 2012-03-19 + * @brief CMSIS Peripheral Access Layer for MK20DX256 + * + * CMSIS Peripheral Access Layer for MK20DX256 + */ + +#if !defined(MK20DX256_H_) +#define MK20DX256_H_ /**< Symbol preventing repeated inclusion */ +#define MCU_MK20DX256 +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0200u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000u + +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +typedef enum IRQn { + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + + DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */ + DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */ + DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */ + DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */ + DMA4_IRQn = 4, + DMA5_IRQn = 5, + DMA6_IRQn = 6, + DMA7_IRQn = 7, + DMA8_IRQn = 8, + DMA9_IRQn = 9, + DMA10_IRQn = 10, + DMA11_IRQn = 11, + DMA12_IRQn = 12, + DMA13_IRQn = 13, + DMA14_IRQn = 14, + DMA15_IRQn = 15, + DMA_Error_IRQn = 16, /**< DMA error interrupt */ + Reserved33_IRQn = 17, + FTFL_IRQn = 18, /**< FTFL interrupt */ + Read_Collision_IRQn = 19, /**< Read collision interrupt */ + LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ + LLW_IRQn = 21, /**< Low Leakage Wakeup */ + Watchdog_IRQn = 22, /**< WDOG interrupt */ + Reserved39_IRQn = 23, + I2C0_IRQn = 24, /**< I2C0 interrupt */ + I2C1_IRQn = 25, + SPI0_IRQn = 26, /**< SPI0 interrupt */ + SPI1_IRQn = 27, + Reserved44_IRQn = 28, + CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 OR'd message buffers interrupt */ + CAN0_Bus_Off_IRQn = 30, /**< CAN0 bus off interrupt */ + CAN0_Error_IRQn = 31, /**< CAN0 error interrupt */ + CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx warning interrupt */ + CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx warning interrupt */ + CAN0_Wake_Up_IRQn = 34, /**< CAN0 wake up interrupt */ + I2S0_Tx_IRQn = 35, /**< I2S0 transmit interrupt */ + I2S0_Rx_IRQn = 36, /**< I2S0 receive interrupt */ + Reserved53_IRQn = 37, + Reserved54_IRQn = 38, + Reserved55_IRQn = 39, + Reserved56_IRQn = 40, + Reserved57_IRQn = 41, + Reserved58_IRQn = 42, + Reserved59_IRQn = 43, + UART0_LON_IRQn = 44, /**< UART0 LON interrupt */ + UART0_RX_TX_IRQn = 45, /**< UART0 receive/transmit interrupt */ + UART0_ERR_IRQn = 46, /**< UART0 error interrupt */ + UART1_RX_TX_IRQn = 47, /**< UART1 receive/transmit interrupt */ + UART1_ERR_IRQn = 48, /**< UART1 error interrupt */ + UART2_RX_TX_IRQn = 49, /**< UART2 receive/transmit interrupt */ + UART2_ERR_IRQn = 50, /**< UART2 error interrupt */ + Reserved67_IRQn = 51, + Reserved68_IRQn = 52, + Reserved69_IRQn = 53, + Reserved70_IRQn = 54, + Reserved71_IRQn = 55, + Reserved72_IRQn = 56, + ADC0_IRQn = 57, /**< ADC0 interrupt */ + ADC1_IRQn = 58, + CMP0_IRQn = 59, /**< CMP0 interrupt */ + CMP1_IRQn = 60, /**< CMP1 interrupt */ + CMP2_IRQn = 61, + FTM0_IRQn = 62, /**< FTM0 fault, overflow and channels interrupt */ + FTM1_IRQn = 63, /**< FTM1 fault, overflow and channels interrupt */ + FTM2_IRQn = 64, + CMT_IRQn = 65, /**< CMT interrupt */ + RTC_IRQn = 66, /**< RTC interrupt */ + RTC_Seconds_IRQn = 67, /**< RTC seconds interrupt */ + PIT0_IRQn = 68, /**< PIT timer channel 0 interrupt */ + PIT1_IRQn = 69, /**< PIT timer channel 1 interrupt */ + PIT2_IRQn = 70, /**< PIT timer channel 2 interrupt */ + PIT3_IRQn = 71, /**< PIT timer channel 3 interrupt */ + PDB0_IRQn = 72, /**< PDB0 interrupt */ + USB0_IRQn = 73, /**< USB0 interrupt */ + USBDCD_IRQn = 74, /**< USBDCD interrupt */ + Reserved91_IRQn = 75, + Reserved92_IRQn = 76, + Reserved93_IRQn = 77, + Reserved94_IRQn = 78, + Reserved95_IRQn = 79, + Reserved96_IRQn = 80, + DAC0_IRQn = 81, + Reserved98_IRQn = 82, + TSI0_IRQn = 83, /**< TSI0 interrupt */ + MCG_IRQn = 84, /**< MCG interrupt */ + LPTimer_IRQn = 85, /**< LPTimer interrupt */ + Reserved102_IRQn = 86, + PORTA_IRQn = 87, /**< Port A interrupt */ + PORTB_IRQn = 88, /**< Port B interrupt */ + PORTC_IRQn = 89, /**< Port C interrupt */ + PORTD_IRQn = 90, /**< Port D interrupt */ + PORTE_IRQn = 91, /**< Port E interrupt */ + Reserved108_IRQn = 92, + Reserved109_IRQn = 93, + SWI_IRQn = 94 /**< Software interrupt */ + +} IRQn_Type; + +/** + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ +#include "system_MK20DX256.h" /* Device specific configuration file */ + +/** + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */ + __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */ + __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */ + __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */ + __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */ + __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */ + __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */ + __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */ + __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */ + __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */ + __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */ + __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */ + __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */ + __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */ + __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */ + __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */ + __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */ + __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */ + __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */ + __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */ + __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */ + __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */ + __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* SC1 Bit Fields */ +#define ADC_SC1_ADCH_MASK 0x1Fu +#define ADC_SC1_ADCH_SHIFT 0 +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK) +#define ADC_SC1_DIFF_MASK 0x20u +#define ADC_SC1_DIFF_SHIFT 5 +#define ADC_SC1_AIEN_MASK 0x40u +#define ADC_SC1_AIEN_SHIFT 6 +#define ADC_SC1_COCO_MASK 0x80u +#define ADC_SC1_COCO_SHIFT 7 +/* CFG1 Bit Fields */ +#define ADC_CFG1_ADICLK_MASK 0x3u +#define ADC_CFG1_ADICLK_SHIFT 0 +#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK) +#define ADC_CFG1_MODE_MASK 0xCu +#define ADC_CFG1_MODE_SHIFT 2 +#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK) +#define ADC_CFG1_ADLSMP_MASK 0x10u +#define ADC_CFG1_ADLSMP_SHIFT 4 +#define ADC_CFG1_ADIV_MASK 0x60u +#define ADC_CFG1_ADIV_SHIFT 5 +#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK) +#define ADC_CFG1_ADLPC_MASK 0x80u +#define ADC_CFG1_ADLPC_SHIFT 7 +/* CFG2 Bit Fields */ +#define ADC_CFG2_ADLSTS_MASK 0x3u +#define ADC_CFG2_ADLSTS_SHIFT 0 +#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK) +#define ADC_CFG2_ADHSC_MASK 0x4u +#define ADC_CFG2_ADHSC_SHIFT 2 +#define ADC_CFG2_ADACKEN_MASK 0x8u +#define ADC_CFG2_ADACKEN_SHIFT 3 +#define ADC_CFG2_MUXSEL_MASK 0x10u +#define ADC_CFG2_MUXSEL_SHIFT 4 +/* R Bit Fields */ +#define ADC_R_D_MASK 0xFFFFu +#define ADC_R_D_SHIFT 0 +#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK) +/* CV1 Bit Fields */ +#define ADC_CV1_CV_MASK 0xFFFFu +#define ADC_CV1_CV_SHIFT 0 +#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK) +/* CV2 Bit Fields */ +#define ADC_CV2_CV_MASK 0xFFFFu +#define ADC_CV2_CV_SHIFT 0 +#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK) +/* SC2 Bit Fields */ +#define ADC_SC2_REFSEL_MASK 0x3u +#define ADC_SC2_REFSEL_SHIFT 0 +#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK) +#define ADC_SC2_DMAEN_MASK 0x4u +#define ADC_SC2_DMAEN_SHIFT 2 +#define ADC_SC2_ACREN_MASK 0x8u +#define ADC_SC2_ACREN_SHIFT 3 +#define ADC_SC2_ACFGT_MASK 0x10u +#define ADC_SC2_ACFGT_SHIFT 4 +#define ADC_SC2_ACFE_MASK 0x20u +#define ADC_SC2_ACFE_SHIFT 5 +#define ADC_SC2_ADTRG_MASK 0x40u +#define ADC_SC2_ADTRG_SHIFT 6 +#define ADC_SC2_ADACT_MASK 0x80u +#define ADC_SC2_ADACT_SHIFT 7 +/* SC3 Bit Fields */ +#define ADC_SC3_AVGS_MASK 0x3u +#define ADC_SC3_AVGS_SHIFT 0 +#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK) +#define ADC_SC3_AVGE_MASK 0x4u +#define ADC_SC3_AVGE_SHIFT 2 +#define ADC_SC3_ADCO_MASK 0x8u +#define ADC_SC3_ADCO_SHIFT 3 +#define ADC_SC3_CALF_MASK 0x40u +#define ADC_SC3_CALF_SHIFT 6 +#define ADC_SC3_CAL_MASK 0x80u +#define ADC_SC3_CAL_SHIFT 7 +/* OFS Bit Fields */ +#define ADC_OFS_OFS_MASK 0xFFFFu +#define ADC_OFS_OFS_SHIFT 0 +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK) +/* PG Bit Fields */ +#define ADC_PG_PG_MASK 0xFFFFu +#define ADC_PG_PG_SHIFT 0 +#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK) +/* MG Bit Fields */ +#define ADC_MG_MG_MASK 0xFFFFu +#define ADC_MG_MG_SHIFT 0 +#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK) +/* CLPD Bit Fields */ +#define ADC_CLPD_CLPD_MASK 0x3Fu +#define ADC_CLPD_CLPD_SHIFT 0 +#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK) +/* CLPS Bit Fields */ +#define ADC_CLPS_CLPS_MASK 0x3Fu +#define ADC_CLPS_CLPS_SHIFT 0 +#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK) +/* CLP4 Bit Fields */ +#define ADC_CLP4_CLP4_MASK 0x3FFu +#define ADC_CLP4_CLP4_SHIFT 0 +#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK) +/* CLP3 Bit Fields */ +#define ADC_CLP3_CLP3_MASK 0x1FFu +#define ADC_CLP3_CLP3_SHIFT 0 +#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK) +/* CLP2 Bit Fields */ +#define ADC_CLP2_CLP2_MASK 0xFFu +#define ADC_CLP2_CLP2_SHIFT 0 +#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK) +/* CLP1 Bit Fields */ +#define ADC_CLP1_CLP1_MASK 0x7Fu +#define ADC_CLP1_CLP1_SHIFT 0 +#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK) +/* CLP0 Bit Fields */ +#define ADC_CLP0_CLP0_MASK 0x3Fu +#define ADC_CLP0_CLP0_SHIFT 0 +#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK) +/* CLMD Bit Fields */ +#define ADC_CLMD_CLMD_MASK 0x3Fu +#define ADC_CLMD_CLMD_SHIFT 0 +#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK) +/* CLMS Bit Fields */ +#define ADC_CLMS_CLMS_MASK 0x3Fu +#define ADC_CLMS_CLMS_SHIFT 0 +#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK) +/* CLM4 Bit Fields */ +#define ADC_CLM4_CLM4_MASK 0x3FFu +#define ADC_CLM4_CLM4_SHIFT 0 +#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK) +/* CLM3 Bit Fields */ +#define ADC_CLM3_CLM3_MASK 0x1FFu +#define ADC_CLM3_CLM3_SHIFT 0 +#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK) +/* CLM2 Bit Fields */ +#define ADC_CLM2_CLM2_MASK 0xFFu +#define ADC_CLM2_CLM2_SHIFT 0 +#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK) +/* CLM1 Bit Fields */ +#define ADC_CLM1_CLM1_MASK 0x7Fu +#define ADC_CLM1_CLM1_SHIFT 0 +#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK) +/* CLM0 Bit Fields */ +#define ADC_CLM0_CLM0_MASK 0x3Fu +#define ADC_CLM0_CLM0_SHIFT 0 +#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK) + +/** + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x4003B000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) + +/** + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer + * @{ + */ + +/** CMP - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ + __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ + __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ + __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ + __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ + __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ +} CMP_Type; + +/* ---------------------------------------------------------------------------- + -- CMP Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CMP_Register_Masks CMP Register Masks + * @{ + */ + +/* CR0 Bit Fields */ +#define CMP_CR0_HYSTCTR_MASK 0x3u +#define CMP_CR0_HYSTCTR_SHIFT 0 +#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK) +#define CMP_CR0_FILTER_CNT_MASK 0x70u +#define CMP_CR0_FILTER_CNT_SHIFT 4 +#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK) +/* CR1 Bit Fields */ +#define CMP_CR1_EN_MASK 0x1u +#define CMP_CR1_EN_SHIFT 0 +#define CMP_CR1_OPE_MASK 0x2u +#define CMP_CR1_OPE_SHIFT 1 +#define CMP_CR1_COS_MASK 0x4u +#define CMP_CR1_COS_SHIFT 2 +#define CMP_CR1_INV_MASK 0x8u +#define CMP_CR1_INV_SHIFT 3 +#define CMP_CR1_PMODE_MASK 0x10u +#define CMP_CR1_PMODE_SHIFT 4 +#define CMP_CR1_WE_MASK 0x40u +#define CMP_CR1_WE_SHIFT 6 +#define CMP_CR1_SE_MASK 0x80u +#define CMP_CR1_SE_SHIFT 7 +/* FPR Bit Fields */ +#define CMP_FPR_FILT_PER_MASK 0xFFu +#define CMP_FPR_FILT_PER_SHIFT 0 +#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK) +/* SCR Bit Fields */ +#define CMP_SCR_COUT_MASK 0x1u +#define CMP_SCR_COUT_SHIFT 0 +#define CMP_SCR_CFF_MASK 0x2u +#define CMP_SCR_CFF_SHIFT 1 +#define CMP_SCR_CFR_MASK 0x4u +#define CMP_SCR_CFR_SHIFT 2 +#define CMP_SCR_IEF_MASK 0x8u +#define CMP_SCR_IEF_SHIFT 3 +#define CMP_SCR_IER_MASK 0x10u +#define CMP_SCR_IER_SHIFT 4 +#define CMP_SCR_DMAEN_MASK 0x40u +#define CMP_SCR_DMAEN_SHIFT 6 +/* DACCR Bit Fields */ +#define CMP_DACCR_VOSEL_MASK 0x3Fu +#define CMP_DACCR_VOSEL_SHIFT 0 +#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK) +#define CMP_DACCR_VRSEL_MASK 0x40u +#define CMP_DACCR_VRSEL_SHIFT 6 +#define CMP_DACCR_DACEN_MASK 0x80u +#define CMP_DACCR_DACEN_SHIFT 7 +/* MUXCR Bit Fields */ +#define CMP_MUXCR_MSEL_MASK 0x7u +#define CMP_MUXCR_MSEL_SHIFT 0 +#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK) +#define CMP_MUXCR_PSEL_MASK 0x38u +#define CMP_MUXCR_PSEL_SHIFT 3 +#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK) + +/** + * @} + */ /* end of group CMP_Register_Masks */ + + +/* CMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x40073000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((CMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x40073008u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((CMP_Type *)CMP1_BASE) + +/** + * @} + */ /* end of group CMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer + * @{ + */ + +/** CMT - Register Layout Typedef */ +typedef struct { + __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */ + __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */ + __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */ + __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */ + __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */ + __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */ + __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */ + __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */ + __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */ + __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */ + __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */ + __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */ +} CMT_Type; + +/* ---------------------------------------------------------------------------- + -- CMT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CMT_Register_Masks CMT Register Masks + * @{ + */ + +/* CGH1 Bit Fields */ +#define CMT_CGH1_PH_MASK 0xFFu +#define CMT_CGH1_PH_SHIFT 0 +#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK) +/* CGL1 Bit Fields */ +#define CMT_CGL1_PL_MASK 0xFFu +#define CMT_CGL1_PL_SHIFT 0 +#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK) +/* CGH2 Bit Fields */ +#define CMT_CGH2_SH_MASK 0xFFu +#define CMT_CGH2_SH_SHIFT 0 +#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK) +/* CGL2 Bit Fields */ +#define CMT_CGL2_SL_MASK 0xFFu +#define CMT_CGL2_SL_SHIFT 0 +#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK) +/* OC Bit Fields */ +#define CMT_OC_IROPEN_MASK 0x20u +#define CMT_OC_IROPEN_SHIFT 5 +#define CMT_OC_CMTPOL_MASK 0x40u +#define CMT_OC_CMTPOL_SHIFT 6 +#define CMT_OC_IROL_MASK 0x80u +#define CMT_OC_IROL_SHIFT 7 +/* MSC Bit Fields */ +#define CMT_MSC_MCGEN_MASK 0x1u +#define CMT_MSC_MCGEN_SHIFT 0 +#define CMT_MSC_EOCIE_MASK 0x2u +#define CMT_MSC_EOCIE_SHIFT 1 +#define CMT_MSC_FSK_MASK 0x4u +#define CMT_MSC_FSK_SHIFT 2 +#define CMT_MSC_BASE_MASK 0x8u +#define CMT_MSC_BASE_SHIFT 3 +#define CMT_MSC_EXSPC_MASK 0x10u +#define CMT_MSC_EXSPC_SHIFT 4 +#define CMT_MSC_CMTDIV_MASK 0x60u +#define CMT_MSC_CMTDIV_SHIFT 5 +#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK) +#define CMT_MSC_EOCF_MASK 0x80u +#define CMT_MSC_EOCF_SHIFT 7 +/* CMD1 Bit Fields */ +#define CMT_CMD1_MB_MASK 0xFFu +#define CMT_CMD1_MB_SHIFT 0 +#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK) +/* CMD2 Bit Fields */ +#define CMT_CMD2_MB_MASK 0xFFu +#define CMT_CMD2_MB_SHIFT 0 +#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK) +/* CMD3 Bit Fields */ +#define CMT_CMD3_SB_MASK 0xFFu +#define CMT_CMD3_SB_SHIFT 0 +#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK) +/* CMD4 Bit Fields */ +#define CMT_CMD4_SB_MASK 0xFFu +#define CMT_CMD4_SB_SHIFT 0 +#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK) +/* PPS Bit Fields */ +#define CMT_PPS_PPSDIV_MASK 0xFu +#define CMT_PPS_PPSDIV_SHIFT 0 +#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK) +/* DMA Bit Fields */ +#define CMT_DMA_DMA_MASK 0x1u +#define CMT_DMA_DMA_SHIFT 0 + +/** + * @} + */ /* end of group CMT_Register_Masks */ + + +/* CMT - Peripheral instance base addresses */ +/** Peripheral CMT base address */ +#define CMT_BASE (0x40062000u) +/** Peripheral CMT base pointer */ +#define CMT ((CMT_Type *)CMT_BASE) + +/** + * @} + */ /* end of group CMT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */ + __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */ + } ACCESS16BIT; + __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */ + __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */ + __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */ + __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */ + } ACCESS8BIT; + }; + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ + __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ + } GPOLY_ACCESS16BIT; + __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ + __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ + __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ + __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ + } GPOLY_ACCESS8BIT; + }; + union { /* offset: 0x8 */ + __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */ + struct { /* offset: 0x8 */ + uint8_t RESERVED_0[3]; + __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ + } CTRL_ACCESS8BIT; + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/* CRCL Bit Fields */ +#define CRC_CRCL_CRCL_MASK 0xFFFFu +#define CRC_CRCL_CRCL_SHIFT 0 +#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK) +/* CRCH Bit Fields */ +#define CRC_CRCH_CRCH_MASK 0xFFFFu +#define CRC_CRCH_CRCH_SHIFT 0 +#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK) +/* CRC Bit Fields */ +#define CRC_CRC_LL_MASK 0xFFu +#define CRC_CRC_LL_SHIFT 0 +#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK) +#define CRC_CRC_LU_MASK 0xFF00u +#define CRC_CRC_LU_SHIFT 8 +#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK) +#define CRC_CRC_HL_MASK 0xFF0000u +#define CRC_CRC_HL_SHIFT 16 +#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK) +#define CRC_CRC_HU_MASK 0xFF000000u +#define CRC_CRC_HU_SHIFT 24 +#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK) +/* CRCLL Bit Fields */ +#define CRC_CRCLL_CRCLL_MASK 0xFFu +#define CRC_CRCLL_CRCLL_SHIFT 0 +#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK) +/* CRCLU Bit Fields */ +#define CRC_CRCLU_CRCLU_MASK 0xFFu +#define CRC_CRCLU_CRCLU_SHIFT 0 +#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK) +/* CRCHL Bit Fields */ +#define CRC_CRCHL_CRCHL_MASK 0xFFu +#define CRC_CRCHL_CRCHL_SHIFT 0 +#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK) +/* CRCHU Bit Fields */ +#define CRC_CRCHU_CRCHU_MASK 0xFFu +#define CRC_CRCHU_CRCHU_SHIFT 0 +#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK) +/* GPOLYL Bit Fields */ +#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu +#define CRC_GPOLYL_GPOLYL_SHIFT 0 +#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK) +/* GPOLYH Bit Fields */ +#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu +#define CRC_GPOLYH_GPOLYH_SHIFT 0 +#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK) +/* GPOLY Bit Fields */ +#define CRC_GPOLY_LOW_MASK 0xFFFFu +#define CRC_GPOLY_LOW_SHIFT 0 +#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK) +#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u +#define CRC_GPOLY_HIGH_SHIFT 16 +#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK) +/* GPOLYLL Bit Fields */ +#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu +#define CRC_GPOLYLL_GPOLYLL_SHIFT 0 +#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK) +/* GPOLYLU Bit Fields */ +#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu +#define CRC_GPOLYLU_GPOLYLU_SHIFT 0 +#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK) +/* GPOLYHL Bit Fields */ +#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu +#define CRC_GPOLYHL_GPOLYHL_SHIFT 0 +#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK) +/* GPOLYHU Bit Fields */ +#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu +#define CRC_GPOLYHU_GPOLYHU_SHIFT 0 +#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK) +/* CTRL Bit Fields */ +#define CRC_CTRL_TCRC_MASK 0x1000000u +#define CRC_CTRL_TCRC_SHIFT 24 +#define CRC_CTRL_WAS_MASK 0x2000000u +#define CRC_CTRL_WAS_SHIFT 25 +#define CRC_CTRL_FXOR_MASK 0x4000000u +#define CRC_CTRL_FXOR_SHIFT 26 +#define CRC_CTRL_TOTR_MASK 0x30000000u +#define CRC_CTRL_TOTR_SHIFT 28 +#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK) +#define CRC_CTRL_TOT_MASK 0xC0000000u +#define CRC_CTRL_TOT_SHIFT 30 +#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK) +/* CTRLHU Bit Fields */ +#define CRC_CTRLHU_TCRC_MASK 0x1u +#define CRC_CTRLHU_TCRC_SHIFT 0 +#define CRC_CTRLHU_WAS_MASK 0x2u +#define CRC_CTRLHU_WAS_SHIFT 1 +#define CRC_CTRLHU_FXOR_MASK 0x4u +#define CRC_CTRLHU_FXOR_SHIFT 2 +#define CRC_CTRLHU_TOTR_MASK 0x30u +#define CRC_CTRLHU_TOTR_SHIFT 4 +#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK) +#define CRC_CTRLHU_TOT_MASK 0xC0u +#define CRC_CTRLHU_TOT_SHIFT 6 +#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK) + +/** + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC base address */ +#define CRC_BASE (0x40032000u) +/** Peripheral CRC base pointer */ +#define CRC0 ((CRC_Type *)CRC_BASE) + +/** + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DAC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer + * @{ + */ + +/** DAC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x2 */ + __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ + __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ + } DAT[16]; + __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ + __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ + __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ + __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ +} DAC_Type, *DAC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- DAC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DAC_Register_Masks DAC Register Masks + * @{ + */ + +/* DATL Bit Fields */ +#define DAC_DATL_DATA0_MASK 0xFFu +#define DAC_DATL_DATA0_SHIFT 0 +#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK) +/* DATH Bit Fields */ +#define DAC_DATH_DATA1_MASK 0xFu +#define DAC_DATH_DATA1_SHIFT 0 +#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK) +/* SR Bit Fields */ +#define DAC_SR_DACBFRPBF_MASK 0x1u +#define DAC_SR_DACBFRPBF_SHIFT 0 +#define DAC_SR_DACBFRPTF_MASK 0x2u +#define DAC_SR_DACBFRPTF_SHIFT 1 +#define DAC_SR_DACBFWMF_MASK 0x4u +#define DAC_SR_DACBFWMF_SHIFT 2 +/* C0 Bit Fields */ +#define DAC_C0_DACBBIEN_MASK 0x1u +#define DAC_C0_DACBBIEN_SHIFT 0 +#define DAC_C0_DACBTIEN_MASK 0x2u +#define DAC_C0_DACBTIEN_SHIFT 1 +#define DAC_C0_DACBWIEN_MASK 0x4u +#define DAC_C0_DACBWIEN_SHIFT 2 +#define DAC_C0_LPEN_MASK 0x8u +#define DAC_C0_LPEN_SHIFT 3 +#define DAC_C0_DACSWTRG_MASK 0x10u +#define DAC_C0_DACSWTRG_SHIFT 4 +#define DAC_C0_DACTRGSEL_MASK 0x20u +#define DAC_C0_DACTRGSEL_SHIFT 5 +#define DAC_C0_DACRFS_MASK 0x40u +#define DAC_C0_DACRFS_SHIFT 6 +#define DAC_C0_DACEN_MASK 0x80u +#define DAC_C0_DACEN_SHIFT 7 +/* C1 Bit Fields */ +#define DAC_C1_DACBFEN_MASK 0x1u +#define DAC_C1_DACBFEN_SHIFT 0 +#define DAC_C1_DACBFMD_MASK 0x6u +#define DAC_C1_DACBFMD_SHIFT 1 +#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK) +#define DAC_C1_DACBFWM_MASK 0x18u +#define DAC_C1_DACBFWM_SHIFT 3 +#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK) +#define DAC_C1_DMAEN_MASK 0x80u +#define DAC_C1_DMAEN_SHIFT 7 +/* C2 Bit Fields */ +#define DAC_C2_DACBFUP_MASK 0xFu +#define DAC_C2_DACBFUP_SHIFT 0 +#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK) +#define DAC_C2_DACBFRP_MASK 0xF0u +#define DAC_C2_DACBFRP_SHIFT 4 +#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK) + +/** + * @} + */ /* end of group DAC_Register_Masks */ + + +/* DAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x400CC000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((DAC_Type *)DAC0_BASE) +/** Array initializer of DAC peripheral base pointers */ +#define DAC_BASES { DAC0 } + +/** + * @} + */ /* end of group DAC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control Register, offset: 0x0 */ + __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ + uint8_t RESERVED_1[4]; + __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ + __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ + __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ + __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ + __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ + __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ + __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ + __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ + __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ + uint8_t RESERVED_2[4]; + __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ + uint8_t RESERVED_4[4]; + __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ + uint8_t RESERVED_5[200]; + __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ + __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ + __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ + __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ + uint8_t RESERVED_6[3836]; + struct { /* offset: 0x1000, array step: 0x20 */ + __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ + __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ + __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ + union { /* offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */ + }; + __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ + __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ + __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ + union { /* offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ + }; + __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ + __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ + union { /* offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ + }; + } TCD[4]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define DMA_CR_EDBG_MASK 0x2u +#define DMA_CR_EDBG_SHIFT 1 +#define DMA_CR_ERCA_MASK 0x4u +#define DMA_CR_ERCA_SHIFT 2 +#define DMA_CR_HOE_MASK 0x10u +#define DMA_CR_HOE_SHIFT 4 +#define DMA_CR_HALT_MASK 0x20u +#define DMA_CR_HALT_SHIFT 5 +#define DMA_CR_CLM_MASK 0x40u +#define DMA_CR_CLM_SHIFT 6 +#define DMA_CR_EMLM_MASK 0x80u +#define DMA_CR_EMLM_SHIFT 7 +#define DMA_CR_ECX_MASK 0x10000u +#define DMA_CR_ECX_SHIFT 16 +#define DMA_CR_CX_MASK 0x20000u +#define DMA_CR_CX_SHIFT 17 +/* ES Bit Fields */ +#define DMA_ES_DBE_MASK 0x1u +#define DMA_ES_DBE_SHIFT 0 +#define DMA_ES_SBE_MASK 0x2u +#define DMA_ES_SBE_SHIFT 1 +#define DMA_ES_SGE_MASK 0x4u +#define DMA_ES_SGE_SHIFT 2 +#define DMA_ES_NCE_MASK 0x8u +#define DMA_ES_NCE_SHIFT 3 +#define DMA_ES_DOE_MASK 0x10u +#define DMA_ES_DOE_SHIFT 4 +#define DMA_ES_DAE_MASK 0x20u +#define DMA_ES_DAE_SHIFT 5 +#define DMA_ES_SOE_MASK 0x40u +#define DMA_ES_SOE_SHIFT 6 +#define DMA_ES_SAE_MASK 0x80u +#define DMA_ES_SAE_SHIFT 7 +#define DMA_ES_ERRCHN_MASK 0xF00u +#define DMA_ES_ERRCHN_SHIFT 8 +#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK) +#define DMA_ES_CPE_MASK 0x4000u +#define DMA_ES_CPE_SHIFT 14 +#define DMA_ES_ECX_MASK 0x10000u +#define DMA_ES_ECX_SHIFT 16 +#define DMA_ES_VLD_MASK 0x80000000u +#define DMA_ES_VLD_SHIFT 31 +/* ERQ Bit Fields */ +#define DMA_ERQ_ERQ0_MASK 0x1u +#define DMA_ERQ_ERQ0_SHIFT 0 +#define DMA_ERQ_ERQ1_MASK 0x2u +#define DMA_ERQ_ERQ1_SHIFT 1 +#define DMA_ERQ_ERQ2_MASK 0x4u +#define DMA_ERQ_ERQ2_SHIFT 2 +#define DMA_ERQ_ERQ3_MASK 0x8u +#define DMA_ERQ_ERQ3_SHIFT 3 +/* EEI Bit Fields */ +#define DMA_EEI_EEI0_MASK 0x1u +#define DMA_EEI_EEI0_SHIFT 0 +#define DMA_EEI_EEI1_MASK 0x2u +#define DMA_EEI_EEI1_SHIFT 1 +#define DMA_EEI_EEI2_MASK 0x4u +#define DMA_EEI_EEI2_SHIFT 2 +#define DMA_EEI_EEI3_MASK 0x8u +#define DMA_EEI_EEI3_SHIFT 3 +/* CEEI Bit Fields */ +#define DMA_CEEI_CEEI_MASK 0xFu +#define DMA_CEEI_CEEI_SHIFT 0 +#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK) +#define DMA_CEEI_CAEE_MASK 0x40u +#define DMA_CEEI_CAEE_SHIFT 6 +#define DMA_CEEI_NOP_MASK 0x80u +#define DMA_CEEI_NOP_SHIFT 7 +/* SEEI Bit Fields */ +#define DMA_SEEI_SEEI_MASK 0xFu +#define DMA_SEEI_SEEI_SHIFT 0 +#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK) +#define DMA_SEEI_SAEE_MASK 0x40u +#define DMA_SEEI_SAEE_SHIFT 6 +#define DMA_SEEI_NOP_MASK 0x80u +#define DMA_SEEI_NOP_SHIFT 7 +/* CERQ Bit Fields */ +#define DMA_CERQ_CERQ_MASK 0xFu +#define DMA_CERQ_CERQ_SHIFT 0 +#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK) +#define DMA_CERQ_CAER_MASK 0x40u +#define DMA_CERQ_CAER_SHIFT 6 +#define DMA_CERQ_NOP_MASK 0x80u +#define DMA_CERQ_NOP_SHIFT 7 +/* SERQ Bit Fields */ +#define DMA_SERQ_SERQ_MASK 0xFu +#define DMA_SERQ_SERQ_SHIFT 0 +#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK) +#define DMA_SERQ_SAER_MASK 0x40u +#define DMA_SERQ_SAER_SHIFT 6 +#define DMA_SERQ_NOP_MASK 0x80u +#define DMA_SERQ_NOP_SHIFT 7 +/* CDNE Bit Fields */ +#define DMA_CDNE_CDNE_MASK 0xFu +#define DMA_CDNE_CDNE_SHIFT 0 +#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK) +#define DMA_CDNE_CADN_MASK 0x40u +#define DMA_CDNE_CADN_SHIFT 6 +#define DMA_CDNE_NOP_MASK 0x80u +#define DMA_CDNE_NOP_SHIFT 7 +/* SSRT Bit Fields */ +#define DMA_SSRT_SSRT_MASK 0xFu +#define DMA_SSRT_SSRT_SHIFT 0 +#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK) +#define DMA_SSRT_SAST_MASK 0x40u +#define DMA_SSRT_SAST_SHIFT 6 +#define DMA_SSRT_NOP_MASK 0x80u +#define DMA_SSRT_NOP_SHIFT 7 +/* CERR Bit Fields */ +#define DMA_CERR_CERR_MASK 0xFu +#define DMA_CERR_CERR_SHIFT 0 +#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK) +#define DMA_CERR_CAEI_MASK 0x40u +#define DMA_CERR_CAEI_SHIFT 6 +#define DMA_CERR_NOP_MASK 0x80u +#define DMA_CERR_NOP_SHIFT 7 +/* CINT Bit Fields */ +#define DMA_CINT_CINT_MASK 0xFu +#define DMA_CINT_CINT_SHIFT 0 +#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK) +#define DMA_CINT_CAIR_MASK 0x40u +#define DMA_CINT_CAIR_SHIFT 6 +#define DMA_CINT_NOP_MASK 0x80u +#define DMA_CINT_NOP_SHIFT 7 +/* INT Bit Fields */ +#define DMA_INT_INT0_MASK 0x1u +#define DMA_INT_INT0_SHIFT 0 +#define DMA_INT_INT1_MASK 0x2u +#define DMA_INT_INT1_SHIFT 1 +#define DMA_INT_INT2_MASK 0x4u +#define DMA_INT_INT2_SHIFT 2 +#define DMA_INT_INT3_MASK 0x8u +#define DMA_INT_INT3_SHIFT 3 +/* ERR Bit Fields */ +#define DMA_ERR_ERR0_MASK 0x1u +#define DMA_ERR_ERR0_SHIFT 0 +#define DMA_ERR_ERR1_MASK 0x2u +#define DMA_ERR_ERR1_SHIFT 1 +#define DMA_ERR_ERR2_MASK 0x4u +#define DMA_ERR_ERR2_SHIFT 2 +#define DMA_ERR_ERR3_MASK 0x8u +#define DMA_ERR_ERR3_SHIFT 3 +/* HRS Bit Fields */ +#define DMA_HRS_HRS0_MASK 0x1u +#define DMA_HRS_HRS0_SHIFT 0 +#define DMA_HRS_HRS1_MASK 0x2u +#define DMA_HRS_HRS1_SHIFT 1 +#define DMA_HRS_HRS2_MASK 0x4u +#define DMA_HRS_HRS2_SHIFT 2 +#define DMA_HRS_HRS3_MASK 0x8u +#define DMA_HRS_HRS3_SHIFT 3 +/* DCHPRI3 Bit Fields */ +#define DMA_DCHPRI3_CHPRI_MASK 0xFu +#define DMA_DCHPRI3_CHPRI_SHIFT 0 +#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK) +#define DMA_DCHPRI3_DPA_MASK 0x40u +#define DMA_DCHPRI3_DPA_SHIFT 6 +#define DMA_DCHPRI3_ECP_MASK 0x80u +#define DMA_DCHPRI3_ECP_SHIFT 7 +/* DCHPRI2 Bit Fields */ +#define DMA_DCHPRI2_CHPRI_MASK 0xFu +#define DMA_DCHPRI2_CHPRI_SHIFT 0 +#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK) +#define DMA_DCHPRI2_DPA_MASK 0x40u +#define DMA_DCHPRI2_DPA_SHIFT 6 +#define DMA_DCHPRI2_ECP_MASK 0x80u +#define DMA_DCHPRI2_ECP_SHIFT 7 +/* DCHPRI1 Bit Fields */ +#define DMA_DCHPRI1_CHPRI_MASK 0xFu +#define DMA_DCHPRI1_CHPRI_SHIFT 0 +#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK) +#define DMA_DCHPRI1_DPA_MASK 0x40u +#define DMA_DCHPRI1_DPA_SHIFT 6 +#define DMA_DCHPRI1_ECP_MASK 0x80u +#define DMA_DCHPRI1_ECP_SHIFT 7 +/* DCHPRI0 Bit Fields */ +#define DMA_DCHPRI0_CHPRI_MASK 0xFu +#define DMA_DCHPRI0_CHPRI_SHIFT 0 +#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK) +#define DMA_DCHPRI0_DPA_MASK 0x40u +#define DMA_DCHPRI0_DPA_SHIFT 6 +#define DMA_DCHPRI0_ECP_MASK 0x80u +#define DMA_DCHPRI0_ECP_SHIFT 7 +/* SADDR Bit Fields */ +#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu +#define DMA_SADDR_SADDR_SHIFT 0 +#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK) +/* SOFF Bit Fields */ +#define DMA_SOFF_SOFF_MASK 0xFFFFu +#define DMA_SOFF_SOFF_SHIFT 0 +#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK) +/* ATTR Bit Fields */ +#define DMA_ATTR_DSIZE_MASK 0x7u +#define DMA_ATTR_DSIZE_SHIFT 0 +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK) +#define DMA_ATTR_DMOD_MASK 0xF8u +#define DMA_ATTR_DMOD_SHIFT 3 +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK) +#define DMA_ATTR_SSIZE_MASK 0x700u +#define DMA_ATTR_SSIZE_SHIFT 8 +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK) +#define DMA_ATTR_SMOD_MASK 0xF800u +#define DMA_ATTR_SMOD_SHIFT 11 +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK) +/* NBYTES_MLNO Bit Fields */ +#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu +#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0 +#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK) +/* NBYTES_MLOFFNO Bit Fields */ +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu +#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0 +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK) +#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u +#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30 +#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u +#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31 +/* NBYTES_MLOFFYES Bit Fields */ +#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu +#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0 +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK) +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u +#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10 +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK) +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u +#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30 +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u +#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31 +/* SLAST Bit Fields */ +#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu +#define DMA_SLAST_SLAST_SHIFT 0 +#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK) +/* DADDR Bit Fields */ +#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu +#define DMA_DADDR_DADDR_SHIFT 0 +#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK) +/* DOFF Bit Fields */ +#define DMA_DOFF_DOFF_MASK 0xFFFFu +#define DMA_DOFF_DOFF_SHIFT 0 +#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK) +/* CITER_ELINKNO Bit Fields */ +#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu +#define DMA_CITER_ELINKNO_CITER_SHIFT 0 +#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK) +#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u +#define DMA_CITER_ELINKNO_ELINK_SHIFT 15 +/* CITER_ELINKYES Bit Fields */ +#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu +#define DMA_CITER_ELINKYES_CITER_SHIFT 0 +#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK) +#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u +#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9 +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK) +#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u +#define DMA_CITER_ELINKYES_ELINK_SHIFT 15 +/* DLAST_SGA Bit Fields */ +#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu +#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0 +#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK) +/* CSR Bit Fields */ +#define DMA_CSR_START_MASK 0x1u +#define DMA_CSR_START_SHIFT 0 +#define DMA_CSR_INTMAJOR_MASK 0x2u +#define DMA_CSR_INTMAJOR_SHIFT 1 +#define DMA_CSR_INTHALF_MASK 0x4u +#define DMA_CSR_INTHALF_SHIFT 2 +#define DMA_CSR_DREQ_MASK 0x8u +#define DMA_CSR_DREQ_SHIFT 3 +#define DMA_CSR_ESG_MASK 0x10u +#define DMA_CSR_ESG_SHIFT 4 +#define DMA_CSR_MAJORELINK_MASK 0x20u +#define DMA_CSR_MAJORELINK_SHIFT 5 +#define DMA_CSR_ACTIVE_MASK 0x40u +#define DMA_CSR_ACTIVE_SHIFT 6 +#define DMA_CSR_DONE_MASK 0x80u +#define DMA_CSR_DONE_SHIFT 7 +#define DMA_CSR_MAJORLINKCH_MASK 0xF00u +#define DMA_CSR_MAJORLINKCH_SHIFT 8 +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK) +#define DMA_CSR_BWC_MASK 0xC000u +#define DMA_CSR_BWC_SHIFT 14 +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK) +/* BITER_ELINKNO Bit Fields */ +#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu +#define DMA_BITER_ELINKNO_BITER_SHIFT 0 +#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK) +#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u +#define DMA_BITER_ELINKNO_ELINK_SHIFT 15 +/* BITER_ELINKYES Bit Fields */ +#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu +#define DMA_BITER_ELINKYES_BITER_SHIFT 0 +#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK) +#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u +#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9 +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK) +#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u +#define DMA_BITER_ELINKYES_ELINK_SHIFT 15 + +/** + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA base address */ +#define DMA_BASE (0x40008000u) +/** Peripheral DMA base pointer */ +#define DMA0 ((DMA_Type *)DMA_BASE) + +/** + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer + * @{ + */ + +/** DMAMUX - Register Layout Typedef */ +typedef struct { + __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */ +} DMAMUX_Type; + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/* CHCFG Bit Fields */ +#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu +#define DMAMUX_CHCFG_SOURCE_SHIFT 0 +#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK) +#define DMAMUX_CHCFG_TRIG_MASK 0x40u +#define DMAMUX_CHCFG_TRIG_SHIFT 6 +#define DMAMUX_CHCFG_ENBL_MASK 0x80u +#define DMAMUX_CHCFG_ENBL_SHIFT 7 + +/** + * @} + */ /* end of group DMAMUX_Register_Masks */ + + +/* DMAMUX - Peripheral instance base addresses */ +/** Peripheral DMAMUX base address */ +#define DMAMUX_BASE (0x40021000u) +/** Peripheral DMAMUX base pointer */ +#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) + +/** + * @} + */ /* end of group DMAMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer + * @{ + */ + +/** EWM - Register Layout Typedef */ +typedef struct { + __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ + __O uint8_t SERV; /**< Service Register, offset: 0x1 */ + __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ + __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ +} EWM_Type; + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define EWM_CTRL_EWMEN_MASK 0x1u +#define EWM_CTRL_EWMEN_SHIFT 0 +#define EWM_CTRL_ASSIN_MASK 0x2u +#define EWM_CTRL_ASSIN_SHIFT 1 +#define EWM_CTRL_INEN_MASK 0x4u +#define EWM_CTRL_INEN_SHIFT 2 +#define EWM_CTRL_INTEN_MASK 0x8u +#define EWM_CTRL_INTEN_SHIFT 3 +/* SERV Bit Fields */ +#define EWM_SERV_SERVICE_MASK 0xFFu +#define EWM_SERV_SERVICE_SHIFT 0 +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK) +/* CMPL Bit Fields */ +#define EWM_CMPL_COMPAREL_MASK 0xFFu +#define EWM_CMPL_COMPAREL_SHIFT 0 +#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK) +/* CMPH Bit Fields */ +#define EWM_CMPH_COMPAREH_MASK 0xFFu +#define EWM_CMPH_COMPAREH_SHIFT 0 +#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK) + +/** + * @} + */ /* end of group EWM_Register_Masks */ + + +/* EWM - Peripheral instance base addresses */ +/** Peripheral EWM base address */ +#define EWM_BASE (0x40061000u) +/** Peripheral EWM base pointer */ +#define EWM ((EWM_Type *)EWM_BASE) + +/** + * @} + */ /* end of group EWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer + * @{ + */ + +/** FMC - Register Layout Typedef */ +typedef struct { + __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */ + __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */ + uint8_t RESERVED_0[248]; + struct { /* offset: 0x100, array step: 0x20 */ + __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */ + uint8_t RESERVED_0[24]; + } TAG_WAY[4]; + uint8_t RESERVED_1[132]; + struct { /* offset: 0x204, array step: 0x8 */ + __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */ + uint8_t RESERVED_0[4]; + } DATAW0S[2]; + uint8_t RESERVED_2[48]; + struct { /* offset: 0x244, array step: 0x8 */ + __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */ + uint8_t RESERVED_0[4]; + } DATAW1S[2]; + uint8_t RESERVED_3[48]; + struct { /* offset: 0x284, array step: 0x8 */ + __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */ + uint8_t RESERVED_0[4]; + } DATAW2S[2]; + uint8_t RESERVED_4[48]; + struct { /* offset: 0x2C4, array step: 0x8 */ + __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */ + uint8_t RESERVED_0[4]; + } DATAW3S[2]; +} FMC_Type; + +/* ---------------------------------------------------------------------------- + -- FMC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FMC_Register_Masks FMC Register Masks + * @{ + */ + +/* PFAPR Bit Fields */ +#define FMC_PFAPR_M0AP_MASK 0x3u +#define FMC_PFAPR_M0AP_SHIFT 0 +#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK) +#define FMC_PFAPR_M1AP_MASK 0xCu +#define FMC_PFAPR_M1AP_SHIFT 2 +#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK) +#define FMC_PFAPR_M2AP_MASK 0x30u +#define FMC_PFAPR_M2AP_SHIFT 4 +#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK) +#define FMC_PFAPR_M3AP_MASK 0xC0u +#define FMC_PFAPR_M3AP_SHIFT 6 +#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK) +#define FMC_PFAPR_M0PFD_MASK 0x10000u +#define FMC_PFAPR_M0PFD_SHIFT 16 +#define FMC_PFAPR_M1PFD_MASK 0x20000u +#define FMC_PFAPR_M1PFD_SHIFT 17 +#define FMC_PFAPR_M2PFD_MASK 0x40000u +#define FMC_PFAPR_M2PFD_SHIFT 18 +#define FMC_PFAPR_M3PFD_MASK 0x80000u +#define FMC_PFAPR_M3PFD_SHIFT 19 +/* PFB0CR Bit Fields */ +#define FMC_PFB0CR_B0SEBE_MASK 0x1u +#define FMC_PFB0CR_B0SEBE_SHIFT 0 +#define FMC_PFB0CR_B0IPE_MASK 0x2u +#define FMC_PFB0CR_B0IPE_SHIFT 1 +#define FMC_PFB0CR_B0DPE_MASK 0x4u +#define FMC_PFB0CR_B0DPE_SHIFT 2 +#define FMC_PFB0CR_B0ICE_MASK 0x8u +#define FMC_PFB0CR_B0ICE_SHIFT 3 +#define FMC_PFB0CR_B0DCE_MASK 0x10u +#define FMC_PFB0CR_B0DCE_SHIFT 4 +#define FMC_PFB0CR_CRC_MASK 0xE0u +#define FMC_PFB0CR_CRC_SHIFT 5 +#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK) +#define FMC_PFB0CR_B0MW_MASK 0x60000u +#define FMC_PFB0CR_B0MW_SHIFT 17 +#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK) +#define FMC_PFB0CR_S_B_INV_MASK 0x80000u +#define FMC_PFB0CR_S_B_INV_SHIFT 19 +#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u +#define FMC_PFB0CR_CINV_WAY_SHIFT 20 +#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK) +#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u +#define FMC_PFB0CR_CLCK_WAY_SHIFT 24 +#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK) +#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u +#define FMC_PFB0CR_B0RWSC_SHIFT 28 +#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK) +/* TAGVD Bit Fields */ +#define FMC_TAGVD_valid_MASK 0x1u +#define FMC_TAGVD_valid_SHIFT 0 +#define FMC_TAGVD_tag_MASK 0x7FFC0u +#define FMC_TAGVD_tag_SHIFT 6 +#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK) +/* DATAW0S Bit Fields */ +#define FMC_DATAW0S_data_MASK 0xFFFFFFFFu +#define FMC_DATAW0S_data_SHIFT 0 +#define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK) +/* DATAW1S Bit Fields */ +#define FMC_DATAW1S_data_MASK 0xFFFFFFFFu +#define FMC_DATAW1S_data_SHIFT 0 +#define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK) +/* DATAW2S Bit Fields */ +#define FMC_DATAW2S_data_MASK 0xFFFFFFFFu +#define FMC_DATAW2S_data_SHIFT 0 +#define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK) +/* DATAW3S Bit Fields */ +#define FMC_DATAW3S_data_MASK 0xFFFFFFFFu +#define FMC_DATAW3S_data_SHIFT 0 +#define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK) + +/** + * @} + */ /* end of group FMC_Register_Masks */ + + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC base address */ +#define FMC_BASE (0x4001F000u) +/** Peripheral FMC base pointer */ +#define FMC ((FMC_Type *)FMC_BASE) + +/** + * @} + */ /* end of group FMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FTFL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer + * @{ + */ + +/** FTFL - Register Layout Typedef */ +typedef struct { + __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ + __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ + __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ + __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ + __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ + __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ + __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ + __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ + __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ + __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ + __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ + __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ + __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ + __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ + __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ + __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ + __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ + __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ + __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ + uint8_t RESERVED_0[2]; + __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */ + __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */ +} FTFL_Type; + +/* ---------------------------------------------------------------------------- + -- FTFL Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTFL_Register_Masks FTFL Register Masks + * @{ + */ + +/* FSTAT Bit Fields */ +#define FTFL_FSTAT_MGSTAT0_MASK 0x1u +#define FTFL_FSTAT_MGSTAT0_SHIFT 0 +#define FTFL_FSTAT_FPVIOL_MASK 0x10u +#define FTFL_FSTAT_FPVIOL_SHIFT 4 +#define FTFL_FSTAT_ACCERR_MASK 0x20u +#define FTFL_FSTAT_ACCERR_SHIFT 5 +#define FTFL_FSTAT_RDCOLERR_MASK 0x40u +#define FTFL_FSTAT_RDCOLERR_SHIFT 6 +#define FTFL_FSTAT_CCIF_MASK 0x80u +#define FTFL_FSTAT_CCIF_SHIFT 7 +/* FCNFG Bit Fields */ +#define FTFL_FCNFG_EEERDY_MASK 0x1u +#define FTFL_FCNFG_EEERDY_SHIFT 0 +#define FTFL_FCNFG_RAMRDY_MASK 0x2u +#define FTFL_FCNFG_RAMRDY_SHIFT 1 +#define FTFL_FCNFG_PFLSH_MASK 0x4u +#define FTFL_FCNFG_PFLSH_SHIFT 2 +#define FTFL_FCNFG_ERSSUSP_MASK 0x10u +#define FTFL_FCNFG_ERSSUSP_SHIFT 4 +#define FTFL_FCNFG_ERSAREQ_MASK 0x20u +#define FTFL_FCNFG_ERSAREQ_SHIFT 5 +#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u +#define FTFL_FCNFG_RDCOLLIE_SHIFT 6 +#define FTFL_FCNFG_CCIE_MASK 0x80u +#define FTFL_FCNFG_CCIE_SHIFT 7 +/* FSEC Bit Fields */ +#define FTFL_FSEC_SEC_MASK 0x3u +#define FTFL_FSEC_SEC_SHIFT 0 +#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK) +#define FTFL_FSEC_FSLACC_MASK 0xCu +#define FTFL_FSEC_FSLACC_SHIFT 2 +#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK) +#define FTFL_FSEC_MEEN_MASK 0x30u +#define FTFL_FSEC_MEEN_SHIFT 4 +#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK) +#define FTFL_FSEC_KEYEN_MASK 0xC0u +#define FTFL_FSEC_KEYEN_SHIFT 6 +#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK) +/* FOPT Bit Fields */ +#define FTFL_FOPT_OPT_MASK 0xFFu +#define FTFL_FOPT_OPT_SHIFT 0 +#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK) +/* FCCOB3 Bit Fields */ +#define FTFL_FCCOB3_CCOBn_MASK 0xFFu +#define FTFL_FCCOB3_CCOBn_SHIFT 0 +#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK) +/* FCCOB2 Bit Fields */ +#define FTFL_FCCOB2_CCOBn_MASK 0xFFu +#define FTFL_FCCOB2_CCOBn_SHIFT 0 +#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK) +/* FCCOB1 Bit Fields */ +#define FTFL_FCCOB1_CCOBn_MASK 0xFFu +#define FTFL_FCCOB1_CCOBn_SHIFT 0 +#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK) +/* FCCOB0 Bit Fields */ +#define FTFL_FCCOB0_CCOBn_MASK 0xFFu +#define FTFL_FCCOB0_CCOBn_SHIFT 0 +#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK) +/* FCCOB7 Bit Fields */ +#define FTFL_FCCOB7_CCOBn_MASK 0xFFu +#define FTFL_FCCOB7_CCOBn_SHIFT 0 +#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK) +/* FCCOB6 Bit Fields */ +#define FTFL_FCCOB6_CCOBn_MASK 0xFFu +#define FTFL_FCCOB6_CCOBn_SHIFT 0 +#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK) +/* FCCOB5 Bit Fields */ +#define FTFL_FCCOB5_CCOBn_MASK 0xFFu +#define FTFL_FCCOB5_CCOBn_SHIFT 0 +#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK) +/* FCCOB4 Bit Fields */ +#define FTFL_FCCOB4_CCOBn_MASK 0xFFu +#define FTFL_FCCOB4_CCOBn_SHIFT 0 +#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK) +/* FCCOBB Bit Fields */ +#define FTFL_FCCOBB_CCOBn_MASK 0xFFu +#define FTFL_FCCOBB_CCOBn_SHIFT 0 +#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK) +/* FCCOBA Bit Fields */ +#define FTFL_FCCOBA_CCOBn_MASK 0xFFu +#define FTFL_FCCOBA_CCOBn_SHIFT 0 +#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK) +/* FCCOB9 Bit Fields */ +#define FTFL_FCCOB9_CCOBn_MASK 0xFFu +#define FTFL_FCCOB9_CCOBn_SHIFT 0 +#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK) +/* FCCOB8 Bit Fields */ +#define FTFL_FCCOB8_CCOBn_MASK 0xFFu +#define FTFL_FCCOB8_CCOBn_SHIFT 0 +#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK) +/* FPROT3 Bit Fields */ +#define FTFL_FPROT3_PROT_MASK 0xFFu +#define FTFL_FPROT3_PROT_SHIFT 0 +#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK) +/* FPROT2 Bit Fields */ +#define FTFL_FPROT2_PROT_MASK 0xFFu +#define FTFL_FPROT2_PROT_SHIFT 0 +#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK) +/* FPROT1 Bit Fields */ +#define FTFL_FPROT1_PROT_MASK 0xFFu +#define FTFL_FPROT1_PROT_SHIFT 0 +#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK) +/* FPROT0 Bit Fields */ +#define FTFL_FPROT0_PROT_MASK 0xFFu +#define FTFL_FPROT0_PROT_SHIFT 0 +#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK) +/* FEPROT Bit Fields */ +#define FTFL_FEPROT_EPROT_MASK 0xFFu +#define FTFL_FEPROT_EPROT_SHIFT 0 +#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK) +/* FDPROT Bit Fields */ +#define FTFL_FDPROT_DPROT_MASK 0xFFu +#define FTFL_FDPROT_DPROT_SHIFT 0 +#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK) + +/** + * @} + */ /* end of group FTFL_Register_Masks */ + + +/* FTFL - Peripheral instance base addresses */ +/** Peripheral FTFL base address */ +#define FTFL_BASE (0x40020000u) +/** Peripheral FTFL base pointer */ +#define FTFL ((FTFL_Type *)FTFL_BASE) + +/** + * @} + */ /* end of group FTFL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FTM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer + * @{ + */ + +/** FTM - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ + __IO uint32_t CNT; /**< Counter, offset: 0x4 */ + __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ + struct { /* offset: 0xC, array step: 0x8 */ + __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ + __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ + } CONTROLS[8]; + __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ + __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ + __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ + __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ + __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */ + __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ + __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */ + __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ + __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ + __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ + __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ + __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ + __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ + __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */ + __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ + __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ + __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ + __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ + __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ + __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ +} FTM_Type; + +/* ---------------------------------------------------------------------------- + -- FTM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup FTM_Register_Masks FTM Register Masks + * @{ + */ + +/* SC Bit Fields */ +#define FTM_SC_PS_MASK 0x7u +#define FTM_SC_PS_SHIFT 0 +#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK) +#define FTM_SC_CLKS_MASK 0x18u +#define FTM_SC_CLKS_SHIFT 3 +#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK) +#define FTM_SC_CPWMS_MASK 0x20u +#define FTM_SC_CPWMS_SHIFT 5 +#define FTM_SC_TOIE_MASK 0x40u +#define FTM_SC_TOIE_SHIFT 6 +#define FTM_SC_TOF_MASK 0x80u +#define FTM_SC_TOF_SHIFT 7 +/* CNT Bit Fields */ +#define FTM_CNT_COUNT_MASK 0xFFFFu +#define FTM_CNT_COUNT_SHIFT 0 +#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK) +/* MOD Bit Fields */ +#define FTM_MOD_MOD_MASK 0xFFFFu +#define FTM_MOD_MOD_SHIFT 0 +#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK) +/* CnSC Bit Fields */ +#define FTM_CnSC_DMA_MASK 0x1u +#define FTM_CnSC_DMA_SHIFT 0 +#define FTM_CnSC_ELSA_MASK 0x4u +#define FTM_CnSC_ELSA_SHIFT 2 +#define FTM_CnSC_ELSB_MASK 0x8u +#define FTM_CnSC_ELSB_SHIFT 3 +#define FTM_CnSC_MSA_MASK 0x10u +#define FTM_CnSC_MSA_SHIFT 4 +#define FTM_CnSC_MSB_MASK 0x20u +#define FTM_CnSC_MSB_SHIFT 5 +#define FTM_CnSC_CHIE_MASK 0x40u +#define FTM_CnSC_CHIE_SHIFT 6 +#define FTM_CnSC_CHF_MASK 0x80u +#define FTM_CnSC_CHF_SHIFT 7 +/* CnV Bit Fields */ +#define FTM_CnV_VAL_MASK 0xFFFFu +#define FTM_CnV_VAL_SHIFT 0 +#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK) +/* CNTIN Bit Fields */ +#define FTM_CNTIN_INIT_MASK 0xFFFFu +#define FTM_CNTIN_INIT_SHIFT 0 +#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK) +/* STATUS Bit Fields */ +#define FTM_STATUS_CH0F_MASK 0x1u +#define FTM_STATUS_CH0F_SHIFT 0 +#define FTM_STATUS_CH1F_MASK 0x2u +#define FTM_STATUS_CH1F_SHIFT 1 +#define FTM_STATUS_CH2F_MASK 0x4u +#define FTM_STATUS_CH2F_SHIFT 2 +#define FTM_STATUS_CH3F_MASK 0x8u +#define FTM_STATUS_CH3F_SHIFT 3 +#define FTM_STATUS_CH4F_MASK 0x10u +#define FTM_STATUS_CH4F_SHIFT 4 +#define FTM_STATUS_CH5F_MASK 0x20u +#define FTM_STATUS_CH5F_SHIFT 5 +#define FTM_STATUS_CH6F_MASK 0x40u +#define FTM_STATUS_CH6F_SHIFT 6 +#define FTM_STATUS_CH7F_MASK 0x80u +#define FTM_STATUS_CH7F_SHIFT 7 +/* MODE Bit Fields */ +#define FTM_MODE_FTMEN_MASK 0x1u +#define FTM_MODE_FTMEN_SHIFT 0 +#define FTM_MODE_INIT_MASK 0x2u +#define FTM_MODE_INIT_SHIFT 1 +#define FTM_MODE_WPDIS_MASK 0x4u +#define FTM_MODE_WPDIS_SHIFT 2 +#define FTM_MODE_PWMSYNC_MASK 0x8u +#define FTM_MODE_PWMSYNC_SHIFT 3 +#define FTM_MODE_CAPTEST_MASK 0x10u +#define FTM_MODE_CAPTEST_SHIFT 4 +#define FTM_MODE_FAULTM_MASK 0x60u +#define FTM_MODE_FAULTM_SHIFT 5 +#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK) +#define FTM_MODE_FAULTIE_MASK 0x80u +#define FTM_MODE_FAULTIE_SHIFT 7 +/* SYNC Bit Fields */ +#define FTM_SYNC_CNTMIN_MASK 0x1u +#define FTM_SYNC_CNTMIN_SHIFT 0 +#define FTM_SYNC_CNTMAX_MASK 0x2u +#define FTM_SYNC_CNTMAX_SHIFT 1 +#define FTM_SYNC_REINIT_MASK 0x4u +#define FTM_SYNC_REINIT_SHIFT 2 +#define FTM_SYNC_SYNCHOM_MASK 0x8u +#define FTM_SYNC_SYNCHOM_SHIFT 3 +#define FTM_SYNC_TRIG0_MASK 0x10u +#define FTM_SYNC_TRIG0_SHIFT 4 +#define FTM_SYNC_TRIG1_MASK 0x20u +#define FTM_SYNC_TRIG1_SHIFT 5 +#define FTM_SYNC_TRIG2_MASK 0x40u +#define FTM_SYNC_TRIG2_SHIFT 6 +#define FTM_SYNC_SWSYNC_MASK 0x80u +#define FTM_SYNC_SWSYNC_SHIFT 7 +/* OUTINIT Bit Fields */ +#define FTM_OUTINIT_CH0OI_MASK 0x1u +#define FTM_OUTINIT_CH0OI_SHIFT 0 +#define FTM_OUTINIT_CH1OI_MASK 0x2u +#define FTM_OUTINIT_CH1OI_SHIFT 1 +#define FTM_OUTINIT_CH2OI_MASK 0x4u +#define FTM_OUTINIT_CH2OI_SHIFT 2 +#define FTM_OUTINIT_CH3OI_MASK 0x8u +#define FTM_OUTINIT_CH3OI_SHIFT 3 +#define FTM_OUTINIT_CH4OI_MASK 0x10u +#define FTM_OUTINIT_CH4OI_SHIFT 4 +#define FTM_OUTINIT_CH5OI_MASK 0x20u +#define FTM_OUTINIT_CH5OI_SHIFT 5 +#define FTM_OUTINIT_CH6OI_MASK 0x40u +#define FTM_OUTINIT_CH6OI_SHIFT 6 +#define FTM_OUTINIT_CH7OI_MASK 0x80u +#define FTM_OUTINIT_CH7OI_SHIFT 7 +/* OUTMASK Bit Fields */ +#define FTM_OUTMASK_CH0OM_MASK 0x1u +#define FTM_OUTMASK_CH0OM_SHIFT 0 +#define FTM_OUTMASK_CH1OM_MASK 0x2u +#define FTM_OUTMASK_CH1OM_SHIFT 1 +#define FTM_OUTMASK_CH2OM_MASK 0x4u +#define FTM_OUTMASK_CH2OM_SHIFT 2 +#define FTM_OUTMASK_CH3OM_MASK 0x8u +#define FTM_OUTMASK_CH3OM_SHIFT 3 +#define FTM_OUTMASK_CH4OM_MASK 0x10u +#define FTM_OUTMASK_CH4OM_SHIFT 4 +#define FTM_OUTMASK_CH5OM_MASK 0x20u +#define FTM_OUTMASK_CH5OM_SHIFT 5 +#define FTM_OUTMASK_CH6OM_MASK 0x40u +#define FTM_OUTMASK_CH6OM_SHIFT 6 +#define FTM_OUTMASK_CH7OM_MASK 0x80u +#define FTM_OUTMASK_CH7OM_SHIFT 7 +/* COMBINE Bit Fields */ +#define FTM_COMBINE_COMBINE0_MASK 0x1u +#define FTM_COMBINE_COMBINE0_SHIFT 0 +#define FTM_COMBINE_COMP0_MASK 0x2u +#define FTM_COMBINE_COMP0_SHIFT 1 +#define FTM_COMBINE_DECAPEN0_MASK 0x4u +#define FTM_COMBINE_DECAPEN0_SHIFT 2 +#define FTM_COMBINE_DECAP0_MASK 0x8u +#define FTM_COMBINE_DECAP0_SHIFT 3 +#define FTM_COMBINE_DTEN0_MASK 0x10u +#define FTM_COMBINE_DTEN0_SHIFT 4 +#define FTM_COMBINE_SYNCEN0_MASK 0x20u +#define FTM_COMBINE_SYNCEN0_SHIFT 5 +#define FTM_COMBINE_FAULTEN0_MASK 0x40u +#define FTM_COMBINE_FAULTEN0_SHIFT 6 +#define FTM_COMBINE_COMBINE1_MASK 0x100u +#define FTM_COMBINE_COMBINE1_SHIFT 8 +#define FTM_COMBINE_COMP1_MASK 0x200u +#define FTM_COMBINE_COMP1_SHIFT 9 +#define FTM_COMBINE_DECAPEN1_MASK 0x400u +#define FTM_COMBINE_DECAPEN1_SHIFT 10 +#define FTM_COMBINE_DECAP1_MASK 0x800u +#define FTM_COMBINE_DECAP1_SHIFT 11 +#define FTM_COMBINE_DTEN1_MASK 0x1000u +#define FTM_COMBINE_DTEN1_SHIFT 12 +#define FTM_COMBINE_SYNCEN1_MASK 0x2000u +#define FTM_COMBINE_SYNCEN1_SHIFT 13 +#define FTM_COMBINE_FAULTEN1_MASK 0x4000u +#define FTM_COMBINE_FAULTEN1_SHIFT 14 +#define FTM_COMBINE_COMBINE2_MASK 0x10000u +#define FTM_COMBINE_COMBINE2_SHIFT 16 +#define FTM_COMBINE_COMP2_MASK 0x20000u +#define FTM_COMBINE_COMP2_SHIFT 17 +#define FTM_COMBINE_DECAPEN2_MASK 0x40000u +#define FTM_COMBINE_DECAPEN2_SHIFT 18 +#define FTM_COMBINE_DECAP2_MASK 0x80000u +#define FTM_COMBINE_DECAP2_SHIFT 19 +#define FTM_COMBINE_DTEN2_MASK 0x100000u +#define FTM_COMBINE_DTEN2_SHIFT 20 +#define FTM_COMBINE_SYNCEN2_MASK 0x200000u +#define FTM_COMBINE_SYNCEN2_SHIFT 21 +#define FTM_COMBINE_FAULTEN2_MASK 0x400000u +#define FTM_COMBINE_FAULTEN2_SHIFT 22 +#define FTM_COMBINE_COMBINE3_MASK 0x1000000u +#define FTM_COMBINE_COMBINE3_SHIFT 24 +#define FTM_COMBINE_COMP3_MASK 0x2000000u +#define FTM_COMBINE_COMP3_SHIFT 25 +#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u +#define FTM_COMBINE_DECAPEN3_SHIFT 26 +#define FTM_COMBINE_DECAP3_MASK 0x8000000u +#define FTM_COMBINE_DECAP3_SHIFT 27 +#define FTM_COMBINE_DTEN3_MASK 0x10000000u +#define FTM_COMBINE_DTEN3_SHIFT 28 +#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u +#define FTM_COMBINE_SYNCEN3_SHIFT 29 +#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u +#define FTM_COMBINE_FAULTEN3_SHIFT 30 +/* DEADTIME Bit Fields */ +#define FTM_DEADTIME_DTVAL_MASK 0x3Fu +#define FTM_DEADTIME_DTVAL_SHIFT 0 +#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK) +#define FTM_DEADTIME_DTPS_MASK 0xC0u +#define FTM_DEADTIME_DTPS_SHIFT 6 +#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK) +/* EXTTRIG Bit Fields */ +#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u +#define FTM_EXTTRIG_CH2TRIG_SHIFT 0 +#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u +#define FTM_EXTTRIG_CH3TRIG_SHIFT 1 +#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u +#define FTM_EXTTRIG_CH4TRIG_SHIFT 2 +#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u +#define FTM_EXTTRIG_CH5TRIG_SHIFT 3 +#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u +#define FTM_EXTTRIG_CH0TRIG_SHIFT 4 +#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u +#define FTM_EXTTRIG_CH1TRIG_SHIFT 5 +#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u +#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6 +#define FTM_EXTTRIG_TRIGF_MASK 0x80u +#define FTM_EXTTRIG_TRIGF_SHIFT 7 +/* POL Bit Fields */ +#define FTM_POL_POL0_MASK 0x1u +#define FTM_POL_POL0_SHIFT 0 +#define FTM_POL_POL1_MASK 0x2u +#define FTM_POL_POL1_SHIFT 1 +#define FTM_POL_POL2_MASK 0x4u +#define FTM_POL_POL2_SHIFT 2 +#define FTM_POL_POL3_MASK 0x8u +#define FTM_POL_POL3_SHIFT 3 +#define FTM_POL_POL4_MASK 0x10u +#define FTM_POL_POL4_SHIFT 4 +#define FTM_POL_POL5_MASK 0x20u +#define FTM_POL_POL5_SHIFT 5 +#define FTM_POL_POL6_MASK 0x40u +#define FTM_POL_POL6_SHIFT 6 +#define FTM_POL_POL7_MASK 0x80u +#define FTM_POL_POL7_SHIFT 7 +/* FMS Bit Fields */ +#define FTM_FMS_FAULTF0_MASK 0x1u +#define FTM_FMS_FAULTF0_SHIFT 0 +#define FTM_FMS_FAULTF1_MASK 0x2u +#define FTM_FMS_FAULTF1_SHIFT 1 +#define FTM_FMS_FAULTF2_MASK 0x4u +#define FTM_FMS_FAULTF2_SHIFT 2 +#define FTM_FMS_FAULTF3_MASK 0x8u +#define FTM_FMS_FAULTF3_SHIFT 3 +#define FTM_FMS_FAULTIN_MASK 0x20u +#define FTM_FMS_FAULTIN_SHIFT 5 +#define FTM_FMS_WPEN_MASK 0x40u +#define FTM_FMS_WPEN_SHIFT 6 +#define FTM_FMS_FAULTF_MASK 0x80u +#define FTM_FMS_FAULTF_SHIFT 7 +/* FILTER Bit Fields */ +#define FTM_FILTER_CH0FVAL_MASK 0xFu +#define FTM_FILTER_CH0FVAL_SHIFT 0 +#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK) +#define FTM_FILTER_CH1FVAL_MASK 0xF0u +#define FTM_FILTER_CH1FVAL_SHIFT 4 +#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK) +#define FTM_FILTER_CH2FVAL_MASK 0xF00u +#define FTM_FILTER_CH2FVAL_SHIFT 8 +#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK) +#define FTM_FILTER_CH3FVAL_MASK 0xF000u +#define FTM_FILTER_CH3FVAL_SHIFT 12 +#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK) +/* FLTCTRL Bit Fields */ +#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u +#define FTM_FLTCTRL_FAULT0EN_SHIFT 0 +#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u +#define FTM_FLTCTRL_FAULT1EN_SHIFT 1 +#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u +#define FTM_FLTCTRL_FAULT2EN_SHIFT 2 +#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u +#define FTM_FLTCTRL_FAULT3EN_SHIFT 3 +#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u +#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4 +#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u +#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5 +#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u +#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6 +#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u +#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7 +#define FTM_FLTCTRL_FFVAL_MASK 0xF00u +#define FTM_FLTCTRL_FFVAL_SHIFT 8 +#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK) +/* QDCTRL Bit Fields */ +#define FTM_QDCTRL_QUADEN_MASK 0x1u +#define FTM_QDCTRL_QUADEN_SHIFT 0 +#define FTM_QDCTRL_TOFDIR_MASK 0x2u +#define FTM_QDCTRL_TOFDIR_SHIFT 1 +#define FTM_QDCTRL_QUADIR_MASK 0x4u +#define FTM_QDCTRL_QUADIR_SHIFT 2 +#define FTM_QDCTRL_QUADMODE_MASK 0x8u +#define FTM_QDCTRL_QUADMODE_SHIFT 3 +#define FTM_QDCTRL_PHBPOL_MASK 0x10u +#define FTM_QDCTRL_PHBPOL_SHIFT 4 +#define FTM_QDCTRL_PHAPOL_MASK 0x20u +#define FTM_QDCTRL_PHAPOL_SHIFT 5 +#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u +#define FTM_QDCTRL_PHBFLTREN_SHIFT 6 +#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u +#define FTM_QDCTRL_PHAFLTREN_SHIFT 7 +/* CONF Bit Fields */ +#define FTM_CONF_NUMTOF_MASK 0x1Fu +#define FTM_CONF_NUMTOF_SHIFT 0 +#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK) +#define FTM_CONF_BDMMODE_MASK 0xC0u +#define FTM_CONF_BDMMODE_SHIFT 6 +#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK) +#define FTM_CONF_GTBEEN_MASK 0x200u +#define FTM_CONF_GTBEEN_SHIFT 9 +#define FTM_CONF_GTBEOUT_MASK 0x400u +#define FTM_CONF_GTBEOUT_SHIFT 10 +/* FLTPOL Bit Fields */ +#define FTM_FLTPOL_FLT0POL_MASK 0x1u +#define FTM_FLTPOL_FLT0POL_SHIFT 0 +#define FTM_FLTPOL_FLT1POL_MASK 0x2u +#define FTM_FLTPOL_FLT1POL_SHIFT 1 +#define FTM_FLTPOL_FLT2POL_MASK 0x4u +#define FTM_FLTPOL_FLT2POL_SHIFT 2 +#define FTM_FLTPOL_FLT3POL_MASK 0x8u +#define FTM_FLTPOL_FLT3POL_SHIFT 3 +/* SYNCONF Bit Fields */ +#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u +#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0 +#define FTM_SYNCONF_CNTINC_MASK 0x4u +#define FTM_SYNCONF_CNTINC_SHIFT 2 +#define FTM_SYNCONF_INVC_MASK 0x10u +#define FTM_SYNCONF_INVC_SHIFT 4 +#define FTM_SYNCONF_SWOC_MASK 0x20u +#define FTM_SYNCONF_SWOC_SHIFT 5 +#define FTM_SYNCONF_SYNCMODE_MASK 0x80u +#define FTM_SYNCONF_SYNCMODE_SHIFT 7 +#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u +#define FTM_SYNCONF_SWRSTCNT_SHIFT 8 +#define FTM_SYNCONF_SWWRBUF_MASK 0x200u +#define FTM_SYNCONF_SWWRBUF_SHIFT 9 +#define FTM_SYNCONF_SWOM_MASK 0x400u +#define FTM_SYNCONF_SWOM_SHIFT 10 +#define FTM_SYNCONF_SWINVC_MASK 0x800u +#define FTM_SYNCONF_SWINVC_SHIFT 11 +#define FTM_SYNCONF_SWSOC_MASK 0x1000u +#define FTM_SYNCONF_SWSOC_SHIFT 12 +#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u +#define FTM_SYNCONF_HWRSTCNT_SHIFT 16 +#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u +#define FTM_SYNCONF_HWWRBUF_SHIFT 17 +#define FTM_SYNCONF_HWOM_MASK 0x40000u +#define FTM_SYNCONF_HWOM_SHIFT 18 +#define FTM_SYNCONF_HWINVC_MASK 0x80000u +#define FTM_SYNCONF_HWINVC_SHIFT 19 +#define FTM_SYNCONF_HWSOC_MASK 0x100000u +#define FTM_SYNCONF_HWSOC_SHIFT 20 +/* INVCTRL Bit Fields */ +#define FTM_INVCTRL_INV0EN_MASK 0x1u +#define FTM_INVCTRL_INV0EN_SHIFT 0 +#define FTM_INVCTRL_INV1EN_MASK 0x2u +#define FTM_INVCTRL_INV1EN_SHIFT 1 +#define FTM_INVCTRL_INV2EN_MASK 0x4u +#define FTM_INVCTRL_INV2EN_SHIFT 2 +#define FTM_INVCTRL_INV3EN_MASK 0x8u +#define FTM_INVCTRL_INV3EN_SHIFT 3 +/* SWOCTRL Bit Fields */ +#define FTM_SWOCTRL_CH0OC_MASK 0x1u +#define FTM_SWOCTRL_CH0OC_SHIFT 0 +#define FTM_SWOCTRL_CH1OC_MASK 0x2u +#define FTM_SWOCTRL_CH1OC_SHIFT 1 +#define FTM_SWOCTRL_CH2OC_MASK 0x4u +#define FTM_SWOCTRL_CH2OC_SHIFT 2 +#define FTM_SWOCTRL_CH3OC_MASK 0x8u +#define FTM_SWOCTRL_CH3OC_SHIFT 3 +#define FTM_SWOCTRL_CH4OC_MASK 0x10u +#define FTM_SWOCTRL_CH4OC_SHIFT 4 +#define FTM_SWOCTRL_CH5OC_MASK 0x20u +#define FTM_SWOCTRL_CH5OC_SHIFT 5 +#define FTM_SWOCTRL_CH6OC_MASK 0x40u +#define FTM_SWOCTRL_CH6OC_SHIFT 6 +#define FTM_SWOCTRL_CH7OC_MASK 0x80u +#define FTM_SWOCTRL_CH7OC_SHIFT 7 +#define FTM_SWOCTRL_CH0OCV_MASK 0x100u +#define FTM_SWOCTRL_CH0OCV_SHIFT 8 +#define FTM_SWOCTRL_CH1OCV_MASK 0x200u +#define FTM_SWOCTRL_CH1OCV_SHIFT 9 +#define FTM_SWOCTRL_CH2OCV_MASK 0x400u +#define FTM_SWOCTRL_CH2OCV_SHIFT 10 +#define FTM_SWOCTRL_CH3OCV_MASK 0x800u +#define FTM_SWOCTRL_CH3OCV_SHIFT 11 +#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u +#define FTM_SWOCTRL_CH4OCV_SHIFT 12 +#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u +#define FTM_SWOCTRL_CH5OCV_SHIFT 13 +#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u +#define FTM_SWOCTRL_CH6OCV_SHIFT 14 +#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u +#define FTM_SWOCTRL_CH7OCV_SHIFT 15 +/* PWMLOAD Bit Fields */ +#define FTM_PWMLOAD_CH0SEL_MASK 0x1u +#define FTM_PWMLOAD_CH0SEL_SHIFT 0 +#define FTM_PWMLOAD_CH1SEL_MASK 0x2u +#define FTM_PWMLOAD_CH1SEL_SHIFT 1 +#define FTM_PWMLOAD_CH2SEL_MASK 0x4u +#define FTM_PWMLOAD_CH2SEL_SHIFT 2 +#define FTM_PWMLOAD_CH3SEL_MASK 0x8u +#define FTM_PWMLOAD_CH3SEL_SHIFT 3 +#define FTM_PWMLOAD_CH4SEL_MASK 0x10u +#define FTM_PWMLOAD_CH4SEL_SHIFT 4 +#define FTM_PWMLOAD_CH5SEL_MASK 0x20u +#define FTM_PWMLOAD_CH5SEL_SHIFT 5 +#define FTM_PWMLOAD_CH6SEL_MASK 0x40u +#define FTM_PWMLOAD_CH6SEL_SHIFT 6 +#define FTM_PWMLOAD_CH7SEL_MASK 0x80u +#define FTM_PWMLOAD_CH7SEL_SHIFT 7 +#define FTM_PWMLOAD_LDOK_MASK 0x200u +#define FTM_PWMLOAD_LDOK_SHIFT 9 + +/** + * @} + */ /* end of group FTM_Register_Masks */ + + +/* FTM - Peripheral instance base addresses */ +/** Peripheral FTM0 base address */ +#define FTM0_BASE (0x40038000u) +/** Peripheral FTM0 base pointer */ +#define FTM0 ((FTM_Type *)FTM0_BASE) +/** Peripheral FTM1 base address */ +#define FTM1_BASE (0x40039000u) +/** Peripheral FTM1 base pointer */ +#define FTM1 ((FTM_Type *)FTM1_BASE) + +/** + * @} + */ /* end of group FTM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ + __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ + __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ + __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ + __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ + __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/* PDOR Bit Fields */ +#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu +#define GPIO_PDOR_PDO_SHIFT 0 +#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK) +/* PSOR Bit Fields */ +#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu +#define GPIO_PSOR_PTSO_SHIFT 0 +#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK) +/* PCOR Bit Fields */ +#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu +#define GPIO_PCOR_PTCO_SHIFT 0 +#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK) +/* PTOR Bit Fields */ +#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu +#define GPIO_PTOR_PTTO_SHIFT 0 +#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK) +/* PDIR Bit Fields */ +#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu +#define GPIO_PDIR_PDI_SHIFT 0 +#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK) +/* PDDR Bit Fields */ +#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu +#define GPIO_PDDR_PDD_SHIFT 0 +#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK) + +/** + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral PTA base address */ +#define PTA_BASE (0x400FF000u) +/** Peripheral PTA base pointer */ +#define PTA ((GPIO_Type *)PTA_BASE) +/** Peripheral PTB base address */ +#define PTB_BASE (0x400FF040u) +/** Peripheral PTB base pointer */ +#define PTB ((GPIO_Type *)PTB_BASE) +/** Peripheral PTC base address */ +#define PTC_BASE (0x400FF080u) +/** Peripheral PTC base pointer */ +#define PTC ((GPIO_Type *)PTC_BASE) +/** Peripheral PTD base address */ +#define PTD_BASE (0x400FF0C0u) +/** Peripheral PTD base pointer */ +#define PTD ((GPIO_Type *)PTD_BASE) +/** Peripheral PTE base address */ +#define PTE_BASE (0x400FF100u) +/** Peripheral PTE base pointer */ +#define PTE ((GPIO_Type *)PTE_BASE) + +/** + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ + __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ + __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ + __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */ + __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ + __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ + __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ + __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ + __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ + __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ + __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ + __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/* A1 Bit Fields */ +#define I2C_A1_AD_MASK 0xFEu +#define I2C_A1_AD_SHIFT 1 +#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK) +/* F Bit Fields */ +#define I2C_F_ICR_MASK 0x3Fu +#define I2C_F_ICR_SHIFT 0 +#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK) +#define I2C_F_MULT_MASK 0xC0u +#define I2C_F_MULT_SHIFT 6 +#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK) +/* C1 Bit Fields */ +#define I2C_C1_DMAEN_MASK 0x1u +#define I2C_C1_DMAEN_SHIFT 0 +#define I2C_C1_WUEN_MASK 0x2u +#define I2C_C1_WUEN_SHIFT 1 +#define I2C_C1_RSTA_MASK 0x4u +#define I2C_C1_RSTA_SHIFT 2 +#define I2C_C1_TXAK_MASK 0x8u +#define I2C_C1_TXAK_SHIFT 3 +#define I2C_C1_TX_MASK 0x10u +#define I2C_C1_TX_SHIFT 4 +#define I2C_C1_MST_MASK 0x20u +#define I2C_C1_MST_SHIFT 5 +#define I2C_C1_IICIE_MASK 0x40u +#define I2C_C1_IICIE_SHIFT 6 +#define I2C_C1_IICEN_MASK 0x80u +#define I2C_C1_IICEN_SHIFT 7 +/* S Bit Fields */ +#define I2C_S_RXAK_MASK 0x1u +#define I2C_S_RXAK_SHIFT 0 +#define I2C_S_IICIF_MASK 0x2u +#define I2C_S_IICIF_SHIFT 1 +#define I2C_S_SRW_MASK 0x4u +#define I2C_S_SRW_SHIFT 2 +#define I2C_S_RAM_MASK 0x8u +#define I2C_S_RAM_SHIFT 3 +#define I2C_S_ARBL_MASK 0x10u +#define I2C_S_ARBL_SHIFT 4 +#define I2C_S_BUSY_MASK 0x20u +#define I2C_S_BUSY_SHIFT 5 +#define I2C_S_IAAS_MASK 0x40u +#define I2C_S_IAAS_SHIFT 6 +#define I2C_S_TCF_MASK 0x80u +#define I2C_S_TCF_SHIFT 7 +/* D Bit Fields */ +#define I2C_D_DATA_MASK 0xFFu +#define I2C_D_DATA_SHIFT 0 +#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK) +/* C2 Bit Fields */ +#define I2C_C2_AD_MASK 0x7u +#define I2C_C2_AD_SHIFT 0 +#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK) +#define I2C_C2_RMEN_MASK 0x8u +#define I2C_C2_RMEN_SHIFT 3 +#define I2C_C2_SBRC_MASK 0x10u +#define I2C_C2_SBRC_SHIFT 4 +#define I2C_C2_HDRS_MASK 0x20u +#define I2C_C2_HDRS_SHIFT 5 +#define I2C_C2_ADEXT_MASK 0x40u +#define I2C_C2_ADEXT_SHIFT 6 +#define I2C_C2_GCAEN_MASK 0x80u +#define I2C_C2_GCAEN_SHIFT 7 +/* FLT Bit Fields */ +#define I2C_FLT_FLT_MASK 0x1Fu +#define I2C_FLT_FLT_SHIFT 0 +#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK) +/* RA Bit Fields */ +#define I2C_RA_RAD_MASK 0xFEu +#define I2C_RA_RAD_SHIFT 1 +#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK) +/* SMB Bit Fields */ +#define I2C_SMB_SHTF2IE_MASK 0x1u +#define I2C_SMB_SHTF2IE_SHIFT 0 +#define I2C_SMB_SHTF2_MASK 0x2u +#define I2C_SMB_SHTF2_SHIFT 1 +#define I2C_SMB_SHTF1_MASK 0x4u +#define I2C_SMB_SHTF1_SHIFT 2 +#define I2C_SMB_SLTF_MASK 0x8u +#define I2C_SMB_SLTF_SHIFT 3 +#define I2C_SMB_TCKSEL_MASK 0x10u +#define I2C_SMB_TCKSEL_SHIFT 4 +#define I2C_SMB_SIICAEN_MASK 0x20u +#define I2C_SMB_SIICAEN_SHIFT 5 +#define I2C_SMB_ALERTEN_MASK 0x40u +#define I2C_SMB_ALERTEN_SHIFT 6 +#define I2C_SMB_FACK_MASK 0x80u +#define I2C_SMB_FACK_SHIFT 7 +/* A2 Bit Fields */ +#define I2C_A2_SAD_MASK 0xFEu +#define I2C_A2_SAD_SHIFT 1 +#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK) +/* SLTH Bit Fields */ +#define I2C_SLTH_SSLT_MASK 0xFFu +#define I2C_SLTH_SSLT_SHIFT 0 +#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK) +/* SLTL Bit Fields */ +#define I2C_SLTL_SSLT_MASK 0xFFu +#define I2C_SLTL_SSLT_SHIFT 0 +#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK) + +/** + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C0 base address */ +#define I2C0_BASE (0x40066000u) +#define I2C1_BASE (0x40067000u) +/** Peripheral I2C0 base pointer */ +#define I2C0 ((I2C_Type *)I2C0_BASE) +#define I2C1 ((I2C_Type *)I2C1_BASE) +/** + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[24]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_3[28]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ + uint8_t RESERVED_4[8]; + __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_5[24]; + __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_6[24]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ + uint8_t RESERVED_7[28]; + __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ + __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/* TCSR Bit Fields */ +#define I2S_TCSR_FRDE_MASK 0x1u +#define I2S_TCSR_FRDE_SHIFT 0 +#define I2S_TCSR_FWDE_MASK 0x2u +#define I2S_TCSR_FWDE_SHIFT 1 +#define I2S_TCSR_FRIE_MASK 0x100u +#define I2S_TCSR_FRIE_SHIFT 8 +#define I2S_TCSR_FWIE_MASK 0x200u +#define I2S_TCSR_FWIE_SHIFT 9 +#define I2S_TCSR_FEIE_MASK 0x400u +#define I2S_TCSR_FEIE_SHIFT 10 +#define I2S_TCSR_SEIE_MASK 0x800u +#define I2S_TCSR_SEIE_SHIFT 11 +#define I2S_TCSR_WSIE_MASK 0x1000u +#define I2S_TCSR_WSIE_SHIFT 12 +#define I2S_TCSR_FRF_MASK 0x10000u +#define I2S_TCSR_FRF_SHIFT 16 +#define I2S_TCSR_FWF_MASK 0x20000u +#define I2S_TCSR_FWF_SHIFT 17 +#define I2S_TCSR_FEF_MASK 0x40000u +#define I2S_TCSR_FEF_SHIFT 18 +#define I2S_TCSR_SEF_MASK 0x80000u +#define I2S_TCSR_SEF_SHIFT 19 +#define I2S_TCSR_WSF_MASK 0x100000u +#define I2S_TCSR_WSF_SHIFT 20 +#define I2S_TCSR_SR_MASK 0x1000000u +#define I2S_TCSR_SR_SHIFT 24 +#define I2S_TCSR_FR_MASK 0x2000000u +#define I2S_TCSR_FR_SHIFT 25 +#define I2S_TCSR_BCE_MASK 0x10000000u +#define I2S_TCSR_BCE_SHIFT 28 +#define I2S_TCSR_DBGE_MASK 0x20000000u +#define I2S_TCSR_DBGE_SHIFT 29 +#define I2S_TCSR_STOPE_MASK 0x40000000u +#define I2S_TCSR_STOPE_SHIFT 30 +#define I2S_TCSR_TE_MASK 0x80000000u +#define I2S_TCSR_TE_SHIFT 31 +/* TCR1 Bit Fields */ +#define I2S_TCR1_TFW_MASK 0x7u +#define I2S_TCR1_TFW_SHIFT 0 +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK) +/* TCR2 Bit Fields */ +#define I2S_TCR2_DIV_MASK 0xFFu +#define I2S_TCR2_DIV_SHIFT 0 +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK 0x1000000u +#define I2S_TCR2_BCD_SHIFT 24 +#define I2S_TCR2_BCP_MASK 0x2000000u +#define I2S_TCR2_BCP_SHIFT 25 +#define I2S_TCR2_MSEL_MASK 0xC000000u +#define I2S_TCR2_MSEL_SHIFT 26 +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK 0x10000000u +#define I2S_TCR2_BCI_SHIFT 28 +#define I2S_TCR2_BCS_MASK 0x20000000u +#define I2S_TCR2_BCS_SHIFT 29 +#define I2S_TCR2_SYNC_MASK 0xC0000000u +#define I2S_TCR2_SYNC_SHIFT 30 +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK) +/* TCR3 Bit Fields */ +#define I2S_TCR3_WDFL_MASK 0x1Fu +#define I2S_TCR3_WDFL_SHIFT 0 +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK 0x30000u +#define I2S_TCR3_TCE_SHIFT 16 +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK) +/* TCR4 Bit Fields */ +#define I2S_TCR4_FSD_MASK 0x1u +#define I2S_TCR4_FSD_SHIFT 0 +#define I2S_TCR4_FSP_MASK 0x2u +#define I2S_TCR4_FSP_SHIFT 1 +#define I2S_TCR4_FSE_MASK 0x8u +#define I2S_TCR4_FSE_SHIFT 3 +#define I2S_TCR4_MF_MASK 0x10u +#define I2S_TCR4_MF_SHIFT 4 +#define I2S_TCR4_SYWD_MASK 0x1F00u +#define I2S_TCR4_SYWD_SHIFT 8 +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK 0x1F0000u +#define I2S_TCR4_FRSZ_SHIFT 16 +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK) +/* TCR5 Bit Fields */ +#define I2S_TCR5_FBT_MASK 0x1F00u +#define I2S_TCR5_FBT_SHIFT 8 +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK 0x1F0000u +#define I2S_TCR5_W0W_SHIFT 16 +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK 0x1F000000u +#define I2S_TCR5_WNW_SHIFT 24 +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK) +/* TDR Bit Fields */ +#define I2S_TDR_TDR_MASK 0xFFFFFFFFu +#define I2S_TDR_TDR_SHIFT 0 +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK) +/* TFR Bit Fields */ +#define I2S_TFR_RFP_MASK 0xFu +#define I2S_TFR_RFP_SHIFT 0 +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK 0xF0000u +#define I2S_TFR_WFP_SHIFT 16 +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK) +/* TMR Bit Fields */ +#define I2S_TMR_TWM_MASK 0xFFFFFFFFu +#define I2S_TMR_TWM_SHIFT 0 +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK) +/* RCSR Bit Fields */ +#define I2S_RCSR_FRDE_MASK 0x1u +#define I2S_RCSR_FRDE_SHIFT 0 +#define I2S_RCSR_FWDE_MASK 0x2u +#define I2S_RCSR_FWDE_SHIFT 1 +#define I2S_RCSR_FRIE_MASK 0x100u +#define I2S_RCSR_FRIE_SHIFT 8 +#define I2S_RCSR_FWIE_MASK 0x200u +#define I2S_RCSR_FWIE_SHIFT 9 +#define I2S_RCSR_FEIE_MASK 0x400u +#define I2S_RCSR_FEIE_SHIFT 10 +#define I2S_RCSR_SEIE_MASK 0x800u +#define I2S_RCSR_SEIE_SHIFT 11 +#define I2S_RCSR_WSIE_MASK 0x1000u +#define I2S_RCSR_WSIE_SHIFT 12 +#define I2S_RCSR_FRF_MASK 0x10000u +#define I2S_RCSR_FRF_SHIFT 16 +#define I2S_RCSR_FWF_MASK 0x20000u +#define I2S_RCSR_FWF_SHIFT 17 +#define I2S_RCSR_FEF_MASK 0x40000u +#define I2S_RCSR_FEF_SHIFT 18 +#define I2S_RCSR_SEF_MASK 0x80000u +#define I2S_RCSR_SEF_SHIFT 19 +#define I2S_RCSR_WSF_MASK 0x100000u +#define I2S_RCSR_WSF_SHIFT 20 +#define I2S_RCSR_SR_MASK 0x1000000u +#define I2S_RCSR_SR_SHIFT 24 +#define I2S_RCSR_FR_MASK 0x2000000u +#define I2S_RCSR_FR_SHIFT 25 +#define I2S_RCSR_BCE_MASK 0x10000000u +#define I2S_RCSR_BCE_SHIFT 28 +#define I2S_RCSR_DBGE_MASK 0x20000000u +#define I2S_RCSR_DBGE_SHIFT 29 +#define I2S_RCSR_STOPE_MASK 0x40000000u +#define I2S_RCSR_STOPE_SHIFT 30 +#define I2S_RCSR_RE_MASK 0x80000000u +#define I2S_RCSR_RE_SHIFT 31 +/* RCR1 Bit Fields */ +#define I2S_RCR1_RFW_MASK 0x7u +#define I2S_RCR1_RFW_SHIFT 0 +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK) +/* RCR2 Bit Fields */ +#define I2S_RCR2_DIV_MASK 0xFFu +#define I2S_RCR2_DIV_SHIFT 0 +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK 0x1000000u +#define I2S_RCR2_BCD_SHIFT 24 +#define I2S_RCR2_BCP_MASK 0x2000000u +#define I2S_RCR2_BCP_SHIFT 25 +#define I2S_RCR2_MSEL_MASK 0xC000000u +#define I2S_RCR2_MSEL_SHIFT 26 +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK 0x10000000u +#define I2S_RCR2_BCI_SHIFT 28 +#define I2S_RCR2_BCS_MASK 0x20000000u +#define I2S_RCR2_BCS_SHIFT 29 +#define I2S_RCR2_SYNC_MASK 0xC0000000u +#define I2S_RCR2_SYNC_SHIFT 30 +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK) +/* RCR3 Bit Fields */ +#define I2S_RCR3_WDFL_MASK 0x1Fu +#define I2S_RCR3_WDFL_SHIFT 0 +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK 0x30000u +#define I2S_RCR3_RCE_SHIFT 16 +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK) +/* RCR4 Bit Fields */ +#define I2S_RCR4_FSD_MASK 0x1u +#define I2S_RCR4_FSD_SHIFT 0 +#define I2S_RCR4_FSP_MASK 0x2u +#define I2S_RCR4_FSP_SHIFT 1 +#define I2S_RCR4_FSE_MASK 0x8u +#define I2S_RCR4_FSE_SHIFT 3 +#define I2S_RCR4_MF_MASK 0x10u +#define I2S_RCR4_MF_SHIFT 4 +#define I2S_RCR4_SYWD_MASK 0x1F00u +#define I2S_RCR4_SYWD_SHIFT 8 +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK 0x1F0000u +#define I2S_RCR4_FRSZ_SHIFT 16 +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK) +/* RCR5 Bit Fields */ +#define I2S_RCR5_FBT_MASK 0x1F00u +#define I2S_RCR5_FBT_SHIFT 8 +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK 0x1F0000u +#define I2S_RCR5_W0W_SHIFT 16 +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK 0x1F000000u +#define I2S_RCR5_WNW_SHIFT 24 +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK) +/* RDR Bit Fields */ +#define I2S_RDR_RDR_MASK 0xFFFFFFFFu +#define I2S_RDR_RDR_SHIFT 0 +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK) +/* RFR Bit Fields */ +#define I2S_RFR_RFP_MASK 0xFu +#define I2S_RFR_RFP_SHIFT 0 +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK) +#define I2S_RFR_WFP_MASK 0xF0000u +#define I2S_RFR_WFP_SHIFT 16 +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK) +/* RMR Bit Fields */ +#define I2S_RMR_RWM_MASK 0xFFFFFFFFu +#define I2S_RMR_RWM_SHIFT 0 +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK) +/* MCR Bit Fields */ +#define I2S_MCR_MICS_MASK 0x3000000u +#define I2S_MCR_MICS_SHIFT 24 +#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK) +#define I2S_MCR_MOE_MASK 0x40000000u +#define I2S_MCR_MOE_SHIFT 30 +#define I2S_MCR_DUF_MASK 0x80000000u +#define I2S_MCR_DUF_SHIFT 31 +/* MDR Bit Fields */ +#define I2S_MDR_DIVIDE_MASK 0xFFFu +#define I2S_MDR_DIVIDE_SHIFT 0 +#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK) +#define I2S_MDR_FRACT_MASK 0xFF000u +#define I2S_MDR_FRACT_SHIFT 12 +#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK) + +/** + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S0 base address */ +#define I2S0_BASE (0x4002F000u) +/** Peripheral I2S0 base pointer */ +#define I2S0 ((I2S_Type *)I2S0_BASE) + +/** + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LLWU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer + * @{ + */ + +/** LLWU - Register Layout Typedef */ +typedef struct { + __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */ + __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */ + __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */ + __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */ + __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */ + __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */ + __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */ + __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */ + __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */ + __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */ + __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */ +} LLWU_Type; + +/* ---------------------------------------------------------------------------- + -- LLWU Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LLWU_Register_Masks LLWU Register Masks + * @{ + */ + +/* PE1 Bit Fields */ +#define LLWU_PE1_WUPE0_MASK 0x3u +#define LLWU_PE1_WUPE0_SHIFT 0 +#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK) +#define LLWU_PE1_WUPE1_MASK 0xCu +#define LLWU_PE1_WUPE1_SHIFT 2 +#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK) +#define LLWU_PE1_WUPE2_MASK 0x30u +#define LLWU_PE1_WUPE2_SHIFT 4 +#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK) +#define LLWU_PE1_WUPE3_MASK 0xC0u +#define LLWU_PE1_WUPE3_SHIFT 6 +#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK) +/* PE2 Bit Fields */ +#define LLWU_PE2_WUPE4_MASK 0x3u +#define LLWU_PE2_WUPE4_SHIFT 0 +#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK) +#define LLWU_PE2_WUPE5_MASK 0xCu +#define LLWU_PE2_WUPE5_SHIFT 2 +#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK) +#define LLWU_PE2_WUPE6_MASK 0x30u +#define LLWU_PE2_WUPE6_SHIFT 4 +#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK) +#define LLWU_PE2_WUPE7_MASK 0xC0u +#define LLWU_PE2_WUPE7_SHIFT 6 +#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK) +/* PE3 Bit Fields */ +#define LLWU_PE3_WUPE8_MASK 0x3u +#define LLWU_PE3_WUPE8_SHIFT 0 +#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK) +#define LLWU_PE3_WUPE9_MASK 0xCu +#define LLWU_PE3_WUPE9_SHIFT 2 +#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK) +#define LLWU_PE3_WUPE10_MASK 0x30u +#define LLWU_PE3_WUPE10_SHIFT 4 +#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK) +#define LLWU_PE3_WUPE11_MASK 0xC0u +#define LLWU_PE3_WUPE11_SHIFT 6 +#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK) +/* PE4 Bit Fields */ +#define LLWU_PE4_WUPE12_MASK 0x3u +#define LLWU_PE4_WUPE12_SHIFT 0 +#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK) +#define LLWU_PE4_WUPE13_MASK 0xCu +#define LLWU_PE4_WUPE13_SHIFT 2 +#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK) +#define LLWU_PE4_WUPE14_MASK 0x30u +#define LLWU_PE4_WUPE14_SHIFT 4 +#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK) +#define LLWU_PE4_WUPE15_MASK 0xC0u +#define LLWU_PE4_WUPE15_SHIFT 6 +#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK) +/* ME Bit Fields */ +#define LLWU_ME_WUME0_MASK 0x1u +#define LLWU_ME_WUME0_SHIFT 0 +#define LLWU_ME_WUME1_MASK 0x2u +#define LLWU_ME_WUME1_SHIFT 1 +#define LLWU_ME_WUME2_MASK 0x4u +#define LLWU_ME_WUME2_SHIFT 2 +#define LLWU_ME_WUME3_MASK 0x8u +#define LLWU_ME_WUME3_SHIFT 3 +#define LLWU_ME_WUME4_MASK 0x10u +#define LLWU_ME_WUME4_SHIFT 4 +#define LLWU_ME_WUME5_MASK 0x20u +#define LLWU_ME_WUME5_SHIFT 5 +#define LLWU_ME_WUME6_MASK 0x40u +#define LLWU_ME_WUME6_SHIFT 6 +#define LLWU_ME_WUME7_MASK 0x80u +#define LLWU_ME_WUME7_SHIFT 7 +/* F1 Bit Fields */ +#define LLWU_F1_WUF0_MASK 0x1u +#define LLWU_F1_WUF0_SHIFT 0 +#define LLWU_F1_WUF1_MASK 0x2u +#define LLWU_F1_WUF1_SHIFT 1 +#define LLWU_F1_WUF2_MASK 0x4u +#define LLWU_F1_WUF2_SHIFT 2 +#define LLWU_F1_WUF3_MASK 0x8u +#define LLWU_F1_WUF3_SHIFT 3 +#define LLWU_F1_WUF4_MASK 0x10u +#define LLWU_F1_WUF4_SHIFT 4 +#define LLWU_F1_WUF5_MASK 0x20u +#define LLWU_F1_WUF5_SHIFT 5 +#define LLWU_F1_WUF6_MASK 0x40u +#define LLWU_F1_WUF6_SHIFT 6 +#define LLWU_F1_WUF7_MASK 0x80u +#define LLWU_F1_WUF7_SHIFT 7 +/* F2 Bit Fields */ +#define LLWU_F2_WUF8_MASK 0x1u +#define LLWU_F2_WUF8_SHIFT 0 +#define LLWU_F2_WUF9_MASK 0x2u +#define LLWU_F2_WUF9_SHIFT 1 +#define LLWU_F2_WUF10_MASK 0x4u +#define LLWU_F2_WUF10_SHIFT 2 +#define LLWU_F2_WUF11_MASK 0x8u +#define LLWU_F2_WUF11_SHIFT 3 +#define LLWU_F2_WUF12_MASK 0x10u +#define LLWU_F2_WUF12_SHIFT 4 +#define LLWU_F2_WUF13_MASK 0x20u +#define LLWU_F2_WUF13_SHIFT 5 +#define LLWU_F2_WUF14_MASK 0x40u +#define LLWU_F2_WUF14_SHIFT 6 +#define LLWU_F2_WUF15_MASK 0x80u +#define LLWU_F2_WUF15_SHIFT 7 +/* F3 Bit Fields */ +#define LLWU_F3_MWUF0_MASK 0x1u +#define LLWU_F3_MWUF0_SHIFT 0 +#define LLWU_F3_MWUF1_MASK 0x2u +#define LLWU_F3_MWUF1_SHIFT 1 +#define LLWU_F3_MWUF2_MASK 0x4u +#define LLWU_F3_MWUF2_SHIFT 2 +#define LLWU_F3_MWUF3_MASK 0x8u +#define LLWU_F3_MWUF3_SHIFT 3 +#define LLWU_F3_MWUF4_MASK 0x10u +#define LLWU_F3_MWUF4_SHIFT 4 +#define LLWU_F3_MWUF5_MASK 0x20u +#define LLWU_F3_MWUF5_SHIFT 5 +#define LLWU_F3_MWUF6_MASK 0x40u +#define LLWU_F3_MWUF6_SHIFT 6 +#define LLWU_F3_MWUF7_MASK 0x80u +#define LLWU_F3_MWUF7_SHIFT 7 +/* FILT1 Bit Fields */ +#define LLWU_FILT1_FILTSEL_MASK 0xFu +#define LLWU_FILT1_FILTSEL_SHIFT 0 +#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK) +#define LLWU_FILT1_FILTE_MASK 0x60u +#define LLWU_FILT1_FILTE_SHIFT 5 +#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK) +#define LLWU_FILT1_FILTF_MASK 0x80u +#define LLWU_FILT1_FILTF_SHIFT 7 +/* FILT2 Bit Fields */ +#define LLWU_FILT2_FILTSEL_MASK 0xFu +#define LLWU_FILT2_FILTSEL_SHIFT 0 +#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK) +#define LLWU_FILT2_FILTE_MASK 0x60u +#define LLWU_FILT2_FILTE_SHIFT 5 +#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK) +#define LLWU_FILT2_FILTF_MASK 0x80u +#define LLWU_FILT2_FILTF_SHIFT 7 +/* RST Bit Fields */ +#define LLWU_RST_RSTFILT_MASK 0x1u +#define LLWU_RST_RSTFILT_SHIFT 0 +#define LLWU_RST_LLRSTE_MASK 0x2u +#define LLWU_RST_LLRSTE_SHIFT 1 + +/** + * @} + */ /* end of group LLWU_Register_Masks */ + + +/* LLWU - Peripheral instance base addresses */ +/** Peripheral LLWU base address */ +#define LLWU_BASE (0x4007C000u) +/** Peripheral LLWU base pointer */ +#define LLWU ((LLWU_Type *)LLWU_BASE) + +/** + * @} + */ /* end of group LLWU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer + * @{ + */ + +/** LPTMR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ + __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ + __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ + __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ +} LPTMR_Type; + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/* CSR Bit Fields */ +#define LPTMR_CSR_TEN_MASK 0x1u +#define LPTMR_CSR_TEN_SHIFT 0 +#define LPTMR_CSR_TMS_MASK 0x2u +#define LPTMR_CSR_TMS_SHIFT 1 +#define LPTMR_CSR_TFC_MASK 0x4u +#define LPTMR_CSR_TFC_SHIFT 2 +#define LPTMR_CSR_TPP_MASK 0x8u +#define LPTMR_CSR_TPP_SHIFT 3 +#define LPTMR_CSR_TPS_MASK 0x30u +#define LPTMR_CSR_TPS_SHIFT 4 +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK) +#define LPTMR_CSR_TIE_MASK 0x40u +#define LPTMR_CSR_TIE_SHIFT 6 +#define LPTMR_CSR_TCF_MASK 0x80u +#define LPTMR_CSR_TCF_SHIFT 7 +/* PSR Bit Fields */ +#define LPTMR_PSR_PCS_MASK 0x3u +#define LPTMR_PSR_PCS_SHIFT 0 +#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK) +#define LPTMR_PSR_PBYP_MASK 0x4u +#define LPTMR_PSR_PBYP_SHIFT 2 +#define LPTMR_PSR_PRESCALE_MASK 0x78u +#define LPTMR_PSR_PRESCALE_SHIFT 3 +#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK) +/* CMR Bit Fields */ +#define LPTMR_CMR_COMPARE_MASK 0xFFFFu +#define LPTMR_CMR_COMPARE_SHIFT 0 +#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK) +/* CNR Bit Fields */ +#define LPTMR_CNR_COUNTER_MASK 0xFFFFu +#define LPTMR_CNR_COUNTER_SHIFT 0 +#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK) + +/** + * @} + */ /* end of group LPTMR_Register_Masks */ + + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x40040000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + +/** + * @} + */ /* end of group LPTMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MCG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer + * @{ + */ + +/** MCG - Register Layout Typedef */ +typedef struct { + __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ + __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ + __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ + __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ + __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ + __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ + __I uint8_t S; /**< MCG Status Register, offset: 0x6 */ + uint8_t RESERVED_0[1]; + __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ + uint8_t RESERVED_1[1]; + __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ + __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ + __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ + __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ +} MCG_Type; + +/* ---------------------------------------------------------------------------- + -- MCG Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup MCG_Register_Masks MCG Register Masks + * @{ + */ + +/* C1 Bit Fields */ +#define MCG_C1_IREFSTEN_MASK 0x1u +#define MCG_C1_IREFSTEN_SHIFT 0 +#define MCG_C1_IRCLKEN_MASK 0x2u +#define MCG_C1_IRCLKEN_SHIFT 1 +#define MCG_C1_IREFS_MASK 0x4u +#define MCG_C1_IREFS_SHIFT 2 +#define MCG_C1_FRDIV_MASK 0x38u +#define MCG_C1_FRDIV_SHIFT 3 +#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK) +#define MCG_C1_CLKS_MASK 0xC0u +#define MCG_C1_CLKS_SHIFT 6 +#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK) +/* C2 Bit Fields */ +#define MCG_C2_IRCS_MASK 0x1u +#define MCG_C2_IRCS_SHIFT 0 +#define MCG_C2_LP_MASK 0x2u +#define MCG_C2_LP_SHIFT 1 +#define MCG_C2_EREFS0_MASK 0x4u +#define MCG_C2_EREFS0_SHIFT 2 +#define MCG_C2_HGO0_MASK 0x8u +#define MCG_C2_HGO0_SHIFT 3 +#define MCG_C2_RANGE0_MASK 0x30u +#define MCG_C2_RANGE0_SHIFT 4 +#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK) +#define MCG_C2_LOCRE0_MASK 0x80u +#define MCG_C2_LOCRE0_SHIFT 7 +/* C3 Bit Fields */ +#define MCG_C3_SCTRIM_MASK 0xFFu +#define MCG_C3_SCTRIM_SHIFT 0 +#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK) +/* C4 Bit Fields */ +#define MCG_C4_SCFTRIM_MASK 0x1u +#define MCG_C4_SCFTRIM_SHIFT 0 +#define MCG_C4_FCTRIM_MASK 0x1Eu +#define MCG_C4_FCTRIM_SHIFT 1 +#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK) +#define MCG_C4_DRST_DRS_MASK 0x60u +#define MCG_C4_DRST_DRS_SHIFT 5 +#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK) +#define MCG_C4_DMX32_MASK 0x80u +#define MCG_C4_DMX32_SHIFT 7 +/* C5 Bit Fields */ +#define MCG_C5_PRDIV0_MASK 0x1Fu +#define MCG_C5_PRDIV0_SHIFT 0 +#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK) +#define MCG_C5_PLLSTEN0_MASK 0x20u +#define MCG_C5_PLLSTEN0_SHIFT 5 +#define MCG_C5_PLLCLKEN0_MASK 0x40u +#define MCG_C5_PLLCLKEN0_SHIFT 6 +/* C6 Bit Fields */ +#define MCG_C6_VDIV0_MASK 0x1Fu +#define MCG_C6_VDIV0_SHIFT 0 +#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK) +#define MCG_C6_CME0_MASK 0x20u +#define MCG_C6_CME0_SHIFT 5 +#define MCG_C6_PLLS_MASK 0x40u +#define MCG_C6_PLLS_SHIFT 6 +#define MCG_C6_LOLIE0_MASK 0x80u +#define MCG_C6_LOLIE0_SHIFT 7 +/* S Bit Fields */ +#define MCG_S_IRCST_MASK 0x1u +#define MCG_S_IRCST_SHIFT 0 +#define MCG_S_OSCINIT0_MASK 0x2u +#define MCG_S_OSCINIT0_SHIFT 1 +#define MCG_S_CLKST_MASK 0xCu +#define MCG_S_CLKST_SHIFT 2 +#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK) +#define MCG_S_IREFST_MASK 0x10u +#define MCG_S_IREFST_SHIFT 4 +#define MCG_S_PLLST_MASK 0x20u +#define MCG_S_PLLST_SHIFT 5 +#define MCG_S_LOCK0_MASK 0x40u +#define MCG_S_LOCK0_SHIFT 6 +#define MCG_S_LOLS0_MASK 0x80u +#define MCG_S_LOLS0_SHIFT 7 +/* SC Bit Fields */ +#define MCG_SC_LOCS0_MASK 0x1u +#define MCG_SC_LOCS0_SHIFT 0 +#define MCG_SC_FCRDIV_MASK 0xEu +#define MCG_SC_FCRDIV_SHIFT 1 +#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK) +#define MCG_SC_FLTPRSRV_MASK 0x10u +#define MCG_SC_FLTPRSRV_SHIFT 4 +#define MCG_SC_ATMF_MASK 0x20u +#define MCG_SC_ATMF_SHIFT 5 +#define MCG_SC_ATMS_MASK 0x40u +#define MCG_SC_ATMS_SHIFT 6 +#define MCG_SC_ATME_MASK 0x80u +#define MCG_SC_ATME_SHIFT 7 +/* ATCVH Bit Fields */ +#define MCG_ATCVH_ATCVH_MASK 0xFFu +#define MCG_ATCVH_ATCVH_SHIFT 0 +#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK) +/* ATCVL Bit Fields */ +#define MCG_ATCVL_ATCVL_MASK 0xFFu +#define MCG_ATCVL_ATCVL_SHIFT 0 +#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK) +/* C7 Bit Fields */ +#define MCG_C7_OSCSEL_MASK 0x1u +#define MCG_C7_OSCSEL_SHIFT 0 +/* C8 Bit Fields */ +#define MCG_C8_LOCS1_MASK 0x1u +#define MCG_C8_LOCS1_SHIFT 0 +#define MCG_C8_CME1_MASK 0x20u +#define MCG_C8_CME1_SHIFT 5 +#define MCG_C8_LOLRE_MASK 0x40u +#define MCG_C8_LOLRE_SHIFT 6 +#define MCG_C8_LOCRE1_MASK 0x80u +#define MCG_C8_LOCRE1_SHIFT 7 + +/** + * @} + */ /* end of group MCG_Register_Masks */ + + +/* MCG - Peripheral instance base addresses */ +/** Peripheral MCG base address */ +#define MCG_BASE (0x40064000u) +/** Peripheral MCG base pointer */ +#define MCG ((MCG_Type *)MCG_BASE) + +/** + * @} + */ /* end of group MCG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- NV Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer + * @{ + */ + +/** NV - Register Layout Typedef */ +typedef struct { + __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ + __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ + __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ + __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ + __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ + __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ + __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ + __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ + __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ + __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ + __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ + __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ + __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ + __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ + __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */ + __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */ +} NV_Type; + +/* ---------------------------------------------------------------------------- + -- NV Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup NV_Register_Masks NV Register Masks + * @{ + */ + +/* BACKKEY3 Bit Fields */ +#define NV_BACKKEY3_KEY_MASK 0xFFu +#define NV_BACKKEY3_KEY_SHIFT 0 +#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK) +/* BACKKEY2 Bit Fields */ +#define NV_BACKKEY2_KEY_MASK 0xFFu +#define NV_BACKKEY2_KEY_SHIFT 0 +#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK) +/* BACKKEY1 Bit Fields */ +#define NV_BACKKEY1_KEY_MASK 0xFFu +#define NV_BACKKEY1_KEY_SHIFT 0 +#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK) +/* BACKKEY0 Bit Fields */ +#define NV_BACKKEY0_KEY_MASK 0xFFu +#define NV_BACKKEY0_KEY_SHIFT 0 +#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK) +/* BACKKEY7 Bit Fields */ +#define NV_BACKKEY7_KEY_MASK 0xFFu +#define NV_BACKKEY7_KEY_SHIFT 0 +#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK) +/* BACKKEY6 Bit Fields */ +#define NV_BACKKEY6_KEY_MASK 0xFFu +#define NV_BACKKEY6_KEY_SHIFT 0 +#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK) +/* BACKKEY5 Bit Fields */ +#define NV_BACKKEY5_KEY_MASK 0xFFu +#define NV_BACKKEY5_KEY_SHIFT 0 +#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK) +/* BACKKEY4 Bit Fields */ +#define NV_BACKKEY4_KEY_MASK 0xFFu +#define NV_BACKKEY4_KEY_SHIFT 0 +#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK) +/* FPROT3 Bit Fields */ +#define NV_FPROT3_PROT_MASK 0xFFu +#define NV_FPROT3_PROT_SHIFT 0 +#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK) +/* FPROT2 Bit Fields */ +#define NV_FPROT2_PROT_MASK 0xFFu +#define NV_FPROT2_PROT_SHIFT 0 +#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK) +/* FPROT1 Bit Fields */ +#define NV_FPROT1_PROT_MASK 0xFFu +#define NV_FPROT1_PROT_SHIFT 0 +#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK) +/* FPROT0 Bit Fields */ +#define NV_FPROT0_PROT_MASK 0xFFu +#define NV_FPROT0_PROT_SHIFT 0 +#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK) +/* FSEC Bit Fields */ +#define NV_FSEC_SEC_MASK 0x3u +#define NV_FSEC_SEC_SHIFT 0 +#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK) +#define NV_FSEC_FSLACC_MASK 0xCu +#define NV_FSEC_FSLACC_SHIFT 2 +#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK) +#define NV_FSEC_MEEN_MASK 0x30u +#define NV_FSEC_MEEN_SHIFT 4 +#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK) +#define NV_FSEC_KEYEN_MASK 0xC0u +#define NV_FSEC_KEYEN_SHIFT 6 +#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK) +/* FOPT Bit Fields */ +#define NV_FOPT_LPBOOT_MASK 0x1u +#define NV_FOPT_LPBOOT_SHIFT 0 +#define NV_FOPT_EZPORT_DIS_MASK 0x2u +#define NV_FOPT_EZPORT_DIS_SHIFT 1 +/* FEPROT Bit Fields */ +#define NV_FEPROT_EPROT_MASK 0xFFu +#define NV_FEPROT_EPROT_SHIFT 0 +#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK) +/* FDPROT Bit Fields */ +#define NV_FDPROT_DPROT_MASK 0xFFu +#define NV_FDPROT_DPROT_SHIFT 0 +#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK) + +/** + * @} + */ /* end of group NV_Register_Masks */ + + +/* NV - Peripheral instance base addresses */ +/** Peripheral FTFL_FlashConfig base address */ +#define FTFL_FlashConfig_BASE (0x400u) +/** Peripheral FTFL_FlashConfig base pointer */ +#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE) + +/** + * @} + */ /* end of group NV_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer + * @{ + */ + +/** OSC - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ +} OSC_Type; + +/* ---------------------------------------------------------------------------- + -- OSC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup OSC_Register_Masks OSC Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define OSC_CR_SC16P_MASK 0x1u +#define OSC_CR_SC16P_SHIFT 0 +#define OSC_CR_SC8P_MASK 0x2u +#define OSC_CR_SC8P_SHIFT 1 +#define OSC_CR_SC4P_MASK 0x4u +#define OSC_CR_SC4P_SHIFT 2 +#define OSC_CR_SC2P_MASK 0x8u +#define OSC_CR_SC2P_SHIFT 3 +#define OSC_CR_EREFSTEN_MASK 0x20u +#define OSC_CR_EREFSTEN_SHIFT 5 +#define OSC_CR_ERCLKEN_MASK 0x80u +#define OSC_CR_ERCLKEN_SHIFT 7 + +/** + * @} + */ /* end of group OSC_Register_Masks */ + + +/* OSC - Peripheral instance base addresses */ +/** Peripheral OSC0 base address */ +#define OSC0_BASE (0x40065000u) +/** Peripheral OSC0 base pointer */ +#define OSC0 ((OSC_Type *)OSC0_BASE) + +/** + * @} + */ /* end of group OSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PDB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer + * @{ + */ + +/** PDB - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */ + __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */ + __I uint32_t CNT; /**< Counter Register, offset: 0x8 */ + __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */ + struct { /* offset: 0x10, array step: 0x10 */ + __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */ + __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */ + __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */ + } CH[1]; + uint8_t RESERVED_0[368]; + __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */ + __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */ +} PDB_Type; + +/* ---------------------------------------------------------------------------- + -- PDB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PDB_Register_Masks PDB Register Masks + * @{ + */ + +/* SC Bit Fields */ +#define PDB_SC_LDOK_MASK 0x1u +#define PDB_SC_LDOK_SHIFT 0 +#define PDB_SC_CONT_MASK 0x2u +#define PDB_SC_CONT_SHIFT 1 +#define PDB_SC_MULT_MASK 0xCu +#define PDB_SC_MULT_SHIFT 2 +#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK) +#define PDB_SC_PDBIE_MASK 0x20u +#define PDB_SC_PDBIE_SHIFT 5 +#define PDB_SC_PDBIF_MASK 0x40u +#define PDB_SC_PDBIF_SHIFT 6 +#define PDB_SC_PDBEN_MASK 0x80u +#define PDB_SC_PDBEN_SHIFT 7 +#define PDB_SC_TRGSEL_MASK 0xF00u +#define PDB_SC_TRGSEL_SHIFT 8 +#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK) +#define PDB_SC_PRESCALER_MASK 0x7000u +#define PDB_SC_PRESCALER_SHIFT 12 +#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK) +#define PDB_SC_DMAEN_MASK 0x8000u +#define PDB_SC_DMAEN_SHIFT 15 +#define PDB_SC_SWTRIG_MASK 0x10000u +#define PDB_SC_SWTRIG_SHIFT 16 +#define PDB_SC_PDBEIE_MASK 0x20000u +#define PDB_SC_PDBEIE_SHIFT 17 +#define PDB_SC_LDMOD_MASK 0xC0000u +#define PDB_SC_LDMOD_SHIFT 18 +#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK) +/* MOD Bit Fields */ +#define PDB_MOD_MOD_MASK 0xFFFFu +#define PDB_MOD_MOD_SHIFT 0 +#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK) +/* CNT Bit Fields */ +#define PDB_CNT_CNT_MASK 0xFFFFu +#define PDB_CNT_CNT_SHIFT 0 +#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK) +/* IDLY Bit Fields */ +#define PDB_IDLY_IDLY_MASK 0xFFFFu +#define PDB_IDLY_IDLY_SHIFT 0 +#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK) +/* C1 Bit Fields */ +#define PDB_C1_EN_MASK 0xFFu +#define PDB_C1_EN_SHIFT 0 +#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK) +#define PDB_C1_TOS_MASK 0xFF00u +#define PDB_C1_TOS_SHIFT 8 +#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK) +#define PDB_C1_BB_MASK 0xFF0000u +#define PDB_C1_BB_SHIFT 16 +#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK) +/* S Bit Fields */ +#define PDB_S_ERR_MASK 0xFFu +#define PDB_S_ERR_SHIFT 0 +#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK) +#define PDB_S_CF_MASK 0xFF0000u +#define PDB_S_CF_SHIFT 16 +#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK) +/* DLY Bit Fields */ +#define PDB_DLY_DLY_MASK 0xFFFFu +#define PDB_DLY_DLY_SHIFT 0 +#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK) +/* POEN Bit Fields */ +#define PDB_POEN_POEN_MASK 0xFFu +#define PDB_POEN_POEN_SHIFT 0 +#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK) +/* PODLY Bit Fields */ +#define PDB_PODLY_DLY2_MASK 0xFFFFu +#define PDB_PODLY_DLY2_SHIFT 0 +#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK) +#define PDB_PODLY_DLY1_MASK 0xFFFF0000u +#define PDB_PODLY_DLY1_SHIFT 16 +#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK) + +/** + * @} + */ /* end of group PDB_Register_Masks */ + + +/* PDB - Peripheral instance base addresses */ +/** Peripheral PDB0 base address */ +#define PDB0_BASE (0x40036000u) +/** Peripheral PDB0 base pointer */ +#define PDB0 ((PDB_Type *)PDB0_BASE) + +/** + * @} + */ /* end of group PDB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer + * @{ + */ + +/** PIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ + uint8_t RESERVED_0[252]; + struct { /* offset: 0x100, array step: 0x10 */ + __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ + __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ + __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ + __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ + } CHANNEL[4]; +} PIT_Type; + +/* ---------------------------------------------------------------------------- + -- PIT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PIT_Register_Masks PIT Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define PIT_MCR_FRZ_MASK 0x1u +#define PIT_MCR_FRZ_SHIFT 0 +#define PIT_MCR_MDIS_MASK 0x2u +#define PIT_MCR_MDIS_SHIFT 1 +/* LDVAL Bit Fields */ +#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu +#define PIT_LDVAL_TSV_SHIFT 0 +#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK) +/* CVAL Bit Fields */ +#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu +#define PIT_CVAL_TVL_SHIFT 0 +#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK) +/* TCTRL Bit Fields */ +#define PIT_TCTRL_TEN_MASK 0x1u +#define PIT_TCTRL_TEN_SHIFT 0 +#define PIT_TCTRL_TIE_MASK 0x2u +#define PIT_TCTRL_TIE_SHIFT 1 +/* TFLG Bit Fields */ +#define PIT_TFLG_TIF_MASK 0x1u +#define PIT_TFLG_TIF_SHIFT 0 + +/** + * @} + */ /* end of group PIT_Register_Masks */ + + +/* PIT - Peripheral instance base addresses */ +/** Peripheral PIT base address */ +#define PIT_BASE (0x40037000u) +/** Peripheral PIT base pointer */ +#define PIT ((PIT_Type *)PIT_BASE) + +/** + * @} + */ /* end of group PIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer + * @{ + */ + +/** PMC - Register Layout Typedef */ +typedef struct { + __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */ + __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */ + __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */ +} PMC_Type; + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/* LVDSC1 Bit Fields */ +#define PMC_LVDSC1_LVDV_MASK 0x3u +#define PMC_LVDSC1_LVDV_SHIFT 0 +#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) +#define PMC_LVDSC1_LVDRE_MASK 0x10u +#define PMC_LVDSC1_LVDRE_SHIFT 4 +#define PMC_LVDSC1_LVDIE_MASK 0x20u +#define PMC_LVDSC1_LVDIE_SHIFT 5 +#define PMC_LVDSC1_LVDACK_MASK 0x40u +#define PMC_LVDSC1_LVDACK_SHIFT 6 +#define PMC_LVDSC1_LVDF_MASK 0x80u +#define PMC_LVDSC1_LVDF_SHIFT 7 +/* LVDSC2 Bit Fields */ +#define PMC_LVDSC2_LVWV_MASK 0x3u +#define PMC_LVDSC2_LVWV_SHIFT 0 +#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) +#define PMC_LVDSC2_LVWIE_MASK 0x20u +#define PMC_LVDSC2_LVWIE_SHIFT 5 +#define PMC_LVDSC2_LVWACK_MASK 0x40u +#define PMC_LVDSC2_LVWACK_SHIFT 6 +#define PMC_LVDSC2_LVWF_MASK 0x80u +#define PMC_LVDSC2_LVWF_SHIFT 7 +/* REGSC Bit Fields */ +#define PMC_REGSC_BGBE_MASK 0x1u +#define PMC_REGSC_BGBE_SHIFT 0 +#define PMC_REGSC_REGONS_MASK 0x4u +#define PMC_REGSC_REGONS_SHIFT 2 +#define PMC_REGSC_ACKISO_MASK 0x8u +#define PMC_REGSC_ACKISO_SHIFT 3 + +/** + * @} + */ /* end of group PMC_Register_Masks */ + + +/* PMC - Peripheral instance base addresses */ +/** Peripheral PMC base address */ +#define PMC_BASE (0x4007D000u) +/** Peripheral PMC base pointer */ +#define PMC ((PMC_Type *)PMC_BASE) + +/** + * @} + */ /* end of group PMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PORT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer + * @{ + */ + +/** PORT - Register Layout Typedef */ +typedef struct { + __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ + __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ + __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ + uint8_t RESERVED_0[24]; + __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ + uint8_t RESERVED_1[28]; + __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ + __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ + __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ +} PORT_Type; + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/* PCR Bit Fields */ +#define PORT_PCR_PS_MASK 0x1u +#define PORT_PCR_PS_SHIFT 0 +#define PORT_PCR_PE_MASK 0x2u +#define PORT_PCR_PE_SHIFT 1 +#define PORT_PCR_SRE_MASK 0x4u +#define PORT_PCR_SRE_SHIFT 2 +#define PORT_PCR_PFE_MASK 0x10u +#define PORT_PCR_PFE_SHIFT 4 +#define PORT_PCR_ODE_MASK 0x20u +#define PORT_PCR_ODE_SHIFT 5 +#define PORT_PCR_DSE_MASK 0x40u +#define PORT_PCR_DSE_SHIFT 6 +#define PORT_PCR_MUX_MASK 0x700u +#define PORT_PCR_MUX_SHIFT 8 +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK) +#define PORT_PCR_LK_MASK 0x8000u +#define PORT_PCR_LK_SHIFT 15 +#define PORT_PCR_IRQC_MASK 0xF0000u +#define PORT_PCR_IRQC_SHIFT 16 +#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK) +#define PORT_PCR_ISF_MASK 0x1000000u +#define PORT_PCR_ISF_SHIFT 24 +/* GPCLR Bit Fields */ +#define PORT_GPCLR_GPWD_MASK 0xFFFFu +#define PORT_GPCLR_GPWD_SHIFT 0 +#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK) +#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u +#define PORT_GPCLR_GPWE_SHIFT 16 +#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK) +/* GPCHR Bit Fields */ +#define PORT_GPCHR_GPWD_MASK 0xFFFFu +#define PORT_GPCHR_GPWD_SHIFT 0 +#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK) +#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u +#define PORT_GPCHR_GPWE_SHIFT 16 +#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK) +/* ISFR Bit Fields */ +#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu +#define PORT_ISFR_ISF_SHIFT 0 +#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK) +/* DFER Bit Fields */ +#define PORT_DFER_DFE_MASK 0xFFFFFFFFu +#define PORT_DFER_DFE_SHIFT 0 +#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK) +/* DFCR Bit Fields */ +#define PORT_DFCR_CS_MASK 0x1u +#define PORT_DFCR_CS_SHIFT 0 +/* DFWR Bit Fields */ +#define PORT_DFWR_FILT_MASK 0x1Fu +#define PORT_DFWR_FILT_SHIFT 0 +#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK) + +/** + * @} + */ /* end of group PORT_Register_Masks */ + + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORTA base address */ +#define PORTA_BASE (0x40049000u) +/** Peripheral PORTA base pointer */ +#define PORTA ((PORT_Type *)PORTA_BASE) +/** Peripheral PORTB base address */ +#define PORTB_BASE (0x4004A000u) +/** Peripheral PORTB base pointer */ +#define PORTB ((PORT_Type *)PORTB_BASE) +/** Peripheral PORTC base address */ +#define PORTC_BASE (0x4004B000u) +/** Peripheral PORTC base pointer */ +#define PORTC ((PORT_Type *)PORTC_BASE) +/** Peripheral PORTD base address */ +#define PORTD_BASE (0x4004C000u) +/** Peripheral PORTD base pointer */ +#define PORTD ((PORT_Type *)PORTD_BASE) +/** Peripheral PORTE base address */ +#define PORTE_BASE (0x4004D000u) +/** Peripheral PORTE base pointer */ +#define PORTE ((PORT_Type *)PORTE_BASE) + +/** + * @} + */ /* end of group PORT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer + * @{ + */ + +/** RCM - Register Layout Typedef */ +typedef struct { + __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ + __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ + uint8_t RESERVED_0[2]; + __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */ + __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */ + uint8_t RESERVED_1[1]; + __I uint8_t MR; /**< Mode Register, offset: 0x7 */ +} RCM_Type; + +/* ---------------------------------------------------------------------------- + -- RCM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RCM_Register_Masks RCM Register Masks + * @{ + */ + +/* SRS0 Bit Fields */ +#define RCM_SRS0_WAKEUP_MASK 0x1u +#define RCM_SRS0_WAKEUP_SHIFT 0 +#define RCM_SRS0_LVD_MASK 0x2u +#define RCM_SRS0_LVD_SHIFT 1 +#define RCM_SRS0_LOC_MASK 0x4u +#define RCM_SRS0_LOC_SHIFT 2 +#define RCM_SRS0_LOL_MASK 0x8u +#define RCM_SRS0_LOL_SHIFT 3 +#define RCM_SRS0_WDOG_MASK 0x20u +#define RCM_SRS0_WDOG_SHIFT 5 +#define RCM_SRS0_PIN_MASK 0x40u +#define RCM_SRS0_PIN_SHIFT 6 +#define RCM_SRS0_POR_MASK 0x80u +#define RCM_SRS0_POR_SHIFT 7 +/* SRS1 Bit Fields */ +#define RCM_SRS1_JTAG_MASK 0x1u +#define RCM_SRS1_JTAG_SHIFT 0 +#define RCM_SRS1_LOCKUP_MASK 0x2u +#define RCM_SRS1_LOCKUP_SHIFT 1 +#define RCM_SRS1_SW_MASK 0x4u +#define RCM_SRS1_SW_SHIFT 2 +#define RCM_SRS1_MDM_AP_MASK 0x8u +#define RCM_SRS1_MDM_AP_SHIFT 3 +#define RCM_SRS1_EZPT_MASK 0x10u +#define RCM_SRS1_EZPT_SHIFT 4 +#define RCM_SRS1_SACKERR_MASK 0x20u +#define RCM_SRS1_SACKERR_SHIFT 5 +/* RPFC Bit Fields */ +#define RCM_RPFC_RSTFLTSRW_MASK 0x3u +#define RCM_RPFC_RSTFLTSRW_SHIFT 0 +#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK) +#define RCM_RPFC_RSTFLTSS_MASK 0x4u +#define RCM_RPFC_RSTFLTSS_SHIFT 2 +/* RPFW Bit Fields */ +#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu +#define RCM_RPFW_RSTFLTSEL_SHIFT 0 +#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK) +/* MR Bit Fields */ +#define RCM_MR_EZP_MS_MASK 0x2u +#define RCM_MR_EZP_MS_SHIFT 1 + +/** + * @} + */ /* end of group RCM_Register_Masks */ + + +/* RCM - Peripheral instance base addresses */ +/** Peripheral RCM base address */ +#define RCM_BASE (0x4007F000u) +/** Peripheral RCM base pointer */ +#define RCM ((RCM_Type *)RCM_BASE) + +/** + * @} + */ /* end of group RCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RFSYS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer + * @{ + */ + +/** RFSYS - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ +} RFSYS_Type; + +/* ---------------------------------------------------------------------------- + -- RFSYS Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RFSYS_Register_Masks RFSYS Register Masks + * @{ + */ + +/* REG Bit Fields */ +#define RFSYS_REG_LL_MASK 0xFFu +#define RFSYS_REG_LL_SHIFT 0 +#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK) +#define RFSYS_REG_LH_MASK 0xFF00u +#define RFSYS_REG_LH_SHIFT 8 +#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK) +#define RFSYS_REG_HL_MASK 0xFF0000u +#define RFSYS_REG_HL_SHIFT 16 +#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK) +#define RFSYS_REG_HH_MASK 0xFF000000u +#define RFSYS_REG_HH_SHIFT 24 +#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK) + +/** + * @} + */ /* end of group RFSYS_Register_Masks */ + + +/* RFSYS - Peripheral instance base addresses */ +/** Peripheral RFSYS base address */ +#define RFSYS_BASE (0x40041000u) +/** Peripheral RFSYS base pointer */ +#define RFSYS ((RFSYS_Type *)RFSYS_BASE) + +/** + * @} + */ /* end of group RFSYS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RFVBAT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer + * @{ + */ + +/** RFVBAT - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */ +} RFVBAT_Type; + +/* ---------------------------------------------------------------------------- + -- RFVBAT Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks + * @{ + */ + +/* REG Bit Fields */ +#define RFVBAT_REG_LL_MASK 0xFFu +#define RFVBAT_REG_LL_SHIFT 0 +#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK) +#define RFVBAT_REG_LH_MASK 0xFF00u +#define RFVBAT_REG_LH_SHIFT 8 +#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK) +#define RFVBAT_REG_HL_MASK 0xFF0000u +#define RFVBAT_REG_HL_SHIFT 16 +#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK) +#define RFVBAT_REG_HH_MASK 0xFF000000u +#define RFVBAT_REG_HH_SHIFT 24 +#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK) + +/** + * @} + */ /* end of group RFVBAT_Register_Masks */ + + +/* RFVBAT - Peripheral instance base addresses */ +/** Peripheral RFVBAT base address */ +#define RFVBAT_BASE (0x4003E000u) +/** Peripheral RFVBAT base pointer */ +#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE) + +/** + * @} + */ /* end of group RFVBAT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ + __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ + __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ + __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ + __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ + __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ + __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ + __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ + uint8_t RESERVED_0[2016]; + __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ + __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/* TSR Bit Fields */ +#define RTC_TSR_TSR_MASK 0xFFFFFFFFu +#define RTC_TSR_TSR_SHIFT 0 +#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK) +/* TPR Bit Fields */ +#define RTC_TPR_TPR_MASK 0xFFFFu +#define RTC_TPR_TPR_SHIFT 0 +#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK) +/* TAR Bit Fields */ +#define RTC_TAR_TAR_MASK 0xFFFFFFFFu +#define RTC_TAR_TAR_SHIFT 0 +#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK) +/* TCR Bit Fields */ +#define RTC_TCR_TCR_MASK 0xFFu +#define RTC_TCR_TCR_SHIFT 0 +#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK) +#define RTC_TCR_CIR_MASK 0xFF00u +#define RTC_TCR_CIR_SHIFT 8 +#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK) +#define RTC_TCR_TCV_MASK 0xFF0000u +#define RTC_TCR_TCV_SHIFT 16 +#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK) +#define RTC_TCR_CIC_MASK 0xFF000000u +#define RTC_TCR_CIC_SHIFT 24 +#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK) +/* CR Bit Fields */ +#define RTC_CR_SWR_MASK 0x1u +#define RTC_CR_SWR_SHIFT 0 +#define RTC_CR_WPE_MASK 0x2u +#define RTC_CR_WPE_SHIFT 1 +#define RTC_CR_SUP_MASK 0x4u +#define RTC_CR_SUP_SHIFT 2 +#define RTC_CR_UM_MASK 0x8u +#define RTC_CR_UM_SHIFT 3 +#define RTC_CR_OSCE_MASK 0x100u +#define RTC_CR_OSCE_SHIFT 8 +#define RTC_CR_CLKO_MASK 0x200u +#define RTC_CR_CLKO_SHIFT 9 +#define RTC_CR_SC16P_MASK 0x400u +#define RTC_CR_SC16P_SHIFT 10 +#define RTC_CR_SC8P_MASK 0x800u +#define RTC_CR_SC8P_SHIFT 11 +#define RTC_CR_SC4P_MASK 0x1000u +#define RTC_CR_SC4P_SHIFT 12 +#define RTC_CR_SC2P_MASK 0x2000u +#define RTC_CR_SC2P_SHIFT 13 +/* SR Bit Fields */ +#define RTC_SR_TIF_MASK 0x1u +#define RTC_SR_TIF_SHIFT 0 +#define RTC_SR_TOF_MASK 0x2u +#define RTC_SR_TOF_SHIFT 1 +#define RTC_SR_TAF_MASK 0x4u +#define RTC_SR_TAF_SHIFT 2 +#define RTC_SR_TCE_MASK 0x10u +#define RTC_SR_TCE_SHIFT 4 +/* LR Bit Fields */ +#define RTC_LR_TCL_MASK 0x8u +#define RTC_LR_TCL_SHIFT 3 +#define RTC_LR_CRL_MASK 0x10u +#define RTC_LR_CRL_SHIFT 4 +#define RTC_LR_SRL_MASK 0x20u +#define RTC_LR_SRL_SHIFT 5 +#define RTC_LR_LRL_MASK 0x40u +#define RTC_LR_LRL_SHIFT 6 +/* IER Bit Fields */ +#define RTC_IER_TIIE_MASK 0x1u +#define RTC_IER_TIIE_SHIFT 0 +#define RTC_IER_TOIE_MASK 0x2u +#define RTC_IER_TOIE_SHIFT 1 +#define RTC_IER_TAIE_MASK 0x4u +#define RTC_IER_TAIE_SHIFT 2 +#define RTC_IER_TSIE_MASK 0x10u +#define RTC_IER_TSIE_SHIFT 4 +/* WAR Bit Fields */ +#define RTC_WAR_TSRW_MASK 0x1u +#define RTC_WAR_TSRW_SHIFT 0 +#define RTC_WAR_TPRW_MASK 0x2u +#define RTC_WAR_TPRW_SHIFT 1 +#define RTC_WAR_TARW_MASK 0x4u +#define RTC_WAR_TARW_SHIFT 2 +#define RTC_WAR_TCRW_MASK 0x8u +#define RTC_WAR_TCRW_SHIFT 3 +#define RTC_WAR_CRW_MASK 0x10u +#define RTC_WAR_CRW_SHIFT 4 +#define RTC_WAR_SRW_MASK 0x20u +#define RTC_WAR_SRW_SHIFT 5 +#define RTC_WAR_LRW_MASK 0x40u +#define RTC_WAR_LRW_SHIFT 6 +#define RTC_WAR_IERW_MASK 0x80u +#define RTC_WAR_IERW_SHIFT 7 +/* RAR Bit Fields */ +#define RTC_RAR_TSRR_MASK 0x1u +#define RTC_RAR_TSRR_SHIFT 0 +#define RTC_RAR_TPRR_MASK 0x2u +#define RTC_RAR_TPRR_SHIFT 1 +#define RTC_RAR_TARR_MASK 0x4u +#define RTC_RAR_TARR_SHIFT 2 +#define RTC_RAR_TCRR_MASK 0x8u +#define RTC_RAR_TCRR_SHIFT 3 +#define RTC_RAR_CRR_MASK 0x10u +#define RTC_RAR_CRR_SHIFT 4 +#define RTC_RAR_SRR_MASK 0x20u +#define RTC_RAR_SRR_SHIFT 5 +#define RTC_RAR_LRR_MASK 0x40u +#define RTC_RAR_LRR_SHIFT 6 +#define RTC_RAR_IERR_MASK 0x80u +#define RTC_RAR_IERR_SHIFT 7 + +/** + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC base address */ +#define RTC_BASE (0x4003D000u) +/** Peripheral RTC base pointer */ +#define RTC ((RTC_Type *)RTC_BASE) + +/** + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer + * @{ + */ + +/** SIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ + __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ + uint8_t RESERVED_0[4092]; + __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ + __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ + uint8_t RESERVED_3[8]; + __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ + __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */ + __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */ + __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */ + __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ + __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ + __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ + __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ + __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ + __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */ + __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ + __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ + __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */ + __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ + __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ + __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ +} SIM_Type; + +/* ---------------------------------------------------------------------------- + -- SIM Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SIM_Register_Masks SIM Register Masks + * @{ + */ + +/* SOPT1 Bit Fields */ +#define SIM_SOPT1_RAMSIZE_MASK 0xF000u +#define SIM_SOPT1_RAMSIZE_SHIFT 12 +#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK) +#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 +#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK) +#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u +#define SIM_SOPT1_USBVSTBY_SHIFT 29 +#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u +#define SIM_SOPT1_USBSSTBY_SHIFT 30 +#define SIM_SOPT1_USBREGEN_MASK 0x80000000u +#define SIM_SOPT1_USBREGEN_SHIFT 31 +/* SOPT1CFG Bit Fields */ +#define SIM_SOPT1CFG_URWE_MASK 0x1000000u +#define SIM_SOPT1CFG_URWE_SHIFT 24 +#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u +#define SIM_SOPT1CFG_UVSWE_SHIFT 25 +#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u +#define SIM_SOPT1CFG_USSWE_SHIFT 26 +/* SOPT2 Bit Fields */ +#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u +#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4 +#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 +#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK) +#define SIM_SOPT2_PTD7PAD_MASK 0x800u +#define SIM_SOPT2_PTD7PAD_SHIFT 11 +#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u +#define SIM_SOPT2_TRACECLKSEL_SHIFT 12 +#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u +#define SIM_SOPT2_PLLFLLSEL_SHIFT 16 +#define SIM_SOPT2_USBSRC_MASK 0x40000u +#define SIM_SOPT2_USBSRC_SHIFT 18 +/* SOPT4 Bit Fields */ +#define SIM_SOPT4_FTM0FLT0_MASK 0x1u +#define SIM_SOPT4_FTM0FLT0_SHIFT 0 +#define SIM_SOPT4_FTM0FLT1_MASK 0x2u +#define SIM_SOPT4_FTM0FLT1_SHIFT 1 +#define SIM_SOPT4_FTM0FLT2_MASK 0x4u +#define SIM_SOPT4_FTM0FLT2_SHIFT 2 +#define SIM_SOPT4_FTM1FLT0_MASK 0x10u +#define SIM_SOPT4_FTM1FLT0_SHIFT 4 +#define SIM_SOPT4_FTM2FLT0_MASK 0x100u +#define SIM_SOPT4_FTM2FLT0_SHIFT 8 +#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u +#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18 +#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK) +#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u +#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20 +#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK) +#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u +#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24 +#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u +#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25 +#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u +#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26 +#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u +#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28 +#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u +#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29 +/* SOPT5 Bit Fields */ +#define SIM_SOPT5_UART0TXSRC_MASK 0x1u +#define SIM_SOPT5_UART0TXSRC_SHIFT 0 +#define SIM_SOPT5_UART0RXSRC_MASK 0xCu +#define SIM_SOPT5_UART0RXSRC_SHIFT 2 +#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK) +#define SIM_SOPT5_UART1TXSRC_MASK 0x10u +#define SIM_SOPT5_UART1TXSRC_SHIFT 4 +#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u +#define SIM_SOPT5_UART1RXSRC_SHIFT 6 +#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK) +/* SOPT7 Bit Fields */ +#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu +#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 +#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK) +#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u +#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4 +#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u +#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7 +#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u +#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8 +#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK) +#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u +#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12 +#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u +#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15 +/* SDID Bit Fields */ +#define SIM_SDID_PINID_MASK 0xFu +#define SIM_SDID_PINID_SHIFT 0 +#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK) +#define SIM_SDID_FAMID_MASK 0x70u +#define SIM_SDID_FAMID_SHIFT 4 +#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK) +#define SIM_SDID_REVID_MASK 0xF000u +#define SIM_SDID_REVID_SHIFT 12 +#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK) +/* SCGC2 Bit Fields */ +#define SIM_SCGC2_DAC0_MASK 0x1000u +#define SIM_SCGC2_DAC0_SHIFT 12 +/* SCGC3 Bit Fields */ +#define SIM_SCGC3_FTM2_MASK 0x1000000u +#define SIM_SCGC3_FTM2_SHIFT 24 +#define SIM_SCGC3_ADC1_MASK 0x8000000u +#define SIM_SCGC3_ADC1_SHIFT 27 +/* SCGC4 Bit Fields */ +#define SIM_SCGC4_EWM_MASK 0x2u +#define SIM_SCGC4_EWM_SHIFT 1 +#define SIM_SCGC4_CMT_MASK 0x4u +#define SIM_SCGC4_CMT_SHIFT 2 +#define SIM_SCGC4_I2C0_MASK 0x40u +#define SIM_SCGC4_I2C0_SHIFT 6 +#define SIM_SCGC4_I2C1_MASK 0x80u +#define SIM_SCGC4_I2C1_SHIFT 7 +#define SIM_SCGC4_UART0_MASK 0x400u +#define SIM_SCGC4_UART0_SHIFT 10 +#define SIM_SCGC4_UART1_MASK 0x800u +#define SIM_SCGC4_UART1_SHIFT 11 +#define SIM_SCGC4_UART2_MASK 0x1000u +#define SIM_SCGC4_UART2_SHIFT 12 +#define SIM_SCGC4_USBOTG_MASK 0x40000u +#define SIM_SCGC4_USBOTG_SHIFT 18 +#define SIM_SCGC4_CMP_MASK 0x80000u +#define SIM_SCGC4_CMP_SHIFT 19 +#define SIM_SCGC4_VREF_MASK 0x100000u +#define SIM_SCGC4_VREF_SHIFT 20 +/* SCGC5 Bit Fields */ +#define SIM_SCGC5_LPTIMER_MASK 0x1u +#define SIM_SCGC5_LPTIMER_SHIFT 0 +#define SIM_SCGC5_TSI_MASK 0x20u +#define SIM_SCGC5_TSI_SHIFT 5 +#define SIM_SCGC5_PORTA_MASK 0x200u +#define SIM_SCGC5_PORTA_SHIFT 9 +#define SIM_SCGC5_PORTB_MASK 0x400u +#define SIM_SCGC5_PORTB_SHIFT 10 +#define SIM_SCGC5_PORTC_MASK 0x800u +#define SIM_SCGC5_PORTC_SHIFT 11 +#define SIM_SCGC5_PORTD_MASK 0x1000u +#define SIM_SCGC5_PORTD_SHIFT 12 +#define SIM_SCGC5_PORTE_MASK 0x2000u +#define SIM_SCGC5_PORTE_SHIFT 13 +/* SCGC6 Bit Fields */ +#define SIM_SCGC6_FTFL_MASK 0x1u +#define SIM_SCGC6_FTFL_SHIFT 0 +#define SIM_SCGC6_DMAMUX_MASK 0x2u +#define SIM_SCGC6_DMAMUX_SHIFT 1 +#define SIM_SCGC6_FLEXCAN0_MASK 0x10u +#define SIM_SCGC6_FLEXCAN0_SHIFT 4 +#define SIM_SCGC6_SPI0_MASK 0x1000u +#define SIM_SCGC6_SPI0_SHIFT 12 +#define SIM_SCGC6_SPI1_MASK 0x2000u +#define SIM_SCGC6_SPI1_SHIFT 13 +#define SIM_SCGC6_I2S_MASK 0x8000u +#define SIM_SCGC6_I2S_SHIFT 15 +#define SIM_SCGC6_CRC_MASK 0x40000u +#define SIM_SCGC6_CRC_SHIFT 18 +#define SIM_SCGC6_USBDCD_MASK 0x200000u +#define SIM_SCGC6_USBDCD_SHIFT 21 +#define SIM_SCGC6_PDB_MASK 0x400000u +#define SIM_SCGC6_PDB_SHIFT 22 +#define SIM_SCGC6_PIT_MASK 0x800000u +#define SIM_SCGC6_PIT_SHIFT 23 +#define SIM_SCGC6_FTM0_MASK 0x1000000u +#define SIM_SCGC6_FTM0_SHIFT 24 +#define SIM_SCGC6_FTM1_MASK 0x2000000u +#define SIM_SCGC6_FTM1_SHIFT 25 +#define SIM_SCGC6_ADC0_MASK 0x8000000u +#define SIM_SCGC6_ADC0_SHIFT 27 +#define SIM_SCGC6_RTC_MASK 0x20000000u +#define SIM_SCGC6_RTC_SHIFT 29 +/* SCGC7 Bit Fields */ +#define SIM_SCGC7_DMA_MASK 0x2u +#define SIM_SCGC7_DMA_SHIFT 1 +/* CLKDIV1 Bit Fields */ +#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 +#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK) +#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u +#define SIM_CLKDIV1_OUTDIV2_SHIFT 24 +#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK) +#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 +#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK) +/* CLKDIV2 Bit Fields */ +#define SIM_CLKDIV2_USBFRAC_MASK 0x1u +#define SIM_CLKDIV2_USBFRAC_SHIFT 0 +#define SIM_CLKDIV2_USBDIV_MASK 0xEu +#define SIM_CLKDIV2_USBDIV_SHIFT 1 +#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK) +/* FCFG1 Bit Fields */ +#define SIM_FCFG1_FLASHDIS_MASK 0x1u +#define SIM_FCFG1_FLASHDIS_SHIFT 0 +#define SIM_FCFG1_FLASHDOZE_MASK 0x2u +#define SIM_FCFG1_FLASHDOZE_SHIFT 1 +#define SIM_FCFG1_DEPART_MASK 0xF00u +#define SIM_FCFG1_DEPART_SHIFT 8 +#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK) +#define SIM_FCFG1_EESIZE_MASK 0xF0000u +#define SIM_FCFG1_EESIZE_SHIFT 16 +#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK) +#define SIM_FCFG1_PFSIZE_MASK 0xF000000u +#define SIM_FCFG1_PFSIZE_SHIFT 24 +#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK) +#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u +#define SIM_FCFG1_NVMSIZE_SHIFT 28 +#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK) +/* FCFG2 Bit Fields */ +#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u +#define SIM_FCFG2_MAXADDR1_SHIFT 16 +#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK) +#define SIM_FCFG2_PFLSH_MASK 0x800000u +#define SIM_FCFG2_PFLSH_SHIFT 23 +#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u +#define SIM_FCFG2_MAXADDR0_SHIFT 24 +#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK) +/* UIDH Bit Fields */ +#define SIM_UIDH_UID_MASK 0xFFFFFFFFu +#define SIM_UIDH_UID_SHIFT 0 +#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK) +/* UIDMH Bit Fields */ +#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu +#define SIM_UIDMH_UID_SHIFT 0 +#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK) +/* UIDML Bit Fields */ +#define SIM_UIDML_UID_MASK 0xFFFFFFFFu +#define SIM_UIDML_UID_SHIFT 0 +#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK) +/* UIDL Bit Fields */ +#define SIM_UIDL_UID_MASK 0xFFFFFFFFu +#define SIM_UIDL_UID_SHIFT 0 +#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK) + +/** + * @} + */ /* end of group SIM_Register_Masks */ + + +/* SIM - Peripheral instance base addresses */ +/** Peripheral SIM base address */ +#define SIM_BASE (0x40047000u) +/** Peripheral SIM base pointer */ +#define SIM ((SIM_Type *)SIM_BASE) + +/** + * @} + */ /* end of group SIM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer + * @{ + */ + +/** SMC - Register Layout Typedef */ +typedef struct { + __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */ + __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */ + __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */ + __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */ +} SMC_Type; + +/* ---------------------------------------------------------------------------- + -- SMC Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SMC_Register_Masks SMC Register Masks + * @{ + */ + +/* PMPROT Bit Fields */ +#define SMC_PMPROT_AVLLS_MASK 0x2u +#define SMC_PMPROT_AVLLS_SHIFT 1 +#define SMC_PMPROT_ALLS_MASK 0x8u +#define SMC_PMPROT_ALLS_SHIFT 3 +#define SMC_PMPROT_AVLP_MASK 0x20u +#define SMC_PMPROT_AVLP_SHIFT 5 +/* PMCTRL Bit Fields */ +#define SMC_PMCTRL_STOPM_MASK 0x7u +#define SMC_PMCTRL_STOPM_SHIFT 0 +#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK) +#define SMC_PMCTRL_STOPA_MASK 0x8u +#define SMC_PMCTRL_STOPA_SHIFT 3 +#define SMC_PMCTRL_RUNM_MASK 0x60u +#define SMC_PMCTRL_RUNM_SHIFT 5 +#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK) +#define SMC_PMCTRL_LPWUI_MASK 0x80u +#define SMC_PMCTRL_LPWUI_SHIFT 7 +/* VLLSCTRL Bit Fields */ +#define SMC_VLLSCTRL_VLLSM_MASK 0x7u +#define SMC_VLLSCTRL_VLLSM_SHIFT 0 +#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK) +#define SMC_VLLSCTRL_PORPO_MASK 0x20u +#define SMC_VLLSCTRL_PORPO_SHIFT 5 +/* PMSTAT Bit Fields */ +#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu +#define SMC_PMSTAT_PMSTAT_SHIFT 0 +#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK) + +/** + * @} + */ /* end of group SMC_Register_Masks */ + + +/* SMC - Peripheral instance base addresses */ +/** Peripheral SMC base address */ +#define SMC_BASE (0x4007E000u) +/** Peripheral SMC base pointer */ +#define SMC ((SMC_Type *)SMC_BASE) + +/** + * @} + */ /* end of group SMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */ + union { /* offset: 0xC */ + __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ + __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ + }; + uint8_t RESERVED_1[24]; + __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */ + __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ + union { /* offset: 0x34 */ + __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */ + __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ + }; + __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */ + __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */ + __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */ + __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */ + __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */ + uint8_t RESERVED_2[48]; + __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */ + __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */ + __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */ + __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define SPI_MCR_HALT_MASK 0x1u +#define SPI_MCR_HALT_SHIFT 0 +#define SPI_MCR_SMPL_PT_MASK 0x300u +#define SPI_MCR_SMPL_PT_SHIFT 8 +#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK) +#define SPI_MCR_CLR_RXF_MASK 0x400u +#define SPI_MCR_CLR_RXF_SHIFT 10 +#define SPI_MCR_CLR_TXF_MASK 0x800u +#define SPI_MCR_CLR_TXF_SHIFT 11 +#define SPI_MCR_DIS_RXF_MASK 0x1000u +#define SPI_MCR_DIS_RXF_SHIFT 12 +#define SPI_MCR_DIS_TXF_MASK 0x2000u +#define SPI_MCR_DIS_TXF_SHIFT 13 +#define SPI_MCR_MDIS_MASK 0x4000u +#define SPI_MCR_MDIS_SHIFT 14 +#define SPI_MCR_DOZE_MASK 0x8000u +#define SPI_MCR_DOZE_SHIFT 15 +#define SPI_MCR_PCSIS_MASK 0x3F0000u +#define SPI_MCR_PCSIS_SHIFT 16 +#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK) +#define SPI_MCR_ROOE_MASK 0x1000000u +#define SPI_MCR_ROOE_SHIFT 24 +#define SPI_MCR_PCSSE_MASK 0x2000000u +#define SPI_MCR_PCSSE_SHIFT 25 +#define SPI_MCR_MTFE_MASK 0x4000000u +#define SPI_MCR_MTFE_SHIFT 26 +#define SPI_MCR_FRZ_MASK 0x8000000u +#define SPI_MCR_FRZ_SHIFT 27 +#define SPI_MCR_DCONF_MASK 0x30000000u +#define SPI_MCR_DCONF_SHIFT 28 +#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK) +#define SPI_MCR_CONT_SCKE_MASK 0x40000000u +#define SPI_MCR_CONT_SCKE_SHIFT 30 +#define SPI_MCR_MSTR_MASK 0x80000000u +#define SPI_MCR_MSTR_SHIFT 31 +/* TCR Bit Fields */ +#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u +#define SPI_TCR_SPI_TCNT_SHIFT 16 +#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK) +/* CTAR Bit Fields */ +#define SPI_CTAR_BR_MASK 0xFu +#define SPI_CTAR_BR_SHIFT 0 +#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK) +#define SPI_CTAR_DT_MASK 0xF0u +#define SPI_CTAR_DT_SHIFT 4 +#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK) +#define SPI_CTAR_ASC_MASK 0xF00u +#define SPI_CTAR_ASC_SHIFT 8 +#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK) +#define SPI_CTAR_CSSCK_MASK 0xF000u +#define SPI_CTAR_CSSCK_SHIFT 12 +#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK) +#define SPI_CTAR_PBR_MASK 0x30000u +#define SPI_CTAR_PBR_SHIFT 16 +#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK) +#define SPI_CTAR_PDT_MASK 0xC0000u +#define SPI_CTAR_PDT_SHIFT 18 +#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK) +#define SPI_CTAR_PASC_MASK 0x300000u +#define SPI_CTAR_PASC_SHIFT 20 +#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK) +#define SPI_CTAR_PCSSCK_MASK 0xC00000u +#define SPI_CTAR_PCSSCK_SHIFT 22 +#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK) +#define SPI_CTAR_LSBFE_MASK 0x1000000u +#define SPI_CTAR_LSBFE_SHIFT 24 +#define SPI_CTAR_CPHA_MASK 0x2000000u +#define SPI_CTAR_CPHA_SHIFT 25 +#define SPI_CTAR_CPOL_MASK 0x4000000u +#define SPI_CTAR_CPOL_SHIFT 26 +#define SPI_CTAR_FMSZ_MASK 0x78000000u +#define SPI_CTAR_FMSZ_SHIFT 27 +#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK) +#define SPI_CTAR_DBR_MASK 0x80000000u +#define SPI_CTAR_DBR_SHIFT 31 +/* CTAR_SLAVE Bit Fields */ +#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u +#define SPI_CTAR_SLAVE_CPHA_SHIFT 25 +#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u +#define SPI_CTAR_SLAVE_CPOL_SHIFT 26 +#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u +#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27 +#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK) +/* SR Bit Fields */ +#define SPI_SR_POPNXTPTR_MASK 0xFu +#define SPI_SR_POPNXTPTR_SHIFT 0 +#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK) +#define SPI_SR_RXCTR_MASK 0xF0u +#define SPI_SR_RXCTR_SHIFT 4 +#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK) +#define SPI_SR_TXNXTPTR_MASK 0xF00u +#define SPI_SR_TXNXTPTR_SHIFT 8 +#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK) +#define SPI_SR_TXCTR_MASK 0xF000u +#define SPI_SR_TXCTR_SHIFT 12 +#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK) +#define SPI_SR_RFDF_MASK 0x20000u +#define SPI_SR_RFDF_SHIFT 17 +#define SPI_SR_RFOF_MASK 0x80000u +#define SPI_SR_RFOF_SHIFT 19 +#define SPI_SR_TFFF_MASK 0x2000000u +#define SPI_SR_TFFF_SHIFT 25 +#define SPI_SR_TFUF_MASK 0x8000000u +#define SPI_SR_TFUF_SHIFT 27 +#define SPI_SR_EOQF_MASK 0x10000000u +#define SPI_SR_EOQF_SHIFT 28 +#define SPI_SR_TXRXS_MASK 0x40000000u +#define SPI_SR_TXRXS_SHIFT 30 +#define SPI_SR_TCF_MASK 0x80000000u +#define SPI_SR_TCF_SHIFT 31 +/* RSER Bit Fields */ +#define SPI_RSER_RFDF_DIRS_MASK 0x10000u +#define SPI_RSER_RFDF_DIRS_SHIFT 16 +#define SPI_RSER_RFDF_RE_MASK 0x20000u +#define SPI_RSER_RFDF_RE_SHIFT 17 +#define SPI_RSER_RFOF_RE_MASK 0x80000u +#define SPI_RSER_RFOF_RE_SHIFT 19 +#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u +#define SPI_RSER_TFFF_DIRS_SHIFT 24 +#define SPI_RSER_TFFF_RE_MASK 0x2000000u +#define SPI_RSER_TFFF_RE_SHIFT 25 +#define SPI_RSER_TFUF_RE_MASK 0x8000000u +#define SPI_RSER_TFUF_RE_SHIFT 27 +#define SPI_RSER_EOQF_RE_MASK 0x10000000u +#define SPI_RSER_EOQF_RE_SHIFT 28 +#define SPI_RSER_TCF_RE_MASK 0x80000000u +#define SPI_RSER_TCF_RE_SHIFT 31 +/* PUSHR Bit Fields */ +#define SPI_PUSHR_TXDATA_MASK 0xFFFFu +#define SPI_PUSHR_TXDATA_SHIFT 0 +#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK) +#define SPI_PUSHR_PCS_MASK 0x3F0000u +#define SPI_PUSHR_PCS_SHIFT 16 +#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK) +#define SPI_PUSHR_CTCNT_MASK 0x4000000u +#define SPI_PUSHR_CTCNT_SHIFT 26 +#define SPI_PUSHR_EOQ_MASK 0x8000000u +#define SPI_PUSHR_EOQ_SHIFT 27 +#define SPI_PUSHR_CTAS_MASK 0x70000000u +#define SPI_PUSHR_CTAS_SHIFT 28 +#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK) +#define SPI_PUSHR_CONT_MASK 0x80000000u +#define SPI_PUSHR_CONT_SHIFT 31 +/* PUSHR_SLAVE Bit Fields */ +#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu +#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0 +#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK) +/* POPR Bit Fields */ +#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu +#define SPI_POPR_RXDATA_SHIFT 0 +#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK) +/* TXFR0 Bit Fields */ +#define SPI_TXFR0_TXDATA_MASK 0xFFFFu +#define SPI_TXFR0_TXDATA_SHIFT 0 +#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK) +#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u +#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16 +#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK) +/* TXFR1 Bit Fields */ +#define SPI_TXFR1_TXDATA_MASK 0xFFFFu +#define SPI_TXFR1_TXDATA_SHIFT 0 +#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK) +#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u +#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16 +#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK) +/* TXFR2 Bit Fields */ +#define SPI_TXFR2_TXDATA_MASK 0xFFFFu +#define SPI_TXFR2_TXDATA_SHIFT 0 +#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK) +#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u +#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16 +#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK) +/* TXFR3 Bit Fields */ +#define SPI_TXFR3_TXDATA_MASK 0xFFFFu +#define SPI_TXFR3_TXDATA_SHIFT 0 +#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK) +#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u +#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16 +#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK) +/* RXFR0 Bit Fields */ +#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu +#define SPI_RXFR0_RXDATA_SHIFT 0 +#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK) +/* RXFR1 Bit Fields */ +#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu +#define SPI_RXFR1_RXDATA_SHIFT 0 +#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK) +/* RXFR2 Bit Fields */ +#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu +#define SPI_RXFR2_RXDATA_SHIFT 0 +#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK) +/* RXFR3 Bit Fields */ +#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu +#define SPI_RXFR3_RXDATA_SHIFT 0 +#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK) + +/** + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +/** Peripheral SPI0 base address */ +#define SPI0_BASE (0x4002C000u) +/** Peripheral SPI0 base pointer */ +#define SPI0 ((SPI_Type *)SPI0_BASE) + +/** + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TSI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer + * @{ + */ + +/** TSI - Register Layout Typedef */ +typedef struct { + __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */ + __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */ + __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */ + __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */ + uint8_t RESERVED_0[240]; + __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */ + __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */ + __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */ + __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */ + __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */ + __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */ + __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */ + __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */ + __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */ +} TSI_Type; + +/* ---------------------------------------------------------------------------- + -- TSI Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup TSI_Register_Masks TSI Register Masks + * @{ + */ + +/* GENCS Bit Fields */ +#define TSI_GENCS_STPE_MASK 0x1u +#define TSI_GENCS_STPE_SHIFT 0 +#define TSI_GENCS_STM_MASK 0x2u +#define TSI_GENCS_STM_SHIFT 1 +#define TSI_GENCS_ESOR_MASK 0x10u +#define TSI_GENCS_ESOR_SHIFT 4 +#define TSI_GENCS_ERIE_MASK 0x20u +#define TSI_GENCS_ERIE_SHIFT 5 +#define TSI_GENCS_TSIIE_MASK 0x40u +#define TSI_GENCS_TSIIE_SHIFT 6 +#define TSI_GENCS_TSIEN_MASK 0x80u +#define TSI_GENCS_TSIEN_SHIFT 7 +#define TSI_GENCS_SWTS_MASK 0x100u +#define TSI_GENCS_SWTS_SHIFT 8 +#define TSI_GENCS_SCNIP_MASK 0x200u +#define TSI_GENCS_SCNIP_SHIFT 9 +#define TSI_GENCS_OVRF_MASK 0x1000u +#define TSI_GENCS_OVRF_SHIFT 12 +#define TSI_GENCS_EXTERF_MASK 0x2000u +#define TSI_GENCS_EXTERF_SHIFT 13 +#define TSI_GENCS_OUTRGF_MASK 0x4000u +#define TSI_GENCS_OUTRGF_SHIFT 14 +#define TSI_GENCS_EOSF_MASK 0x8000u +#define TSI_GENCS_EOSF_SHIFT 15 +#define TSI_GENCS_PS_MASK 0x70000u +#define TSI_GENCS_PS_SHIFT 16 +#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK) +#define TSI_GENCS_NSCN_MASK 0xF80000u +#define TSI_GENCS_NSCN_SHIFT 19 +#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK) +#define TSI_GENCS_LPSCNITV_MASK 0xF000000u +#define TSI_GENCS_LPSCNITV_SHIFT 24 +#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK) +#define TSI_GENCS_LPCLKS_MASK 0x10000000u +#define TSI_GENCS_LPCLKS_SHIFT 28 +/* SCANC Bit Fields */ +#define TSI_SCANC_AMPSC_MASK 0x7u +#define TSI_SCANC_AMPSC_SHIFT 0 +#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK) +#define TSI_SCANC_AMCLKS_MASK 0x18u +#define TSI_SCANC_AMCLKS_SHIFT 3 +#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK) +#define TSI_SCANC_SMOD_MASK 0xFF00u +#define TSI_SCANC_SMOD_SHIFT 8 +#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK) +#define TSI_SCANC_EXTCHRG_MASK 0xF0000u +#define TSI_SCANC_EXTCHRG_SHIFT 16 +#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK) +#define TSI_SCANC_REFCHRG_MASK 0xF000000u +#define TSI_SCANC_REFCHRG_SHIFT 24 +#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK) +/* PEN Bit Fields */ +#define TSI_PEN_PEN0_MASK 0x1u +#define TSI_PEN_PEN0_SHIFT 0 +#define TSI_PEN_PEN1_MASK 0x2u +#define TSI_PEN_PEN1_SHIFT 1 +#define TSI_PEN_PEN2_MASK 0x4u +#define TSI_PEN_PEN2_SHIFT 2 +#define TSI_PEN_PEN3_MASK 0x8u +#define TSI_PEN_PEN3_SHIFT 3 +#define TSI_PEN_PEN4_MASK 0x10u +#define TSI_PEN_PEN4_SHIFT 4 +#define TSI_PEN_PEN5_MASK 0x20u +#define TSI_PEN_PEN5_SHIFT 5 +#define TSI_PEN_PEN6_MASK 0x40u +#define TSI_PEN_PEN6_SHIFT 6 +#define TSI_PEN_PEN7_MASK 0x80u +#define TSI_PEN_PEN7_SHIFT 7 +#define TSI_PEN_PEN8_MASK 0x100u +#define TSI_PEN_PEN8_SHIFT 8 +#define TSI_PEN_PEN9_MASK 0x200u +#define TSI_PEN_PEN9_SHIFT 9 +#define TSI_PEN_PEN10_MASK 0x400u +#define TSI_PEN_PEN10_SHIFT 10 +#define TSI_PEN_PEN11_MASK 0x800u +#define TSI_PEN_PEN11_SHIFT 11 +#define TSI_PEN_PEN12_MASK 0x1000u +#define TSI_PEN_PEN12_SHIFT 12 +#define TSI_PEN_PEN13_MASK 0x2000u +#define TSI_PEN_PEN13_SHIFT 13 +#define TSI_PEN_PEN14_MASK 0x4000u +#define TSI_PEN_PEN14_SHIFT 14 +#define TSI_PEN_PEN15_MASK 0x8000u +#define TSI_PEN_PEN15_SHIFT 15 +#define TSI_PEN_LPSP_MASK 0xF0000u +#define TSI_PEN_LPSP_SHIFT 16 +#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK) +/* WUCNTR Bit Fields */ +#define TSI_WUCNTR_WUCNT_MASK 0xFFFFu +#define TSI_WUCNTR_WUCNT_SHIFT 0 +#define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK) +/* CNTR1 Bit Fields */ +#define TSI_CNTR1_CTN1_MASK 0xFFFFu +#define TSI_CNTR1_CTN1_SHIFT 0 +#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK) +#define TSI_CNTR1_CTN_MASK 0xFFFF0000u +#define TSI_CNTR1_CTN_SHIFT 16 +#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK) +/* CNTR3 Bit Fields */ +#define TSI_CNTR3_CTN1_MASK 0xFFFFu +#define TSI_CNTR3_CTN1_SHIFT 0 +#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK) +#define TSI_CNTR3_CTN_MASK 0xFFFF0000u +#define TSI_CNTR3_CTN_SHIFT 16 +#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK) +/* CNTR5 Bit Fields */ +#define TSI_CNTR5_CTN1_MASK 0xFFFFu +#define TSI_CNTR5_CTN1_SHIFT 0 +#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK) +#define TSI_CNTR5_CTN_MASK 0xFFFF0000u +#define TSI_CNTR5_CTN_SHIFT 16 +#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK) +/* CNTR7 Bit Fields */ +#define TSI_CNTR7_CTN1_MASK 0xFFFFu +#define TSI_CNTR7_CTN1_SHIFT 0 +#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK) +#define TSI_CNTR7_CTN_MASK 0xFFFF0000u +#define TSI_CNTR7_CTN_SHIFT 16 +#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK) +/* CNTR9 Bit Fields */ +#define TSI_CNTR9_CTN1_MASK 0xFFFFu +#define TSI_CNTR9_CTN1_SHIFT 0 +#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK) +#define TSI_CNTR9_CTN_MASK 0xFFFF0000u +#define TSI_CNTR9_CTN_SHIFT 16 +#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK) +/* CNTR11 Bit Fields */ +#define TSI_CNTR11_CTN1_MASK 0xFFFFu +#define TSI_CNTR11_CTN1_SHIFT 0 +#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK) +#define TSI_CNTR11_CTN_MASK 0xFFFF0000u +#define TSI_CNTR11_CTN_SHIFT 16 +#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK) +/* CNTR13 Bit Fields */ +#define TSI_CNTR13_CTN1_MASK 0xFFFFu +#define TSI_CNTR13_CTN1_SHIFT 0 +#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK) +#define TSI_CNTR13_CTN_MASK 0xFFFF0000u +#define TSI_CNTR13_CTN_SHIFT 16 +#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK) +/* CNTR15 Bit Fields */ +#define TSI_CNTR15_CTN1_MASK 0xFFFFu +#define TSI_CNTR15_CTN1_SHIFT 0 +#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK) +#define TSI_CNTR15_CTN_MASK 0xFFFF0000u +#define TSI_CNTR15_CTN_SHIFT 16 +#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK) +/* THRESHOLD Bit Fields */ +#define TSI_THRESHOLD_HTHH_MASK 0xFFFFu +#define TSI_THRESHOLD_HTHH_SHIFT 0 +#define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK) +#define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u +#define TSI_THRESHOLD_LTHH_SHIFT 16 +#define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK) + +/** + * @} + */ /* end of group TSI_Register_Masks */ + + +/* TSI - Peripheral instance base addresses */ +/** Peripheral TSI0 base address */ +#define TSI0_BASE (0x40045000u) +/** Peripheral TSI0 base pointer */ +#define TSI0 ((TSI_Type *)TSI0_BASE) + +/** + * @} + */ /* end of group TSI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer + * @{ + */ + +/** UART - Register Layout Typedef */ +typedef struct { + __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */ + __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ + __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ + __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ + __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ + __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ + __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ + __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ + __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ + __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ + __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ + __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ + __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */ + __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */ + __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */ + uint8_t RESERVED_0[1]; + __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */ + __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */ + __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */ + __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */ + __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */ + __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */ + __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */ + uint8_t RESERVED_1[1]; + __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ + __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ + __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ + union { /* offset: 0x1B */ + __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ + __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ + }; + __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ + __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ + __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ + __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ + uint8_t RESERVED_2[1]; + __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */ + __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */ + __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */ + __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */ + __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */ + __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */ + __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */ + __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */ + __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */ + __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */ + __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */ + __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */ + __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */ + __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */ + __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */ + __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */ + __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */ +} UART_Type; + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/* BDH Bit Fields */ +#define UART_BDH_SBR_MASK 0x1Fu +#define UART_BDH_SBR_SHIFT 0 +#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK) +#define UART_BDH_RXEDGIE_MASK 0x40u +#define UART_BDH_RXEDGIE_SHIFT 6 +#define UART_BDH_LBKDIE_MASK 0x80u +#define UART_BDH_LBKDIE_SHIFT 7 +/* BDL Bit Fields */ +#define UART_BDL_SBR_MASK 0xFFu +#define UART_BDL_SBR_SHIFT 0 +#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK) +/* C1 Bit Fields */ +#define UART_C1_PT_MASK 0x1u +#define UART_C1_PT_SHIFT 0 +#define UART_C1_PE_MASK 0x2u +#define UART_C1_PE_SHIFT 1 +#define UART_C1_ILT_MASK 0x4u +#define UART_C1_ILT_SHIFT 2 +#define UART_C1_WAKE_MASK 0x8u +#define UART_C1_WAKE_SHIFT 3 +#define UART_C1_M_MASK 0x10u +#define UART_C1_M_SHIFT 4 +#define UART_C1_RSRC_MASK 0x20u +#define UART_C1_RSRC_SHIFT 5 +#define UART_C1_UARTSWAI_MASK 0x40u +#define UART_C1_UARTSWAI_SHIFT 6 +#define UART_C1_LOOPS_MASK 0x80u +#define UART_C1_LOOPS_SHIFT 7 +/* C2 Bit Fields */ +#define UART_C2_SBK_MASK 0x1u +#define UART_C2_SBK_SHIFT 0 +#define UART_C2_RWU_MASK 0x2u +#define UART_C2_RWU_SHIFT 1 +#define UART_C2_RE_MASK 0x4u +#define UART_C2_RE_SHIFT 2 +#define UART_C2_TE_MASK 0x8u +#define UART_C2_TE_SHIFT 3 +#define UART_C2_ILIE_MASK 0x10u +#define UART_C2_ILIE_SHIFT 4 +#define UART_C2_RIE_MASK 0x20u +#define UART_C2_RIE_SHIFT 5 +#define UART_C2_TCIE_MASK 0x40u +#define UART_C2_TCIE_SHIFT 6 +#define UART_C2_TIE_MASK 0x80u +#define UART_C2_TIE_SHIFT 7 +/* S1 Bit Fields */ +#define UART_S1_PF_MASK 0x1u +#define UART_S1_PF_SHIFT 0 +#define UART_S1_FE_MASK 0x2u +#define UART_S1_FE_SHIFT 1 +#define UART_S1_NF_MASK 0x4u +#define UART_S1_NF_SHIFT 2 +#define UART_S1_OR_MASK 0x8u +#define UART_S1_OR_SHIFT 3 +#define UART_S1_IDLE_MASK 0x10u +#define UART_S1_IDLE_SHIFT 4 +#define UART_S1_RDRF_MASK 0x20u +#define UART_S1_RDRF_SHIFT 5 +#define UART_S1_TC_MASK 0x40u +#define UART_S1_TC_SHIFT 6 +#define UART_S1_TDRE_MASK 0x80u +#define UART_S1_TDRE_SHIFT 7 +/* S2 Bit Fields */ +#define UART_S2_RAF_MASK 0x1u +#define UART_S2_RAF_SHIFT 0 +#define UART_S2_LBKDE_MASK 0x2u +#define UART_S2_LBKDE_SHIFT 1 +#define UART_S2_BRK13_MASK 0x4u +#define UART_S2_BRK13_SHIFT 2 +#define UART_S2_RWUID_MASK 0x8u +#define UART_S2_RWUID_SHIFT 3 +#define UART_S2_RXINV_MASK 0x10u +#define UART_S2_RXINV_SHIFT 4 +#define UART_S2_MSBF_MASK 0x20u +#define UART_S2_MSBF_SHIFT 5 +#define UART_S2_RXEDGIF_MASK 0x40u +#define UART_S2_RXEDGIF_SHIFT 6 +#define UART_S2_LBKDIF_MASK 0x80u +#define UART_S2_LBKDIF_SHIFT 7 +/* C3 Bit Fields */ +#define UART_C3_PEIE_MASK 0x1u +#define UART_C3_PEIE_SHIFT 0 +#define UART_C3_FEIE_MASK 0x2u +#define UART_C3_FEIE_SHIFT 1 +#define UART_C3_NEIE_MASK 0x4u +#define UART_C3_NEIE_SHIFT 2 +#define UART_C3_ORIE_MASK 0x8u +#define UART_C3_ORIE_SHIFT 3 +#define UART_C3_TXINV_MASK 0x10u +#define UART_C3_TXINV_SHIFT 4 +#define UART_C3_TXDIR_MASK 0x20u +#define UART_C3_TXDIR_SHIFT 5 +#define UART_C3_T8_MASK 0x40u +#define UART_C3_T8_SHIFT 6 +#define UART_C3_R8_MASK 0x80u +#define UART_C3_R8_SHIFT 7 +/* D Bit Fields */ +#define UART_D_RT_MASK 0xFFu +#define UART_D_RT_SHIFT 0 +#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK) +/* MA1 Bit Fields */ +#define UART_MA1_MA_MASK 0xFFu +#define UART_MA1_MA_SHIFT 0 +#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK) +/* MA2 Bit Fields */ +#define UART_MA2_MA_MASK 0xFFu +#define UART_MA2_MA_SHIFT 0 +#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK) +/* C4 Bit Fields */ +#define UART_C4_BRFA_MASK 0x1Fu +#define UART_C4_BRFA_SHIFT 0 +#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK) +#define UART_C4_M10_MASK 0x20u +#define UART_C4_M10_SHIFT 5 +#define UART_C4_MAEN2_MASK 0x40u +#define UART_C4_MAEN2_SHIFT 6 +#define UART_C4_MAEN1_MASK 0x80u +#define UART_C4_MAEN1_SHIFT 7 +/* C5 Bit Fields */ +#define UART_C5_RDMAS_MASK 0x20u +#define UART_C5_RDMAS_SHIFT 5 +#define UART_C5_TDMAS_MASK 0x80u +#define UART_C5_TDMAS_SHIFT 7 +/* ED Bit Fields */ +#define UART_ED_PARITYE_MASK 0x40u +#define UART_ED_PARITYE_SHIFT 6 +#define UART_ED_NOISY_MASK 0x80u +#define UART_ED_NOISY_SHIFT 7 +/* MODEM Bit Fields */ +#define UART_MODEM_TXCTSE_MASK 0x1u +#define UART_MODEM_TXCTSE_SHIFT 0 +#define UART_MODEM_TXRTSE_MASK 0x2u +#define UART_MODEM_TXRTSE_SHIFT 1 +#define UART_MODEM_TXRTSPOL_MASK 0x4u +#define UART_MODEM_TXRTSPOL_SHIFT 2 +#define UART_MODEM_RXRTSE_MASK 0x8u +#define UART_MODEM_RXRTSE_SHIFT 3 +/* IR Bit Fields */ +#define UART_IR_TNP_MASK 0x3u +#define UART_IR_TNP_SHIFT 0 +#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK) +#define UART_IR_IREN_MASK 0x4u +#define UART_IR_IREN_SHIFT 2 +/* PFIFO Bit Fields */ +#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u +#define UART_PFIFO_RXFIFOSIZE_SHIFT 0 +#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK) +#define UART_PFIFO_RXFE_MASK 0x8u +#define UART_PFIFO_RXFE_SHIFT 3 +#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u +#define UART_PFIFO_TXFIFOSIZE_SHIFT 4 +#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK) +#define UART_PFIFO_TXFE_MASK 0x80u +#define UART_PFIFO_TXFE_SHIFT 7 +/* CFIFO Bit Fields */ +#define UART_CFIFO_RXUFE_MASK 0x1u +#define UART_CFIFO_RXUFE_SHIFT 0 +#define UART_CFIFO_TXOFE_MASK 0x2u +#define UART_CFIFO_TXOFE_SHIFT 1 +#define UART_CFIFO_RXFLUSH_MASK 0x40u +#define UART_CFIFO_RXFLUSH_SHIFT 6 +#define UART_CFIFO_TXFLUSH_MASK 0x80u +#define UART_CFIFO_TXFLUSH_SHIFT 7 +/* SFIFO Bit Fields */ +#define UART_SFIFO_RXUF_MASK 0x1u +#define UART_SFIFO_RXUF_SHIFT 0 +#define UART_SFIFO_TXOF_MASK 0x2u +#define UART_SFIFO_TXOF_SHIFT 1 +#define UART_SFIFO_RXEMPT_MASK 0x40u +#define UART_SFIFO_RXEMPT_SHIFT 6 +#define UART_SFIFO_TXEMPT_MASK 0x80u +#define UART_SFIFO_TXEMPT_SHIFT 7 +/* TWFIFO Bit Fields */ +#define UART_TWFIFO_TXWATER_MASK 0xFFu +#define UART_TWFIFO_TXWATER_SHIFT 0 +#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK) +/* TCFIFO Bit Fields */ +#define UART_TCFIFO_TXCOUNT_MASK 0xFFu +#define UART_TCFIFO_TXCOUNT_SHIFT 0 +#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK) +/* RWFIFO Bit Fields */ +#define UART_RWFIFO_RXWATER_MASK 0xFFu +#define UART_RWFIFO_RXWATER_SHIFT 0 +#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK) +/* RCFIFO Bit Fields */ +#define UART_RCFIFO_RXCOUNT_MASK 0xFFu +#define UART_RCFIFO_RXCOUNT_SHIFT 0 +#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK) +/* C7816 Bit Fields */ +#define UART_C7816_ISO_7816E_MASK 0x1u +#define UART_C7816_ISO_7816E_SHIFT 0 +#define UART_C7816_TTYPE_MASK 0x2u +#define UART_C7816_TTYPE_SHIFT 1 +#define UART_C7816_INIT_MASK 0x4u +#define UART_C7816_INIT_SHIFT 2 +#define UART_C7816_ANACK_MASK 0x8u +#define UART_C7816_ANACK_SHIFT 3 +#define UART_C7816_ONACK_MASK 0x10u +#define UART_C7816_ONACK_SHIFT 4 +/* IE7816 Bit Fields */ +#define UART_IE7816_RXTE_MASK 0x1u +#define UART_IE7816_RXTE_SHIFT 0 +#define UART_IE7816_TXTE_MASK 0x2u +#define UART_IE7816_TXTE_SHIFT 1 +#define UART_IE7816_GTVE_MASK 0x4u +#define UART_IE7816_GTVE_SHIFT 2 +#define UART_IE7816_INITDE_MASK 0x10u +#define UART_IE7816_INITDE_SHIFT 4 +#define UART_IE7816_BWTE_MASK 0x20u +#define UART_IE7816_BWTE_SHIFT 5 +#define UART_IE7816_CWTE_MASK 0x40u +#define UART_IE7816_CWTE_SHIFT 6 +#define UART_IE7816_WTE_MASK 0x80u +#define UART_IE7816_WTE_SHIFT 7 +/* IS7816 Bit Fields */ +#define UART_IS7816_RXT_MASK 0x1u +#define UART_IS7816_RXT_SHIFT 0 +#define UART_IS7816_TXT_MASK 0x2u +#define UART_IS7816_TXT_SHIFT 1 +#define UART_IS7816_GTV_MASK 0x4u +#define UART_IS7816_GTV_SHIFT 2 +#define UART_IS7816_INITD_MASK 0x10u +#define UART_IS7816_INITD_SHIFT 4 +#define UART_IS7816_BWT_MASK 0x20u +#define UART_IS7816_BWT_SHIFT 5 +#define UART_IS7816_CWT_MASK 0x40u +#define UART_IS7816_CWT_SHIFT 6 +#define UART_IS7816_WT_MASK 0x80u +#define UART_IS7816_WT_SHIFT 7 +/* WP7816_T_TYPE0 Bit Fields */ +#define UART_WP7816_T_TYPE0_WI_MASK 0xFFu +#define UART_WP7816_T_TYPE0_WI_SHIFT 0 +#define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK) +/* WP7816_T_TYPE1 Bit Fields */ +#define UART_WP7816_T_TYPE1_BWI_MASK 0xFu +#define UART_WP7816_T_TYPE1_BWI_SHIFT 0 +#define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK) +#define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u +#define UART_WP7816_T_TYPE1_CWI_SHIFT 4 +#define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK) +/* WN7816 Bit Fields */ +#define UART_WN7816_GTN_MASK 0xFFu +#define UART_WN7816_GTN_SHIFT 0 +#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK) +/* WF7816 Bit Fields */ +#define UART_WF7816_GTFD_MASK 0xFFu +#define UART_WF7816_GTFD_SHIFT 0 +#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK) +/* ET7816 Bit Fields */ +#define UART_ET7816_RXTHRESHOLD_MASK 0xFu +#define UART_ET7816_RXTHRESHOLD_SHIFT 0 +#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK) +#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u +#define UART_ET7816_TXTHRESHOLD_SHIFT 4 +#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK) +/* TL7816 Bit Fields */ +#define UART_TL7816_TLEN_MASK 0xFFu +#define UART_TL7816_TLEN_SHIFT 0 +#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK) +/* C6 Bit Fields */ +#define UART_C6_CP_MASK 0x10u +#define UART_C6_CP_SHIFT 4 +#define UART_C6_CE_MASK 0x20u +#define UART_C6_CE_SHIFT 5 +#define UART_C6_TX709_MASK 0x40u +#define UART_C6_TX709_SHIFT 6 +#define UART_C6_EN709_MASK 0x80u +#define UART_C6_EN709_SHIFT 7 +/* PCTH Bit Fields */ +#define UART_PCTH_PCTH_MASK 0xFFu +#define UART_PCTH_PCTH_SHIFT 0 +#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK) +/* PCTL Bit Fields */ +#define UART_PCTL_PCTL_MASK 0xFFu +#define UART_PCTL_PCTL_SHIFT 0 +#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK) +/* B1T Bit Fields */ +#define UART_B1T_B1T_MASK 0xFFu +#define UART_B1T_B1T_SHIFT 0 +#define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK) +/* SDTH Bit Fields */ +#define UART_SDTH_SDTH_MASK 0xFFu +#define UART_SDTH_SDTH_SHIFT 0 +#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK) +/* SDTL Bit Fields */ +#define UART_SDTL_SDTL_MASK 0xFFu +#define UART_SDTL_SDTL_SHIFT 0 +#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK) +/* PRE Bit Fields */ +#define UART_PRE_PREAMBLE_MASK 0xFFu +#define UART_PRE_PREAMBLE_SHIFT 0 +#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK) +/* TPL Bit Fields */ +#define UART_TPL_TPL_MASK 0xFFu +#define UART_TPL_TPL_SHIFT 0 +#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK) +/* IE Bit Fields */ +#define UART_IE_TXFIE_MASK 0x1u +#define UART_IE_TXFIE_SHIFT 0 +#define UART_IE_PSIE_MASK 0x2u +#define UART_IE_PSIE_SHIFT 1 +#define UART_IE_PCTEIE_MASK 0x4u +#define UART_IE_PCTEIE_SHIFT 2 +#define UART_IE_PTXIE_MASK 0x8u +#define UART_IE_PTXIE_SHIFT 3 +#define UART_IE_PRXIE_MASK 0x10u +#define UART_IE_PRXIE_SHIFT 4 +#define UART_IE_ISDIE_MASK 0x20u +#define UART_IE_ISDIE_SHIFT 5 +#define UART_IE_WBEIE_MASK 0x40u +#define UART_IE_WBEIE_SHIFT 6 +/* WB Bit Fields */ +#define UART_WB_WBASE_MASK 0xFFu +#define UART_WB_WBASE_SHIFT 0 +#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK) +/* S3 Bit Fields */ +#define UART_S3_TXFF_MASK 0x1u +#define UART_S3_TXFF_SHIFT 0 +#define UART_S3_PSF_MASK 0x2u +#define UART_S3_PSF_SHIFT 1 +#define UART_S3_PCTEF_MASK 0x4u +#define UART_S3_PCTEF_SHIFT 2 +#define UART_S3_PTXF_MASK 0x8u +#define UART_S3_PTXF_SHIFT 3 +#define UART_S3_PRXF_MASK 0x10u +#define UART_S3_PRXF_SHIFT 4 +#define UART_S3_ISD_MASK 0x20u +#define UART_S3_ISD_SHIFT 5 +#define UART_S3_WBEF_MASK 0x40u +#define UART_S3_WBEF_SHIFT 6 +#define UART_S3_PEF_MASK 0x80u +#define UART_S3_PEF_SHIFT 7 +/* S4 Bit Fields */ +#define UART_S4_FE_MASK 0x1u +#define UART_S4_FE_SHIFT 0 +#define UART_S4_ILCV_MASK 0x2u +#define UART_S4_ILCV_SHIFT 1 +#define UART_S4_CDET_MASK 0xCu +#define UART_S4_CDET_SHIFT 2 +#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK) +#define UART_S4_INITF_MASK 0x10u +#define UART_S4_INITF_SHIFT 4 +/* RPL Bit Fields */ +#define UART_RPL_RPL_MASK 0xFFu +#define UART_RPL_RPL_SHIFT 0 +#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK) +/* RPREL Bit Fields */ +#define UART_RPREL_RPREL_MASK 0xFFu +#define UART_RPREL_RPREL_SHIFT 0 +#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK) +/* CPW Bit Fields */ +#define UART_CPW_CPW_MASK 0xFFu +#define UART_CPW_CPW_SHIFT 0 +#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK) +/* RIDT Bit Fields */ +#define UART_RIDT_RIDT_MASK 0xFFu +#define UART_RIDT_RIDT_SHIFT 0 +#define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK) +/* TIDT Bit Fields */ +#define UART_TIDT_TIDT_MASK 0xFFu +#define UART_TIDT_TIDT_SHIFT 0 +#define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK) + +/** + * @} + */ /* end of group UART_Register_Masks */ + + +/* UART - Peripheral instance base addresses */ +/** Peripheral UART0 base address */ +#define UART0_BASE (0x4006A000u) +/** Peripheral UART0 base pointer */ +#define UART0 ((UART_Type *)UART0_BASE) +/** Peripheral UART1 base address */ +#define UART1_BASE (0x4006B000u) +/** Peripheral UART1 base pointer */ +#define UART1 ((UART_Type *)UART1_BASE) +/** Peripheral UART2 base address */ +#define UART2_BASE (0x4006C000u) +/** Peripheral UART2 base pointer */ +#define UART2 ((UART_Type *)UART2_BASE) + +/** + * @} + */ /* end of group UART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */ + uint8_t RESERVED_0[3]; + __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */ + uint8_t RESERVED_1[3]; + __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */ + uint8_t RESERVED_2[3]; + __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */ + uint8_t RESERVED_3[3]; + __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */ + uint8_t RESERVED_4[3]; + __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */ + uint8_t RESERVED_5[3]; + __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */ + uint8_t RESERVED_6[3]; + __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */ + uint8_t RESERVED_7[99]; + __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */ + uint8_t RESERVED_8[3]; + __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */ + uint8_t RESERVED_9[3]; + __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */ + uint8_t RESERVED_10[3]; + __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */ + uint8_t RESERVED_11[3]; + __I uint8_t STAT; /**< Status Register, offset: 0x90 */ + uint8_t RESERVED_12[3]; + __IO uint8_t CTL; /**< Control Register, offset: 0x94 */ + uint8_t RESERVED_13[3]; + __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */ + uint8_t RESERVED_14[3]; + __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */ + uint8_t RESERVED_15[3]; + __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ + uint8_t RESERVED_16[3]; + __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ + uint8_t RESERVED_17[3]; + __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */ + uint8_t RESERVED_18[3]; + __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */ + uint8_t RESERVED_19[3]; + __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ + uint8_t RESERVED_20[3]; + __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ + uint8_t RESERVED_21[11]; + struct { /* offset: 0xC0, array step: 0x4 */ + __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_0[3]; + } ENDPOINT[16]; + __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */ + uint8_t RESERVED_22[3]; + __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */ + uint8_t RESERVED_23[3]; + __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */ + uint8_t RESERVED_24[3]; + __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */ + uint8_t RESERVED_25[7]; + __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/* PERID Bit Fields */ +#define USB_PERID_ID_MASK 0x3Fu +#define USB_PERID_ID_SHIFT 0 +#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK) +/* IDCOMP Bit Fields */ +#define USB_IDCOMP_NID_MASK 0x3Fu +#define USB_IDCOMP_NID_SHIFT 0 +#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK) +/* REV Bit Fields */ +#define USB_REV_REV_MASK 0xFFu +#define USB_REV_REV_SHIFT 0 +#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK) +/* ADDINFO Bit Fields */ +#define USB_ADDINFO_IEHOST_MASK 0x1u +#define USB_ADDINFO_IEHOST_SHIFT 0 +#define USB_ADDINFO_IRQNUM_MASK 0xF8u +#define USB_ADDINFO_IRQNUM_SHIFT 3 +#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK) +/* OTGISTAT Bit Fields */ +#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u +#define USB_OTGISTAT_AVBUSCHG_SHIFT 0 +#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u +#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2 +#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u +#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3 +#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u +#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5 +#define USB_OTGISTAT_ONEMSEC_MASK 0x40u +#define USB_OTGISTAT_ONEMSEC_SHIFT 6 +#define USB_OTGISTAT_IDCHG_MASK 0x80u +#define USB_OTGISTAT_IDCHG_SHIFT 7 +/* OTGICR Bit Fields */ +#define USB_OTGICR_AVBUSEN_MASK 0x1u +#define USB_OTGICR_AVBUSEN_SHIFT 0 +#define USB_OTGICR_BSESSEN_MASK 0x4u +#define USB_OTGICR_BSESSEN_SHIFT 2 +#define USB_OTGICR_SESSVLDEN_MASK 0x8u +#define USB_OTGICR_SESSVLDEN_SHIFT 3 +#define USB_OTGICR_LINESTATEEN_MASK 0x20u +#define USB_OTGICR_LINESTATEEN_SHIFT 5 +#define USB_OTGICR_ONEMSECEN_MASK 0x40u +#define USB_OTGICR_ONEMSECEN_SHIFT 6 +#define USB_OTGICR_IDEN_MASK 0x80u +#define USB_OTGICR_IDEN_SHIFT 7 +/* OTGSTAT Bit Fields */ +#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u +#define USB_OTGSTAT_AVBUSVLD_SHIFT 0 +#define USB_OTGSTAT_BSESSEND_MASK 0x4u +#define USB_OTGSTAT_BSESSEND_SHIFT 2 +#define USB_OTGSTAT_SESS_VLD_MASK 0x8u +#define USB_OTGSTAT_SESS_VLD_SHIFT 3 +#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u +#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5 +#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u +#define USB_OTGSTAT_ONEMSECEN_SHIFT 6 +#define USB_OTGSTAT_ID_MASK 0x80u +#define USB_OTGSTAT_ID_SHIFT 7 +/* OTGCTL Bit Fields */ +#define USB_OTGCTL_OTGEN_MASK 0x4u +#define USB_OTGCTL_OTGEN_SHIFT 2 +#define USB_OTGCTL_DMLOW_MASK 0x10u +#define USB_OTGCTL_DMLOW_SHIFT 4 +#define USB_OTGCTL_DPLOW_MASK 0x20u +#define USB_OTGCTL_DPLOW_SHIFT 5 +#define USB_OTGCTL_DPHIGH_MASK 0x80u +#define USB_OTGCTL_DPHIGH_SHIFT 7 +/* ISTAT Bit Fields */ +#define USB_ISTAT_USBRST_MASK 0x1u +#define USB_ISTAT_USBRST_SHIFT 0 +#define USB_ISTAT_ERROR_MASK 0x2u +#define USB_ISTAT_ERROR_SHIFT 1 +#define USB_ISTAT_SOFTOK_MASK 0x4u +#define USB_ISTAT_SOFTOK_SHIFT 2 +#define USB_ISTAT_TOKDNE_MASK 0x8u +#define USB_ISTAT_TOKDNE_SHIFT 3 +#define USB_ISTAT_SLEEP_MASK 0x10u +#define USB_ISTAT_SLEEP_SHIFT 4 +#define USB_ISTAT_RESUME_MASK 0x20u +#define USB_ISTAT_RESUME_SHIFT 5 +#define USB_ISTAT_ATTACH_MASK 0x40u +#define USB_ISTAT_ATTACH_SHIFT 6 +#define USB_ISTAT_STALL_MASK 0x80u +#define USB_ISTAT_STALL_SHIFT 7 +/* INTEN Bit Fields */ +#define USB_INTEN_USBRSTEN_MASK 0x1u +#define USB_INTEN_USBRSTEN_SHIFT 0 +#define USB_INTEN_ERROREN_MASK 0x2u +#define USB_INTEN_ERROREN_SHIFT 1 +#define USB_INTEN_SOFTOKEN_MASK 0x4u +#define USB_INTEN_SOFTOKEN_SHIFT 2 +#define USB_INTEN_TOKDNEEN_MASK 0x8u +#define USB_INTEN_TOKDNEEN_SHIFT 3 +#define USB_INTEN_SLEEPEN_MASK 0x10u +#define USB_INTEN_SLEEPEN_SHIFT 4 +#define USB_INTEN_RESUMEEN_MASK 0x20u +#define USB_INTEN_RESUMEEN_SHIFT 5 +#define USB_INTEN_ATTACHEN_MASK 0x40u +#define USB_INTEN_ATTACHEN_SHIFT 6 +#define USB_INTEN_STALLEN_MASK 0x80u +#define USB_INTEN_STALLEN_SHIFT 7 +/* ERRSTAT Bit Fields */ +#define USB_ERRSTAT_PIDERR_MASK 0x1u +#define USB_ERRSTAT_PIDERR_SHIFT 0 +#define USB_ERRSTAT_CRC5EOF_MASK 0x2u +#define USB_ERRSTAT_CRC5EOF_SHIFT 1 +#define USB_ERRSTAT_CRC16_MASK 0x4u +#define USB_ERRSTAT_CRC16_SHIFT 2 +#define USB_ERRSTAT_DFN8_MASK 0x8u +#define USB_ERRSTAT_DFN8_SHIFT 3 +#define USB_ERRSTAT_BTOERR_MASK 0x10u +#define USB_ERRSTAT_BTOERR_SHIFT 4 +#define USB_ERRSTAT_DMAERR_MASK 0x20u +#define USB_ERRSTAT_DMAERR_SHIFT 5 +#define USB_ERRSTAT_BTSERR_MASK 0x80u +#define USB_ERRSTAT_BTSERR_SHIFT 7 +/* ERREN Bit Fields */ +#define USB_ERREN_PIDERREN_MASK 0x1u +#define USB_ERREN_PIDERREN_SHIFT 0 +#define USB_ERREN_CRC5EOFEN_MASK 0x2u +#define USB_ERREN_CRC5EOFEN_SHIFT 1 +#define USB_ERREN_CRC16EN_MASK 0x4u +#define USB_ERREN_CRC16EN_SHIFT 2 +#define USB_ERREN_DFN8EN_MASK 0x8u +#define USB_ERREN_DFN8EN_SHIFT 3 +#define USB_ERREN_BTOERREN_MASK 0x10u +#define USB_ERREN_BTOERREN_SHIFT 4 +#define USB_ERREN_DMAERREN_MASK 0x20u +#define USB_ERREN_DMAERREN_SHIFT 5 +#define USB_ERREN_BTSERREN_MASK 0x80u +#define USB_ERREN_BTSERREN_SHIFT 7 +/* STAT Bit Fields */ +#define USB_STAT_ODD_MASK 0x4u +#define USB_STAT_ODD_SHIFT 2 +#define USB_STAT_TX_MASK 0x8u +#define USB_STAT_TX_SHIFT 3 +#define USB_STAT_ENDP_MASK 0xF0u +#define USB_STAT_ENDP_SHIFT 4 +#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK) +/* CTL Bit Fields */ +#define USB_CTL_USBENSOFEN_MASK 0x1u +#define USB_CTL_USBENSOFEN_SHIFT 0 +#define USB_CTL_ODDRST_MASK 0x2u +#define USB_CTL_ODDRST_SHIFT 1 +#define USB_CTL_RESUME_MASK 0x4u +#define USB_CTL_RESUME_SHIFT 2 +#define USB_CTL_HOSTMODEEN_MASK 0x8u +#define USB_CTL_HOSTMODEEN_SHIFT 3 +#define USB_CTL_RESET_MASK 0x10u +#define USB_CTL_RESET_SHIFT 4 +#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u +#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5 +#define USB_CTL_SE0_MASK 0x40u +#define USB_CTL_SE0_SHIFT 6 +#define USB_CTL_JSTATE_MASK 0x80u +#define USB_CTL_JSTATE_SHIFT 7 +/* ADDR Bit Fields */ +#define USB_ADDR_ADDR_MASK 0x7Fu +#define USB_ADDR_ADDR_SHIFT 0 +#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK) +#define USB_ADDR_LSEN_MASK 0x80u +#define USB_ADDR_LSEN_SHIFT 7 +/* BDTPAGE1 Bit Fields */ +#define USB_BDTPAGE1_BDTBA_MASK 0xFEu +#define USB_BDTPAGE1_BDTBA_SHIFT 1 +#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK) +/* FRMNUML Bit Fields */ +#define USB_FRMNUML_FRM_MASK 0xFFu +#define USB_FRMNUML_FRM_SHIFT 0 +#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK) +/* FRMNUMH Bit Fields */ +#define USB_FRMNUMH_FRM_MASK 0x7u +#define USB_FRMNUMH_FRM_SHIFT 0 +#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK) +/* TOKEN Bit Fields */ +#define USB_TOKEN_TOKENENDPT_MASK 0xFu +#define USB_TOKEN_TOKENENDPT_SHIFT 0 +#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK) +#define USB_TOKEN_TOKENPID_MASK 0xF0u +#define USB_TOKEN_TOKENPID_SHIFT 4 +#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK) +/* SOFTHLD Bit Fields */ +#define USB_SOFTHLD_CNT_MASK 0xFFu +#define USB_SOFTHLD_CNT_SHIFT 0 +#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK) +/* BDTPAGE2 Bit Fields */ +#define USB_BDTPAGE2_BDTBA_MASK 0xFFu +#define USB_BDTPAGE2_BDTBA_SHIFT 0 +#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK) +/* BDTPAGE3 Bit Fields */ +#define USB_BDTPAGE3_BDTBA_MASK 0xFFu +#define USB_BDTPAGE3_BDTBA_SHIFT 0 +#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK) +/* ENDPT Bit Fields */ +#define USB_ENDPT_EPHSHK_MASK 0x1u +#define USB_ENDPT_EPHSHK_SHIFT 0 +#define USB_ENDPT_EPSTALL_MASK 0x2u +#define USB_ENDPT_EPSTALL_SHIFT 1 +#define USB_ENDPT_EPTXEN_MASK 0x4u +#define USB_ENDPT_EPTXEN_SHIFT 2 +#define USB_ENDPT_EPRXEN_MASK 0x8u +#define USB_ENDPT_EPRXEN_SHIFT 3 +#define USB_ENDPT_EPCTLDIS_MASK 0x10u +#define USB_ENDPT_EPCTLDIS_SHIFT 4 +#define USB_ENDPT_RETRYDIS_MASK 0x40u +#define USB_ENDPT_RETRYDIS_SHIFT 6 +#define USB_ENDPT_HOSTWOHUB_MASK 0x80u +#define USB_ENDPT_HOSTWOHUB_SHIFT 7 +/* USBCTRL Bit Fields */ +#define USB_USBCTRL_PDE_MASK 0x40u +#define USB_USBCTRL_PDE_SHIFT 6 +#define USB_USBCTRL_SUSP_MASK 0x80u +#define USB_USBCTRL_SUSP_SHIFT 7 +/* OBSERVE Bit Fields */ +#define USB_OBSERVE_DMPD_MASK 0x10u +#define USB_OBSERVE_DMPD_SHIFT 4 +#define USB_OBSERVE_DPPD_MASK 0x40u +#define USB_OBSERVE_DPPD_SHIFT 6 +#define USB_OBSERVE_DPPU_MASK 0x80u +#define USB_OBSERVE_DPPU_SHIFT 7 +/* CONTROL Bit Fields */ +#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u +#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4 +/* USBTRC0 Bit Fields */ +#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u +#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0 +#define USB_USBTRC0_SYNC_DET_MASK 0x2u +#define USB_USBTRC0_SYNC_DET_SHIFT 1 +#define USB_USBTRC0_USBRESMEN_MASK 0x20u +#define USB_USBTRC0_USBRESMEN_SHIFT 5 +#define USB_USBTRC0_USBRESET_MASK 0x80u +#define USB_USBTRC0_USBRESET_SHIFT 7 +/* USBFRMADJUST Bit Fields */ +#define USB_USBFRMADJUST_ADJ_MASK 0xFFu +#define USB_USBFRMADJUST_ADJ_SHIFT 0 +#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK) + +/** + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x40072000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) + +/** + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBDCD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer + * @{ + */ + +/** USBDCD - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */ + __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */ + __I uint32_t STATUS; /**< Status Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */ + __IO uint32_t TIMER1; /**< , offset: 0x14 */ + __IO uint32_t TIMER2; /**< , offset: 0x18 */ +} USBDCD_Type; + +/* ---------------------------------------------------------------------------- + -- USBDCD Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup USBDCD_Register_Masks USBDCD Register Masks + * @{ + */ + +/* CONTROL Bit Fields */ +#define USBDCD_CONTROL_IACK_MASK 0x1u +#define USBDCD_CONTROL_IACK_SHIFT 0 +#define USBDCD_CONTROL_IF_MASK 0x100u +#define USBDCD_CONTROL_IF_SHIFT 8 +#define USBDCD_CONTROL_IE_MASK 0x10000u +#define USBDCD_CONTROL_IE_SHIFT 16 +#define USBDCD_CONTROL_START_MASK 0x1000000u +#define USBDCD_CONTROL_START_SHIFT 24 +#define USBDCD_CONTROL_SR_MASK 0x2000000u +#define USBDCD_CONTROL_SR_SHIFT 25 +/* CLOCK Bit Fields */ +#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u +#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0 +#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu +#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2 +#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK) +/* STATUS Bit Fields */ +#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u +#define USBDCD_STATUS_SEQ_RES_SHIFT 16 +#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK) +#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u +#define USBDCD_STATUS_SEQ_STAT_SHIFT 18 +#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK) +#define USBDCD_STATUS_ERR_MASK 0x100000u +#define USBDCD_STATUS_ERR_SHIFT 20 +#define USBDCD_STATUS_TO_MASK 0x200000u +#define USBDCD_STATUS_TO_SHIFT 21 +#define USBDCD_STATUS_ACTIVE_MASK 0x400000u +#define USBDCD_STATUS_ACTIVE_SHIFT 22 +/* TIMER0 Bit Fields */ +#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu +#define USBDCD_TIMER0_TUNITCON_SHIFT 0 +#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK) +#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u +#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16 +#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK) +/* TIMER1 Bit Fields */ +#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu +#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0 +#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK) +#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u +#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16 +#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK) +/* TIMER2 Bit Fields */ +#define USBDCD_TIMER2_CHECK_DM_MASK 0xFu +#define USBDCD_TIMER2_CHECK_DM_SHIFT 0 +#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK) +#define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u +#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16 +#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK) + +/** + * @} + */ /* end of group USBDCD_Register_Masks */ + + +/* USBDCD - Peripheral instance base addresses */ +/** Peripheral USBDCD base address */ +#define USBDCD_BASE (0x40035000u) +/** Peripheral USBDCD base pointer */ +#define USBDCD ((USBDCD_Type *)USBDCD_BASE) + +/** + * @} + */ /* end of group USBDCD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- VREF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer + * @{ + */ + +/** VREF - Register Layout Typedef */ +typedef struct { + __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ + __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ +} VREF_Type; + +/* ---------------------------------------------------------------------------- + -- VREF Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup VREF_Register_Masks VREF Register Masks + * @{ + */ + +/* TRM Bit Fields */ +#define VREF_TRM_TRIM_MASK 0x3Fu +#define VREF_TRM_TRIM_SHIFT 0 +#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK) +#define VREF_TRM_CHOPEN_MASK 0x40u +#define VREF_TRM_CHOPEN_SHIFT 6 +/* SC Bit Fields */ +#define VREF_SC_MODE_LV_MASK 0x3u +#define VREF_SC_MODE_LV_SHIFT 0 +#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK) +#define VREF_SC_VREFST_MASK 0x4u +#define VREF_SC_VREFST_SHIFT 2 +#define VREF_SC_REGEN_MASK 0x40u +#define VREF_SC_REGEN_SHIFT 6 +#define VREF_SC_VREFEN_MASK 0x80u +#define VREF_SC_VREFEN_SHIFT 7 + +/** + * @} + */ /* end of group VREF_Register_Masks */ + + +/* VREF - Peripheral instance base addresses */ +/** Peripheral VREF base address */ +#define VREF_BASE (0x40074000u) +/** Peripheral VREF base pointer */ +#define VREF ((VREF_Type *)VREF_BASE) + +/** + * @} + */ /* end of group VREF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */ + __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */ + __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */ + __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */ + __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */ + __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */ + __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */ + __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */ + __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */ + __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */ + __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */ + __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/* STCTRLH Bit Fields */ +#define WDOG_STCTRLH_WDOGEN_MASK 0x1u +#define WDOG_STCTRLH_WDOGEN_SHIFT 0 +#define WDOG_STCTRLH_CLKSRC_MASK 0x2u +#define WDOG_STCTRLH_CLKSRC_SHIFT 1 +#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u +#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 +#define WDOG_STCTRLH_WINEN_MASK 0x8u +#define WDOG_STCTRLH_WINEN_SHIFT 3 +#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u +#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 +#define WDOG_STCTRLH_DBGEN_MASK 0x20u +#define WDOG_STCTRLH_DBGEN_SHIFT 5 +#define WDOG_STCTRLH_STOPEN_MASK 0x40u +#define WDOG_STCTRLH_STOPEN_SHIFT 6 +#define WDOG_STCTRLH_WAITEN_MASK 0x80u +#define WDOG_STCTRLH_WAITEN_SHIFT 7 +#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u +#define WDOG_STCTRLH_TESTWDOG_SHIFT 10 +#define WDOG_STCTRLH_TESTSEL_MASK 0x800u +#define WDOG_STCTRLH_TESTSEL_SHIFT 11 +#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u +#define WDOG_STCTRLH_BYTESEL_SHIFT 12 +#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK) +#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u +#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14 +/* STCTRLL Bit Fields */ +#define WDOG_STCTRLL_INTFLG_MASK 0x8000u +#define WDOG_STCTRLL_INTFLG_SHIFT 15 +/* TOVALH Bit Fields */ +#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu +#define WDOG_TOVALH_TOVALHIGH_SHIFT 0 +#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK) +/* TOVALL Bit Fields */ +#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu +#define WDOG_TOVALL_TOVALLOW_SHIFT 0 +#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK) +/* WINH Bit Fields */ +#define WDOG_WINH_WINHIGH_MASK 0xFFFFu +#define WDOG_WINH_WINHIGH_SHIFT 0 +#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK) +/* WINL Bit Fields */ +#define WDOG_WINL_WINLOW_MASK 0xFFFFu +#define WDOG_WINL_WINLOW_SHIFT 0 +#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK) +/* REFRESH Bit Fields */ +#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu +#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0 +#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK) +/* UNLOCK Bit Fields */ +#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu +#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0 +#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK) +/* TMROUTH Bit Fields */ +#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu +#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0 +#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK) +/* TMROUTL Bit Fields */ +#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu +#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0 +#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK) +/* RSTCNT Bit Fields */ +#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu +#define WDOG_RSTCNT_RSTCNT_SHIFT 0 +#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK) +/* PRESC Bit Fields */ +#define WDOG_PRESC_PRESCVAL_MASK 0x700u +#define WDOG_PRESC_PRESCVAL_SHIFT 8 +#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK) + +/** + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG base address */ +#define WDOG_BASE (0x40052000u) +/** Peripheral WDOG base pointer */ +#define WDOG ((WDOG_Type *)WDOG_BASE) + +/** + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__CWCC__) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/** + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Backward Compatibility + ---------------------------------------------------------------------------- */ + +/** + * @addtogroup Backward_Compatibility_Symbols Backward Compatibility + * @{ + */ + +/* No backward compatibility issues. */ + +/** + * @} + */ /* end of group Backward_Compatibility_Symbols */ + + +#endif /* #if !defined(MK20D5_H_) */ + +/* MK20D5.h, eof. */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/MK20DX256.sct Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,13 @@ + +LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k) + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; 8_byte_aligned(112 vect * 4 bytes) = 8_byte_aligned(0x1C0) = 0x1C0 + ; 0x10000 - 0x1C0 = 0xFE40 + RW_IRAM1 0x1FFF81C0 0xFE40 { + .ANY (+RW +ZI) + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/startup_MK20DX256.s Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,559 @@ +;/***************************************************************************** +; * @file: startup_MK20DX256.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the +; * MK20DX256 +; * @version: 1.0 +; * @date: 2011-12-15 +; * +; * Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved. +;* +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt + DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt + DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt + DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt + DCD DMA4_IRQHandler ; DMA channel 4 transfer complete interrupt + DCD DMA5_IRQHandler ; DMA channel 5 transfer complete interrupt + DCD DMA6_IRQHandler ; DMA channel 6 transfer complete interrupt + DCD DMA7_IRQHandler ; DMA channel 7 transfer complete interrupt + DCD DMA8_IRQHandler ; DMA channel 8 transfer complete interrupt + DCD DMA9_IRQHandler ; DMA channel 9 transfer complete interrupt + DCD DMA10_IRQHandler ; DMA channel 10 transfer complete interrupt + DCD DMA11_IRQHandler ; DMA channel 11 transfer complete interrupt + DCD DMA12_IRQHandler ; DMA channel 12 transfer complete interrupt + DCD DMA13_IRQHandler ; DMA channel 13 transfer complete interrupt + DCD DMA14_IRQHandler ; DMA channel 14 transfer complete interrupt + DCD DMA15_IRQHandler ; DMA channel 15 transfer complete interrupt + DCD DMA_Error_IRQHandler ; DMA error interrupt + DCD Reserved33_IRQHandler ; Reserved interrupt 33 + DCD FTFL_IRQHandler ; FTFL interrupt + DCD Read_Collision_IRQHandler ; Read collision interrupt + DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning + DCD LLW_IRQHandler ; Low Leakage Wakeup + DCD Watchdog_IRQHandler ; WDOG interrupt + DCD Reserved39_IRQHandler ; Reserved interrupt 39 + DCD I2C0_IRQHandler ; I2C0 interrupt + DCD I2C1_IRQHandler ; I2C1 interrupt + DCD SPI0_IRQHandler ; SPI0 interrupt + DCD SPI1_IRQHandler ; SPI1 interrupt + DCD Reserved44_IRQHandler ; Reserved interrupt 44 + DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt + DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt + DCD CAN0_Error_IRQHandler ; CAN0 error interrupt + DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt + DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt + DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt + DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt + DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt + DCD Reserved53_IRQHandler ; Reserved interrupt 53 + DCD Reserved54_IRQHandler ; Reserved interrupt 54 + DCD Reserved55_IRQHandler ; Reserved interrupt 55 + DCD Reserved56_IRQHandler ; Reserved interrupt 56 + DCD Reserved57_IRQHandler ; Reserved interrupt 57 + DCD Reserved58_IRQHandler ; Reserved interrupt 58 + DCD Reserved59_IRQHandler ; Reserved interrupt 59 + DCD UART0_LON_IRQHandler ; UART0 LON interrupt + DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt + DCD UART0_ERR_IRQHandler ; UART0 error interrupt + DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt + DCD UART1_ERR_IRQHandler ; UART1 error interrupt + DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt + DCD UART2_ERR_IRQHandler ; UART2 error interrupt + DCD Reserved67_IRQHandler ; Reserved interrupt 67 + DCD Reserved68_IRQHandler ; Reserved interrupt 68 + DCD Reserved69_IRQHandler ; Reserved interrupt 69 + DCD Reserved70_IRQHandler ; Reserved interrupt 70 + DCD Reserved71_IRQHandler ; Reserved interrupt 71 + DCD Reserved72_IRQHandler ; Reserved interrupt 72 + DCD ADC0_IRQHandler ; ADC0 interrupt + DCD ADC1_IRQHandler ; ADC1 interrupt + DCD CMP0_IRQHandler ; CMP0 interrupt + DCD CMP1_IRQHandler ; CMP1 interrupt + DCD CMP2_IRQHandler ; CMP2 interrupt + DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt + DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt + DCD CMT_IRQHandler ; CMT interrupt + DCD RTC_IRQHandler ; RTC interrupt + DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt + DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt + DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt + DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt + DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt + DCD PDB0_IRQHandler ; PDB0 interrupt + DCD USB0_IRQHandler ; USB0 interrupt + DCD USBDCD_IRQHandler ; USBDCD interrupt + DCD Reserved91_IRQHandler ; Reserved interrupt 91 + DCD Reserved92_IRQHandler ; Reserved interrupt 92 + DCD Reserved93_IRQHandler ; Reserved interrupt 93 + DCD Reserved94_IRQHandler ; Reserved interrupt 94 + DCD Reserved95_IRQHandler ; Reserved interrupt 95 + DCD Reserved96_IRQHandler ; Reserved interrupt 96 + DCD DAC0_IRQHandler ; DAC0 interrupt + DCD Reserved98_IRQHandler ; Reserved interrupt 98 + DCD TSI0_IRQHandler ; TSI0 interrupt + DCD MCG_IRQHandler ; MCG interrupt + DCD LPTimer_IRQHandler ; LPTimer interrupt + DCD Reserved102_IRQHandler ; Reserved interrupt 102 + DCD PORTA_IRQHandler ; Port A interrupt + DCD PORTB_IRQHandler ; Port B interrupt + DCD PORTC_IRQHandler ; Port C interrupt + DCD PORTD_IRQHandler ; Port D interrupt + DCD PORTE_IRQHandler ; Port E interrupt + DCD Reserved108_IRQHandler ; Reserved interrupt 108 + DCD Reserved109_IRQHandler ; Reserved interrupt 109 + DCD SWI_IRQHandler ; Software interrupt +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; <h> Flash Configuration +; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) +; <i> and security information that allows the MCU to restrict acces to the FTFL module. +; <h> Backdoor Comparison Key +; <o0> Backdoor Key 0 <0x0-0xFF:2> +; <o1> Backdoor Key 1 <0x0-0xFF:2> +; <o2> Backdoor Key 2 <0x0-0xFF:2> +; <o3> Backdoor Key 3 <0x0-0xFF:2> +; <o4> Backdoor Key 4 <0x0-0xFF:2> +; <o5> Backdoor Key 5 <0x0-0xFF:2> +; <o6> Backdoor Key 6 <0x0-0xFF:2> +; <o7> Backdoor Key 7 <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; </h> +; <h> Program flash protection bytes (FPROT) +; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; <i> Each bit protects a 1/32 region of the program flash memory. +; <h> FPROT0 +; <i> Program flash protection bytes +; <i> 1/32 - 8/32 region +; <o.0> FPROT0.0 +; <o.1> FPROT0.1 +; <o.2> FPROT0.2 +; <o.3> FPROT0.3 +; <o.4> FPROT0.4 +; <o.5> FPROT0.5 +; <o.6> FPROT0.6 +; <o.7> FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; </h> +; <h> FPROT1 +; <i> Program Flash Region Protect Register 1 +; <i> 9/32 - 16/32 region +; <o.0> FPROT1.0 +; <o.1> FPROT1.1 +; <o.2> FPROT1.2 +; <o.3> FPROT1.3 +; <o.4> FPROT1.4 +; <o.5> FPROT1.5 +; <o.6> FPROT1.6 +; <o.7> FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; </h> +; <h> FPROT2 +; <i> Program Flash Region Protect Register 2 +; <i> 17/32 - 24/32 region +; <o.0> FPROT2.0 +; <o.1> FPROT2.1 +; <o.2> FPROT2.2 +; <o.3> FPROT2.3 +; <o.4> FPROT2.4 +; <o.5> FPROT2.5 +; <o.6> FPROT2.6 +; <o.7> FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; </h> +; <h> FPROT3 +; <i> Program Flash Region Protect Register 3 +; <i> 25/32 - 32/32 region +; <o.0> FPROT3.0 +; <o.1> FPROT3.1 +; <o.2> FPROT3.2 +; <o.3> FPROT3.3 +; <o.4> FPROT3.4 +; <o.5> FPROT3.5 +; <o.6> FPROT3.6 +; <o.7> FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; </h> +; </h> +; <h> Data flash protection byte (FDPROT) +; <i> Each bit protects a 1/8 region of the data flash memory. +; <i> (Program flash only devices: Reserved) +; <o.0> FDPROT.0 +; <o.1> FDPROT.1 +; <o.2> FDPROT.2 +; <o.3> FDPROT.3 +; <o.4> FDPROT.4 +; <o.5> FDPROT.5 +; <o.6> FDPROT.6 +; <o.7> FDPROT.7 +nFDPROT EQU 0x00 +FDPROT EQU nFDPROT:EOR:0xFF +; </h> +; <h> EEPROM protection byte (FEPROT) +; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. +; <i> (Program flash only devices: Reserved) +; <o.0> FEPROT.0 +; <o.1> FEPROT.1 +; <o.2> FEPROT.2 +; <o.3> FEPROT.3 +; <o.4> FEPROT.4 +; <o.5> FEPROT.5 +; <o.6> FEPROT.6 +; <o.7> FEPROT.7 +nFEPROT EQU 0x00 +FEPROT EQU nFEPROT:EOR:0xFF +; </h> +; <h> Flash nonvolatile option byte (FOPT) +; <i> Allows the user to customize the operation of the MCU at boot time. +; <o.0> LPBOOT +; <0=> Low-power boot +; <1=> normal boot +; <o.1> EZPORT_DIS +; <0=> EzPort operation is enabled +; <1=> EzPort operation is disabled +FOPT EQU 0xFF +; </h> +; <h> Flash security byte (FSEC) +; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; <o.0..1> SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; <i> Flash Security +; <i> This bits define the security state of the MCU. +; <o.2..3> FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; <i> Freescale Failure Analysis Access Code +; <i> This bits define the security state of the MCU. +; <o.4..5> MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; <i> Mass Erase Enable Bits +; <i> Enables and disables mass erase capability of the FTFL module +; <o.6..7> KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; <i> Backdoor key Security Enable +; <i> These bits enable and disable backdoor key access to the FTFL module. +FSEC EQU 0xFE +; </h> +; </h> + IF :LNOT::DEF:RAM_TARGET + AREA |.ARM.__at_0x400|, CODE, READONLY + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0, FPROT1, FPROT2, FPROT3 + DCB FSEC, FOPT, FEPROT, FDPROT + ENDIF + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT DMA0_IRQHandler [WEAK] + EXPORT DMA1_IRQHandler [WEAK] + EXPORT DMA2_IRQHandler [WEAK] + EXPORT DMA3_IRQHandler [WEAK] + EXPORT DMA4_IRQHandler [WEAK] + EXPORT DMA5_IRQHandler [WEAK] + EXPORT DMA6_IRQHandler [WEAK] + EXPORT DMA7_IRQHandler [WEAK] + EXPORT DMA8_IRQHandler [WEAK] + EXPORT DMA9_IRQHandler [WEAK] + EXPORT DMA10_IRQHandler [WEAK] + EXPORT DMA11_IRQHandler [WEAK] + EXPORT DMA12_IRQHandler [WEAK] + EXPORT DMA13_IRQHandler [WEAK] + EXPORT DMA14_IRQHandler [WEAK] + EXPORT DMA15_IRQHandler [WEAK] + EXPORT DMA_Error_IRQHandler [WEAK] + EXPORT Reserved33_IRQHandler [WEAK] + EXPORT FTFL_IRQHandler [WEAK] + EXPORT Read_Collision_IRQHandler [WEAK] + EXPORT LVD_LVW_IRQHandler [WEAK] + EXPORT LLW_IRQHandler [WEAK] + EXPORT Watchdog_IRQHandler [WEAK] + EXPORT Reserved39_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT Reserved44_IRQHandler [WEAK] + EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] + EXPORT CAN0_Bus_Off_IRQHandler [WEAK] + EXPORT CAN0_Error_IRQHandler [WEAK] + EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] + EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] + EXPORT CAN0_Wake_Up_IRQHandler [WEAK] + EXPORT I2S0_Tx_IRQHandler [WEAK] + EXPORT I2S0_Rx_IRQHandler [WEAK] + EXPORT Reserved53_IRQHandler [WEAK] + EXPORT Reserved54_IRQHandler [WEAK] + EXPORT Reserved55_IRQHandler [WEAK] + EXPORT Reserved56_IRQHandler [WEAK] + EXPORT Reserved57_IRQHandler [WEAK] + EXPORT Reserved58_IRQHandler [WEAK] + EXPORT Reserved59_IRQHandler [WEAK] + EXPORT UART0_LON_IRQHandler [WEAK] + EXPORT UART0_RX_TX_IRQHandler [WEAK] + EXPORT UART0_ERR_IRQHandler [WEAK] + EXPORT UART1_RX_TX_IRQHandler [WEAK] + EXPORT UART1_ERR_IRQHandler [WEAK] + EXPORT UART2_RX_TX_IRQHandler [WEAK] + EXPORT UART2_ERR_IRQHandler [WEAK] + EXPORT Reserved67_IRQHandler [WEAK] + EXPORT Reserved68_IRQHandler [WEAK] + EXPORT Reserved69_IRQHandler [WEAK] + EXPORT Reserved70_IRQHandler [WEAK] + EXPORT Reserved71_IRQHandler [WEAK] + EXPORT Reserved72_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT FTM0_IRQHandler [WEAK] + EXPORT FTM1_IRQHandler [WEAK] + EXPORT FTM2_IRQHandler [WEAK] + EXPORT CMT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT0_IRQHandler [WEAK] + EXPORT PIT1_IRQHandler [WEAK] + EXPORT PIT2_IRQHandler [WEAK] + EXPORT PIT3_IRQHandler [WEAK] + EXPORT PDB0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT USBDCD_IRQHandler [WEAK] + EXPORT Reserved91_IRQHandler [WEAK] + EXPORT Reserved92_IRQHandler [WEAK] + EXPORT Reserved93_IRQHandler [WEAK] + EXPORT Reserved94_IRQHandler [WEAK] + EXPORT Reserved95_IRQHandler [WEAK] + EXPORT Reserved96_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT Reserved98_IRQHandler [WEAK] + EXPORT TSI0_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT LPTimer_IRQHandler [WEAK] + EXPORT Reserved102_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_IRQHandler [WEAK] + EXPORT PORTD_IRQHandler [WEAK] + EXPORT PORTE_IRQHandler [WEAK] + EXPORT Reserved108_IRQHandler [WEAK] + EXPORT Reserved109_IRQHandler [WEAK] + EXPORT SWI_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] + +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +DMA4_IRQHandler +DMA5_IRQHandler +DMA6_IRQHandler +DMA7_IRQHandler +DMA8_IRQHandler +DMA9_IRQHandler +DMA10_IRQHandler +DMA11_IRQHandler +DMA12_IRQHandler +DMA13_IRQHandler +DMA14_IRQHandler +DMA15_IRQHandler +DMA_Error_IRQHandler +Reserved33_IRQHandler +FTFL_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +LLW_IRQHandler +Watchdog_IRQHandler +Reserved39_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +Reserved44_IRQHandler +CAN0_ORed_Message_buffer_IRQHandler +CAN0_Bus_Off_IRQHandler +CAN0_Error_IRQHandler +CAN0_Tx_Warning_IRQHandler +CAN0_Rx_Warning_IRQHandler +CAN0_Wake_Up_IRQHandler +I2S0_Tx_IRQHandler +I2S0_Rx_IRQHandler +Reserved53_IRQHandler +Reserved54_IRQHandler +Reserved55_IRQHandler +Reserved56_IRQHandler +Reserved57_IRQHandler +Reserved58_IRQHandler +Reserved59_IRQHandler +UART0_LON_IRQHandler +UART0_RX_TX_IRQHandler +UART0_ERR_IRQHandler +UART1_RX_TX_IRQHandler +UART1_ERR_IRQHandler +UART2_RX_TX_IRQHandler +UART2_ERR_IRQHandler +Reserved67_IRQHandler +Reserved68_IRQHandler +Reserved69_IRQHandler +Reserved70_IRQHandler +Reserved71_IRQHandler +Reserved72_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +FTM2_IRQHandler +CMT_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +USBDCD_IRQHandler +Reserved91_IRQHandler +Reserved92_IRQHandler +Reserved93_IRQHandler +Reserved94_IRQHandler +Reserved95_IRQHandler +Reserved96_IRQHandler +DAC0_IRQHandler +Reserved98_IRQHandler +TSI0_IRQHandler +MCG_IRQHandler +LPTimer_IRQHandler +Reserved102_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +Reserved108_IRQHandler +Reserved109_IRQHandler +SWI_IRQHandler +DefaultISR + + B . + + ENDP + + + ALIGN + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2015 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rt_misc.h> +#include <stdint.h> + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,163 @@ +/* + * K20DX256 ARM GCC linker script file + */ + +MEMORY +{ + VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010 + FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410 + RAM (rwx) : ORIGIN = 0x1FFF81C0, LENGTH = 64K - 0x1C0 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * _reset_init : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .isr_vector : + { + __vector_table = .; + KEEP(*(.vector_table)) + *(.text.Reset_Handler) + *(.text.System_Init) + . = ALIGN(4); + } > VECTORS + + .flash_protect : + { + KEEP(*(.kinetis_flash_config_field)) + . = ALIGN(4); + } > FLASH_PROTECTION + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,361 @@ +/* File: startup_MK20DX256.s + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.3 + * Date: 08 Feb 2012 + * + * Copyright (c) 2015, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x400 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0xC00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector + +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long DMA0_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA1_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA2_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA3_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA4_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA5_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA6_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA7_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA8_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA9_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA10_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA11_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA12_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA13_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA14_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA15_IRQHandler // DMA channel 0 transfer complete interrupt + .long DMA_Error_IRQHandler // DMA error interrupt + .long Reserved33_IRQHandler // Reserved interrupt 33 + .long FTFL_IRQHandler // FTFL interrupt + .long Read_Collision_IRQHandler // Read collision interrupt + .long LVD_LVW_IRQHandler // Low Voltage Detect, Low Voltage Warning + .long LLW_IRQHandler // Low Leakage Wakeup + .long Watchdog_IRQHandler // WDOG interrupt + .long Reserved39_IRQHandler // Reserved interrupt 39 + .long I2C0_IRQHandler // I2C0 interrupt + .long I2C1_IRQHandler // I2C1 interrupt + .long SPI0_IRQHandler // SPI0 interrupt + .long SPI1_IRQHandler // SPI1 interrupt + .long Reserved44_IRQHandler // Reserved interrupt 44 + .long CAN0_ORed_Message_buffer_IRQHandler // CAN0 OR'd message buffers interrupt + .long CAN0_Bus_Off_IRQHandler // CAN0 bus off interrupt + .long CAN0_Error_IRQHandler // CAN0 error interrupt + .long CAN0_Tx_Warning_IRQHandler // CAN0 Tx warning interrupt + .long CAN0_Rx_Warning_IRQHandler // CAN0 Rx warning interrupt + .long CAN0_Wake_Up_IRQHandler // CAN0 wake up interrupt + .long I2S0_Tx_IRQHandler // I2S0 transmit interrupt + .long I2S0_Rx_IRQHandler // I2S0 receive interrupt + .long Reserved53_IRQHandler // Reserved interrupt 53 + .long Reserved54_IRQHandler // Reserved interrupt 54 + .long Reserved55_IRQHandler // Reserved interrupt 55 + .long Reserved56_IRQHandler // Reserved interrupt 56 + .long Reserved57_IRQHandler // Reserved interrupt 57 + .long Reserved58_IRQHandler // Reserved interrupt 58 + .long Reserved59_IRQHandler // Reserved interrupt 59 + .long UART0_LON_IRQHandler // UART0 LON interrupt + .long UART0_RX_TX_IRQHandler // UART0 receive/transmit interrupt + .long UART0_ERR_IRQHandler // UART0 error interrupt + .long UART1_RX_TX_IRQHandler // UART1 receive/transmit interrupt + .long UART1_ERR_IRQHandler // UART1 error interrupt + .long UART2_RX_TX_IRQHandler // UART2 receive/transmit interrupt + .long UART2_ERR_IRQHandler // UART2 error interrupt + .long Reserved67_IRQHandler // Reserved interrupt 67 + .long Reserved68_IRQHandler // Reserved interrupt 68 + .long Reserved69_IRQHandler // Reserved interrupt 69 + .long Reserved70_IRQHandler // Reserved interrupt 70 + .long Reserved71_IRQHandler // Reserved interrupt 71 + .long Reserved72_IRQHandler // Reserved interrupt 72 + .long ADC0_IRQHandler // ADC0 interrupt + .long ADC1_IRQHandler // ADC1 interrupt + .long CMP0_IRQHandler // CMP0 interrupt + .long CMP1_IRQHandler // CMP1 interrupt + .long CMP2_IRQHandler // CMP2 interrupt + .long FTM0_IRQHandler // FTM0 fault, overflow and channels interrupt + .long FTM1_IRQHandler // FTM1 fault, overflow and channels interrupt + .long FTM2_IRQHandler // FTM2 fault, overflow and channels interrupt + .long CMT_IRQHandler // CMT interrupt + .long RTC_IRQHandler // RTC interrupt + .long RTC_Seconds_IRQHandler // RTC seconds interrupt + .long PIT0_IRQHandler // PIT timer channel 0 interrupt + .long PIT1_IRQHandler // PIT timer channel 1 interrupt + .long PIT2_IRQHandler // PIT timer channel 2 interrupt + .long PIT3_IRQHandler // PIT timer channel 3 interrupt + .long PDB0_IRQHandler // PDB0 interrupt + .long USB0_IRQHandler // USB0 interrupt + .long USBDCD_IRQHandler // USBDCD interrupt + .long Reserved91_IRQHandler // Reserved interrupt 91 + .long Reserved92_IRQHandler // Reserved interrupt 92 + .long Reserved93_IRQHandler // Reserved interrupt 93 + .long Reserved94_IRQHandler // Reserved interrupt 94 + .long Reserved95_IRQHandler // Reserved interrupt 95 + .long Reserved96_IRQHandler // Reserved interrupt 96 + .long DAC0_IRQHandler // DAC0 interrupt + .long Reserved98_IRQHandler // Reserved interrupt 98 + .long TSI0_IRQHandler // TSI0 interrupt + .long MCG_IRQHandler // MCG interrupt + .long LPTimer_IRQHandler // LPTimer interrupt + .long Reserved102_IRQHandler // Reserved interrupt 102 + .long PORTA_IRQHandler // Port A interrupt + .long PORTB_IRQHandler // Port B interrupt + .long PORTC_IRQHandler // Port C interrupt + .long PORTD_IRQHandler // Port D interrupt + .long PORTE_IRQHandler // Port E interrupt + .long Reserved108_IRQHandler // Reserved interrupt 108 + .long Reserved109_IRQHandler // Reserved interrupt 109 + .long SWI_IRQHandler // Software interrupt + + .size __isr_vector, . - __isr_vector + + .section .text.Reset_Handler + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.Lflash_to_ram_loop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .Lflash_to_ram_loop + +.Lflash_to_ram_loop_end: + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + + def_irq_default_handler DMA0_IRQHandler + def_irq_default_handler DMA1_IRQHandler + def_irq_default_handler DMA2_IRQHandler + def_irq_default_handler DMA3_IRQHandler + def_irq_default_handler DMA4_IRQHandler + def_irq_default_handler DMA5_IRQHandler + def_irq_default_handler DMA6_IRQHandler + def_irq_default_handler DMA7_IRQHandler + def_irq_default_handler DMA8_IRQHandler + def_irq_default_handler DMA9_IRQHandler + def_irq_default_handler DMA10_IRQHandler + def_irq_default_handler DMA11_IRQHandler + def_irq_default_handler DMA12_IRQHandler + def_irq_default_handler DMA13_IRQHandler + def_irq_default_handler DMA14_IRQHandler + def_irq_default_handler DMA15_IRQHandler + def_irq_default_handler DMA_Error_IRQHandler + def_irq_default_handler Reserved33_IRQHandler + def_irq_default_handler FTFL_IRQHandler + def_irq_default_handler Read_Collision_IRQHandler + def_irq_default_handler LVD_LVW_IRQHandler + def_irq_default_handler LLW_IRQHandler + def_irq_default_handler Watchdog_IRQHandler + def_irq_default_handler Reserved39_IRQHandler + def_irq_default_handler I2C0_IRQHandler + def_irq_default_handler I2C1_IRQHandler + def_irq_default_handler SPI0_IRQHandler + def_irq_default_handler SPI1_IRQHandler + def_irq_default_handler Reserved44_IRQHandler + def_irq_default_handler CAN0_ORed_Message_buffer_IRQHandler + def_irq_default_handler CAN0_Bus_Off_IRQHandler + def_irq_default_handler CAN0_Error_IRQHandler + def_irq_default_handler CAN0_Tx_Warning_IRQHandler + def_irq_default_handler CAN0_Rx_Warning_IRQHandler + def_irq_default_handler CAN0_Wake_Up_IRQHandler + def_irq_default_handler I2S0_Tx_IRQHandler + def_irq_default_handler I2S0_Rx_IRQHandler + def_irq_default_handler Reserved53_IRQHandler + def_irq_default_handler Reserved54_IRQHandler + def_irq_default_handler Reserved55_IRQHandler + def_irq_default_handler Reserved56_IRQHandler + def_irq_default_handler Reserved57_IRQHandler + def_irq_default_handler Reserved58_IRQHandler + def_irq_default_handler Reserved59_IRQHandler + def_irq_default_handler UART0_LON_IRQHandler + def_irq_default_handler UART0_RX_TX_IRQHandler + def_irq_default_handler UART0_ERR_IRQHandler + def_irq_default_handler UART1_RX_TX_IRQHandler + def_irq_default_handler UART1_ERR_IRQHandler + def_irq_default_handler UART2_RX_TX_IRQHandler + def_irq_default_handler UART2_ERR_IRQHandler + def_irq_default_handler Reserved67_IRQHandler + def_irq_default_handler Reserved68_IRQHandler + def_irq_default_handler Reserved69_IRQHandler + def_irq_default_handler Reserved70_IRQHandler + def_irq_default_handler Reserved71_IRQHandler + def_irq_default_handler Reserved72_IRQHandler + def_irq_default_handler ADC0_IRQHandler + def_irq_default_handler ADC1_IRQHandler + def_irq_default_handler CMP0_IRQHandler + def_irq_default_handler CMP1_IRQHandler + def_irq_default_handler CMP2_IRQHandler + def_irq_default_handler FTM0_IRQHandler + def_irq_default_handler FTM1_IRQHandler + def_irq_default_handler FTM2_IRQHandler + def_irq_default_handler CMT_IRQHandler + def_irq_default_handler RTC_IRQHandler + def_irq_default_handler RTC_Seconds_IRQHandler + def_irq_default_handler PIT0_IRQHandler + def_irq_default_handler PIT1_IRQHandler + def_irq_default_handler PIT2_IRQHandler + def_irq_default_handler PIT3_IRQHandler + def_irq_default_handler PDB0_IRQHandler + def_irq_default_handler USB0_IRQHandler + def_irq_default_handler USBDCD_IRQHandler + def_irq_default_handler Reserved91_IRQHandler + def_irq_default_handler Reserved92_IRQHandler + def_irq_default_handler Reserved93_IRQHandler + def_irq_default_handler Reserved94_IRQHandler + def_irq_default_handler Reserved95_IRQHandler + def_irq_default_handler Reserved96_IRQHandler + def_irq_default_handler DAC0_IRQHandler + def_irq_default_handler Reserved98_IRQHandler + def_irq_default_handler TSI0_IRQHandler + def_irq_default_handler MCG_IRQHandler + def_irq_default_handler LPTimer_IRQHandler + def_irq_default_handler Reserved102_IRQHandler + def_irq_default_handler PORTA_IRQHandler + def_irq_default_handler PORTB_IRQHandler + def_irq_default_handler PORTC_IRQHandler + def_irq_default_handler PORTD_IRQHandler + def_irq_default_handler PORTE_IRQHandler + def_irq_default_handler Reserved108_IRQHandler + def_irq_default_handler Reserved109_IRQHandler + def_irq_default_handler SWI_IRQHandler + def_irq_default_handler DefaultISR + +/* Flash protection region, placed at 0x400 */ + .text + .thumb + .align 2 + .section .kinetis_flash_config_field,"a",%progbits +kinetis_flash_config: + .long 0xffffffff + .long 0xffffffff + .long 0xffffffff + .long 0xfffffffe + + .end
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2015 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC11U24 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "MK20DX256.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2012 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF8000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; i<NVIC_NUM_VECTORS; i++) { + vectors[i] = old_vectors[i]; + } + SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + 16] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + 16]; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 + 95) // CORE + MCU Peripherals +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,330 @@ +/* +** ################################################################### +** Compilers: ARM Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** +** +** Version: rev. 1.0, 2011-12-15 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2011-12-15) +** Initial version +** +** ################################################################### +*/ + +/** + * @file MK20DX256 + * @version 1.0 + * @date 2011-12-15 + * @brief Device specific configuration file for MK20DX256 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include <stdint.h> +#include "MK20DX256.h" + +#define DISABLE_WDOG 1 + +#define CLOCK_SETUP 3 +/* Predefined clock setups + 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode + Reference clock source for MCG module is the slow internal clock source 32.768kHz + Core clock = 41.94MHz, BusClock = 41.94MHz + 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode + Reference clock source for MCG module is an external crystal 8MHz + Core clock = 48MHz, BusClock = 48MHz + 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode + Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication + Core clock = 8MHz, BusClock = 8MHz + 3 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode + Reference clock source for MCG module is an external crystal 16MHz + Core clock = 72MHz, BusClock = 48MHz + This is the Teensy3.1 72Mhz set up +*/ + +/*---------------------------------------------------------------------------- + Define clock source values + *----------------------------------------------------------------------------*/ +#if (CLOCK_SETUP == 0) + #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */ +#elif (CLOCK_SETUP == 1) + #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#elif (CLOCK_SETUP == 2) + #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */ +#elif (CLOCK_SETUP == 3) + #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */ +#endif /* (CLOCK_SETUP == 2) */ + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { +#if (DISABLE_WDOG) + /* Disable the WDOG module */ + /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */ + WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */ + /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */ + WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */ + /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ + WDOG->STCTRLH = (uint16_t)0x01D2u; +#endif /* (DISABLE_WDOG) */ +#if (CLOCK_SETUP == 0) + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* Switch to FEI Mode */ + /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x06u; + /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x00u; + /* MCG_C4: DMX32=0,DRST_DRS=1 */ + MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u); + /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ + MCG->C5 = (uint8_t)0x00u; + /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x00u; + while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */ + } + while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */ + } +#elif (CLOCK_SETUP == 1) + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* Switch to FBE Mode */ + /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + OSC0->CR = (uint8_t)0x00u; + /* MCG->C7: OSCSEL=0 */ + MCG->C7 = (uint8_t)0x00u; + /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x24u; + /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x9Au; + /* MCG->C4: DMX32=0,DRST_DRS=0 */ + MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; + /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = (uint8_t)0x03u; + /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x00u; + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ + } +#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ + while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ + } +#endif + while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ + } + /* Switch to PBE Mode */ + /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = (uint8_t)0x03u; + /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x40u; + while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */ + } + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ + } + /* Switch to PEE Mode */ + /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x1Au; + while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */ + } + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ + } +#elif (CLOCK_SETUP == 2) + /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* Switch to FBE Mode */ + /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + OSC0->CR = (uint8_t)0x00u; + /* MCG->C7: OSCSEL=0 */ + MCG->C7 = (uint8_t)0x00u; + /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x24u; + /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x9Au; + /* MCG->C4: DMX32=0,DRST_DRS=0 */ + MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; + /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ + MCG->C5 = (uint8_t)0x00u; + /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x00u; + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ + } +#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ + while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ + } +#endif + while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ + } + /* Switch to BLPE Mode */ + /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x24u; + +#elif (CLOCK_SETUP == 3) + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* Switch to FBE Mode */ + /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + OSC0->CR = (uint8_t)0x0Au; // this is required if there are no external capacitors fitted to the Xtal + /* MCG->C7: OSCSEL=0 */ + MCG->C7 = (uint8_t)0x00u; + /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x24u; + /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x9Au; + /* MCG->C4: DMX32=0,DRST_DRS=0 */ + MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; + /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = (uint8_t)0x07u; + /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x00u; + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ + } +#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ + while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ + } +#endif + while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ + } + /* Switch to PBE Mode */ + /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = (uint8_t)0x05u; + /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x43u; + while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */ + } + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ + } + /* Switch to PEE Mode */ + /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x22u; + while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */ + } + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ + } + +#endif /* (CLOCK_SETUP == 3) */ +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ + uint8_t Divider; + + if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { + /* Output of FLL or PLL is selected */ + if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { + /* FLL is selected */ + if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { + /* External reference clock is selected */ + if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ + if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { + MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */ + } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */ + } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ + } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ + /* Select correct multiplier to calculate the MCG output clock */ + switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { + case 0x0u: + MCGOUTClock *= 640u; + break; + case 0x20u: + MCGOUTClock *= 1280u; + break; + case 0x40u: + MCGOUTClock *= 1920u; + break; + case 0x60u: + MCGOUTClock *= 2560u; + break; + case 0x80u: + MCGOUTClock *= 732u; + break; + case 0xA0u: + MCGOUTClock *= 1464u; + break; + case 0xC0u: + MCGOUTClock *= 2197u; + break; + case 0xE0u: + MCGOUTClock *= 2929u; + break; + default: + break; + } + } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ + /* PLL is selected */ + Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); + MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ + Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); + MCGOUTClock *= Divider; /* Calculate the MCG output clock */ + } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { + /* Internal reference clock is selected */ + if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ + } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ + MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ + } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { + /* External reference clock is selected */ + if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ + /* Reserved value */ + return; + } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ + SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,85 @@ +/* +** ################################################################### +** Compilers: ARM Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** +** +** Version: rev. 2.0, 2012-03-19 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2011-12-15) +** Initial version +** - rev. 2.0 (2012-03-19) +** PDB Peripheral register structure updated. +** DMA Registers and bits for unsupported DMA channels removed. +** +** ################################################################### +*/ + +/** + * @file MK20DX256 + * @version 2.0 + * @date 2012-03-19 + * @brief Device specific configuration file for MK20DX256 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef SYSTEM_MK20DX256_H_ +#define SYSTEM_MK20DX256_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* #if !defined(SYSTEM_MK20DX256_H_) */
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/PeripheralNames.h Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,78 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)UART0_BASE, - UART_1 = (int)UART1_BASE, - UART_2 = (int)UART2_BASE -} UARTName; -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -typedef enum { - I2C_0 = (int)I2C0_BASE, -} I2CName; - -#define TPM_SHIFT 8 -typedef enum { - PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 - PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 - PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 - PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 - PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 - PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 - PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 - PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 - PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 - PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 -} PWMName; - -typedef enum { - ADC0_SE4b = 4, - ADC0_SE5b = 5, - ADC0_SE6b = 6, - ADC0_SE7b = 7, - ADC0_SE8 = 8, - ADC0_SE9 = 9, - ADC0_SE12 = 12, - ADC0_SE13 = 13, - ADC0_SE14 = 14, - ADC0_SE15 = 15 -} ADCName; - -typedef enum { - DAC_0 = 0 -} DACName; - - -typedef enum { - SPI_0 = (int)SPI0_BASE, -} SPIName; - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/PinNames.h Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,256 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -/* PCR - 0x1000 */ -#define PORT_SHIFT 12 - -typedef enum { - PTA0 = 0x0, - PTA1 = 0x4, - PTA2 = 0x8, - PTA3 = 0xc, - PTA4 = 0x10, - PTA5 = 0x14, - PTA6 = 0x18, - PTA7 = 0x1c, - PTA8 = 0x20, - PTA9 = 0x24, - PTA10 = 0x28, - PTA11 = 0x2c, - PTA12 = 0x30, - PTA13 = 0x34, - PTA14 = 0x38, - PTA15 = 0x3c, - PTA16 = 0x40, - PTA17 = 0x44, - PTA18 = 0x48, - PTA19 = 0x4c, - PTA20 = 0x50, - PTA21 = 0x54, - PTA22 = 0x58, - PTA23 = 0x5c, - PTA24 = 0x60, - PTA25 = 0x64, - PTA26 = 0x68, - PTA27 = 0x6c, - PTA28 = 0x70, - PTA29 = 0x74, - PTA30 = 0x78, - PTA31 = 0x7c, - PTB0 = 0x1000, - PTB1 = 0x1004, - PTB2 = 0x1008, - PTB3 = 0x100c, - PTB4 = 0x1010, - PTB5 = 0x1014, - PTB6 = 0x1018, - PTB7 = 0x101c, - PTB8 = 0x1020, - PTB9 = 0x1024, - PTB10 = 0x1028, - PTB11 = 0x102c, - PTB12 = 0x1030, - PTB13 = 0x1034, - PTB14 = 0x1038, - PTB15 = 0x103c, - PTB16 = 0x1040, - PTB17 = 0x1044, - PTB18 = 0x1048, - PTB19 = 0x104c, - PTB20 = 0x1050, - PTB21 = 0x1054, - PTB22 = 0x1058, - PTB23 = 0x105c, - PTB24 = 0x1060, - PTB25 = 0x1064, - PTB26 = 0x1068, - PTB27 = 0x106c, - PTB28 = 0x1070, - PTB29 = 0x1074, - PTB30 = 0x1078, - PTB31 = 0x107c, - PTC0 = 0x2000, - PTC1 = 0x2004, - PTC2 = 0x2008, - PTC3 = 0x200c, - PTC4 = 0x2010, - PTC5 = 0x2014, - PTC6 = 0x2018, - PTC7 = 0x201c, - PTC8 = 0x2020, - PTC9 = 0x2024, - PTC10 = 0x2028, - PTC11 = 0x202c, - PTC12 = 0x2030, - PTC13 = 0x2034, - PTC14 = 0x2038, - PTC15 = 0x203c, - PTC16 = 0x2040, - PTC17 = 0x2044, - PTC18 = 0x2048, - PTC19 = 0x204c, - PTC20 = 0x2050, - PTC21 = 0x2054, - PTC22 = 0x2058, - PTC23 = 0x205c, - PTC24 = 0x2060, - PTC25 = 0x2064, - PTC26 = 0x2068, - PTC27 = 0x206c, - PTC28 = 0x2070, - PTC29 = 0x2074, - PTC30 = 0x2078, - PTC31 = 0x207c, - PTD0 = 0x3000, - PTD1 = 0x3004, - PTD2 = 0x3008, - PTD3 = 0x300c, - PTD4 = 0x3010, - PTD5 = 0x3014, - PTD6 = 0x3018, - PTD7 = 0x301c, - PTD8 = 0x3020, - PTD9 = 0x3024, - PTD10 = 0x3028, - PTD11 = 0x302c, - PTD12 = 0x3030, - PTD13 = 0x3034, - PTD14 = 0x3038, - PTD15 = 0x303c, - PTD16 = 0x3040, - PTD17 = 0x3044, - PTD18 = 0x3048, - PTD19 = 0x304c, - PTD20 = 0x3050, - PTD21 = 0x3054, - PTD22 = 0x3058, - PTD23 = 0x305c, - PTD24 = 0x3060, - PTD25 = 0x3064, - PTD26 = 0x3068, - PTD27 = 0x306c, - PTD28 = 0x3070, - PTD29 = 0x3074, - PTD30 = 0x3078, - PTD31 = 0x307c, - PTE0 = 0x4000, - PTE1 = 0x4004, - PTE2 = 0x4008, - PTE3 = 0x400c, - PTE4 = 0x4010, - PTE5 = 0x4014, - PTE6 = 0x4018, - PTE7 = 0x401c, - PTE8 = 0x4020, - PTE9 = 0x4024, - PTE10 = 0x4028, - PTE11 = 0x402c, - PTE12 = 0x4030, - PTE13 = 0x4034, - PTE14 = 0x4038, - PTE15 = 0x403c, - PTE16 = 0x4040, - PTE17 = 0x4044, - PTE18 = 0x4048, - PTE19 = 0x404c, - PTE20 = 0x4050, - PTE21 = 0x4054, - PTE22 = 0x4058, - PTE23 = 0x405c, - PTE24 = 0x4060, - PTE25 = 0x4064, - PTE26 = 0x4068, - PTE27 = 0x406c, - PTE28 = 0x4070, - PTE29 = 0x4074, - PTE30 = 0x4078, - PTE31 = 0x407c, - - LED_RED = PTC3, - LED_GREEN = PTD4, - LED_BLUE = PTA2, - - // mbed original LED naming - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_BLUE, - LED4 = LED_BLUE, - - // USB Pins - USBTX = PTB17, - USBRX = PTB16, - - // Arduino Headers - D0 = PTE1, - D1 = PTE0, - D2 = PTA5, - D3 = PTD4, - D4 = PTC8, - D5 = PTA1, - D6 = PTC3, - D7 = PTC4, - D8 = PTA12, - D9 = PTA2, - D10 = PTC2, - D11 = PTD2, - D12 = PTD3, - D13 = PTD1, - D14 = PTB3, - D15 = PTB2, - - A0 = PTC0, - A1 = PTC1, - A2 = PTD6, - A3 = PTD5, - A4 = PTB1, - A5 = PTB0, - - I2C_SCL = D15, - I2C_SDA = D14, - - TSI_ELEC0 = PTB16, - TSI_ELEC1 = PTB17, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - - -typedef enum { - PullNone = 0, - PullDown = 2, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/PortNames.h Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,35 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB = 1, - PortC = 2, - PortD = 3, - PortE = 4 -} PortName; - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/analogin_api.c Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,93 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" - -#include "cmsis.h" -#include "pinmap.h" -#include "clk_freqs.h" - -#define MAX_FADC 6000000 - -static const PinMap PinMap_ADC[] = { - {PTC2, ADC0_SE4b, 0}, - {PTD1, ADC0_SE5b, 0}, - {PTD5, ADC0_SE6b, 0}, - {PTD6, ADC0_SE7b, 0}, - {PTB0, ADC0_SE8, 0}, - {PTB1, ADC0_SE9, 0}, - {PTB2, ADC0_SE12, 0}, - {PTB3, ADC0_SE13, 0}, - {PTC0, ADC0_SE14, 0}, - {PTC1, ADC0_SE15, 0}, - {NC, NC, 0} -}; - -void analogin_init(analogin_t *obj, PinName pin) { - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - SIM->SCGC6 |= SIM_SCGC6_ADC0_MASK; - - uint32_t port = (uint32_t)pin >> PORT_SHIFT; - SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port); - - // bus clk - uint32_t PCLK = bus_frequency(); - uint32_t clkdiv; - for (clkdiv = 0; clkdiv < 4; clkdiv++) { - if ((PCLK >> clkdiv) <= MAX_FADC) - break; - } - if (clkdiv == 4) //Set max div - clkdiv = 0x7; - - ADC0->SC1[1] = ADC_SC1_ADCH(obj->adc); - - ADC0->CFG1 = ADC_CFG1_ADLPC_MASK // Low-Power Configuration - | ADC_CFG1_ADIV(clkdiv & 0x3) // Clock Divide Select - | ADC_CFG1_ADLSMP_MASK // Long Sample Time - | ADC_CFG1_MODE(3) // (16)bits Resolution - | ADC_CFG1_ADICLK(clkdiv >> 2); // Input Clock - - ADC0->CFG2 = ADC_CFG2_MUXSEL_MASK // ADxxb or ADxxa channels - | ADC_CFG2_ADACKEN_MASK // Asynchronous Clock Output Enable - | ADC_CFG2_ADHSC_MASK // High-Speed Configuration - | ADC_CFG2_ADLSTS(0); // Long Sample Time Select - - ADC0->SC2 = ADC_SC2_REFSEL(0); // Default Voltage Reference - - ADC0->SC3 = ADC_SC3_AVGE_MASK // Hardware Average Enable - | ADC_SC3_AVGS(0); // 4 Samples Averaged - - pinmap_pinout(pin, PinMap_ADC); -} - -uint16_t analogin_read_u16(analogin_t *obj) { - // start conversion - ADC0->SC1[0] = ADC_SC1_ADCH(obj->adc); - - // Wait Conversion Complete - while ((ADC0->SC1[0] & ADC_SC1_COCO_MASK) != ADC_SC1_COCO_MASK); - - return (uint16_t)ADC0->R[0]; -} - -float analogin_read(analogin_t *obj) { - uint16_t value = analogin_read_u16(obj); - return (float)value * (1.0f / (float)0xFFFF); -} -
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/clk_freqs.h Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,115 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef CLK_FREQS_H -#define CLK_FREQS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * \brief Get the peripheral bus clock frequency - * \return Bus frequency - */ -static inline uint32_t bus_frequency(void) { - return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) + 1); -} - -/*! - * \brief Get external oscillator (crystal) frequency - * \return External osc frequency - */ -static uint32_t extosc_frequency(void) { - uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)); - - if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock - return MCGClock; - - if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected - uint32_t divider, multiplier; - if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected - if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference - divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); - if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) - divider <<= 5u; - /* Select correct multiplier to calculate the MCG output clock */ - switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { - case 0x0u: - multiplier = 640u; - break; - case 0x20u: - multiplier = 1280u; - break; - case 0x40u: - multiplier = 1920u; - break; - case 0x60u: - multiplier = 2560u; - break; - case 0x80u: - multiplier = 732u; - break; - case 0xA0u: - multiplier = 1464u; - break; - case 0xC0u: - multiplier = 2197u; - break; - case 0xE0u: - default: - multiplier = 2929u; - break; - } - - return MCGClock * divider / multiplier; - } - } else { //PLL is selected - divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); - multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); - return MCGClock * divider / multiplier; - } - } - - //In all other cases either there is no crystal or we cannot determine it - //For example when the FLL is running on the internal reference, and there is also an - //external crystal. However these are unlikely situations - return 0; -} - -//Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit -static uint32_t mcgpllfll_frequency(void) { - if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected - return 0; - - uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)); - if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected - SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output - return MCGClock; - } else { //PLL is selected - SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output - return MCGClock; - } - - //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active - //for the peripherals, this is however an unlikely setup -} - - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/device.h Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,58 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 0 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 1 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 1 -#define DEVICE_LOCALFILESYSTEM 0 -#define DEVICE_ID_LENGTH 24 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_RED 1 - -#include "objects.h" - -#endif
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_api.c Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,56 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" - -uint32_t gpio_set(PinName pin) { - MBED_ASSERT(pin != (PinName)NC); - pin_function(pin, 1); - return 1 << ((pin & 0x7F) >> 2); -} - -void gpio_init(gpio_t *obj, PinName pin) { - obj->pin = pin; - if (pin == (PinName)NC) - return; - - obj->mask = gpio_set(pin); - - unsigned int port = (unsigned int)pin >> PORT_SHIFT; - - GPIO_Type *reg = (GPIO_Type *)(PTA_BASE + port * 0x40); - obj->reg_set = ®->PSOR; - obj->reg_clr = ®->PCOR; - obj->reg_in = ®->PDIR; - obj->reg_dir = ®->PDDR; -} - -void gpio_mode(gpio_t *obj, PinMode mode) { - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) { - MBED_ASSERT(obj->pin != (PinName)NC); - switch (direction) { - case PIN_INPUT : - *obj->reg_dir &= ~obj->mask; - break; - case PIN_OUTPUT: - *obj->reg_dir |= obj->mask; - break; - } -}
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_irq_api.c Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,225 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include <stddef.h> -#include "cmsis.h" - -#include "gpio_irq_api.h" -#include "mbed_error.h" - -#define CHANNEL_NUM 160 - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler irq_handler; - -#define IRQ_DISABLED (0) -#define IRQ_RAISING_EDGE PORT_PCR_IRQC(9) -#define IRQ_FALLING_EDGE PORT_PCR_IRQC(10) -#define IRQ_EITHER_EDGE PORT_PCR_IRQC(11) - -static void handle_interrupt_in(PORT_Type *port, int ch_base) { - uint32_t isfr; - uint32_t pin; - - while ((isfr = port->ISFR) != 0) { - pin = 31 - __CLZ(isfr); - uint32_t id = channel_ids[ch_base + pin]; - if (id == 0) { - continue; - } - - GPIO_Type *gpio = PTA; - gpio_irq_event event = IRQ_NONE; - uint32_t port_num = (port - PORTA) >> 12; - - switch (port->PCR[pin] & PORT_PCR_IRQC_MASK) { - case IRQ_RAISING_EDGE: - event = IRQ_RISE; - break; - case IRQ_FALLING_EDGE: - event = IRQ_FALL; - break; - case IRQ_EITHER_EDGE: - gpio += (port_num * 0x40); - event = (gpio->PDIR & (1 << pin)) ? (IRQ_RISE) : (IRQ_FALL); - break; - } - if (event != IRQ_NONE) { - irq_handler(id, event); - } - port->ISFR = 1 << pin; - } -} - -void gpio_irqA(void) { - handle_interrupt_in(PORTA, 0); -} - -void gpio_irqB(void) -{ - handle_interrupt_in(PORTB, 32); -} - -void gpio_irqC(void) -{ - handle_interrupt_in(PORTC, 64); -} - -void gpio_irqD(void) -{ - handle_interrupt_in(PORTD, 96); -} - -void gpio_irqE(void) -{ - handle_interrupt_in(PORTE, 128); -} - - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { - if (pin == NC) - return -1; - - irq_handler = handler; - - obj->port = pin >> PORT_SHIFT; - obj->pin = (pin & 0x7F) >> 2; - - uint32_t ch_base, vector; - IRQn_Type irq_n; - switch (obj->port) { - case PortA: - ch_base = 0; - irq_n = PORTA_IRQn; - vector = (uint32_t)gpio_irqA; - break; - case PortB: - ch_base = 32; - irq_n = PORTB_IRQn; - vector = (uint32_t)gpio_irqB; - break; - case PortC: - ch_base = 64; - irq_n = PORTC_IRQn; - vector = (uint32_t)gpio_irqC; - break; - case PortD: - ch_base = 96; - irq_n = PORTD_IRQn; vector = (uint32_t)gpio_irqD; - break; - case PortE: - ch_base = 128; - irq_n = PORTE_IRQn; - vector = (uint32_t)gpio_irqE; - break; - - default: - error("gpio_irq only supported on port A-E."); - break; - } - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - obj->ch = ch_base + obj->pin; - channel_ids[obj->ch] = id; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->ch] = 0; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { - PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port); - - uint32_t irq_settings = IRQ_DISABLED; - - switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) { - case IRQ_DISABLED: - if (enable) - irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE); - break; - - case IRQ_RAISING_EDGE: - if (enable) { - irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE); - } else { - if (event == IRQ_FALL) - irq_settings = IRQ_RAISING_EDGE; - } - break; - - case IRQ_FALLING_EDGE: - if (enable) { - irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE); - } else { - if (event == IRQ_RISE) - irq_settings = IRQ_FALLING_EDGE; - } - break; - - case IRQ_EITHER_EDGE: - if (enable) { - irq_settings = IRQ_EITHER_EDGE; - } else { - irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE); - } - break; - } - - // Interrupt configuration and clear interrupt - port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK; -} - -void gpio_irq_enable(gpio_irq_t *obj) { - switch (obj->port) { - case PortA: - NVIC_EnableIRQ(PORTA_IRQn); - break; - case PortB: - NVIC_EnableIRQ(PORTB_IRQn); - break; - case PortC: - NVIC_EnableIRQ(PORTC_IRQn); - break; - case PortD: - NVIC_EnableIRQ(PORTD_IRQn); - break; - case PortE: - NVIC_EnableIRQ(PORTE_IRQn); - break; - } -} - -void gpio_irq_disable(gpio_irq_t *obj) { - switch (obj->port) { - case PortA: - NVIC_DisableIRQ(PORTA_IRQn); - break; - case PortB: - NVIC_DisableIRQ(PORTB_IRQn); - break; - case PortC: - NVIC_DisableIRQ(PORTC_IRQn); - break; - case PortD: - NVIC_DisableIRQ(PORTD_IRQn); - break; - case PortE: - NVIC_DisableIRQ(PORTE_IRQn); - break; - } -}
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_object.h Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,53 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - - __IO uint32_t *reg_dir; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; - __I uint32_t *reg_in; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) { - *obj->reg_set = obj->mask; - } else { - *obj->reg_clr = obj->mask; - } -} - -static inline int gpio_read(gpio_t *obj) { - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/i2c_api.c Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,384 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#include "cmsis.h" -#include "pinmap.h" -#include "clk_freqs.h" - -static const PinMap PinMap_I2C_SDA[] = { - {PTB1, I2C_0, 2}, - {PTB3, I2C_0, 2}, - {NC , NC , 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {PTB0, I2C_0, 2}, - {PTB2, I2C_0, 2}, - {NC , NC, 0} -}; - -static const uint16_t ICR[0x40] = { - 20, 22, 24, 26, 28, - 30, 34, 40, 28, 32, - 36, 40, 44, 48, 56, - 68, 48, 56, 64, 72, - 80, 88, 104, 128, 80, - 96, 112, 128, 144, 160, - 192, 240, 160, 192, 224, - 256, 288, 320, 384, 480, - 320, 384, 448, 512, 576, - 640, 768, 960, 640, 768, - 896, 1024, 1152, 1280, 1536, - 1920, 1280, 1536, 1792, 2048, - 2304, 2560, 3072, 3840 -}; - - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) { - // determine the I2C to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - obj->i2c = (I2C_Type*)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)obj->i2c != NC); - - SIM->SCGC4 |= SIM_SCGC4_I2C0_MASK; - SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK; - - // set default frequency at 100k - i2c_frequency(obj, 100000); - - // enable I2C interface - obj->i2c->C1 |= 0x80; - - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - /* enable open drain for I2C pins, only port b available */ - uint32_t pin_n = (uint32_t)(sda & 0x7C) >> 2; - PORTB->PCR[pin_n] |= PORT_PCR_ODE_MASK; - pin_n = (uint32_t)(scl & 0x7C) >> 2; - PORTB->PCR[pin_n] |= PORT_PCR_ODE_MASK; -} - -int i2c_start(i2c_t *obj) { - // if we are in the middle of a transaction - // activate the repeat_start flag - if (obj->i2c->S & I2C_S_BUSY_MASK) { - obj->i2c->C1 |= 0x04; - } else { - obj->i2c->C1 |= I2C_C1_MST_MASK; - obj->i2c->C1 |= I2C_C1_TX_MASK; - } - return 0; -} - -int i2c_stop(i2c_t *obj) { - volatile uint32_t n = 0; - obj->i2c->C1 &= ~I2C_C1_MST_MASK; - obj->i2c->C1 &= ~I2C_C1_TX_MASK; - - // It seems that there are timing problems - // when there is no waiting time after a STOP. - // This wait is also included on the samples - // code provided with the freedom board - for (n = 0; n < 100; n++) - __NOP(); - return 0; -} - -static int timeout_status_poll(i2c_t *obj, uint32_t mask) { - uint32_t i, timeout = 100000; - - for (i = 0; i < timeout; i++) { - if (obj->i2c->S & mask) - return 0; - } - - return 1; -} - -// this function waits the end of a tx transfer and return the status of the transaction: -// 0: OK ack received -// 1: OK ack not received -// 2: failure -static int i2c_wait_end_tx_transfer(i2c_t *obj) { - - // wait for the interrupt flag - if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) { - return 2; - } - - obj->i2c->S |= I2C_S_IICIF_MASK; - - // wait transfer complete - if (timeout_status_poll(obj, I2C_S_TCF_MASK)) { - return 2; - } - - // check if we received the ACK or not - return obj->i2c->S & I2C_S_RXAK_MASK ? 1 : 0; -} - -// this function waits the end of a rx transfer and return the status of the transaction: -// 0: OK -// 1: failure -static int i2c_wait_end_rx_transfer(i2c_t *obj) { - // wait for the end of the rx transfer - if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) { - return 1; - } - - obj->i2c->S |= I2C_S_IICIF_MASK; - - return 0; -} - -static void i2c_send_nack(i2c_t *obj) { - obj->i2c->C1 |= I2C_C1_TXAK_MASK; // NACK -} - -static void i2c_send_ack(i2c_t *obj) { - obj->i2c->C1 &= ~I2C_C1_TXAK_MASK; // ACK -} - -static int i2c_do_write(i2c_t *obj, int value) { - // write the data - obj->i2c->D = value; - - // init and wait the end of the transfer - return i2c_wait_end_tx_transfer(obj); -} - -static int i2c_do_read(i2c_t *obj, char * data, int last) { - if (last) { - i2c_send_nack(obj); - } else { - i2c_send_ack(obj); - } - - *data = (obj->i2c->D & 0xFF); - - // start rx transfer and wait the end of the transfer - return i2c_wait_end_rx_transfer(obj); -} - -void i2c_frequency(i2c_t *obj, int hz) { - uint8_t icr = 0; - uint8_t mult = 0; - uint32_t error = 0; - uint32_t p_error = 0xffffffff; - uint32_t ref = 0; - uint8_t i, j; - // bus clk - uint32_t PCLK = bus_frequency(); - uint32_t pulse = PCLK / (hz * 2); - - // we look for the values that minimize the error - - // test all the MULT values - for (i = 1; i < 5; i*=2) { - for (j = 0; j < 0x40; j++) { - ref = PCLK / (i*ICR[j]); - if (ref > (uint32_t)hz) - continue; - error = hz - ref; - if (error < p_error) { - icr = j; - mult = i/2; - p_error = error; - } - } - } - pulse = icr | (mult << 6); - - // I2C Rate - obj->i2c->F = pulse; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { - int count; - char dummy_read, *ptr; - - if (i2c_start(obj)) { - i2c_stop(obj); - return I2C_ERROR_BUS_BUSY; - } - - if (i2c_do_write(obj, (address | 0x01))) { - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - - // set rx mode - obj->i2c->C1 &= ~I2C_C1_TX_MASK; - - // Read in bytes - for (count = 0; count < (length); count++) { - ptr = (count == 0) ? &dummy_read : &data[count - 1]; - uint8_t stop_ = (count == (length - 1)) ? 1 : 0; - if (i2c_do_read(obj, ptr, stop_)) { - i2c_stop(obj); - return count; - } - } - - // If not repeated start, send stop. - if (stop) - i2c_stop(obj); - - // last read - data[count-1] = obj->i2c->D; - - return length; -} -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { - int i; - - if (i2c_start(obj)) { - i2c_stop(obj); - return I2C_ERROR_BUS_BUSY; - } - - if (i2c_do_write(obj, (address & 0xFE))) { - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - - for (i = 0; i < length; i++) { - if(i2c_do_write(obj, data[i])) { - i2c_stop(obj); - return i; - } - } - - if (stop) - i2c_stop(obj); - - return length; -} - -void i2c_reset(i2c_t *obj) { - i2c_stop(obj); -} - -int i2c_byte_read(i2c_t *obj, int last) { - char data; - - // set rx mode - obj->i2c->C1 &= ~I2C_C1_TX_MASK; - - // Setup read - i2c_do_read(obj, &data, last); - - // set tx mode - obj->i2c->C1 |= I2C_C1_TX_MASK; - return obj->i2c->D; -} - -int i2c_byte_write(i2c_t *obj, int data) { - // set tx mode - obj->i2c->C1 |= I2C_C1_TX_MASK; - - return !i2c_do_write(obj, (data & 0xFF)); -} - - -#if DEVICE_I2CSLAVE -void i2c_slave_mode(i2c_t *obj, int enable_slave) { - if (enable_slave) { - // set slave mode - obj->i2c->C1 &= ~I2C_C1_MST_MASK; - obj->i2c->C1 |= I2C_C1_IICIE_MASK; - } else { - // set master mode - obj->i2c->C1 |= I2C_C1_MST_MASK; - } -} - -int i2c_slave_receive(i2c_t *obj) { - switch(obj->i2c->S) { - // read addressed - case 0xE6: - return 1; - // write addressed - case 0xE2: - return 3; - default: - return 0; - } -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) { - uint8_t dummy_read; - uint8_t * ptr; - int count; - - // set rx mode - obj->i2c->C1 &= ~I2C_C1_TX_MASK; - - // first dummy read - dummy_read = obj->i2c->D; - if (i2c_wait_end_rx_transfer(obj)) - return 0; - - // read address - dummy_read = obj->i2c->D; - if (i2c_wait_end_rx_transfer(obj)) - return 0; - - // read (length - 1) bytes - for (count = 0; count < (length - 1); count++) { - data[count] = obj->i2c->D; - if (i2c_wait_end_rx_transfer(obj)) - return count; - } - - // read last byte - ptr = (length == 0) ? &dummy_read : (uint8_t *)&data[count]; - *ptr = obj->i2c->D; - - return (length) ? (count + 1) : 0; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) { - int i, count = 0; - - // set tx mode - obj->i2c->C1 |= I2C_C1_TX_MASK; - - for (i = 0; i < length; i++) { - if (i2c_do_write(obj, data[count++]) == 2) - return i; - } - - // set rx mode - obj->i2c->C1 &= ~I2C_C1_TX_MASK; - - // dummy rx transfer needed - // otherwise the master cannot generate a stop bit - obj->i2c->D; - if (i2c_wait_end_rx_transfer(obj) == 2) - return count; - - return count; -} - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { - obj->i2c->A1 = address & 0xfe; -} -#endif -
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/objects.h Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,71 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - uint32_t port; - uint32_t pin; - uint32_t ch; -}; - -struct port_s { - __IO uint32_t *reg_dir; - __IO uint32_t *reg_out; - __I uint32_t *reg_in; - PortName port; - uint32_t mask; -}; - -struct pwmout_s { - __IO uint32_t *MOD; - __IO uint32_t *CNT; - __IO uint32_t *CnV; -}; - -struct serial_s { - UART_Type *uart; - int index; -}; - -struct analogin_s { - ADCName adc; -}; - -struct i2c_s { - I2C_Type *i2c; -}; - -struct spi_s { - SPI_Type *spi; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/pinmap.c Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,38 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" - -void pin_function(PinName pin, int function) { - MBED_ASSERT(pin != (PinName)NC); - - uint32_t port_n = (uint32_t)pin >> PORT_SHIFT; - uint32_t pin_n = (uint32_t)(pin & 0x7C) >> 2; - - SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port_n); - __IO uint32_t* pin_pcr = &(((PORT_Type *)(PORTA_BASE + 0x1000 * port_n)))->PCR[pin_n]; - - // pin mux bits: [10:8] -> 11100000000 = (0x700) - *pin_pcr = (*pin_pcr & ~0x700) | (function << 8); -} - -void pin_mode(PinName pin, PinMode mode) { - MBED_ASSERT(pin != (PinName)NC); - __IO uint32_t* pin_pcr = (__IO uint32_t*)(PORTA_BASE + pin); - - // pin pullup bits: [1:0] -> 11 = (0x3) - *pin_pcr = (*pin_pcr & ~0x3) | mode; -}
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/port_api.c Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,72 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" - -PinName port_pin(PortName port, int pin_n) { - return (PinName)((port << PORT_SHIFT) | (pin_n << 2)); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { - obj->port = port; - obj->mask = mask; - - GPIO_Type *reg = (GPIO_Type *)(PTA_BASE + port * 0x40); - - obj->reg_out = ®->PDOR; - obj->reg_in = ®->PDIR; - obj->reg_dir = ®->PDDR; - - uint32_t i; - // The function is set per pin: reuse gpio logic - for (i=0; i<32; i++) { - if (obj->mask & (1<<i)) { - gpio_set(port_pin(obj->port, i)); - } - } - - port_dir(obj, dir); -} - -void port_mode(port_t *obj, PinMode mode) { - uint32_t i; - // The mode is set per pin: reuse pinmap logic - for (i=0; i<32; i++) { - if (obj->mask & (1<<i)) { - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) { - switch (dir) { - case PIN_INPUT : - *obj->reg_dir &= ~obj->mask; - break; - case PIN_OUTPUT: - *obj->reg_dir |= obj->mask; - break; - } -} - -void port_write(port_t *obj, int value) { - *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) { - return (*obj->reg_in & obj->mask); -}
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/pwmout_api.c Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,135 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pwmout_api.h" - -#include "cmsis.h" -#include "pinmap.h" - -static const PinMap PinMap_PWM[] = { - // LEDs - {LED_RED , PWM_3 , 4}, // PTC3, FTM0 CH2 - {LED_GREEN, PWM_5, 4}, // PTD4, FTM0 CH4 - {LED_BLUE , PWM_8 , 3}, // PTA2, FTM0 CH7 - - // Arduino digital pinout - {D3, PWM_5 , 4}, // PTD4, FTM0 CH4 - {D5, PWM_7 , 3}, // PTA1, FTM0 CH6 - {D6, PWM_3 , 4}, // PTC3, FTM0 CH2 - {D9, PWM_6 , 4}, // PTD5, FTM0 CH6 - {D10, PWM_2 , 4}, // PTC2, FTM0 CH1 - - {PTA0, PWM_6 , 3}, // PTA0, FTM0 CH5 - {PTA3, PWM_1 , 3}, // PTA3, FTM0 CH0 - {PTA4, PWM_2 , 3}, // PTA4, FTM0 CH1 - {PTA5, PWM_3 , 3}, // PTA5, FTM0 CH2 - {PTA12, PWM_9 , 3}, // PTA12, FTM1 CH0 - {PTA13, PWM_10, 3}, // PTA13, FTM1 CH1 - {PTB0, PWM_9 , 3}, // PTB0, FTM1 CH0 - {PTB1, PWM_10, 3}, // PTB1, FTM1 CH1 - {PTC1, PWM_1 , 4}, // PTC1, FTM0 CH0 - {PTD4, PWM_4 , 4}, // PTD4, FTM0 CH3 - {PTD6, PWM_7 , 4}, // PTD6, FTM0 CH6 - {PTD7, PWM_8 , 4}, // PTD7, FTM0 CH7 - - {NC , NC , 0} -}; - -static float pwm_clock = 0; - -void pwmout_init(pwmout_t* obj, PinName pin) { - // determine the channel - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - MBED_ASSERT(pwm != (PWMName)NC); - - uint32_t clkdiv = 0; - float clkval = SystemCoreClock / 1000000.0f; - - while (clkval > 1) { - clkdiv++; - clkval /= 2.0; - if (clkdiv == 7) - break; - } - - pwm_clock = clkval; - unsigned int port = (unsigned int)pin >> PORT_SHIFT; - unsigned int ftm_n = (pwm >> TPM_SHIFT); - unsigned int ch_n = (pwm & 0xFF); - - SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port); - SIM->SCGC6 |= 1 << (SIM_SCGC6_FTM0_SHIFT + ftm_n); - - FTM_Type *ftm = (FTM_Type *)(FTM0_BASE + 0x1000 * ftm_n); - ftm->CONF |= FTM_CONF_BDMMODE(3); - ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(clkdiv); // (clock)MHz / clkdiv ~= (0.75)MHz - ftm->CONTROLS[ch_n].CnSC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK); /* No Interrupts; High True pulses on Edge Aligned PWM */ - - obj->CnV = &ftm->CONTROLS[ch_n].CnV; - obj->MOD = &ftm->MOD; - obj->CNT = &ftm->CNT; - - // default to 20ms: standard for servos, and fine for e.g. brightness control - pwmout_period_ms(obj, 20); - pwmout_write(obj, 0); - - // Wire pinout - pinmap_pinout(pin, PinMap_PWM); -} - -void pwmout_free(pwmout_t* obj) {} - -void pwmout_write(pwmout_t* obj, float value) { - if (value < 0.0) { - value = 0.0; - } else if (value > 1.0) { - value = 1.0; - } - - *obj->CnV = (uint32_t)((float)(*obj->MOD + 1) * value); -} - -float pwmout_read(pwmout_t* obj) { - float v = (float)(*obj->CnV) / (float)(*obj->MOD + 1); - return (v > 1.0) ? (1.0) : (v); -} - -void pwmout_period(pwmout_t* obj, float seconds) { - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) { - pwmout_period_us(obj, ms * 1000); -} - -// Set the PWM period, keeping the duty cycle the same. -void pwmout_period_us(pwmout_t* obj, int us) { - float dc = pwmout_read(obj); - *obj->MOD = (uint32_t)(pwm_clock * (float)us) - 1; - pwmout_write(obj, dc); -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) { - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) { - *obj->CnV = (uint32_t)(pwm_clock * (float)us); -}
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/rtc_api.c Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,85 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "rtc_api.h" - -static void init(void) { - // enable PORTC clock - SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK; - - // enable RTC clock - SIM->SCGC6 |= SIM_SCGC6_RTC_MASK; - - // OSC32 as source - SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK; - SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0); -} - -void rtc_init(void) { - init(); - - // Enable the oscillator - RTC->CR |= RTC_CR_OSCE_MASK; - - //Configure the TSR. default value: 1 - RTC->TSR = 1; - - // enable counter - RTC->SR |= RTC_SR_TCE_MASK; -} - -void rtc_free(void) { - // [TODO] -} - -/* - * Little check routine to see if the RTC has been enabled - * 0 = Disabled, 1 = Enabled - */ -int rtc_isenabled(void) { - // even if the RTC module is enabled, - // as we use RTC_CLKIN and an external clock, - // we need to reconfigure the pins. That is why we - // call init() if the rtc is enabled - - // if RTC not enabled return 0 - SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK; - SIM->SCGC6 |= SIM_SCGC6_RTC_MASK; - if ((RTC->SR & RTC_SR_TCE_MASK) == 0) - return 0; - - init(); - return 1; -} - -time_t rtc_read(void) { - return RTC->TSR; -} - -void rtc_write(time_t t) { - // disable counter - RTC->SR &= ~RTC_SR_TCE_MASK; - - // we do not write 0 into TSR - // to avoid invalid time - if (t == 0) - t = 1; - - // write seconds - RTC->TSR = t; - - // re-enable counter - RTC->SR |= RTC_SR_TCE_MASK; -}
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/serial_api.c Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,319 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "serial_api.h" - -#include <string.h> - -#include "cmsis.h" -#include "pinmap.h" -#include "clk_freqs.h" - -static const PinMap PinMap_UART_TX[] = { - {PTB17, UART_0, 3}, - {PTC4 , UART_1, 3}, - {PTD3 , UART_2, 3}, - {PTD7 , UART_0, 3}, - {PTE0 , UART_1, 3}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PTB16, UART_0, 3}, - {PTC3 , UART_1, 3}, - {PTD2 , UART_2, 3}, - {PTD6 , UART_0, 3}, - {PTE1 , UART_1, 3}, - {NC , NC , 0} -}; - -#define UART_NUM 3 - -static uint32_t serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) { - // determine the UART to use - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)uart != NC); - - obj->uart = (UART_Type *)uart; - // enable clk - switch (uart) { - case UART_0: - mcgpllfll_frequency(); - SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; - break; - case UART_1: - mcgpllfll_frequency(); - SIM->SCGC4 |= SIM_SCGC4_UART1_MASK; - break; - case UART_2: - SIM->SCGC4 |= SIM_SCGC4_UART2_MASK; - break; - } - // Disable UART before changing registers - obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK); - - switch (uart) { - case UART_0: - obj->index = 0; - break; - case UART_1: - obj->index = 1; - break; - case UART_2: - obj->index = 2; - break; - } - - // set default baud rate and format - serial_baud (obj, 9600); - serial_format(obj, 8, ParityNone, 1); - - // pinout the chosen uart - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - // set rx/tx pins in PullUp mode - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - obj->uart->C2 |= (UART_C2_RE_MASK | UART_C2_TE_MASK); - - if (uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) { - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) { - // save C2 state - uint8_t c2_state = (obj->uart->C2 & (UART_C2_RE_MASK | UART_C2_TE_MASK)); - - // Disable UART before changing registers - obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK); - - uint32_t PCLK; - if (obj->uart != UART2) { - PCLK = mcgpllfll_frequency(); - } - else { - PCLK = bus_frequency(); - } - - uint16_t DL = PCLK / (16 * baudrate); - uint32_t BRFA = (2 * PCLK) / baudrate - 32 * DL; - - // set BDH and BDL - obj->uart->BDH = (obj->uart->BDH & ~(0x1f)) | ((DL >> 8) & 0x1f); - obj->uart->BDL = (obj->uart->BDL & ~(0xff)) | ((DL >> 0) & 0xff); - - obj->uart->C4 &= ~0x1F; - obj->uart->C4 |= BRFA & 0x1F; - - // restore C2 state - obj->uart->C2 |= c2_state; -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); - MBED_ASSERT((data_bits == 8) || (data_bits == 9)); - - // save C2 state - uint32_t c2_state = (obj->uart->C2 & (UART_C2_RE_MASK | UART_C2_TE_MASK)); - - // Disable UART before changing registers - obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK); - - // 8 data bits = 0 ... 9 data bits = 1 - data_bits -= 8; - - uint32_t parity_enable, parity_select; - switch (parity) { - case ParityNone: - parity_enable = 0; - parity_select = 0; - break; - case ParityOdd : - parity_enable = 1; - parity_select = 1; - data_bits++; - break; - case ParityEven: - parity_enable = 1; - parity_select = 0; - data_bits++; - break; - default: - break; - } - - stop_bits -= 1; - - uint32_t m10 = 0; - - // 9 data bits + parity - only uart0 support - if (data_bits == 2) { - MBED_ASSERT(obj->index == 0); - data_bits = 0; - m10 = 1; - } - - // data bits, parity and parity mode - obj->uart->C1 = ((data_bits << 4) - | (parity_enable << 1) - | (parity_select << 0)); - - //enable 10bit mode if needed - if (obj->index == 0) { - obj->uart->C4 &= ~UART_C4_M10_MASK; - obj->uart->C4 |= (m10 << UART_C4_M10_SHIFT); - } - - // stop bits - obj->uart->BDH &= ~UART_BDH_SBR_MASK; - obj->uart->BDH |= (stop_bits << UART_BDH_SBR_SHIFT); - - // restore C2 state - obj->uart->C2 |= c2_state; -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -static inline void uart_irq(uint8_t status, uint32_t index) { - if (serial_irq_ids[index] != 0) { - if (status & UART_S1_TDRE_MASK) - irq_handler(serial_irq_ids[index], TxIrq); - - if (status & UART_S1_RDRF_MASK) - irq_handler(serial_irq_ids[index], RxIrq); - } -} - -void uart0_irq() {uart_irq(UART0->S1, 0);} -void uart1_irq() {uart_irq(UART1->S1, 1);} -void uart2_irq() {uart_irq(UART2->S1, 2);} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - switch ((int)obj->uart) { - case UART_0: - irq_n=UART0_RX_TX_IRQn; - vector = (uint32_t)&uart0_irq; - break; - case UART_1: - irq_n=UART1_RX_TX_IRQn; - vector = (uint32_t)&uart1_irq; - break; - case UART_2: - irq_n=UART2_RX_TX_IRQn; - vector = (uint32_t)&uart2_irq; - break; - } - - if (enable) { - switch (irq) { - case RxIrq: - obj->uart->C2 |= (UART_C2_RIE_MASK); - break; - case TxIrq: - obj->uart->C2 |= (UART_C2_TIE_MASK); - break; - } - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - } else { // disable - int all_disabled = 0; - SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); - switch (irq) { - case RxIrq: - obj->uart->C2 &= ~(UART_C2_RIE_MASK); - break; - case TxIrq: - obj->uart->C2 &= ~(UART_C2_TIE_MASK); - break; - } - switch (other_irq) { - case RxIrq: - all_disabled = (obj->uart->C2 & (UART_C2_RIE_MASK)) == 0; - break; - case TxIrq: - all_disabled = (obj->uart->C2 & (UART_C2_TIE_MASK)) == 0; - break; - } - if (all_disabled) - NVIC_DisableIRQ(irq_n); - } -} - -int serial_getc(serial_t *obj) { - while (!serial_readable(obj)); - return obj->uart->D; -} - -void serial_putc(serial_t *obj, int c) { - while (!serial_writable(obj)); - obj->uart->D = c; -} - -int serial_readable(serial_t *obj) { - - return (obj->uart->S1 & UART_S1_RDRF_MASK); -} - -int serial_writable(serial_t *obj) { - - return (obj->uart->S1 & UART_S1_TDRE_MASK); -} - -void serial_clear(serial_t *obj) { -} - -void serial_pinout_tx(PinName tx) { - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) { - obj->uart->C2 |= UART_C2_SBK_MASK; -} - -void serial_break_clear(serial_t *obj) { - obj->uart->C2 &= ~UART_C2_SBK_MASK; -} -
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/sleep.c Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,51 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "cmsis.h" - -//Normal wait mode -void sleep(void) -{ - SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK; - - //Normal sleep mode for ARM core: - SCB->SCR = 0; - __WFI(); -} - -//Very low-power stop mode -void deepsleep(void) -{ - //Check if PLL/FLL is enabled: - uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0); - - SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK; - SMC->PMCTRL = SMC_PMCTRL_STOPM(2); - - //Deep sleep for ARM core: - SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos; - - __WFI(); - - //Switch back to PLL as clock source if needed - //The interrupt that woke up the device will run at reduced speed - if (PLL_FLL_en) { - if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */ - while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */ - MCG->C1 &= ~MCG_C1_CLKS_MASK; - } - -}
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/spi_api.c Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,174 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "spi_api.h" - -#include <math.h> - -#include "cmsis.h" -#include "pinmap.h" -#include "clk_freqs.h" - -static const PinMap PinMap_SPI_SCLK[] = { - {PTC5, SPI_0, 2}, - {PTD1, SPI_0, 2}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {PTD2, SPI_0, 2}, - {PTC6, SPI_0, 2}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {PTD3, SPI_0, 2}, - {PTC7, SPI_0, 2}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {PTD0, SPI_0, 2}, - {PTC4, SPI_0, 2}, - {NC , NC , 0} -}; - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - // determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT((int)obj->spi != NC); - - SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK; - SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK; - - obj->spi->MCR &= ~(SPI_MCR_MDIS_MASK | SPI_MCR_HALT_MASK); - //obj->spi->MCR |= SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK; - - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // not halt in the debug mode - obj->spi->SR |= SPI_SR_EOQF_MASK; - - // pin out the spi pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } -} - -void spi_free(spi_t *obj) { - // [TODO] -} -void spi_format(spi_t *obj, int bits, int mode, int slave) { - MBED_ASSERT((bits > 4) || (bits < 16)); - MBED_ASSERT((mode >= 0) && (mode <= 3)); - - uint32_t polarity = (mode & 0x2) ? 1 : 0; - uint32_t phase = (mode & 0x1) ? 1 : 0; - - // set master/slave - obj->spi->MCR &= ~SPI_MCR_MSTR_MASK; - obj->spi->MCR |= ((!slave) << SPI_MCR_MSTR_SHIFT); - - // CTAR0 is used - obj->spi->CTAR[0] &= ~(SPI_CTAR_CPHA_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_FMSZ_MASK); - obj->spi->CTAR[0] |= (polarity << SPI_CTAR_CPOL_SHIFT) | (phase << SPI_CTAR_CPHA_SHIFT) | ((bits - 1) << SPI_CTAR_FMSZ_SHIFT); -} - -static const uint8_t baudrate_prescaler[] = {2,3,5,7}; -static const uint16_t baudrate_scaler[] = {2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768}; - -void spi_frequency(spi_t *obj, int hz) { - uint32_t f_error = 0; - uint32_t p_error = 0xffffffff; - uint32_t ref = 0; - uint32_t br = 0; - uint32_t ref_spr = 0; - uint32_t ref_prescaler = 0; - uint32_t ref_dr = 0; - - // bus clk - uint32_t PCLK = bus_frequency(); - - for (uint32_t i = 0; i < 4; i++) { - for (br = 0; br <= 15; br++) { - for (uint32_t dr = 0; dr < 2; dr++) { - ref = (PCLK * (1U + dr) / baudrate_prescaler[i]) / baudrate_scaler[br]; - if (ref > (uint32_t)hz) - continue; - f_error = hz - ref; - if (f_error < p_error) { - ref_spr = br; - ref_prescaler = i; - ref_dr = dr; - p_error = f_error; - } - } - } - } - - // set PBR and BR - obj->spi->CTAR[0] &= ~(SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK | SPI_CTAR_DBR_MASK); - obj->spi->CTAR[0] |= (ref_prescaler << SPI_CTAR_PBR_SHIFT) | (ref_spr << SPI_CTAR_BR_SHIFT) | (ref_dr << SPI_CTAR_DBR_SHIFT); -} - -static inline int spi_writeable(spi_t *obj) { - return (obj->spi->SR & SPI_SR_TFFF_MASK) ? 1 : 0; -} - -static inline int spi_readable(spi_t *obj) { - return (obj->spi->SR & SPI_SR_RFDF_MASK) ? 1 : 0; -} - -int spi_master_write(spi_t *obj, int value) { - //clear RX buffer flag - obj->spi->SR |= SPI_SR_RFDF_MASK; - // wait tx buffer empty - while(!spi_writeable(obj)); - obj->spi->PUSHR = SPI_PUSHR_TXDATA(value & 0xffff) /*| SPI_PUSHR_EOQ_MASK*/; - - // wait rx buffer full - while (!spi_readable(obj)); - return obj->spi->POPR; -} - -int spi_slave_receive(spi_t *obj) { - return spi_readable(obj); -} - -int spi_slave_read(spi_t *obj) { - obj->spi->SR |= SPI_SR_RFDF_MASK; - return obj->spi->POPR; -} - -void spi_slave_write(spi_t *obj, int value) { - while (!spi_writeable(obj)); -}
--- a/targets/hal/TARGET_Freescale/TARGET_K20D50M/us_ticker.c Wed Jan 14 09:30:07 2015 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,159 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include <stddef.h> -#include "us_ticker_api.h" -#include "PeripheralNames.h" -#include "clk_freqs.h" - -#define PIT_TIMER PIT->CHANNEL[0] -#define PIT_TIMER_IRQ PIT0_IRQn -#define PIT_TICKER PIT->CHANNEL[1] -#define PIT_TICKER_IRQ PIT1_IRQn - -static void timer_init(void); -static void ticker_init(void); - - -static int us_ticker_inited = 0; -static uint32_t clk_mhz; - -void us_ticker_init(void) { - if (us_ticker_inited) - return; - us_ticker_inited = 1; - - SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT - PIT->MCR = 0; // Enable PIT - - clk_mhz = bus_frequency() / 1000000; - - timer_init(); - ticker_init(); -} - -/****************************************************************************** - * Timer for us timing. - * - * The K20D5M does not have a prescaler on its PIT timer nor the option - * to chain timers, which is why a software timer is required to get 32-bit - * word length. - ******************************************************************************/ -static volatile uint32_t msb_counter = 0; -static uint32_t timer_ldval = 0; - -static void timer_isr(void) { - msb_counter++; - PIT_TIMER.TFLG = 1; -} - -static void timer_init(void) { - //CLZ counts the leading zeros, returning number of bits not used by clk_mhz - timer_ldval = clk_mhz << __CLZ(clk_mhz); - - PIT_TIMER.LDVAL = timer_ldval; // 1us - PIT_TIMER.TCTRL |= PIT_TCTRL_TIE_MASK; - PIT_TIMER.TCTRL |= PIT_TCTRL_TEN_MASK; // Start timer 0 - - NVIC_SetVector(PIT_TIMER_IRQ, (uint32_t)timer_isr); - NVIC_EnableIRQ(PIT_TIMER_IRQ); -} - -uint32_t us_ticker_read() { - if (!us_ticker_inited) - us_ticker_init(); - - uint32_t retval; - __disable_irq(); - retval = (timer_ldval - PIT_TIMER.CVAL) / clk_mhz; //Hardware bits - retval |= msb_counter << __CLZ(clk_mhz); //Software bits - - if (PIT_TIMER.TFLG == 1) { //If overflow bit is set, force it to be handled - timer_isr(); //Handle IRQ, read again to make sure software/hardware bits are synced - NVIC_ClearPendingIRQ(PIT_TIMER_IRQ); - return us_ticker_read(); - } - - __enable_irq(); - return retval; -} - -/****************************************************************************** - * Timer Event - * - * It schedules interrupts at given (32bit)us interval of time. - * It is implemented using PIT channel 1, since no prescaler is available, - * some bits are implemented in software. - ******************************************************************************/ -static void ticker_isr(void); - -static void ticker_init(void) { - /* Set interrupt handler */ - NVIC_SetVector(PIT_TICKER_IRQ, (uint32_t)ticker_isr); - NVIC_EnableIRQ(PIT_TICKER_IRQ); -} - -void us_ticker_disable_interrupt(void) { - PIT_TICKER.TCTRL &= ~PIT_TCTRL_TIE_MASK; -} - -void us_ticker_clear_interrupt(void) { - // we already clear interrupt in lptmr_isr -} - -static uint32_t us_ticker_int_counter = 0; - -inline static void ticker_set(uint32_t count) { - PIT_TICKER.TCTRL = 0; - PIT_TICKER.LDVAL = count; - PIT_TICKER.TCTRL = PIT_TCTRL_TIE_MASK | PIT_TCTRL_TEN_MASK; -} - -static void ticker_isr(void) { - // Clear IRQ flag - PIT_TICKER.TFLG = 1; - - if (us_ticker_int_counter > 0) { - ticker_set(0xFFFFFFFF); - us_ticker_int_counter--; - } else { - // This function is going to disable the interrupts if there are - // no other events in the queue - us_ticker_irq_handler(); - } -} - -void us_ticker_set_interrupt(timestamp_t timestamp) { - int delta = (int)((uint32_t)timestamp - us_ticker_read()); - if (delta <= 0) { - // This event was in the past: - us_ticker_irq_handler(); - return; - } - - //Calculate how much falls outside the 32-bit after multiplying with clk_mhz - //We shift twice 16-bit to keep everything within the 32-bit variable - us_ticker_int_counter = (uint32_t)(delta >> 16); - us_ticker_int_counter *= clk_mhz; - us_ticker_int_counter >>= 16; - - uint32_t us_ticker_int_remainder = (uint32_t)delta * clk_mhz; - if (us_ticker_int_remainder == 0) { - ticker_set(0xFFFFFFFF); - us_ticker_int_counter--; - } else { - ticker_set(us_ticker_int_remainder); - } -}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/PeripheralPins.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,46 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/PortNames.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,35 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4 +} PortName; + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PeripheralNames.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,73 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)UART0_BASE, + UART_1 = (int)UART1_BASE, + UART_2 = (int)UART2_BASE +} UARTName; +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_0 = (int)I2C0_BASE, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 +} PWMName; + +typedef enum { + ADC0_SE4b = 4, + ADC0_SE5b = 5, + ADC0_SE6b = 6, + ADC0_SE7b = 7, + ADC0_SE8 = 8, + ADC0_SE9 = 9, + ADC0_SE12 = 12, + ADC0_SE13 = 13, + ADC0_SE14 = 14, + ADC0_SE15 = 15 +} ADCName; + +typedef enum { + SPI_0 = (int)SPI0_BASE, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PeripheralPins.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,120 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PTC2, ADC0_SE4b, 0}, + {PTD1, ADC0_SE5b, 0}, + {PTD5, ADC0_SE6b, 0}, + {PTD6, ADC0_SE7b, 0}, + {PTB0, ADC0_SE8, 0}, + {PTB1, ADC0_SE9, 0}, + {PTB2, ADC0_SE12, 0}, + {PTB3, ADC0_SE13, 0}, + {PTC0, ADC0_SE14, 0}, + {PTC1, ADC0_SE15, 0}, + {NC, NC, 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTB1, I2C_0, 2}, + {PTB3, I2C_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTB0, I2C_0, 2}, + {PTB2, I2C_0, 2}, + {NC , NC, 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {PTB17, UART_0, 3}, + {PTC4 , UART_1, 3}, + {PTD3 , UART_2, 3}, + {PTD7 , UART_0, 3}, + {PTE0 , UART_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTB16, UART_0, 3}, + {PTC3 , UART_1, 3}, + {PTD2 , UART_2, 3}, + {PTD6 , UART_0, 3}, + {PTE1 , UART_1, 3}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {PTC5, SPI_0, 2}, + {PTD1, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PTD2, SPI_0, 2}, + {PTC6, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PTD3, SPI_0, 2}, + {PTC7, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PTD0, SPI_0, 2}, + {PTC4, SPI_0, 2}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + // LEDs + {LED_RED , PWM_3 , 4}, // PTC3, FTM0 CH2 + {LED_GREEN, PWM_5, 4}, // PTD4, FTM0 CH4 + {LED_BLUE , PWM_8 , 3}, // PTA2, FTM0 CH7 + + // Arduino digital pinout + {D3, PWM_5 , 4}, // PTD4, FTM0 CH4 + {D5, PWM_7 , 3}, // PTA1, FTM0 CH6 + {D6, PWM_3 , 4}, // PTC3, FTM0 CH2 + {D9, PWM_6 , 4}, // PTD5, FTM0 CH6 + {D10, PWM_2 , 4}, // PTC2, FTM0 CH1 + + {PTA0, PWM_6 , 3}, // PTA0, FTM0 CH5 + {PTA3, PWM_1 , 3}, // PTA3, FTM0 CH0 + {PTA4, PWM_2 , 3}, // PTA4, FTM0 CH1 + {PTA5, PWM_3 , 3}, // PTA5, FTM0 CH2 + {PTA12, PWM_9 , 3}, // PTA12, FTM1 CH0 + {PTA13, PWM_10, 3}, // PTA13, FTM1 CH1 + {PTB0, PWM_9 , 3}, // PTB0, FTM1 CH0 + {PTB1, PWM_10, 3}, // PTB1, FTM1 CH1 + {PTC1, PWM_1 , 4}, // PTC1, FTM0 CH0 + {PTD4, PWM_4 , 4}, // PTD4, FTM0 CH3 + {PTD6, PWM_7 , 4}, // PTD6, FTM0 CH6 + {PTD7, PWM_8 , 4}, // PTD7, FTM0 CH7 + + {NC , NC , 0} +};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PinNames.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,256 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +/* PCR - 0x1000 */ +#define PORT_SHIFT 12 + +typedef enum { + PTA0 = 0x0, + PTA1 = 0x4, + PTA2 = 0x8, + PTA3 = 0xc, + PTA4 = 0x10, + PTA5 = 0x14, + PTA6 = 0x18, + PTA7 = 0x1c, + PTA8 = 0x20, + PTA9 = 0x24, + PTA10 = 0x28, + PTA11 = 0x2c, + PTA12 = 0x30, + PTA13 = 0x34, + PTA14 = 0x38, + PTA15 = 0x3c, + PTA16 = 0x40, + PTA17 = 0x44, + PTA18 = 0x48, + PTA19 = 0x4c, + PTA20 = 0x50, + PTA21 = 0x54, + PTA22 = 0x58, + PTA23 = 0x5c, + PTA24 = 0x60, + PTA25 = 0x64, + PTA26 = 0x68, + PTA27 = 0x6c, + PTA28 = 0x70, + PTA29 = 0x74, + PTA30 = 0x78, + PTA31 = 0x7c, + PTB0 = 0x1000, + PTB1 = 0x1004, + PTB2 = 0x1008, + PTB3 = 0x100c, + PTB4 = 0x1010, + PTB5 = 0x1014, + PTB6 = 0x1018, + PTB7 = 0x101c, + PTB8 = 0x1020, + PTB9 = 0x1024, + PTB10 = 0x1028, + PTB11 = 0x102c, + PTB12 = 0x1030, + PTB13 = 0x1034, + PTB14 = 0x1038, + PTB15 = 0x103c, + PTB16 = 0x1040, + PTB17 = 0x1044, + PTB18 = 0x1048, + PTB19 = 0x104c, + PTB20 = 0x1050, + PTB21 = 0x1054, + PTB22 = 0x1058, + PTB23 = 0x105c, + PTB24 = 0x1060, + PTB25 = 0x1064, + PTB26 = 0x1068, + PTB27 = 0x106c, + PTB28 = 0x1070, + PTB29 = 0x1074, + PTB30 = 0x1078, + PTB31 = 0x107c, + PTC0 = 0x2000, + PTC1 = 0x2004, + PTC2 = 0x2008, + PTC3 = 0x200c, + PTC4 = 0x2010, + PTC5 = 0x2014, + PTC6 = 0x2018, + PTC7 = 0x201c, + PTC8 = 0x2020, + PTC9 = 0x2024, + PTC10 = 0x2028, + PTC11 = 0x202c, + PTC12 = 0x2030, + PTC13 = 0x2034, + PTC14 = 0x2038, + PTC15 = 0x203c, + PTC16 = 0x2040, + PTC17 = 0x2044, + PTC18 = 0x2048, + PTC19 = 0x204c, + PTC20 = 0x2050, + PTC21 = 0x2054, + PTC22 = 0x2058, + PTC23 = 0x205c, + PTC24 = 0x2060, + PTC25 = 0x2064, + PTC26 = 0x2068, + PTC27 = 0x206c, + PTC28 = 0x2070, + PTC29 = 0x2074, + PTC30 = 0x2078, + PTC31 = 0x207c, + PTD0 = 0x3000, + PTD1 = 0x3004, + PTD2 = 0x3008, + PTD3 = 0x300c, + PTD4 = 0x3010, + PTD5 = 0x3014, + PTD6 = 0x3018, + PTD7 = 0x301c, + PTD8 = 0x3020, + PTD9 = 0x3024, + PTD10 = 0x3028, + PTD11 = 0x302c, + PTD12 = 0x3030, + PTD13 = 0x3034, + PTD14 = 0x3038, + PTD15 = 0x303c, + PTD16 = 0x3040, + PTD17 = 0x3044, + PTD18 = 0x3048, + PTD19 = 0x304c, + PTD20 = 0x3050, + PTD21 = 0x3054, + PTD22 = 0x3058, + PTD23 = 0x305c, + PTD24 = 0x3060, + PTD25 = 0x3064, + PTD26 = 0x3068, + PTD27 = 0x306c, + PTD28 = 0x3070, + PTD29 = 0x3074, + PTD30 = 0x3078, + PTD31 = 0x307c, + PTE0 = 0x4000, + PTE1 = 0x4004, + PTE2 = 0x4008, + PTE3 = 0x400c, + PTE4 = 0x4010, + PTE5 = 0x4014, + PTE6 = 0x4018, + PTE7 = 0x401c, + PTE8 = 0x4020, + PTE9 = 0x4024, + PTE10 = 0x4028, + PTE11 = 0x402c, + PTE12 = 0x4030, + PTE13 = 0x4034, + PTE14 = 0x4038, + PTE15 = 0x403c, + PTE16 = 0x4040, + PTE17 = 0x4044, + PTE18 = 0x4048, + PTE19 = 0x404c, + PTE20 = 0x4050, + PTE21 = 0x4054, + PTE22 = 0x4058, + PTE23 = 0x405c, + PTE24 = 0x4060, + PTE25 = 0x4064, + PTE26 = 0x4068, + PTE27 = 0x406c, + PTE28 = 0x4070, + PTE29 = 0x4074, + PTE30 = 0x4078, + PTE31 = 0x407c, + + LED_RED = PTC3, + LED_GREEN = PTD4, + LED_BLUE = PTA2, + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_BLUE, + + // USB Pins + USBTX = PTB17, + USBRX = PTB16, + + // Arduino Headers + D0 = PTE1, + D1 = PTE0, + D2 = PTA5, + D3 = PTD4, + D4 = PTC8, + D5 = PTA1, + D6 = PTC3, + D7 = PTC4, + D8 = PTA12, + D9 = PTA2, + D10 = PTC2, + D11 = PTD2, + D12 = PTD3, + D13 = PTD1, + D14 = PTB3, + D15 = PTB2, + + A0 = PTC0, + A1 = PTC1, + A2 = PTD6, + A3 = PTD5, + A4 = PTB1, + A5 = PTB0, + + I2C_SCL = D15, + I2C_SDA = D14, + + TSI_ELEC0 = PTB16, + TSI_ELEC1 = PTB17, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 2, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/device.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 1 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralNames.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,86 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)UART0_BASE, + UART_1 = (int)UART1_BASE, + UART_2 = (int)UART2_BASE +} UARTName; +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_0 = (int)I2C0_BASE, + I2C_1 = (int)I2C1_BASE, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 +} PWMName; + +typedef enum { + ADC0_SE4b = 4, + ADC0_SE5b = 5, + ADC0_SE6b = 6, + ADC0_SE7b = 7, + ADC0_SE8 = 8, + ADC0_SE9 = 9, + ADC0_SE12 = 12, + ADC0_SE13 = 13, + ADC0_SE14 = 14, + ADC0_SE15 = 15, + ADC1_SE4b = 16, + ADC1_SE5b = 17, + ADC1_SE6b = 18, + ADC1_SE7b = 19, +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + +typedef enum { + SPI_0 = (int)SPI0_BASE, + SPI_1 = (int)SPI0_BASE, + SPI_2 = (int)SPI0_BASE, + SPI_3 = (int)SPI0_BASE, + SPI_4 = (int)SPI0_BASE, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralPins.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,137 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PTC2, ADC0_SE4b, 0}, + {PTD1, ADC0_SE5b, 0}, + {PTD5, ADC0_SE6b, 0}, + {PTD6, ADC0_SE7b, 0}, + {PTB0, ADC0_SE8, 0}, + {PTB1, ADC0_SE9, 0}, + {PTB2, ADC0_SE12, 0}, + {PTB3, ADC0_SE13, 0}, + {PTC0, ADC0_SE14, 0}, + {PTC1, ADC0_SE15, 0}, + {PTC8, ADC1_SE4b, 0}, + {PTC9, ADC1_SE5b, 0}, + {PTC10,ADC1_SE6b, 0}, + {PTC11,ADC1_SE7b, 0}, + {NC, NC, 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {DAC0_OUT, DAC_0, 0}, + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTB1, I2C_0, 2}, + {PTB3, I2C_0, 2}, + {PTE0, I2C_1, 2}, + {PTC11, I2C_1, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTB0, I2C_0, 2}, + {PTB2, I2C_0, 2}, + {PTE1, I2C_1, 2}, + {PTC10, I2C_1, 2}, + {NC , NC, 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {PTB17, UART_0, 3}, + {PTC4 , UART_1, 3}, + {PTD3 , UART_2, 3}, + {PTD7 , UART_0, 3}, + {PTE0 , UART_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTB16, UART_0, 3}, + {PTC3 , UART_1, 3}, + {PTD2 , UART_2, 3}, + {PTD6 , UART_0, 3}, + {PTE1 , UART_1, 3}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { // SCK + {PTC5, SPI_0, 2}, + {PTD1, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { // DOUT + {PTD2, SPI_0, 2}, + {PTC6, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { // DIN + {PTD3, SPI_0, 2}, + {PTC7, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { // CS + {PTD0, SPI_0, 2}, + {PTC4, SPI_0, 2}, + {PTD4, SPI_0, 2}, + {PTC3, SPI_0, 2}, + {PTC2, SPI_0, 2}, + {PTD5, SPI_0, 2}, + {PTD6, SPI_0, 2}, + {PTC1, SPI_0, 2}, + {PTC0, SPI_0, 2} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + // LEDs + {LED_RED , PWM_3 , 4}, // PTC3, FTM0 CH2 + {LED_GREEN, PWM_5, 4}, // PTD4, FTM0 CH4 + {LED_BLUE , PWM_8 , 3}, // PTA2, FTM0 CH7 + + {PTA0, PWM_6 , 3}, // PTA0, FTM0 CH5 + {PTA1, PWM_7 , 3}, // PTA1, FTM0 CH6 + {PTA3, PWM_1 , 3}, // PTA3, FTM0 CH0 + {PTA4, PWM_2 , 3}, // PTA4, FTM0 CH1 + {PTA5, PWM_3 , 3}, // PTA5, FTM0 CH2 + {PTA12, PWM_9 , 3}, // PTA12, FTM1 CH0 + {PTA13, PWM_10, 3}, // PTA13, FTM1 CH1 + {PTB0, PWM_9 , 3}, // PTB0, FTM1 CH0 + {PTB1, PWM_10, 3}, // PTB1, FTM1 CH1 + {PTC1, PWM_1 , 4}, // PTC1, FTM0 CH0 + {PTC2, PWM_2 , 4}, // PTC2, FTM0 CH1 + {PTC3, PWM_3 , 4}, // PTC3, FTM0 CH2 + {PTD4, PWM_4 , 4}, // PTD4, FTM0 CH3 + {PTD5, PWM_6 , 4}, // PTD5, FTM0 CH6 + {PTD6, PWM_7 , 4}, // PTD6, FTM0 CH6 + {PTD7, PWM_8 , 4}, // PTD7, FTM0 CH7 + + {NC , NC , 0} +};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,293 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +/* PCR - 0x1000 */ +#define PORT_SHIFT 12 + +typedef enum { + PTA0 = 0x0, + PTA1 = 0x4, + PTA2 = 0x8, + PTA3 = 0xc, + PTA4 = 0x10, + PTA5 = 0x14, + PTA6 = 0x18, + PTA7 = 0x1c, + PTA8 = 0x20, + PTA9 = 0x24, + PTA10 = 0x28, + PTA11 = 0x2c, + PTA12 = 0x30, + PTA13 = 0x34, + PTA14 = 0x38, + PTA15 = 0x3c, + PTA16 = 0x40, + PTA17 = 0x44, + PTA18 = 0x48, + PTA19 = 0x4c, + PTA20 = 0x50, + PTA21 = 0x54, + PTA22 = 0x58, + PTA23 = 0x5c, + PTA24 = 0x60, + PTA25 = 0x64, + PTA26 = 0x68, + PTA27 = 0x6c, + PTA28 = 0x70, + PTA29 = 0x74, + PTA30 = 0x78, + PTA31 = 0x7c, + PTB0 = 0x1000, + PTB1 = 0x1004, + PTB2 = 0x1008, + PTB3 = 0x100c, + PTB4 = 0x1010, + PTB5 = 0x1014, + PTB6 = 0x1018, + PTB7 = 0x101c, + PTB8 = 0x1020, + PTB9 = 0x1024, + PTB10 = 0x1028, + PTB11 = 0x102c, + PTB12 = 0x1030, + PTB13 = 0x1034, + PTB14 = 0x1038, + PTB15 = 0x103c, + PTB16 = 0x1040, + PTB17 = 0x1044, + PTB18 = 0x1048, + PTB19 = 0x104c, + PTB20 = 0x1050, + PTB21 = 0x1054, + PTB22 = 0x1058, + PTB23 = 0x105c, + PTB24 = 0x1060, + PTB25 = 0x1064, + PTB26 = 0x1068, + PTB27 = 0x106c, + PTB28 = 0x1070, + PTB29 = 0x1074, + PTB30 = 0x1078, + PTB31 = 0x107c, + PTC0 = 0x2000, + PTC1 = 0x2004, + PTC2 = 0x2008, + PTC3 = 0x200c, + PTC4 = 0x2010, + PTC5 = 0x2014, + PTC6 = 0x2018, + PTC7 = 0x201c, + PTC8 = 0x2020, + PTC9 = 0x2024, + PTC10 = 0x2028, + PTC11 = 0x202c, + PTC12 = 0x2030, + PTC13 = 0x2034, + PTC14 = 0x2038, + PTC15 = 0x203c, + PTC16 = 0x2040, + PTC17 = 0x2044, + PTC18 = 0x2048, + PTC19 = 0x204c, + PTC20 = 0x2050, + PTC21 = 0x2054, + PTC22 = 0x2058, + PTC23 = 0x205c, + PTC24 = 0x2060, + PTC25 = 0x2064, + PTC26 = 0x2068, + PTC27 = 0x206c, + PTC28 = 0x2070, + PTC29 = 0x2074, + PTC30 = 0x2078, + PTC31 = 0x207c, + PTD0 = 0x3000, + PTD1 = 0x3004, + PTD2 = 0x3008, + PTD3 = 0x300c, + PTD4 = 0x3010, + PTD5 = 0x3014, + PTD6 = 0x3018, + PTD7 = 0x301c, + PTD8 = 0x3020, + PTD9 = 0x3024, + PTD10 = 0x3028, + PTD11 = 0x302c, + PTD12 = 0x3030, + PTD13 = 0x3034, + PTD14 = 0x3038, + PTD15 = 0x303c, + PTD16 = 0x3040, + PTD17 = 0x3044, + PTD18 = 0x3048, + PTD19 = 0x304c, + PTD20 = 0x3050, + PTD21 = 0x3054, + PTD22 = 0x3058, + PTD23 = 0x305c, + PTD24 = 0x3060, + PTD25 = 0x3064, + PTD26 = 0x3068, + PTD27 = 0x306c, + PTD28 = 0x3070, + PTD29 = 0x3074, + PTD30 = 0x3078, + PTD31 = 0x307c, + PTE0 = 0x4000, + PTE1 = 0x4004, + PTE2 = 0x4008, + PTE3 = 0x400c, + PTE4 = 0x4010, + PTE5 = 0x4014, + PTE6 = 0x4018, + PTE7 = 0x401c, + PTE8 = 0x4020, + PTE9 = 0x4024, + PTE10 = 0x4028, + PTE11 = 0x402c, + PTE12 = 0x4030, + PTE13 = 0x4034, + PTE14 = 0x4038, + PTE15 = 0x403c, + PTE16 = 0x4040, + PTE17 = 0x4044, + PTE18 = 0x4048, + PTE19 = 0x404c, + PTE20 = 0x4050, + PTE21 = 0x4054, + PTE22 = 0x4058, + PTE23 = 0x405c, + PTE24 = 0x4060, + PTE25 = 0x4064, + PTE26 = 0x4068, + PTE27 = 0x406c, + PTE28 = 0x4070, + PTE29 = 0x4074, + PTE30 = 0x4078, + PTE31 = 0x407c, + + LED_RED = PTC5, // set these to the only led on board + LED_GREEN = PTC5, // + LED_BLUE = PTC5, // + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_BLUE, + + // USB Pins + USBTX = PTB17, + USBRX = PTB16, + + // DAC Pins + DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ + + // Teensy3.1 Headers + p0 = PTB16, + p1 = PTB17, + p2 = PTD0, + p3 = PTA12, + p4 = PTA13, + p5 = PTD7, + p6 = PTD4, + p7 = PTD2, + p8 = PTD3, + p9 = PTC3, + p10 = PTC4, + p11 = PTC6, + p12 = PTC7, + p13 = PTC5, + p14 = PTD1, + p15 = PTC0, + p16 = PTB0, + p17 = PTB1, + p18 = PTB3, + p19 = PTB2, + p20 = PTD5, + p21 = PTD6, + p22 = PTC1, + p23 = PTC2, + p24 = PTA5, + p25 = PTD19, + p26 = PTE1, + p27 = PTC9, + p28 = PTC8, + p29 = PTC10, + p30 = PTC11, + p31 = PTE0, + p32 = PTB18, + p33 = PTA4, + + A0 = PTD1, + A1 = PTC0, + A2 = PTB0, + A3 = PTB1, + A4 = PTB3, + A5 = PTB2, + A6 = PTD5, + A7 = PTD6, + A8 = PTC1, + A9 = PTC2, + + I2C_SCL = PTB3, + I2C_SDA = PTB2, + + SPI_SCK = PTC5, // sclk + SPI_DOUT = PTC6, // mosi + SPI_DIN = PTC7, // miso + SPI_CS = PTC4, // ssel + + SERIAL_TX = PTB17, + SERIAL_RX = PTB16, + + PWM = PTD7, + + DAC = DAC0_OUT, + + TSI_ELEC0 = PTC1, + TSI_ELEC1 = PTC2, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 2, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 1 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/analogin_api.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,79 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogin_api.h" + +#include "cmsis.h" +#include "pinmap.h" +#include "clk_freqs.h" +#include "PeripheralPins.h" + +#define MAX_FADC 6000000 + +void analogin_init(analogin_t *obj, PinName pin) { + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + + SIM->SCGC6 |= SIM_SCGC6_ADC0_MASK; + + uint32_t port = (uint32_t)pin >> PORT_SHIFT; + SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port); + + // bus clk + uint32_t PCLK = bus_frequency(); + uint32_t clkdiv; + for (clkdiv = 0; clkdiv < 4; clkdiv++) { + if ((PCLK >> clkdiv) <= MAX_FADC) + break; + } + if (clkdiv == 4) //Set max div + clkdiv = 0x7; + + ADC0->SC1[1] = ADC_SC1_ADCH(obj->adc); + + ADC0->CFG1 = ADC_CFG1_ADLPC_MASK // Low-Power Configuration + | ADC_CFG1_ADIV(clkdiv & 0x3) // Clock Divide Select + | ADC_CFG1_ADLSMP_MASK // Long Sample Time + | ADC_CFG1_MODE(3) // (16)bits Resolution + | ADC_CFG1_ADICLK(clkdiv >> 2); // Input Clock + + ADC0->CFG2 = ADC_CFG2_MUXSEL_MASK // ADxxb or ADxxa channels + | ADC_CFG2_ADACKEN_MASK // Asynchronous Clock Output Enable + | ADC_CFG2_ADHSC_MASK // High-Speed Configuration + | ADC_CFG2_ADLSTS(0); // Long Sample Time Select + + ADC0->SC2 = ADC_SC2_REFSEL(0); // Default Voltage Reference + + ADC0->SC3 = ADC_SC3_AVGE_MASK // Hardware Average Enable + | ADC_SC3_AVGS(0); // 4 Samples Averaged + + pinmap_pinout(pin, PinMap_ADC); +} + +uint16_t analogin_read_u16(analogin_t *obj) { + // start conversion + ADC0->SC1[0] = ADC_SC1_ADCH(obj->adc); + + // Wait Conversion Complete + while ((ADC0->SC1[0] & ADC_SC1_COCO_MASK) != ADC_SC1_COCO_MASK); + + return (uint16_t)ADC0->R[0]; +} + +float analogin_read(analogin_t *obj) { + uint16_t value = analogin_read_u16(obj); + return (float)value * (1.0f / (float)0xFFFF); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/analogout_api.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,84 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "analogout_api.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +#define RANGE_12BIT 0xFFF + +void analogout_init(dac_t *obj, PinName pin) { + obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT(obj->dac != (DACName)NC); + + SIM->SCGC2 |= SIM_SCGC2_DAC0_MASK; + + uint32_t port = (uint32_t)pin >> PORT_SHIFT; + SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port); + + DAC0->DAT[obj->dac].DATH = 0; + DAC0->DAT[obj->dac].DATL = 0; + + DAC0->C1 = DAC_C1_DACBFMD_MASK; // One-Time Scan Mode + + DAC0->C0 = DAC_C0_DACEN_MASK // Enable + | DAC_C0_DACSWTRG_MASK // Software Trigger + | DAC_C0_DACRFS_MASK; // VDDA selected + + analogout_write_u16(obj, 0); +} + +void analogout_free(dac_t *obj) {} + +static inline void dac_write(dac_t *obj, int value) { + DAC0->DAT[obj->dac].DATL = (uint8_t)( value & 0xFF); + DAC0->DAT[obj->dac].DATH = (uint8_t)((value >> 8) & 0xFF); +} + +static inline int dac_read(dac_t *obj) { + return ((DAC0->DAT[obj->dac].DATH << 8) | DAC0->DAT[obj->dac].DATL); +} + +void analogout_write(dac_t *obj, float value) { + if (value < 0.0) { + dac_write(obj, 0); + } else if (value > 1.0) { + dac_write(obj, RANGE_12BIT); + } else { + dac_write(obj, value * (float)RANGE_12BIT); + } +} + +void analogout_write_u16(dac_t *obj, uint16_t value) { + dac_write(obj, value >> 4); // 12-bit +} + +float analogout_read(dac_t *obj) { + uint32_t value = dac_read(obj); + return (float)value * (1.0f / (float)RANGE_12BIT); +} + +uint16_t analogout_read_u16(dac_t *obj) { + uint32_t value = dac_read(obj); // 12-bit + return (value << 4) | ((value >> 8) & 0x003F); +} + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/clk_freqs.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,115 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef CLK_FREQS_H +#define CLK_FREQS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * \brief Get the peripheral bus clock frequency + * \return Bus frequency + */ +static inline uint32_t bus_frequency(void) { + return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) + 1); +} + +/*! + * \brief Get external oscillator (crystal) frequency + * \return External osc frequency + */ +static uint32_t extosc_frequency(void) { + uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)); + + if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock + return MCGClock; + + if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected + uint32_t divider, multiplier; + if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected + if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference + divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) + divider <<= 5u; + /* Select correct multiplier to calculate the MCG output clock */ + switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { + case 0x0u: + multiplier = 640u; + break; + case 0x20u: + multiplier = 1280u; + break; + case 0x40u: + multiplier = 1920u; + break; + case 0x60u: + multiplier = 2560u; + break; + case 0x80u: + multiplier = 732u; + break; + case 0xA0u: + multiplier = 1464u; + break; + case 0xC0u: + multiplier = 2197u; + break; + case 0xE0u: + default: + multiplier = 2929u; + break; + } + + return MCGClock * divider / multiplier; + } + } else { //PLL is selected + divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); + multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); + return MCGClock * divider / multiplier; + } + } + + //In all other cases either there is no crystal or we cannot determine it + //For example when the FLL is running on the internal reference, and there is also an + //external crystal. However these are unlikely situations + return 0; +} + +//Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit +static uint32_t mcgpllfll_frequency(void) { + if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected + return 0; + + uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)); + if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected + SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output + return MCGClock; + } else { //PLL is selected + SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output + return MCGClock; + } + + //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active + //for the peripherals, this is however an unlikely setup +} + + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_api.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" + +uint32_t gpio_set(PinName pin) { + MBED_ASSERT(pin != (PinName)NC); + pin_function(pin, 1); + return 1 << ((pin & 0x7F) >> 2); +} + +void gpio_init(gpio_t *obj, PinName pin) { + obj->pin = pin; + if (pin == (PinName)NC) + return; + + obj->mask = gpio_set(pin); + + unsigned int port = (unsigned int)pin >> PORT_SHIFT; + + GPIO_Type *reg = (GPIO_Type *)(PTA_BASE + port * 0x40); + obj->reg_set = ®->PSOR; + obj->reg_clr = ®->PCOR; + obj->reg_in = ®->PDIR; + obj->reg_dir = ®->PDDR; +} + +void gpio_mode(gpio_t *obj, PinMode mode) { + pin_mode(obj->pin, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) { + MBED_ASSERT(obj->pin != (PinName)NC); + switch (direction) { + case PIN_INPUT : + *obj->reg_dir &= ~obj->mask; + break; + case PIN_OUTPUT: + *obj->reg_dir |= obj->mask; + break; + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_irq_api.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,225 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include <stddef.h> +#include "cmsis.h" + +#include "gpio_irq_api.h" +#include "mbed_error.h" + +#define CHANNEL_NUM 160 + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler irq_handler; + +#define IRQ_DISABLED (0) +#define IRQ_RAISING_EDGE PORT_PCR_IRQC(9) +#define IRQ_FALLING_EDGE PORT_PCR_IRQC(10) +#define IRQ_EITHER_EDGE PORT_PCR_IRQC(11) + +static void handle_interrupt_in(PORT_Type *port, int ch_base) { + uint32_t isfr; + uint32_t pin; + + while ((isfr = port->ISFR) != 0) { + pin = 31 - __CLZ(isfr); + uint32_t id = channel_ids[ch_base + pin]; + if (id == 0) { + continue; + } + + GPIO_Type *gpio = PTA; + gpio_irq_event event = IRQ_NONE; + uint32_t port_num = (port - PORTA) >> 12; + + switch (port->PCR[pin] & PORT_PCR_IRQC_MASK) { + case IRQ_RAISING_EDGE: + event = IRQ_RISE; + break; + case IRQ_FALLING_EDGE: + event = IRQ_FALL; + break; + case IRQ_EITHER_EDGE: + gpio += (port_num * 0x40); + event = (gpio->PDIR & (1 << pin)) ? (IRQ_RISE) : (IRQ_FALL); + break; + } + if (event != IRQ_NONE) { + irq_handler(id, event); + } + port->ISFR = 1 << pin; + } +} + +void gpio_irqA(void) { + handle_interrupt_in(PORTA, 0); +} + +void gpio_irqB(void) +{ + handle_interrupt_in(PORTB, 32); +} + +void gpio_irqC(void) +{ + handle_interrupt_in(PORTC, 64); +} + +void gpio_irqD(void) +{ + handle_interrupt_in(PORTD, 96); +} + +void gpio_irqE(void) +{ + handle_interrupt_in(PORTE, 128); +} + + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { + if (pin == NC) + return -1; + + irq_handler = handler; + + obj->port = pin >> PORT_SHIFT; + obj->pin = (pin & 0x7F) >> 2; + + uint32_t ch_base, vector; + IRQn_Type irq_n; + switch (obj->port) { + case PortA: + ch_base = 0; + irq_n = PORTA_IRQn; + vector = (uint32_t)gpio_irqA; + break; + case PortB: + ch_base = 32; + irq_n = PORTB_IRQn; + vector = (uint32_t)gpio_irqB; + break; + case PortC: + ch_base = 64; + irq_n = PORTC_IRQn; + vector = (uint32_t)gpio_irqC; + break; + case PortD: + ch_base = 96; + irq_n = PORTD_IRQn; vector = (uint32_t)gpio_irqD; + break; + case PortE: + ch_base = 128; + irq_n = PORTE_IRQn; + vector = (uint32_t)gpio_irqE; + break; + + default: + error("gpio_irq only supported on port A-E."); + break; + } + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + + obj->ch = ch_base + obj->pin; + channel_ids[obj->ch] = id; + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) { + channel_ids[obj->ch] = 0; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { + PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port); + + uint32_t irq_settings = IRQ_DISABLED; + + switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) { + case IRQ_DISABLED: + if (enable) + irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE); + break; + + case IRQ_RAISING_EDGE: + if (enable) { + irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE); + } else { + if (event == IRQ_FALL) + irq_settings = IRQ_RAISING_EDGE; + } + break; + + case IRQ_FALLING_EDGE: + if (enable) { + irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE); + } else { + if (event == IRQ_RISE) + irq_settings = IRQ_FALLING_EDGE; + } + break; + + case IRQ_EITHER_EDGE: + if (enable) { + irq_settings = IRQ_EITHER_EDGE; + } else { + irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE); + } + break; + } + + // Interrupt configuration and clear interrupt + port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK; +} + +void gpio_irq_enable(gpio_irq_t *obj) { + switch (obj->port) { + case PortA: + NVIC_EnableIRQ(PORTA_IRQn); + break; + case PortB: + NVIC_EnableIRQ(PORTB_IRQn); + break; + case PortC: + NVIC_EnableIRQ(PORTC_IRQn); + break; + case PortD: + NVIC_EnableIRQ(PORTD_IRQn); + break; + case PortE: + NVIC_EnableIRQ(PORTE_IRQn); + break; + } +} + +void gpio_irq_disable(gpio_irq_t *obj) { + switch (obj->port) { + case PortA: + NVIC_DisableIRQ(PORTA_IRQn); + break; + case PortB: + NVIC_DisableIRQ(PORTB_IRQn); + break; + case PortC: + NVIC_DisableIRQ(PORTC_IRQn); + break; + case PortD: + NVIC_DisableIRQ(PORTD_IRQn); + break; + case PortE: + NVIC_DisableIRQ(PORTE_IRQn); + break; + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_object.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,52 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + __IO uint32_t *reg_dir; + __IO uint32_t *reg_set; + __IO uint32_t *reg_clr; + __I uint32_t *reg_in; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) { + MBED_ASSERT(obj->pin != (PinName)NC); + if (value) { + *obj->reg_set = obj->mask; + } else { + *obj->reg_clr = obj->mask; + } +} + +static inline int gpio_read(gpio_t *obj) { + MBED_ASSERT(obj->pin != (PinName)NC); + return ((*obj->reg_in & obj->mask) ? 1 : 0); +} + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/i2c_api.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,378 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "i2c_api.h" + +#include "cmsis.h" +#include "pinmap.h" +#include "clk_freqs.h" +#include "PeripheralPins.h" + +static const uint16_t ICR[0x40] = { + 20, 22, 24, 26, 28, + 30, 34, 40, 28, 32, + 36, 40, 44, 48, 56, + 68, 48, 56, 64, 72, + 80, 88, 104, 128, 80, + 96, 112, 128, 144, 160, + 192, 240, 160, 192, 224, + 256, 288, 320, 384, 480, + 320, 384, 448, 512, 576, + 640, 768, 960, 640, 768, + 896, 1024, 1152, 1280, 1536, + 1920, 1280, 1536, 1792, 2048, + 2304, 2560, 3072, 3840 +}; + + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) { + // determine the I2C to use + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + obj->i2c = (I2C_Type*)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)obj->i2c != NC); + +#if defined(TARGET_K20DX256) + switch ((int)obj->i2c) { + case I2C_0: SIM->SCGC4 |= SIM_SCGC4_I2C0_MASK; + case I2C_1: SIM->SCGC4 |= SIM_SCGC4_I2C1_MASK; + } +#else + SIM->SCGC4 |= SIM_SCGC4_I2C0_MASK; +#endif + + // set default frequency at 100k + i2c_frequency(obj, 100000); + + // enable I2C interface + obj->i2c->C1 |= 0x80; + + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + /* enable open drain for I2C pins, only port b available */ + uint32_t pin_n = (uint32_t)(sda & 0x7C) >> 2; + PORTB->PCR[pin_n] |= PORT_PCR_ODE_MASK; + pin_n = (uint32_t)(scl & 0x7C) >> 2; + PORTB->PCR[pin_n] |= PORT_PCR_ODE_MASK; +} + +int i2c_start(i2c_t *obj) { + // if we are in the middle of a transaction + // activate the repeat_start flag + if (obj->i2c->S & I2C_S_BUSY_MASK) { + obj->i2c->C1 |= 0x04; + } else { + obj->i2c->C1 |= I2C_C1_MST_MASK; + obj->i2c->C1 |= I2C_C1_TX_MASK; + } + return 0; +} + +int i2c_stop(i2c_t *obj) { + volatile uint32_t n = 0; + obj->i2c->C1 &= ~I2C_C1_MST_MASK; + obj->i2c->C1 &= ~I2C_C1_TX_MASK; + + // It seems that there are timing problems + // when there is no waiting time after a STOP. + // This wait is also included on the samples + // code provided with the freedom board + for (n = 0; n < 100; n++) + __NOP(); + return 0; +} + +static int timeout_status_poll(i2c_t *obj, uint32_t mask) { + uint32_t i, timeout = 100000; + + for (i = 0; i < timeout; i++) { + if (obj->i2c->S & mask) + return 0; + } + + return 1; +} + +// this function waits the end of a tx transfer and return the status of the transaction: +// 0: OK ack received +// 1: OK ack not received +// 2: failure +static int i2c_wait_end_tx_transfer(i2c_t *obj) { + + // wait for the interrupt flag + if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) { + return 2; + } + + obj->i2c->S |= I2C_S_IICIF_MASK; + + // wait transfer complete + if (timeout_status_poll(obj, I2C_S_TCF_MASK)) { + return 2; + } + + // check if we received the ACK or not + return obj->i2c->S & I2C_S_RXAK_MASK ? 1 : 0; +} + +// this function waits the end of a rx transfer and return the status of the transaction: +// 0: OK +// 1: failure +static int i2c_wait_end_rx_transfer(i2c_t *obj) { + // wait for the end of the rx transfer + if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) { + return 1; + } + + obj->i2c->S |= I2C_S_IICIF_MASK; + + return 0; +} + +static void i2c_send_nack(i2c_t *obj) { + obj->i2c->C1 |= I2C_C1_TXAK_MASK; // NACK +} + +static void i2c_send_ack(i2c_t *obj) { + obj->i2c->C1 &= ~I2C_C1_TXAK_MASK; // ACK +} + +static int i2c_do_write(i2c_t *obj, int value) { + // write the data + obj->i2c->D = value; + + // init and wait the end of the transfer + return i2c_wait_end_tx_transfer(obj); +} + +static int i2c_do_read(i2c_t *obj, char * data, int last) { + if (last) { + i2c_send_nack(obj); + } else { + i2c_send_ack(obj); + } + + *data = (obj->i2c->D & 0xFF); + + // start rx transfer and wait the end of the transfer + return i2c_wait_end_rx_transfer(obj); +} + +void i2c_frequency(i2c_t *obj, int hz) { + uint8_t icr = 0; + uint8_t mult = 0; + uint32_t error = 0; + uint32_t p_error = 0xffffffff; + uint32_t ref = 0; + uint8_t i, j; + // bus clk + uint32_t PCLK = bus_frequency(); + uint32_t pulse = PCLK / (hz * 2); + + // we look for the values that minimize the error + + // test all the MULT values + for (i = 1; i < 5; i*=2) { + for (j = 0; j < 0x40; j++) { + ref = PCLK / (i*ICR[j]); + if (ref > (uint32_t)hz) + continue; + error = hz - ref; + if (error < p_error) { + icr = j; + mult = i/2; + p_error = error; + } + } + } + pulse = icr | (mult << 6); + + // I2C Rate + obj->i2c->F = pulse; +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { + int count; + char dummy_read, *ptr; + + if (i2c_start(obj)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + if (i2c_do_write(obj, (address | 0x01))) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + // set rx mode + obj->i2c->C1 &= ~I2C_C1_TX_MASK; + + // Read in bytes + for (count = 0; count < (length); count++) { + ptr = (count == 0) ? &dummy_read : &data[count - 1]; + uint8_t stop_ = (count == (length - 1)) ? 1 : 0; + if (i2c_do_read(obj, ptr, stop_)) { + i2c_stop(obj); + return count; + } + } + + // If not repeated start, send stop. + if (stop) + i2c_stop(obj); + + // last read + data[count-1] = obj->i2c->D; + + return length; +} +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { + int i; + + if (i2c_start(obj)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + if (i2c_do_write(obj, (address & 0xFE))) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + for (i = 0; i < length; i++) { + if(i2c_do_write(obj, data[i])) { + i2c_stop(obj); + return i; + } + } + + if (stop) + i2c_stop(obj); + + return length; +} + +void i2c_reset(i2c_t *obj) { + i2c_stop(obj); +} + +int i2c_byte_read(i2c_t *obj, int last) { + char data; + + // set rx mode + obj->i2c->C1 &= ~I2C_C1_TX_MASK; + + // Setup read + i2c_do_read(obj, &data, last); + + // set tx mode + obj->i2c->C1 |= I2C_C1_TX_MASK; + return obj->i2c->D; +} + +int i2c_byte_write(i2c_t *obj, int data) { + // set tx mode + obj->i2c->C1 |= I2C_C1_TX_MASK; + + return !i2c_do_write(obj, (data & 0xFF)); +} + + +#if DEVICE_I2CSLAVE +void i2c_slave_mode(i2c_t *obj, int enable_slave) { + if (enable_slave) { + // set slave mode + obj->i2c->C1 &= ~I2C_C1_MST_MASK; + obj->i2c->C1 |= I2C_C1_IICIE_MASK; + } else { + // set master mode + obj->i2c->C1 |= I2C_C1_MST_MASK; + } +} + +int i2c_slave_receive(i2c_t *obj) { + switch(obj->i2c->S) { + // read addressed + case 0xE6: + return 1; + // write addressed + case 0xE2: + return 3; + default: + return 0; + } +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) { + uint8_t dummy_read; + uint8_t * ptr; + int count; + + // set rx mode + obj->i2c->C1 &= ~I2C_C1_TX_MASK; + + // first dummy read + dummy_read = obj->i2c->D; + if (i2c_wait_end_rx_transfer(obj)) + return 0; + + // read address + dummy_read = obj->i2c->D; + if (i2c_wait_end_rx_transfer(obj)) + return 0; + + // read (length - 1) bytes + for (count = 0; count < (length - 1); count++) { + data[count] = obj->i2c->D; + if (i2c_wait_end_rx_transfer(obj)) + return count; + } + + // read last byte + ptr = (length == 0) ? &dummy_read : (uint8_t *)&data[count]; + *ptr = obj->i2c->D; + + return (length) ? (count + 1) : 0; +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) { + int i, count = 0; + + // set tx mode + obj->i2c->C1 |= I2C_C1_TX_MASK; + + for (i = 0; i < length; i++) { + if (i2c_do_write(obj, data[count++]) == 2) + return i; + } + + // set rx mode + obj->i2c->C1 &= ~I2C_C1_TX_MASK; + + // dummy rx transfer needed + // otherwise the master cannot generate a stop bit + obj->i2c->D; + if (i2c_wait_end_rx_transfer(obj) == 2) + return count; + + return count; +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { + obj->i2c->A1 = address & 0xfe; +} +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/objects.h Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,77 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + uint32_t port; + uint32_t pin; + uint32_t ch; +}; + +struct port_s { + __IO uint32_t *reg_dir; + __IO uint32_t *reg_out; + __I uint32_t *reg_in; + PortName port; + uint32_t mask; +}; + +struct pwmout_s { + __IO uint32_t *MOD; + __IO uint32_t *CNT; + __IO uint32_t *CnV; +}; + +struct serial_s { + UART_Type *uart; + int index; +}; + +struct analogin_s { + ADCName adc; +}; + +#if DEVICE_ANALOGOUT +struct dac_s { + DACName dac; +}; +#endif + +struct i2c_s { + I2C_Type *i2c; +}; + +struct spi_s { + SPI_Type *spi; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/pinmap.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pinmap.h" + +void pin_function(PinName pin, int function) { + MBED_ASSERT(pin != (PinName)NC); + + uint32_t port_n = (uint32_t)pin >> PORT_SHIFT; + uint32_t pin_n = (uint32_t)(pin & 0x7C) >> 2; + + SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port_n); + __IO uint32_t* pin_pcr = &(((PORT_Type *)(PORTA_BASE + 0x1000 * port_n)))->PCR[pin_n]; + + // pin mux bits: [10:8] -> 11100000000 = (0x700) + *pin_pcr = (*pin_pcr & ~0x700) | (function << 8); +} + +void pin_mode(PinName pin, PinMode mode) { + MBED_ASSERT(pin != (PinName)NC); + __IO uint32_t* pin_pcr = (__IO uint32_t*)(PORTA_BASE + pin); + + // pin pullup bits: [1:0] -> 11 = (0x3) + *pin_pcr = (*pin_pcr & ~0x3) | mode; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/port_api.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,72 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" + +PinName port_pin(PortName port, int pin_n) { + return (PinName)((port << PORT_SHIFT) | (pin_n << 2)); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { + obj->port = port; + obj->mask = mask; + + GPIO_Type *reg = (GPIO_Type *)(PTA_BASE + port * 0x40); + + obj->reg_out = ®->PDOR; + obj->reg_in = ®->PDIR; + obj->reg_dir = ®->PDDR; + + uint32_t i; + // The function is set per pin: reuse gpio logic + for (i=0; i<32; i++) { + if (obj->mask & (1<<i)) { + gpio_set(port_pin(obj->port, i)); + } + } + + port_dir(obj, dir); +} + +void port_mode(port_t *obj, PinMode mode) { + uint32_t i; + // The mode is set per pin: reuse pinmap logic + for (i=0; i<32; i++) { + if (obj->mask & (1<<i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) { + switch (dir) { + case PIN_INPUT : + *obj->reg_dir &= ~obj->mask; + break; + case PIN_OUTPUT: + *obj->reg_dir |= obj->mask; + break; + } +} + +void port_write(port_t *obj, int value) { + *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask); +} + +int port_read(port_t *obj) { + return (*obj->reg_in & obj->mask); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/pwmout_api.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,107 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pwmout_api.h" + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +static float pwm_clock = 0; + +void pwmout_init(pwmout_t* obj, PinName pin) { + // determine the channel + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(pwm != (PWMName)NC); + + uint32_t clkdiv = 0; + float clkval = SystemCoreClock / 1000000.0f; + + while (clkval > 1) { + clkdiv++; + clkval /= 2.0; + if (clkdiv == 7) + break; + } + + pwm_clock = clkval; + unsigned int port = (unsigned int)pin >> PORT_SHIFT; + unsigned int ftm_n = (pwm >> TPM_SHIFT); + unsigned int ch_n = (pwm & 0xFF); + + SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port); + SIM->SCGC6 |= 1 << (SIM_SCGC6_FTM0_SHIFT + ftm_n); + + FTM_Type *ftm = (FTM_Type *)(FTM0_BASE + 0x1000 * ftm_n); + ftm->CONF |= FTM_CONF_BDMMODE(3); + ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(clkdiv); // (clock)MHz / clkdiv ~= (0.75)MHz + ftm->CONTROLS[ch_n].CnSC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK); /* No Interrupts; High True pulses on Edge Aligned PWM */ + + obj->CnV = &ftm->CONTROLS[ch_n].CnV; + obj->MOD = &ftm->MOD; + obj->CNT = &ftm->CNT; + + // default to 20ms: standard for servos, and fine for e.g. brightness control + pwmout_period_ms(obj, 20); + pwmout_write(obj, 0); + + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); +} + +void pwmout_free(pwmout_t* obj) {} + +void pwmout_write(pwmout_t* obj, float value) { + if (value < 0.0) { + value = 0.0; + } else if (value > 1.0) { + value = 1.0; + } + + *obj->CnV = (uint32_t)((float)(*obj->MOD + 1) * value); +} + +float pwmout_read(pwmout_t* obj) { + float v = (float)(*obj->CnV) / (float)(*obj->MOD + 1); + return (v > 1.0) ? (1.0) : (v); +} + +void pwmout_period(pwmout_t* obj, float seconds) { + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) { + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t* obj, int us) { + float dc = pwmout_read(obj); + *obj->MOD = (uint32_t)(pwm_clock * (float)us) - 1; + pwmout_write(obj, dc); +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) { + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) { + *obj->CnV = (uint32_t)(pwm_clock * (float)us); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc.api.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,85 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "rtc_api.h" + +static void init(void) { + // enable PORTC clock + SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK; + + // enable RTC clock + SIM->SCGC6 |= SIM_SCGC6_RTC_MASK; + + // OSC32 as source + SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK; + SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0); +} + +void rtc_init(void) { + init(); + + // Enable the oscillator + RTC->CR |= RTC_CR_OSCE_MASK; + + //Configure the TSR. default value: 1 + RTC->TSR = 1; + + // enable counter + RTC->SR |= RTC_SR_TCE_MASK; +} + +void rtc_free(void) { + // [TODO] +} + +/* + * Little check routine to see if the RTC has been enabled + * 0 = Disabled, 1 = Enabled + */ +int rtc_isenabled(void) { + // even if the RTC module is enabled, + // as we use RTC_CLKIN and an external clock, + // we need to reconfigure the pins. That is why we + // call init() if the rtc is enabled + + // if RTC not enabled return 0 + SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK; + SIM->SCGC6 |= SIM_SCGC6_RTC_MASK; + if ((RTC->SR & RTC_SR_TCE_MASK) == 0) + return 0; + + init(); + return 1; +} + +time_t rtc_read(void) { + return RTC->TSR; +} + +void rtc_write(time_t t) { + // disable counter + RTC->SR &= ~RTC_SR_TCE_MASK; + + // we do not write 0 into TSR + // to avoid invalid time + if (t == 0) + t = 1; + + // write seconds + RTC->TSR = t; + + // re-enable counter + RTC->SR |= RTC_SR_TCE_MASK; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/serial_api.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,301 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "serial_api.h" + +#include <string.h> + +#include "cmsis.h" +#include "pinmap.h" +#include "clk_freqs.h" +#include "PeripheralPins.h" + +#define UART_NUM 3 + +static uint32_t serial_irq_ids[UART_NUM] = {0}; +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + // determine the UART to use + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)uart != NC); + + obj->uart = (UART_Type *)uart; + // enable clk + switch (uart) { + case UART_0: + mcgpllfll_frequency(); + SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; + break; + case UART_1: + mcgpllfll_frequency(); + SIM->SCGC4 |= SIM_SCGC4_UART1_MASK; + break; + case UART_2: + SIM->SCGC4 |= SIM_SCGC4_UART2_MASK; + break; + } + // Disable UART before changing registers + obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK); + + switch (uart) { + case UART_0: + obj->index = 0; + break; + case UART_1: + obj->index = 1; + break; + case UART_2: + obj->index = 2; + break; + } + + // set default baud rate and format + serial_baud (obj, 9600); + serial_format(obj, 8, ParityNone, 1); + + // pinout the chosen uart + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + // set rx/tx pins in PullUp mode + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } + + obj->uart->C2 |= (UART_C2_RE_MASK | UART_C2_TE_MASK); + + if (uart == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + serial_irq_ids[obj->index] = 0; +} + +void serial_baud(serial_t *obj, int baudrate) { + // save C2 state + uint8_t c2_state = (obj->uart->C2 & (UART_C2_RE_MASK | UART_C2_TE_MASK)); + + // Disable UART before changing registers + obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK); + + uint32_t PCLK; + if (obj->uart != UART2) { + PCLK = mcgpllfll_frequency(); + } + else { + PCLK = bus_frequency(); + } + + uint16_t DL = PCLK / (16 * baudrate); + uint32_t BRFA = (2 * PCLK) / baudrate - 32 * DL; + + // set BDH and BDL + obj->uart->BDH = (obj->uart->BDH & ~(0x1f)) | ((DL >> 8) & 0x1f); + obj->uart->BDL = (obj->uart->BDL & ~(0xff)) | ((DL >> 0) & 0xff); + + obj->uart->C4 &= ~0x1F; + obj->uart->C4 |= BRFA & 0x1F; + + // restore C2 state + obj->uart->C2 |= c2_state; +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); + MBED_ASSERT((data_bits == 8) || (data_bits == 9)); + + // save C2 state + uint32_t c2_state = (obj->uart->C2 & (UART_C2_RE_MASK | UART_C2_TE_MASK)); + + // Disable UART before changing registers + obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK); + + // 8 data bits = 0 ... 9 data bits = 1 + data_bits -= 8; + + uint32_t parity_enable, parity_select; + switch (parity) { + case ParityNone: + parity_enable = 0; + parity_select = 0; + break; + case ParityOdd : + parity_enable = 1; + parity_select = 1; + data_bits++; + break; + case ParityEven: + parity_enable = 1; + parity_select = 0; + data_bits++; + break; + default: + break; + } + + stop_bits -= 1; + + uint32_t m10 = 0; + + // 9 data bits + parity - only uart0 support + if (data_bits == 2) { + MBED_ASSERT(obj->index == 0); + data_bits = 0; + m10 = 1; + } + + // data bits, parity and parity mode + obj->uart->C1 = ((data_bits << 4) + | (parity_enable << 1) + | (parity_select << 0)); + + //enable 10bit mode if needed + if (obj->index == 0) { + obj->uart->C4 &= ~UART_C4_M10_MASK; + obj->uart->C4 |= (m10 << UART_C4_M10_SHIFT); + } + + // stop bits + obj->uart->BDH &= ~UART_BDH_SBR_MASK; + obj->uart->BDH |= (stop_bits << UART_BDH_SBR_SHIFT); + + // restore C2 state + obj->uart->C2 |= c2_state; +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint8_t status, uint32_t index) { + if (serial_irq_ids[index] != 0) { + if (status & UART_S1_TDRE_MASK) + irq_handler(serial_irq_ids[index], TxIrq); + + if (status & UART_S1_RDRF_MASK) + irq_handler(serial_irq_ids[index], RxIrq); + } +} + +void uart0_irq() {uart_irq(UART0->S1, 0);} +void uart1_irq() {uart_irq(UART1->S1, 1);} +void uart2_irq() {uart_irq(UART2->S1, 2);} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + switch ((int)obj->uart) { + case UART_0: + irq_n=UART0_RX_TX_IRQn; + vector = (uint32_t)&uart0_irq; + break; + case UART_1: + irq_n=UART1_RX_TX_IRQn; + vector = (uint32_t)&uart1_irq; + break; + case UART_2: + irq_n=UART2_RX_TX_IRQn; + vector = (uint32_t)&uart2_irq; + break; + } + + if (enable) { + switch (irq) { + case RxIrq: + obj->uart->C2 |= (UART_C2_RIE_MASK); + break; + case TxIrq: + obj->uart->C2 |= (UART_C2_TIE_MASK); + break; + } + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + + } else { // disable + int all_disabled = 0; + SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); + switch (irq) { + case RxIrq: + obj->uart->C2 &= ~(UART_C2_RIE_MASK); + break; + case TxIrq: + obj->uart->C2 &= ~(UART_C2_TIE_MASK); + break; + } + switch (other_irq) { + case RxIrq: + all_disabled = (obj->uart->C2 & (UART_C2_RIE_MASK)) == 0; + break; + case TxIrq: + all_disabled = (obj->uart->C2 & (UART_C2_TIE_MASK)) == 0; + break; + } + if (all_disabled) + NVIC_DisableIRQ(irq_n); + } +} + +int serial_getc(serial_t *obj) { + while (!serial_readable(obj)); + return obj->uart->D; +} + +void serial_putc(serial_t *obj, int c) { + while (!serial_writable(obj)); + obj->uart->D = c; +} + +int serial_readable(serial_t *obj) { + + return (obj->uart->S1 & UART_S1_RDRF_MASK); +} + +int serial_writable(serial_t *obj) { + + return (obj->uart->S1 & UART_S1_TDRE_MASK); +} + +void serial_clear(serial_t *obj) { +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { + obj->uart->C2 |= UART_C2_SBK_MASK; +} + +void serial_break_clear(serial_t *obj) { + obj->uart->C2 &= ~UART_C2_SBK_MASK; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "sleep_api.h" +#include "cmsis.h" + +//Normal wait mode +void sleep(void) +{ + SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK; + + //Normal sleep mode for ARM core: + SCB->SCR = 0; + __WFI(); +} + +//Very low-power stop mode +void deepsleep(void) +{ + //Check if PLL/FLL is enabled: + uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0); + + SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK; + SMC->PMCTRL = SMC_PMCTRL_STOPM(2); + + //Deep sleep for ARM core: + SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos; + + __WFI(); + + //Switch back to PLL as clock source if needed + //The interrupt that woke up the device will run at reduced speed + if (PLL_FLL_en) { + if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */ + while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */ + MCG->C1 &= ~MCG_C1_CLKS_MASK; + } + +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/spi_api.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,151 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "spi_api.h" + +#include <math.h> + +#include "cmsis.h" +#include "pinmap.h" +#include "clk_freqs.h" +#include "PeripheralPins.h" + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + // determine the SPI to use + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + + obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->spi != NC); + + SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK; + SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK; + + obj->spi->MCR &= ~(SPI_MCR_MDIS_MASK | SPI_MCR_HALT_MASK); + //obj->spi->MCR |= SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK; + + // set default format and frequency + if (ssel == NC) { + spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master + } else { + spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave + } + spi_frequency(obj, 1000000); + + // not halt in the debug mode + obj->spi->SR |= SPI_SR_EOQF_MASK; + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) { + // [TODO] +} +void spi_format(spi_t *obj, int bits, int mode, int slave) { + MBED_ASSERT((bits > 4) || (bits < 16)); + MBED_ASSERT((mode >= 0) && (mode <= 3)); + + uint32_t polarity = (mode & 0x2) ? 1 : 0; + uint32_t phase = (mode & 0x1) ? 1 : 0; + + // set master/slave + obj->spi->MCR &= ~SPI_MCR_MSTR_MASK; + obj->spi->MCR |= ((!slave) << SPI_MCR_MSTR_SHIFT); + + // CTAR0 is used + obj->spi->CTAR[0] &= ~(SPI_CTAR_CPHA_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_FMSZ_MASK); + obj->spi->CTAR[0] |= (polarity << SPI_CTAR_CPOL_SHIFT) | (phase << SPI_CTAR_CPHA_SHIFT) | ((bits - 1) << SPI_CTAR_FMSZ_SHIFT); +} + +static const uint8_t baudrate_prescaler[] = {2,3,5,7}; +static const uint16_t baudrate_scaler[] = {2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768}; + +void spi_frequency(spi_t *obj, int hz) { + uint32_t f_error = 0; + uint32_t p_error = 0xffffffff; + uint32_t ref = 0; + uint32_t br = 0; + uint32_t ref_spr = 0; + uint32_t ref_prescaler = 0; + uint32_t ref_dr = 0; + + // bus clk + uint32_t PCLK = bus_frequency(); + + for (uint32_t i = 0; i < 4; i++) { + for (br = 0; br <= 15; br++) { + for (uint32_t dr = 0; dr < 2; dr++) { + ref = (PCLK * (1U + dr) / baudrate_prescaler[i]) / baudrate_scaler[br]; + if (ref > (uint32_t)hz) + continue; + f_error = hz - ref; + if (f_error < p_error) { + ref_spr = br; + ref_prescaler = i; + ref_dr = dr; + p_error = f_error; + } + } + } + } + + // set PBR and BR + obj->spi->CTAR[0] &= ~(SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK | SPI_CTAR_DBR_MASK); + obj->spi->CTAR[0] |= (ref_prescaler << SPI_CTAR_PBR_SHIFT) | (ref_spr << SPI_CTAR_BR_SHIFT) | (ref_dr << SPI_CTAR_DBR_SHIFT); +} + +static inline int spi_writeable(spi_t *obj) { + return (obj->spi->SR & SPI_SR_TFFF_MASK) ? 1 : 0; +} + +static inline int spi_readable(spi_t *obj) { + return (obj->spi->SR & SPI_SR_RFDF_MASK) ? 1 : 0; +} + +int spi_master_write(spi_t *obj, int value) { + //clear RX buffer flag + obj->spi->SR |= SPI_SR_RFDF_MASK; + // wait tx buffer empty + while(!spi_writeable(obj)); + obj->spi->PUSHR = SPI_PUSHR_TXDATA(value & 0xffff) /*| SPI_PUSHR_EOQ_MASK*/; + + // wait rx buffer full + while (!spi_readable(obj)); + return obj->spi->POPR; +} + +int spi_slave_receive(spi_t *obj) { + return spi_readable(obj); +} + +int spi_slave_read(spi_t *obj) { + obj->spi->SR |= SPI_SR_RFDF_MASK; + return obj->spi->POPR; +} + +void spi_slave_write(spi_t *obj, int value) { + while (!spi_writeable(obj)); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Freescale/TARGET_K20XX/us_ticker.c Thu Jan 15 19:30:07 2015 +0000 @@ -0,0 +1,159 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include <stddef.h> +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "clk_freqs.h" + +#define PIT_TIMER PIT->CHANNEL[0] +#define PIT_TIMER_IRQ PIT0_IRQn +#define PIT_TICKER PIT->CHANNEL[1] +#define PIT_TICKER_IRQ PIT1_IRQn + +static void timer_init(void); +static void ticker_init(void); + + +static int us_ticker_inited = 0; +static uint32_t clk_mhz; + +void us_ticker_init(void) { + if (us_ticker_inited) + return; + us_ticker_inited = 1; + + SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT + PIT->MCR = 0; // Enable PIT + + clk_mhz = bus_frequency() / 1000000; + + timer_init(); + ticker_init(); +} + +/****************************************************************************** + * Timer for us timing. + * + * The K20D5M does not have a prescaler on its PIT timer nor the option + * to chain timers, which is why a software timer is required to get 32-bit + * word length. + ******************************************************************************/ +static volatile uint32_t msb_counter = 0; +static uint32_t timer_ldval = 0; + +static void timer_isr(void) { + msb_counter++; + PIT_TIMER.TFLG = 1; +} + +static void timer_init(void) { + //CLZ counts the leading zeros, returning number of bits not used by clk_mhz + timer_ldval = clk_mhz << __CLZ(clk_mhz); + + PIT_TIMER.LDVAL = timer_ldval; // 1us + PIT_TIMER.TCTRL |= PIT_TCTRL_TIE_MASK; + PIT_TIMER.TCTRL |= PIT_TCTRL_TEN_MASK; // Start timer 0 + + NVIC_SetVector(PIT_TIMER_IRQ, (uint32_t)timer_isr); + NVIC_EnableIRQ(PIT_TIMER_IRQ); +} + +uint32_t us_ticker_read() { + if (!us_ticker_inited) + us_ticker_init(); + + uint32_t retval; + __disable_irq(); + retval = (timer_ldval - PIT_TIMER.CVAL) / clk_mhz; //Hardware bits + retval |= msb_counter << __CLZ(clk_mhz); //Software bits + + if (PIT_TIMER.TFLG == 1) { //If overflow bit is set, force it to be handled + timer_isr(); //Handle IRQ, read again to make sure software/hardware bits are synced + NVIC_ClearPendingIRQ(PIT_TIMER_IRQ); + return us_ticker_read(); + } + + __enable_irq(); + return retval; +} + +/****************************************************************************** + * Timer Event + * + * It schedules interrupts at given (32bit)us interval of time. + * It is implemented using PIT channel 1, since no prescaler is available, + * some bits are implemented in software. + ******************************************************************************/ +static void ticker_isr(void); + +static void ticker_init(void) { + /* Set interrupt handler */ + NVIC_SetVector(PIT_TICKER_IRQ, (uint32_t)ticker_isr); + NVIC_EnableIRQ(PIT_TICKER_IRQ); +} + +void us_ticker_disable_interrupt(void) { + PIT_TICKER.TCTRL &= ~PIT_TCTRL_TIE_MASK; +} + +void us_ticker_clear_interrupt(void) { + // we already clear interrupt in lptmr_isr +} + +static uint32_t us_ticker_int_counter = 0; + +inline static void ticker_set(uint32_t count) { + PIT_TICKER.TCTRL = 0; + PIT_TICKER.LDVAL = count; + PIT_TICKER.TCTRL = PIT_TCTRL_TIE_MASK | PIT_TCTRL_TEN_MASK; +} + +static void ticker_isr(void) { + // Clear IRQ flag + PIT_TICKER.TFLG = 1; + + if (us_ticker_int_counter > 0) { + ticker_set(0xFFFFFFFF); + us_ticker_int_counter--; + } else { + // This function is going to disable the interrupts if there are + // no other events in the queue + us_ticker_irq_handler(); + } +} + +void us_ticker_set_interrupt(timestamp_t timestamp) { + int delta = (int)((uint32_t)timestamp - us_ticker_read()); + if (delta <= 0) { + // This event was in the past: + us_ticker_irq_handler(); + return; + } + + //Calculate how much falls outside the 32-bit after multiplying with clk_mhz + //We shift twice 16-bit to keep everything within the 32-bit variable + us_ticker_int_counter = (uint32_t)(delta >> 16); + us_ticker_int_counter *= clk_mhz; + us_ticker_int_counter >>= 16; + + uint32_t us_ticker_int_remainder = (uint32_t)delta * clk_mhz; + if (us_ticker_int_remainder == 0) { + ticker_set(0xFFFFFFFF); + us_ticker_int_counter--; + } else { + ticker_set(us_ticker_int_remainder); + } +}