Semtech
Driver for the SX1272 RF Transceiver
Dependents: LORA-SX1272MB2xAS-PP mDot_Semtech_LoRaWAN_Stack LoRaWAN-demo-72_mdotIKS01A1 lora-project ... more
Revision 0:45c4f0364ca4, committed 2016-01-05
- Comitter:
- mluis
- Date:
- Tue Jan 05 16:43:48 2016 +0000
- Child:
- 1:b0372ef620d0
- Commit message:
- Library creation based on SX1276Lib and https://github.com/Lora-net/LoRaMac-node
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/LICENSE.txt Tue Jan 05 16:43:48 2016 +0000 @@ -0,0 +1,25 @@ +--- Revised BSD License --- +Copyright (c) 2013, SEMTECH S.A. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Semtech corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL SEMTECH S.A. BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/debug/debug.h Tue Jan 05 16:43:48 2016 +0000
@@ -0,0 +1,61 @@
+/* Copyright (c) 2012 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef DEBUG_H
+#define DEBUG_H
+
+/** @file debug.h */
+
+#ifndef NDEBUG
+
+#include <stdarg.h>
+#include <stdio.h>
+
+/** Output a debug message
+ *
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug(const char *format, ...) {
+ va_list args;
+ va_start(args, format);
+ vfprintf(stderr, format, args);
+ va_end(args);
+}
+
+/** Conditionally output a debug message
+ *
+ * @param condition output only if condition is true
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug_if(bool condition, const char *format, ...) {
+ if(condition) {
+ va_list args;
+ va_start(args, format);
+ vfprintf(stderr, format, args);
+ va_end(args);
+ }
+}
+
+#else
+
+static inline void debug(const char *format, ...) {}
+static inline void debug(bool condition, const char *format, ...) {}
+
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/enums/enums.h Tue Jan 05 16:43:48 2016 +0000
@@ -0,0 +1,130 @@
+/*
+ / _____) _ | |
+( (____ _____ ____ _| |_ _____ ____| |__
+ \____ \| ___ | (_ _) ___ |/ ___) _ \
+ _____) ) ____| | | || |_| ____( (___| | | |
+(______/|_____)_|_|_| \__)_____)\____)_| |_|
+ ( C )2015 Semtech
+
+Description: -
+
+License: Revised BSD License, see LICENSE.TXT file include in the project
+
+Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
+*/
+#ifndef __ENUMS_H__
+#define __ENUMS_H__
+
+/*!
+ * Radio driver internal state machine states definition
+ */
+typedef enum RadioState
+{
+ RF_IDLE = 0,
+ RF_RX_RUNNING,
+ RF_TX_RUNNING,
+ RF_CAD,
+}RadioState_t;
+
+/*!
+ * Type of the modem. [LORA / FSK]
+ */
+typedef enum ModemType
+{
+ MODEM_FSK = 0,
+ MODEM_LORA
+}RadioModems_t;
+
+/*!
+ * Type of the supported board. [SX1272MB1DAS / SX1272MB1DCS]
+ */
+typedef enum BoardType
+{
+ SX1272MB1DAS = 0,
+ SX1272MB1DCS,
+ NA_MOTE_72,
+ UNKNOWN
+}BoardType_t;
+
+/*!
+ * Radio FSK modem parameters
+ */
+typedef struct
+{
+ int8_t Power;
+ uint32_t Fdev;
+ uint32_t Bandwidth;
+ uint32_t BandwidthAfc;
+ uint32_t Datarate;
+ uint16_t PreambleLen;
+ bool FixLen;
+ uint8_t PayloadLen;
+ bool CrcOn;
+ bool IqInverted;
+ bool RxContinuous;
+ uint32_t TxTimeout;
+}RadioFskSettings_t;
+
+/*!
+ * Radio FSK packet handler state
+ */
+typedef struct
+{
+ uint8_t PreambleDetected;
+ uint8_t SyncWordDetected;
+ int8_t RssiValue;
+ int32_t AfcValue;
+ uint8_t RxGain;
+ uint16_t Size;
+ uint16_t NbBytes;
+ uint8_t FifoThresh;
+ uint8_t ChunkSize;
+}RadioFskPacketHandler_t;
+
+/*!
+ * Radio LoRa modem parameters
+ */
+typedef struct
+{
+ int8_t Power;
+ uint32_t Bandwidth;
+ uint32_t Datarate;
+ bool LowDatarateOptimize;
+ uint8_t Coderate;
+ uint16_t PreambleLen;
+ bool FixLen;
+ uint8_t PayloadLen;
+ bool CrcOn;
+ bool FreqHopOn;
+ uint8_t HopPeriod;
+ bool IqInverted;
+ bool RxContinuous;
+ uint32_t TxTimeout;
+}RadioLoRaSettings_t;
+
+/*!
+ * Radio LoRa packet handler state
+ */
+typedef struct
+{
+ int8_t SnrValue;
+ int8_t RssiValue;
+ uint8_t Size;
+}RadioLoRaPacketHandler_t;
+
+/*!
+ * Radio Settings
+ */
+typedef struct
+{
+ RadioState State;
+ ModemType Modem;
+ uint32_t Channel;
+ RadioFskSettings_t Fsk;
+ RadioFskPacketHandler_t FskPacketHandler;
+ RadioLoRaSettings_t LoRa;
+ RadioLoRaPacketHandler_t LoRaPacketHandler;
+}RadioSettings_t;
+
+
+#endif //__ENUMS_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/radio/radio.cpp Tue Jan 05 16:43:48 2016 +0000
@@ -0,0 +1,20 @@
+/*
+ / _____) _ | |
+( (____ _____ ____ _| |_ _____ ____| |__
+ \____ \| ___ | (_ _) ___ |/ ___) _ \
+ _____) ) ____| | | || |_| ____( (___| | | |
+(______/|_____)_|_|_| \__)_____)\____)_| |_|
+ (C) 2015 Semtech
+
+Description: Interface for the radios, contains the main functions that a radio needs, and 5 callback functions
+
+License: Revised BSD License, see LICENSE.TXT file include in the project
+
+Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
+*/
+#include "radio.h"
+
+Radio::Radio( RadioEvents_t *events )
+{
+ this->RadioEvents = events;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/radio/radio.h Tue Jan 05 16:43:48 2016 +0000
@@ -0,0 +1,346 @@
+/*
+ / _____) _ | |
+( (____ _____ ____ _| |_ _____ ____| |__
+ \____ \| ___ | (_ _) ___ |/ ___) _ \
+ _____) ) ____| | | || |_| ____( (___| | | |
+(______/|_____)_|_|_| \__)_____)\____)_| |_|
+ (C) 2015 Semtech
+
+Description: Interface for the radios, contains the main functions that a radio needs, and 5 callback functions
+
+License: Revised BSD License, see LICENSE.TXT file include in the project
+
+Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
+*/
+#ifndef __RADIO_H__
+#define __RADIO_H__
+
+#include "mbed.h"
+
+#include "./enums/enums.h"
+
+/*!
+ * @brief Radio driver callback functions
+ */
+typedef struct
+{
+ /*!
+ * @brief Tx Done callback prototype.
+ */
+ void ( *TxDone )( void );
+ /*!
+ * @brief Tx Timeout callback prototype.
+ */
+ void ( *TxTimeout )( void );
+ /*!
+ * @brief Rx Done callback prototype.
+ *
+ * @param [IN] payload Received buffer pointer
+ * @param [IN] size Received buffer size
+ * @param [IN] rssi RSSI value computed while receiving the frame [dBm]
+ * @param [IN] snr Raw SNR value given by the radio hardware
+ * FSK : N/A ( set to 0 )
+ * LoRa: SNR value in dB
+ */
+ void ( *RxDone )( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr );
+ /*!
+ * @brief Rx Timeout callback prototype.
+ */
+ void ( *RxTimeout )( void );
+ /*!
+ * @brief Rx Error callback prototype.
+ */
+ void ( *RxError )( void );
+ /*!
+ * \brief FHSS Change Channel callback prototype.
+ *
+ * \param [IN] currentChannel Index number of the current channel
+ */
+ void ( *FhssChangeChannel )( uint8_t currentChannel );
+
+ /*!
+ * @brief CAD Done callback prototype.
+ *
+ * @param [IN] channelDetected Channel Activity detected during the CAD
+ */
+ void ( *CadDone ) ( bool channelActivityDetected );
+}RadioEvents_t;
+
+/*!
+ * Interface for the radios, contains the main functions that a radio needs, and 5 callback functions
+ */
+class Radio
+{
+protected:
+ RadioEvents_t* RadioEvents;
+
+public:
+ //-------------------------------------------------------------------------
+ // Constructor
+ //-------------------------------------------------------------------------
+ /*!
+ * @brief Constructor of the radio object, the parameters are the callback functions described in the header.
+ *
+ * @param [IN] events Structure containing the driver callback functions
+ */
+ Radio( RadioEvents_t *events );
+ virtual ~Radio( ) {};
+
+ //-------------------------------------------------------------------------
+ // Pure virtual functions
+ //-------------------------------------------------------------------------
+
+ /*!
+ * @brief Initializes the radio
+ *
+ * @param [IN] events Structure containing the driver callback functions
+ */
+ virtual void Init( RadioEvents_t *events ) = 0;
+
+ /*!
+ * @brief Return current radio status
+ *
+ * @param status Radio status.[RF_IDLE, RF_RX_RUNNING, RF_TX_RUNNING]
+ */
+ virtual RadioState GetStatus( void ) = 0;
+
+ /*!
+ * @brief Configures the radio with the given modem
+ *
+ * @param [IN] modem Modem to be used [0: FSK, 1: LoRa]
+ */
+ virtual void SetModem( RadioModems_t modem ) = 0;
+
+ /*!
+ * @brief Sets the channel frequency
+ *
+ * @param [IN] freq Channel RF frequency
+ */
+ virtual void SetChannel( uint32_t freq ) = 0;
+
+ /*!
+ * @brief Sets the channels configuration
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] freq Channel RF frequency
+ * @param [IN] rssiThresh RSSI threshold
+ *
+ * @retval isFree [true: Channel is free, false: Channel is not free]
+ */
+ virtual bool IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh ) = 0;
+
+ /*!
+ * @brief Generates a 32 bits random value based on the RSSI readings
+ *
+ * \remark This function sets the radio in LoRa modem mode and disables
+ * all interrupts.
+ * After calling this function either Radio.SetRxConfig or
+ * Radio.SetTxConfig functions must be called.
+ *
+ * @retval randomValue 32 bits random value
+ */
+ virtual uint32_t Random( void )= 0;
+
+ /*!
+ * @brief Sets the reception parameters
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] bandwidth Sets the bandwidth
+ * FSK : >= 2600 and <= 250000 Hz
+ * LoRa: [0: 125 kHz, 1: 250 kHz,
+ * 2: 500 kHz, 3: Reserved]
+ * @param [IN] datarate Sets the Datarate
+ * FSK : 600..300000 bits/s
+ * LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ * 10: 1024, 11: 2048, 12: 4096 chips]
+ * @param [IN] coderate Sets the coding rate ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * @param [IN] bandwidthAfc Sets the AFC Bandwidth ( FSK only )
+ * FSK : >= 2600 and <= 250000 Hz
+ * LoRa: N/A ( set to 0 )
+ * @param [IN] preambleLen Sets the Preamble length ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: Length in symbols ( the hardware adds 4 more symbols )
+ * @param [IN] symbTimeout Sets the RxSingle timeout value ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: timeout in symbols
+ * @param [IN] fixLen Fixed length packets [0: variable, 1: fixed]
+ * @param [IN] payloadLen Sets payload length when fixed lenght is used
+ * @param [IN] crcOn Enables/Disables the CRC [0: OFF, 1: ON]
+ * @param [IN] freqHopOn Enables disables the intra-packet frequency hopping [0: OFF, 1: ON] (LoRa only)
+ * @param [IN] hopPeriod Number of symbols bewteen each hop (LoRa only)
+ * @param [IN] iqInverted Inverts IQ signals ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [0: not inverted, 1: inverted]
+ * @param [IN] rxContinuous Sets the reception in continuous mode
+ * [false: single mode, true: continuous mode]
+ */
+ virtual void SetRxConfig ( RadioModems_t modem, uint32_t bandwidth,
+ uint32_t datarate, uint8_t coderate,
+ uint32_t bandwidthAfc, uint16_t preambleLen,
+ uint16_t symbTimeout, bool fixLen,
+ uint8_t payloadLen,
+ bool crcOn, bool freqHopOn, uint8_t hopPeriod,
+ bool iqInverted, bool rxContinuous ) = 0;
+
+ /*!
+ * @brief Sets the transmission parameters
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] power Sets the output power [dBm]
+ * @param [IN] fdev Sets the frequency deviation ( FSK only )
+ * FSK : [Hz]
+ * LoRa: 0
+ * @param [IN] bandwidth Sets the bandwidth ( LoRa only )
+ * FSK : 0
+ * LoRa: [0: 125 kHz, 1: 250 kHz,
+ * 2: 500 kHz, 3: Reserved]
+ * @param [IN] datarate Sets the Datarate
+ * FSK : 600..300000 bits/s
+ * LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ * 10: 1024, 11: 2048, 12: 4096 chips]
+ * @param [IN] coderate Sets the coding rate ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * @param [IN] preambleLen Sets the preamble length
+ * @param [IN] fixLen Fixed length packets [0: variable, 1: fixed]
+ * @param [IN] crcOn Enables disables the CRC [0: OFF, 1: ON]
+ * @param [IN] freqHopOn Enables disables the intra-packet frequency hopping [0: OFF, 1: ON] (LoRa only)
+ * @param [IN] hopPeriod Number of symbols bewteen each hop (LoRa only)
+ * @param [IN] iqInverted Inverts IQ signals ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [0: not inverted, 1: inverted]
+ * @param [IN] timeout Transmission timeout [us]
+ */
+ virtual void SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
+ uint32_t bandwidth, uint32_t datarate,
+ uint8_t coderate, uint16_t preambleLen,
+ bool fixLen, bool crcOn, bool freqHopOn,
+ uint8_t hopPeriod, bool iqInverted, uint32_t timeout ) = 0;
+
+ /*!
+ * @brief Checks if the given RF frequency is supported by the hardware
+ *
+ * @param [IN] frequency RF frequency to be checked
+ * @retval isSupported [true: supported, false: unsupported]
+ */
+ virtual bool CheckRfFrequency( uint32_t frequency ) = 0;
+
+ /*!
+ * @brief Computes the packet time on air for the given payload
+ *
+ * \Remark Can only be called once SetRxConfig or SetTxConfig have been called
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] pktLen Packet payload length
+ *
+ * @retval airTime Computed airTime for the given packet payload length
+ */
+ virtual double TimeOnAir ( RadioModems_t modem, uint8_t pktLen ) = 0;
+
+ /*!
+ * @brief Sends the buffer of size. Prepares the packet to be sent and sets
+ * the radio in transmission
+ *
+ * @param [IN]: buffer Buffer pointer
+ * @param [IN]: size Buffer size
+ */
+ virtual void Send( uint8_t *buffer, uint8_t size ) = 0;
+
+ /*!
+ * @brief Sets the radio in sleep mode
+ */
+ virtual void Sleep( void ) = 0;
+
+ /*!
+ * @brief Sets the radio in standby mode
+ */
+ virtual void Standby( void ) = 0;
+
+ /*!
+ * @brief Sets the radio in CAD mode
+ */
+ virtual void StartCad( void ) = 0;
+
+ /*!
+ * @brief Sets the radio in reception mode for the given time
+ * @param [IN] timeout Reception timeout [us]
+ * [0: continuous, others timeout]
+ */
+ virtual void Rx( uint32_t timeout ) = 0;
+
+ /*!
+ * @brief Sets the radio in transmission mode for the given time
+ * @param [IN] timeout Transmission timeout [us]
+ * [0: continuous, others timeout]
+ */
+ virtual void Tx( uint32_t timeout ) = 0;
+
+ /*!
+ * @brief Reads the current RSSI value
+ *
+ * @retval rssiValue Current RSSI value in [dBm]
+ */
+ virtual int16_t GetRssi ( RadioModems_t modem ) = 0;
+
+ /*!
+ * @brief Writes the radio register at the specified address
+ *
+ * @param [IN]: addr Register address
+ * @param [IN]: data New register value
+ */
+ virtual void Write ( uint8_t addr, uint8_t data ) = 0;
+
+ /*!
+ * @brief Reads the radio register at the specified address
+ *
+ * @param [IN]: addr Register address
+ * @retval data Register value
+ */
+ virtual uint8_t Read ( uint8_t addr ) = 0;
+
+ /*!
+ * @brief Writes multiple radio registers starting at address
+ *
+ * @param [IN] addr First Radio register address
+ * @param [IN] buffer Buffer containing the new register's values
+ * @param [IN] size Number of registers to be written
+ */
+ virtual void Write( uint8_t addr, uint8_t *buffer, uint8_t size ) = 0;
+
+ /*!
+ * @brief Reads multiple radio registers starting at address
+ *
+ * @param [IN] addr First Radio register address
+ * @param [OUT] buffer Buffer where to copy the registers data
+ * @param [IN] size Number of registers to be read
+ */
+ virtual void Read ( uint8_t addr, uint8_t *buffer, uint8_t size ) = 0;
+
+ /*!
+ * @brief Writes the buffer contents to the SX1276 FIFO
+ *
+ * @param [IN] buffer Buffer containing data to be put on the FIFO.
+ * @param [IN] size Number of bytes to be written to the FIFO
+ */
+ virtual void WriteFifo( uint8_t *buffer, uint8_t size ) = 0;
+
+ /*!
+ * @brief Reads the contents of the SX1276 FIFO
+ *
+ * @param [OUT] buffer Buffer where to copy the FIFO read data.
+ * @param [IN] size Number of bytes to be read from the FIFO
+ */
+ virtual void ReadFifo( uint8_t *buffer, uint8_t size ) = 0;
+
+ /*!
+ * @brief Sets the maximum payload length.
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] max Maximum payload length in bytes
+ */
+ virtual void SetMaxPayloadLength( RadioModems_t modem, uint8_t max ) = 0;
+};
+
+#endif // __RADIO_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/registers/sx1272Regs-Fsk.h Tue Jan 05 16:43:48 2016 +0000 @@ -0,0 +1,1134 @@ +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C) 2015 Semtech + +Description: SX1272 FSK modem registers and bits definitions + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis and Gregory Cristian +*/ +#ifndef __SX1272_REGS_FSK_H__ +#define __SX1272_REGS_FSK_H__ + +/*! + * ============================================================================ + * SX1272 Internal registers Address + * ============================================================================ + */ +#define REG_FIFO 0x00 +// Common settings +#define REG_OPMODE 0x01 +#define REG_BITRATEMSB 0x02 +#define REG_BITRATELSB 0x03 +#define REG_FDEVMSB 0x04 +#define REG_FDEVLSB 0x05 +#define REG_FRFMSB 0x06 +#define REG_FRFMID 0x07 +#define REG_FRFLSB 0x08 +// Tx settings +#define REG_PACONFIG 0x09 +#define REG_PARAMP 0x0A +#define REG_OCP 0x0B +// Rx settings +#define REG_LNA 0x0C +#define REG_RXCONFIG 0x0D +#define REG_RSSICONFIG 0x0E +#define REG_RSSICOLLISION 0x0F +#define REG_RSSITHRESH 0x10 +#define REG_RSSIVALUE 0x11 +#define REG_RXBW 0x12 +#define REG_AFCBW 0x13 +#define REG_OOKPEAK 0x14 +#define REG_OOKFIX 0x15 +#define REG_OOKAVG 0x16 +#define REG_RES17 0x17 +#define REG_RES18 0x18 +#define REG_RES19 0x19 +#define REG_AFCFEI 0x1A +#define REG_AFCMSB 0x1B +#define REG_AFCLSB 0x1C +#define REG_FEIMSB 0x1D +#define REG_FEILSB 0x1E +#define REG_PREAMBLEDETECT 0x1F +#define REG_RXTIMEOUT1 0x20 +#define REG_RXTIMEOUT2 0x21 +#define REG_RXTIMEOUT3 0x22 +#define REG_RXDELAY 0x23 +// Oscillator settings +#define REG_OSC 0x24 +// Packet handler settings +#define REG_PREAMBLEMSB 0x25 +#define REG_PREAMBLELSB 0x26 +#define REG_SYNCCONFIG 0x27 +#define REG_SYNCVALUE1 0x28 +#define REG_SYNCVALUE2 0x29 +#define REG_SYNCVALUE3 0x2A +#define REG_SYNCVALUE4 0x2B +#define REG_SYNCVALUE5 0x2C +#define REG_SYNCVALUE6 0x2D +#define REG_SYNCVALUE7 0x2E +#define REG_SYNCVALUE8 0x2F +#define REG_PACKETCONFIG1 0x30 +#define REG_PACKETCONFIG2 0x31 +#define REG_PAYLOADLENGTH 0x32 +#define REG_NODEADRS 0x33 +#define REG_BROADCASTADRS 0x34 +#define REG_FIFOTHRESH 0x35 +// SM settings +#define REG_SEQCONFIG1 0x36 +#define REG_SEQCONFIG2 0x37 +#define REG_TIMERRESOL 0x38 +#define REG_TIMER1COEF 0x39 +#define REG_TIMER2COEF 0x3A +// Service settings +#define REG_IMAGECAL 0x3B +#define REG_TEMP 0x3C +#define REG_LOWBAT 0x3D +// Status +#define REG_IRQFLAGS1 0x3E +#define REG_IRQFLAGS2 0x3F +// I/O settings +#define REG_DIOMAPPING1 0x40 +#define REG_DIOMAPPING2 0x41 +// Version +#define REG_VERSION 0x42 +// Additional settings +#define REG_AGCREF 0x43 +#define REG_AGCTHRESH1 0x44 +#define REG_AGCTHRESH2 0x45 +#define REG_AGCTHRESH3 0x46 +#define REG_PLLHOP 0x4B +#define REG_TCXO 0x58 +#define REG_PADAC 0x5A +#define REG_PLL 0x5C +#define REG_PLLLOWPN 0x5E +#define REG_FORMERTEMP 0x6C +#define REG_BITRATEFRAC 0x70 + +/*! + * ============================================================================ + * SX1272 FSK bits control definition + * ============================================================================ + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RF_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RF_OPMODE_LONGRANGEMODE_OFF 0x00 +#define RF_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RF_OPMODE_MODULATIONTYPE_MASK 0x9F +#define RF_OPMODE_MODULATIONTYPE_FSK 0x00 // Default +#define RF_OPMODE_MODULATIONTYPE_OOK 0x20 + +#define RF_OPMODE_MODULATIONSHAPING_MASK 0xE7 +#define RF_OPMODE_MODULATIONSHAPING_00 0x00 // Default +#define RF_OPMODE_MODULATIONSHAPING_01 0x08 +#define RF_OPMODE_MODULATIONSHAPING_10 0x10 +#define RF_OPMODE_MODULATIONSHAPING_11 0x18 + +#define RF_OPMODE_MASK 0xF8 +#define RF_OPMODE_SLEEP 0x00 +#define RF_OPMODE_STANDBY 0x01 // Default +#define RF_OPMODE_SYNTHESIZER_TX 0x02 +#define RF_OPMODE_TRANSMITTER 0x03 +#define RF_OPMODE_SYNTHESIZER_RX 0x04 +#define RF_OPMODE_RECEIVER 0x05 + +/*! + * RegBitRate (bits/sec) + */ +#define RF_BITRATEMSB_1200_BPS 0x68 +#define RF_BITRATELSB_1200_BPS 0x2B +#define RF_BITRATEMSB_2400_BPS 0x34 +#define RF_BITRATELSB_2400_BPS 0x15 +#define RF_BITRATEMSB_4800_BPS 0x1A // Default +#define RF_BITRATELSB_4800_BPS 0x0B // Default +#define RF_BITRATEMSB_9600_BPS 0x0D +#define RF_BITRATELSB_9600_BPS 0x05 +#define RF_BITRATEMSB_15000_BPS 0x08 +#define RF_BITRATELSB_15000_BPS 0x55 +#define RF_BITRATEMSB_19200_BPS 0x06 +#define RF_BITRATELSB_19200_BPS 0x83 +#define RF_BITRATEMSB_38400_BPS 0x03 +#define RF_BITRATELSB_38400_BPS 0x41 +#define RF_BITRATEMSB_76800_BPS 0x01 +#define RF_BITRATELSB_76800_BPS 0xA1 +#define RF_BITRATEMSB_153600_BPS 0x00 +#define RF_BITRATELSB_153600_BPS 0xD0 +#define RF_BITRATEMSB_57600_BPS 0x02 +#define RF_BITRATELSB_57600_BPS 0x2C +#define RF_BITRATEMSB_115200_BPS 0x01 +#define RF_BITRATELSB_115200_BPS 0x16 +#define RF_BITRATEMSB_12500_BPS 0x0A +#define RF_BITRATELSB_12500_BPS 0x00 +#define RF_BITRATEMSB_25000_BPS 0x05 +#define RF_BITRATELSB_25000_BPS 0x00 +#define RF_BITRATEMSB_50000_BPS 0x02 +#define RF_BITRATELSB_50000_BPS 0x80 +#define RF_BITRATEMSB_100000_BPS 0x01 +#define RF_BITRATELSB_100000_BPS 0x40 +#define RF_BITRATEMSB_150000_BPS 0x00 +#define RF_BITRATELSB_150000_BPS 0xD5 +#define RF_BITRATEMSB_200000_BPS 0x00 +#define RF_BITRATELSB_200000_BPS 0xA0 +#define RF_BITRATEMSB_250000_BPS 0x00 +#define RF_BITRATELSB_250000_BPS 0x80 +#define RF_BITRATEMSB_32768_BPS 0x03 +#define RF_BITRATELSB_32768_BPS 0xD1 + +/*! + * RegFdev (Hz) + */ +#define RF_FDEVMSB_2000_HZ 0x00 +#define RF_FDEVLSB_2000_HZ 0x21 +#define RF_FDEVMSB_5000_HZ 0x00 // Default +#define RF_FDEVLSB_5000_HZ 0x52 // Default +#define RF_FDEVMSB_10000_HZ 0x00 +#define RF_FDEVLSB_10000_HZ 0xA4 +#define RF_FDEVMSB_15000_HZ 0x00 +#define RF_FDEVLSB_15000_HZ 0xF6 +#define RF_FDEVMSB_20000_HZ 0x01 +#define RF_FDEVLSB_20000_HZ 0x48 +#define RF_FDEVMSB_25000_HZ 0x01 +#define RF_FDEVLSB_25000_HZ 0x9A +#define RF_FDEVMSB_30000_HZ 0x01 +#define RF_FDEVLSB_30000_HZ 0xEC +#define RF_FDEVMSB_35000_HZ 0x02 +#define RF_FDEVLSB_35000_HZ 0x3D +#define RF_FDEVMSB_40000_HZ 0x02 +#define RF_FDEVLSB_40000_HZ 0x8F +#define RF_FDEVMSB_45000_HZ 0x02 +#define RF_FDEVLSB_45000_HZ 0xE1 +#define RF_FDEVMSB_50000_HZ 0x03 +#define RF_FDEVLSB_50000_HZ 0x33 +#define RF_FDEVMSB_55000_HZ 0x03 +#define RF_FDEVLSB_55000_HZ 0x85 +#define RF_FDEVMSB_60000_HZ 0x03 +#define RF_FDEVLSB_60000_HZ 0xD7 +#define RF_FDEVMSB_65000_HZ 0x04 +#define RF_FDEVLSB_65000_HZ 0x29 +#define RF_FDEVMSB_70000_HZ 0x04 +#define RF_FDEVLSB_70000_HZ 0x7B +#define RF_FDEVMSB_75000_HZ 0x04 +#define RF_FDEVLSB_75000_HZ 0xCD +#define RF_FDEVMSB_80000_HZ 0x05 +#define RF_FDEVLSB_80000_HZ 0x1F +#define RF_FDEVMSB_85000_HZ 0x05 +#define RF_FDEVLSB_85000_HZ 0x71 +#define RF_FDEVMSB_90000_HZ 0x05 +#define RF_FDEVLSB_90000_HZ 0xC3 +#define RF_FDEVMSB_95000_HZ 0x06 +#define RF_FDEVLSB_95000_HZ 0x14 +#define RF_FDEVMSB_100000_HZ 0x06 +#define RF_FDEVLSB_100000_HZ 0x66 +#define RF_FDEVMSB_110000_HZ 0x07 +#define RF_FDEVLSB_110000_HZ 0x0A +#define RF_FDEVMSB_120000_HZ 0x07 +#define RF_FDEVLSB_120000_HZ 0xAE +#define RF_FDEVMSB_130000_HZ 0x08 +#define RF_FDEVLSB_130000_HZ 0x52 +#define RF_FDEVMSB_140000_HZ 0x08 +#define RF_FDEVLSB_140000_HZ 0xF6 +#define RF_FDEVMSB_150000_HZ 0x09 +#define RF_FDEVLSB_150000_HZ 0x9A +#define RF_FDEVMSB_160000_HZ 0x0A +#define RF_FDEVLSB_160000_HZ 0x3D +#define RF_FDEVMSB_170000_HZ 0x0A +#define RF_FDEVLSB_170000_HZ 0xE1 +#define RF_FDEVMSB_180000_HZ 0x0B +#define RF_FDEVLSB_180000_HZ 0x85 +#define RF_FDEVMSB_190000_HZ 0x0C +#define RF_FDEVLSB_190000_HZ 0x29 +#define RF_FDEVMSB_200000_HZ 0x0C +#define RF_FDEVLSB_200000_HZ 0xCD + +/*! + * RegFrf (MHz) + */ +#define RF_FRFMSB_863_MHZ 0xD7 +#define RF_FRFMID_863_MHZ 0xC0 +#define RF_FRFLSB_863_MHZ 0x00 +#define RF_FRFMSB_864_MHZ 0xD8 +#define RF_FRFMID_864_MHZ 0x00 +#define RF_FRFLSB_864_MHZ 0x00 +#define RF_FRFMSB_865_MHZ 0xD8 +#define RF_FRFMID_865_MHZ 0x40 +#define RF_FRFLSB_865_MHZ 0x00 +#define RF_FRFMSB_866_MHZ 0xD8 +#define RF_FRFMID_866_MHZ 0x80 +#define RF_FRFLSB_866_MHZ 0x00 +#define RF_FRFMSB_867_MHZ 0xD8 +#define RF_FRFMID_867_MHZ 0xC0 +#define RF_FRFLSB_867_MHZ 0x00 +#define RF_FRFMSB_868_MHZ 0xD9 +#define RF_FRFMID_868_MHZ 0x00 +#define RF_FRFLSB_868_MHZ 0x00 +#define RF_FRFMSB_869_MHZ 0xD9 +#define RF_FRFMID_869_MHZ 0x40 +#define RF_FRFLSB_869_MHZ 0x00 +#define RF_FRFMSB_870_MHZ 0xD9 +#define RF_FRFMID_870_MHZ 0x80 +#define RF_FRFLSB_870_MHZ 0x00 + +#define RF_FRFMSB_902_MHZ 0xE1 +#define RF_FRFMID_902_MHZ 0x80 +#define RF_FRFLSB_902_MHZ 0x00 +#define RF_FRFMSB_903_MHZ 0xE1 +#define RF_FRFMID_903_MHZ 0xC0 +#define RF_FRFLSB_903_MHZ 0x00 +#define RF_FRFMSB_904_MHZ 0xE2 +#define RF_FRFMID_904_MHZ 0x00 +#define RF_FRFLSB_904_MHZ 0x00 +#define RF_FRFMSB_905_MHZ 0xE2 +#define RF_FRFMID_905_MHZ 0x40 +#define RF_FRFLSB_905_MHZ 0x00 +#define RF_FRFMSB_906_MHZ 0xE2 +#define RF_FRFMID_906_MHZ 0x80 +#define RF_FRFLSB_906_MHZ 0x00 +#define RF_FRFMSB_907_MHZ 0xE2 +#define RF_FRFMID_907_MHZ 0xC0 +#define RF_FRFLSB_907_MHZ 0x00 +#define RF_FRFMSB_908_MHZ 0xE3 +#define RF_FRFMID_908_MHZ 0x00 +#define RF_FRFLSB_908_MHZ 0x00 +#define RF_FRFMSB_909_MHZ 0xE3 +#define RF_FRFMID_909_MHZ 0x40 +#define RF_FRFLSB_909_MHZ 0x00 +#define RF_FRFMSB_910_MHZ 0xE3 +#define RF_FRFMID_910_MHZ 0x80 +#define RF_FRFLSB_910_MHZ 0x00 +#define RF_FRFMSB_911_MHZ 0xE3 +#define RF_FRFMID_911_MHZ 0xC0 +#define RF_FRFLSB_911_MHZ 0x00 +#define RF_FRFMSB_912_MHZ 0xE4 +#define RF_FRFMID_912_MHZ 0x00 +#define RF_FRFLSB_912_MHZ 0x00 +#define RF_FRFMSB_913_MHZ 0xE4 +#define RF_FRFMID_913_MHZ 0x40 +#define RF_FRFLSB_913_MHZ 0x00 +#define RF_FRFMSB_914_MHZ 0xE4 +#define RF_FRFMID_914_MHZ 0x80 +#define RF_FRFLSB_914_MHZ 0x00 +#define RF_FRFMSB_915_MHZ 0xE4 // Default +#define RF_FRFMID_915_MHZ 0xC0 // Default +#define RF_FRFLSB_915_MHZ 0x00 // Default +#define RF_FRFMSB_916_MHZ 0xE5 +#define RF_FRFMID_916_MHZ 0x00 +#define RF_FRFLSB_916_MHZ 0x00 +#define RF_FRFMSB_917_MHZ 0xE5 +#define RF_FRFMID_917_MHZ 0x40 +#define RF_FRFLSB_917_MHZ 0x00 +#define RF_FRFMSB_918_MHZ 0xE5 +#define RF_FRFMID_918_MHZ 0x80 +#define RF_FRFLSB_918_MHZ 0x00 +#define RF_FRFMSB_919_MHZ 0xE5 +#define RF_FRFMID_919_MHZ 0xC0 +#define RF_FRFLSB_919_MHZ 0x00 +#define RF_FRFMSB_920_MHZ 0xE6 +#define RF_FRFMID_920_MHZ 0x00 +#define RF_FRFLSB_920_MHZ 0x00 +#define RF_FRFMSB_921_MHZ 0xE6 +#define RF_FRFMID_921_MHZ 0x40 +#define RF_FRFLSB_921_MHZ 0x00 +#define RF_FRFMSB_922_MHZ 0xE6 +#define RF_FRFMID_922_MHZ 0x80 +#define RF_FRFLSB_922_MHZ 0x00 +#define RF_FRFMSB_923_MHZ 0xE6 +#define RF_FRFMID_923_MHZ 0xC0 +#define RF_FRFLSB_923_MHZ 0x00 +#define RF_FRFMSB_924_MHZ 0xE7 +#define RF_FRFMID_924_MHZ 0x00 +#define RF_FRFLSB_924_MHZ 0x00 +#define RF_FRFMSB_925_MHZ 0xE7 +#define RF_FRFMID_925_MHZ 0x40 +#define RF_FRFLSB_925_MHZ 0x00 +#define RF_FRFMSB_926_MHZ 0xE7 +#define RF_FRFMID_926_MHZ 0x80 +#define RF_FRFLSB_926_MHZ 0x00 +#define RF_FRFMSB_927_MHZ 0xE7 +#define RF_FRFMID_927_MHZ 0xC0 +#define RF_FRFLSB_927_MHZ 0x00 +#define RF_FRFMSB_928_MHZ 0xE8 +#define RF_FRFMID_928_MHZ 0x00 +#define RF_FRFLSB_928_MHZ 0x00 + +/*! + * RegPaConfig + */ +#define RF_PACONFIG_PASELECT_MASK 0x7F +#define RF_PACONFIG_PASELECT_PABOOST 0x80 +#define RF_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RF_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RF_PARAMP_LOWPNTXPLL_MASK 0xE0 +#define RF_PARAMP_LOWPNTXPLL_OFF 0x10 // Default +#define RF_PARAMP_LOWPNTXPLL_ON 0x00 + +#define RF_PARAMP_MASK 0xF0 +#define RF_PARAMP_3400_US 0x00 +#define RF_PARAMP_2000_US 0x01 +#define RF_PARAMP_1000_US 0x02 +#define RF_PARAMP_0500_US 0x03 +#define RF_PARAMP_0250_US 0x04 +#define RF_PARAMP_0125_US 0x05 +#define RF_PARAMP_0100_US 0x06 +#define RF_PARAMP_0062_US 0x07 +#define RF_PARAMP_0050_US 0x08 +#define RF_PARAMP_0040_US 0x09 // Default +#define RF_PARAMP_0031_US 0x0A +#define RF_PARAMP_0025_US 0x0B +#define RF_PARAMP_0020_US 0x0C +#define RF_PARAMP_0015_US 0x0D +#define RF_PARAMP_0012_US 0x0E +#define RF_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RF_OCP_MASK 0xDF +#define RF_OCP_ON 0x20 // Default +#define RF_OCP_OFF 0x00 + +#define RF_OCP_TRIM_MASK 0xE0 +#define RF_OCP_TRIM_045_MA 0x00 +#define RF_OCP_TRIM_050_MA 0x01 +#define RF_OCP_TRIM_055_MA 0x02 +#define RF_OCP_TRIM_060_MA 0x03 +#define RF_OCP_TRIM_065_MA 0x04 +#define RF_OCP_TRIM_070_MA 0x05 +#define RF_OCP_TRIM_075_MA 0x06 +#define RF_OCP_TRIM_080_MA 0x07 +#define RF_OCP_TRIM_085_MA 0x08 +#define RF_OCP_TRIM_090_MA 0x09 +#define RF_OCP_TRIM_095_MA 0x0A +#define RF_OCP_TRIM_100_MA 0x0B // Default +#define RF_OCP_TRIM_105_MA 0x0C +#define RF_OCP_TRIM_110_MA 0x0D +#define RF_OCP_TRIM_115_MA 0x0E +#define RF_OCP_TRIM_120_MA 0x0F +#define RF_OCP_TRIM_130_MA 0x10 +#define RF_OCP_TRIM_140_MA 0x11 +#define RF_OCP_TRIM_150_MA 0x12 +#define RF_OCP_TRIM_160_MA 0x13 +#define RF_OCP_TRIM_170_MA 0x14 +#define RF_OCP_TRIM_180_MA 0x15 +#define RF_OCP_TRIM_190_MA 0x16 +#define RF_OCP_TRIM_200_MA 0x17 +#define RF_OCP_TRIM_210_MA 0x18 +#define RF_OCP_TRIM_220_MA 0x19 +#define RF_OCP_TRIM_230_MA 0x1A +#define RF_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RF_LNA_GAIN_MASK 0x1F +#define RF_LNA_GAIN_G1 0x20 // Default +#define RF_LNA_GAIN_G2 0x40 +#define RF_LNA_GAIN_G3 0x60 +#define RF_LNA_GAIN_G4 0x80 +#define RF_LNA_GAIN_G5 0xA0 +#define RF_LNA_GAIN_G6 0xC0 + +#define RF_LNA_BOOST_MASK 0xFC +#define RF_LNA_BOOST_OFF 0x00 // Default +#define RF_LNA_BOOST_ON 0x03 + +/*! + * RegRxConfig + */ +#define RF_RXCONFIG_RESTARTRXONCOLLISION_MASK 0x7F +#define RF_RXCONFIG_RESTARTRXONCOLLISION_ON 0x80 +#define RF_RXCONFIG_RESTARTRXONCOLLISION_OFF 0x00 // Default + +#define RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK 0x40 // Write only + +#define RF_RXCONFIG_RESTARTRXWITHPLLLOCK 0x20 // Write only + +#define RF_RXCONFIG_AFCAUTO_MASK 0xEF +#define RF_RXCONFIG_AFCAUTO_ON 0x10 +#define RF_RXCONFIG_AFCAUTO_OFF 0x00 // Default + +#define RF_RXCONFIG_AGCAUTO_MASK 0xF7 +#define RF_RXCONFIG_AGCAUTO_ON 0x08 // Default +#define RF_RXCONFIG_AGCAUTO_OFF 0x00 + +#define RF_RXCONFIG_RXTRIGER_MASK 0xF8 +#define RF_RXCONFIG_RXTRIGER_OFF 0x00 +#define RF_RXCONFIG_RXTRIGER_RSSI 0x01 +#define RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT 0x06 // Default +#define RF_RXCONFIG_RXTRIGER_RSSI_PREAMBLEDETECT 0x07 + +/*! + * RegRssiConfig + */ +#define RF_RSSICONFIG_OFFSET_MASK 0x07 +#define RF_RSSICONFIG_OFFSET_P_00_DB 0x00 // Default +#define RF_RSSICONFIG_OFFSET_P_01_DB 0x08 +#define RF_RSSICONFIG_OFFSET_P_02_DB 0x10 +#define RF_RSSICONFIG_OFFSET_P_03_DB 0x18 +#define RF_RSSICONFIG_OFFSET_P_04_DB 0x20 +#define RF_RSSICONFIG_OFFSET_P_05_DB 0x28 +#define RF_RSSICONFIG_OFFSET_P_06_DB 0x30 +#define RF_RSSICONFIG_OFFSET_P_07_DB 0x38 +#define RF_RSSICONFIG_OFFSET_P_08_DB 0x40 +#define RF_RSSICONFIG_OFFSET_P_09_DB 0x48 +#define RF_RSSICONFIG_OFFSET_P_10_DB 0x50 +#define RF_RSSICONFIG_OFFSET_P_11_DB 0x58 +#define RF_RSSICONFIG_OFFSET_P_12_DB 0x60 +#define RF_RSSICONFIG_OFFSET_P_13_DB 0x68 +#define RF_RSSICONFIG_OFFSET_P_14_DB 0x70 +#define RF_RSSICONFIG_OFFSET_P_15_DB 0x78 +#define RF_RSSICONFIG_OFFSET_M_16_DB 0x80 +#define RF_RSSICONFIG_OFFSET_M_15_DB 0x88 +#define RF_RSSICONFIG_OFFSET_M_14_DB 0x90 +#define RF_RSSICONFIG_OFFSET_M_13_DB 0x98 +#define RF_RSSICONFIG_OFFSET_M_12_DB 0xA0 +#define RF_RSSICONFIG_OFFSET_M_11_DB 0xA8 +#define RF_RSSICONFIG_OFFSET_M_10_DB 0xB0 +#define RF_RSSICONFIG_OFFSET_M_09_DB 0xB8 +#define RF_RSSICONFIG_OFFSET_M_08_DB 0xC0 +#define RF_RSSICONFIG_OFFSET_M_07_DB 0xC8 +#define RF_RSSICONFIG_OFFSET_M_06_DB 0xD0 +#define RF_RSSICONFIG_OFFSET_M_05_DB 0xD8 +#define RF_RSSICONFIG_OFFSET_M_04_DB 0xE0 +#define RF_RSSICONFIG_OFFSET_M_03_DB 0xE8 +#define RF_RSSICONFIG_OFFSET_M_02_DB 0xF0 +#define RF_RSSICONFIG_OFFSET_M_01_DB 0xF8 + +#define RF_RSSICONFIG_SMOOTHING_MASK 0xF8 +#define RF_RSSICONFIG_SMOOTHING_2 0x00 +#define RF_RSSICONFIG_SMOOTHING_4 0x01 +#define RF_RSSICONFIG_SMOOTHING_8 0x02 // Default +#define RF_RSSICONFIG_SMOOTHING_16 0x03 +#define RF_RSSICONFIG_SMOOTHING_32 0x04 +#define RF_RSSICONFIG_SMOOTHING_64 0x05 +#define RF_RSSICONFIG_SMOOTHING_128 0x06 +#define RF_RSSICONFIG_SMOOTHING_256 0x07 + +/*! + * RegRssiCollision + */ +#define RF_RSSICOLISION_THRESHOLD 0x0A // Default + +/*! + * RegRssiThresh + */ +#define RF_RSSITHRESH_THRESHOLD 0xFF // Default + +/*! + * RegRssiValue (Read Only) + */ + +/*! + * RegRxBw + */ +#define RF_RXBW_MANT_MASK 0xE7 +#define RF_RXBW_MANT_16 0x00 +#define RF_RXBW_MANT_20 0x08 +#define RF_RXBW_MANT_24 0x10 // Default + +#define RF_RXBW_EXP_MASK 0xF8 +#define RF_RXBW_EXP_0 0x00 +#define RF_RXBW_EXP_1 0x01 +#define RF_RXBW_EXP_2 0x02 +#define RF_RXBW_EXP_3 0x03 +#define RF_RXBW_EXP_4 0x04 +#define RF_RXBW_EXP_5 0x05 // Default +#define RF_RXBW_EXP_6 0x06 +#define RF_RXBW_EXP_7 0x07 + +/*! + * RegAfcBw + */ +#define RF_AFCBW_MANTAFC_MASK 0xE7 +#define RF_AFCBW_MANTAFC_16 0x00 +#define RF_AFCBW_MANTAFC_20 0x08 // Default +#define RF_AFCBW_MANTAFC_24 0x10 + +#define RF_AFCBW_EXPAFC_MASK 0xF8 +#define RF_AFCBW_EXPAFC_0 0x00 +#define RF_AFCBW_EXPAFC_1 0x01 +#define RF_AFCBW_EXPAFC_2 0x02 +#define RF_AFCBW_EXPAFC_3 0x03 // Default +#define RF_AFCBW_EXPAFC_4 0x04 +#define RF_AFCBW_EXPAFC_5 0x05 +#define RF_AFCBW_EXPAFC_6 0x06 +#define RF_AFCBW_EXPAFC_7 0x07 + +/*! + * RegOokPeak + */ +#define RF_OOKPEAK_BITSYNC_MASK 0xDF // Default +#define RF_OOKPEAK_BITSYNC_ON 0x20 // Default +#define RF_OOKPEAK_BITSYNC_OFF 0x00 + +#define RF_OOKPEAK_OOKTHRESHTYPE_MASK 0xE7 +#define RF_OOKPEAK_OOKTHRESHTYPE_FIXED 0x00 +#define RF_OOKPEAK_OOKTHRESHTYPE_PEAK 0x08 // Default +#define RF_OOKPEAK_OOKTHRESHTYPE_AVERAGE 0x10 + +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_MASK 0xF8 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_0_5_DB 0x00 // Default +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_0_DB 0x01 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_5_DB 0x02 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_2_0_DB 0x03 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_3_0_DB 0x04 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_4_0_DB 0x05 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_5_0_DB 0x06 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_6_0_DB 0x07 + +/*! + * RegOokFix + */ +#define RF_OOKFIX_OOKFIXEDTHRESHOLD 0x0C // Default + +/*! + * RegOokAvg + */ +#define RF_OOKAVG_OOKPEAKTHRESHDEC_MASK 0x1F +#define RF_OOKAVG_OOKPEAKTHRESHDEC_000 0x00 // Default +#define RF_OOKAVG_OOKPEAKTHRESHDEC_001 0x20 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_010 0x40 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_011 0x60 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_100 0x80 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_101 0xA0 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_110 0xC0 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_111 0xE0 + +#define RF_OOKAVG_AVERAGEOFFSET_MASK 0xF3 +#define RF_OOKAVG_AVERAGEOFFSET_0_DB 0x00 // Default +#define RF_OOKAVG_AVERAGEOFFSET_2_DB 0x04 +#define RF_OOKAVG_AVERAGEOFFSET_4_DB 0x08 +#define RF_OOKAVG_AVERAGEOFFSET_6_DB 0x0C + +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_MASK 0xFC +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_00 0x00 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_01 0x01 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_10 0x02 // Default +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_11 0x03 + +/*! + * RegAfcFei + */ +#define RF_AFCFEI_AGCSTART 0x10 + +#define RF_AFCFEI_AFCCLEAR 0x02 + +#define RF_AFCFEI_AFCAUTOCLEAR_MASK 0xFE +#define RF_AFCFEI_AFCAUTOCLEAR_ON 0x01 +#define RF_AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default + +/*! + * RegAfcMsb (Read Only) + */ + +/*! + * RegAfcLsb (Read Only) + */ + +/*! + * RegFeiMsb (Read Only) + */ + +/*! + * RegFeiLsb (Read Only) + */ + +/*! + * RegPreambleDetect + */ +#define RF_PREAMBLEDETECT_DETECTOR_MASK 0x7F +#define RF_PREAMBLEDETECT_DETECTOR_ON 0x80 // Default +#define RF_PREAMBLEDETECT_DETECTOR_OFF 0x00 + +#define RF_PREAMBLEDETECT_DETECTORSIZE_MASK 0x9F +#define RF_PREAMBLEDETECT_DETECTORSIZE_1 0x00 +#define RF_PREAMBLEDETECT_DETECTORSIZE_2 0x20 // Default +#define RF_PREAMBLEDETECT_DETECTORSIZE_3 0x40 +#define RF_PREAMBLEDETECT_DETECTORSIZE_4 0x60 + +#define RF_PREAMBLEDETECT_DETECTORTOL_MASK 0xE0 +#define RF_PREAMBLEDETECT_DETECTORTOL_0 0x00 +#define RF_PREAMBLEDETECT_DETECTORTOL_1 0x01 +#define RF_PREAMBLEDETECT_DETECTORTOL_2 0x02 +#define RF_PREAMBLEDETECT_DETECTORTOL_3 0x03 +#define RF_PREAMBLEDETECT_DETECTORTOL_4 0x04 +#define RF_PREAMBLEDETECT_DETECTORTOL_5 0x05 +#define RF_PREAMBLEDETECT_DETECTORTOL_6 0x06 +#define RF_PREAMBLEDETECT_DETECTORTOL_7 0x07 +#define RF_PREAMBLEDETECT_DETECTORTOL_8 0x08 +#define RF_PREAMBLEDETECT_DETECTORTOL_9 0x09 +#define RF_PREAMBLEDETECT_DETECTORTOL_10 0x0A // Default +#define RF_PREAMBLEDETECT_DETECTORTOL_11 0x0B +#define RF_PREAMBLEDETECT_DETECTORTOL_12 0x0C +#define RF_PREAMBLEDETECT_DETECTORTOL_13 0x0D +#define RF_PREAMBLEDETECT_DETECTORTOL_14 0x0E +#define RF_PREAMBLEDETECT_DETECTORTOL_15 0x0F +#define RF_PREAMBLEDETECT_DETECTORTOL_16 0x10 +#define RF_PREAMBLEDETECT_DETECTORTOL_17 0x11 +#define RF_PREAMBLEDETECT_DETECTORTOL_18 0x12 +#define RF_PREAMBLEDETECT_DETECTORTOL_19 0x13 +#define RF_PREAMBLEDETECT_DETECTORTOL_20 0x14 +#define RF_PREAMBLEDETECT_DETECTORTOL_21 0x15 +#define RF_PREAMBLEDETECT_DETECTORTOL_22 0x16 +#define RF_PREAMBLEDETECT_DETECTORTOL_23 0x17 +#define RF_PREAMBLEDETECT_DETECTORTOL_24 0x18 +#define RF_PREAMBLEDETECT_DETECTORTOL_25 0x19 +#define RF_PREAMBLEDETECT_DETECTORTOL_26 0x1A +#define RF_PREAMBLEDETECT_DETECTORTOL_27 0x1B +#define RF_PREAMBLEDETECT_DETECTORTOL_28 0x1C +#define RF_PREAMBLEDETECT_DETECTORTOL_29 0x1D +#define RF_PREAMBLEDETECT_DETECTORTOL_30 0x1E +#define RF_PREAMBLEDETECT_DETECTORTOL_31 0x1F + +/*! + * RegRxTimeout1 + */ +#define RF_RXTIMEOUT1_TIMEOUTRXRSSI 0x00 // Default + +/*! + * RegRxTimeout2 + */ +#define RF_RXTIMEOUT2_TIMEOUTRXPREAMBLE 0x00 // Default + +/*! + * RegRxTimeout3 + */ +#define RF_RXTIMEOUT3_TIMEOUTSIGNALSYNC 0x00 // Default + +/*! + * RegRxDelay + */ +#define RF_RXDELAY_INTERPACKETRXDELAY 0x00 // Default + +/*! + * RegOsc + */ +#define RF_OSC_RCCALSTART 0x08 + +#define RF_OSC_CLKOUT_MASK 0xF8 +#define RF_OSC_CLKOUT_32_MHZ 0x00 +#define RF_OSC_CLKOUT_16_MHZ 0x01 +#define RF_OSC_CLKOUT_8_MHZ 0x02 +#define RF_OSC_CLKOUT_4_MHZ 0x03 +#define RF_OSC_CLKOUT_2_MHZ 0x04 +#define RF_OSC_CLKOUT_1_MHZ 0x05 +#define RF_OSC_CLKOUT_RC 0x06 +#define RF_OSC_CLKOUT_OFF 0x07 // Default + +/*! + * RegPreambleMsb/RegPreambleLsb + */ +#define RF_PREAMBLEMSB_SIZE 0x00 // Default +#define RF_PREAMBLELSB_SIZE 0x03 // Default + +/*! + * RegSyncConfig + */ +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_MASK 0x3F +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON 0x80 // Default +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_OFF 0x40 +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_OFF 0x00 + + +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_MASK 0xDF +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_55 0x20 +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_AA 0x00 // Default + +#define RF_SYNCCONFIG_SYNC_MASK 0xEF +#define RF_SYNCCONFIG_SYNC_ON 0x10 // Default +#define RF_SYNCCONFIG_SYNC_OFF 0x00 + +#define RF_SYNCCONFIG_FIFOFILLCONDITION_MASK 0xF7 +#define RF_SYNCCONFIG_FIFOFILLCONDITION_AUTO 0x00 // Default +#define RF_SYNCCONFIG_FIFOFILLCONDITION_MANUAL 0x08 + +#define RF_SYNCCONFIG_SYNCSIZE_MASK 0xF8 +#define RF_SYNCCONFIG_SYNCSIZE_1 0x00 +#define RF_SYNCCONFIG_SYNCSIZE_2 0x01 +#define RF_SYNCCONFIG_SYNCSIZE_3 0x02 +#define RF_SYNCCONFIG_SYNCSIZE_4 0x03 // Default +#define RF_SYNCCONFIG_SYNCSIZE_5 0x04 +#define RF_SYNCCONFIG_SYNCSIZE_6 0x05 +#define RF_SYNCCONFIG_SYNCSIZE_7 0x06 +#define RF_SYNCCONFIG_SYNCSIZE_8 0x07 + +/*! + * RegSyncValue1-8 + */ +#define RF_SYNCVALUE1_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE2_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE3_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE4_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE5_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE6_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE7_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE8_SYNCVALUE 0x01 // Default + +/*! + * RegPacketConfig1 + */ +#define RF_PACKETCONFIG1_PACKETFORMAT_MASK 0x7F +#define RF_PACKETCONFIG1_PACKETFORMAT_FIXED 0x00 +#define RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE 0x80 // Default + +#define RF_PACKETCONFIG1_DCFREE_MASK 0x9F +#define RF_PACKETCONFIG1_DCFREE_OFF 0x00 // Default +#define RF_PACKETCONFIG1_DCFREE_MANCHESTER 0x20 +#define RF_PACKETCONFIG1_DCFREE_WHITENING 0x40 + +#define RF_PACKETCONFIG1_CRC_MASK 0xEF +#define RF_PACKETCONFIG1_CRC_ON 0x10 // Default +#define RF_PACKETCONFIG1_CRC_OFF 0x00 + +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_MASK 0xF7 +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_ON 0x00 // Default +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 + +#define RF_PACKETCONFIG1_ADDRSFILTERING_MASK 0xF9 +#define RF_PACKETCONFIG1_ADDRSFILTERING_OFF 0x00 // Default +#define RF_PACKETCONFIG1_ADDRSFILTERING_NODE 0x02 +#define RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST 0x04 + +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_MASK 0xFE +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT 0x00 // Default +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_IBM 0x01 + +/*! + * RegPacketConfig2 + */ +#define RF_PACKETCONFIG2_DATAMODE_MASK 0xBF +#define RF_PACKETCONFIG2_DATAMODE_CONTINUOUS 0x00 +#define RF_PACKETCONFIG2_DATAMODE_PACKET 0x40 // Default + +#define RF_PACKETCONFIG2_IOHOME_MASK 0xDF +#define RF_PACKETCONFIG2_IOHOME_ON 0x20 +#define RF_PACKETCONFIG2_IOHOME_OFF 0x00 // Default + +#define RF_PACKETCONFIG2_BEACON_MASK 0xF7 +#define RF_PACKETCONFIG2_BEACON_ON 0x08 +#define RF_PACKETCONFIG2_BEACON_OFF 0x00 // Default + +#define RF_PACKETCONFIG2_PAYLOADLENGTH_MSB_MASK 0xF8 + +/*! + * RegPayloadLength + */ +#define RF_PAYLOADLENGTH_LENGTH 0x40 // Default + +/*! + * RegNodeAdrs + */ +#define RF_NODEADDRESS_ADDRESS 0x00 + +/*! + * RegBroadcastAdrs + */ +#define RF_BROADCASTADDRESS_ADDRESS 0x00 + +/*! + * RegFifoThresh + */ +#define RF_FIFOTHRESH_TXSTARTCONDITION_MASK 0x7F +#define RF_FIFOTHRESH_TXSTARTCONDITION_FIFOTHRESH 0x00 +#define RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY 0x80 // Default + +#define RF_FIFOTHRESH_FIFOTHRESHOLD_MASK 0xC0 +#define RF_FIFOTHRESH_FIFOTHRESHOLD_THRESHOLD 0x0F // Default + +/*! + * RegSeqConfig1 + */ +#define RF_SEQCONFIG1_SEQUENCER_START 0x80 + +#define RF_SEQCONFIG1_SEQUENCER_STOP 0x40 + +#define RF_SEQCONFIG1_IDLEMODE_MASK 0xDF +#define RF_SEQCONFIG1_IDLEMODE_SLEEP 0x20 +#define RF_SEQCONFIG1_IDLEMODE_STANDBY 0x00 // Default + +#define RF_SEQCONFIG1_FROMSTART_MASK 0xE7 +#define RF_SEQCONFIG1_FROMSTART_TOLPS 0x00 // Default +#define RF_SEQCONFIG1_FROMSTART_TORX 0x08 +#define RF_SEQCONFIG1_FROMSTART_TOTX 0x10 +#define RF_SEQCONFIG1_FROMSTART_TOTX_ONFIFOLEVEL 0x18 + +#define RF_SEQCONFIG1_LPS_MASK 0xFB +#define RF_SEQCONFIG1_LPS_SEQUENCER_OFF 0x00 // Default +#define RF_SEQCONFIG1_LPS_IDLE 0x04 + +#define RF_SEQCONFIG1_FROMIDLE_MASK 0xFD +#define RF_SEQCONFIG1_FROMIDLE_TOTX 0x00 // Default +#define RF_SEQCONFIG1_FROMIDLE_TORX 0x02 + +#define RF_SEQCONFIG1_FROMTX_MASK 0xFE +#define RF_SEQCONFIG1_FROMTX_TOLPS 0x00 // Default +#define RF_SEQCONFIG1_FROMTX_TORX 0x01 + +/*! + * RegSeqConfig2 + */ +#define RF_SEQCONFIG2_FROMRX_MASK 0x1F +#define RF_SEQCONFIG2_FROMRX_TOUNUSED_000 0x00 // Default +#define RF_SEQCONFIG2_FROMRX_TORXPKT_ONPLDRDY 0x20 +#define RF_SEQCONFIG2_FROMRX_TOLPS_ONPLDRDY 0x40 +#define RF_SEQCONFIG2_FROMRX_TORXPKT_ONCRCOK 0x60 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONRSSI 0x80 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONSYNC 0xA0 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONPREAMBLE 0xC0 +#define RF_SEQCONFIG2_FROMRX_TOUNUSED_111 0xE0 + +#define RF_SEQCONFIG2_FROMRXTIMEOUT_MASK 0xE7 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TORXRESTART 0x00 // Default +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOTX 0x08 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOLPS 0x10 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOSEQUENCEROFF 0x18 + +#define RF_SEQCONFIG2_FROMRXPKT_MASK 0xF8 +#define RF_SEQCONFIG2_FROMRXPKT_TOSEQUENCEROFF 0x00 // Default +#define RF_SEQCONFIG2_FROMRXPKT_TOTX_ONFIFOEMPTY 0x01 +#define RF_SEQCONFIG2_FROMRXPKT_TOLPS 0x02 +#define RF_SEQCONFIG2_FROMRXPKT_TOSYNTHESIZERRX 0x03 +#define RF_SEQCONFIG2_FROMRXPKT_TORX 0x04 + +/*! + * RegTimerResol + */ +#define RF_TIMERRESOL_TIMER1RESOL_MASK 0xF3 +#define RF_TIMERRESOL_TIMER1RESOL_OFF 0x00 // Default +#define RF_TIMERRESOL_TIMER1RESOL_000064_US 0x04 +#define RF_TIMERRESOL_TIMER1RESOL_004100_US 0x08 +#define RF_TIMERRESOL_TIMER1RESOL_262000_US 0x0C + +#define RF_TIMERRESOL_TIMER2RESOL_MASK 0xFC +#define RF_TIMERRESOL_TIMER2RESOL_OFF 0x00 // Default +#define RF_TIMERRESOL_TIMER2RESOL_000064_US 0x01 +#define RF_TIMERRESOL_TIMER2RESOL_004100_US 0x02 +#define RF_TIMERRESOL_TIMER2RESOL_262000_US 0x03 + +/*! + * RegTimer1Coef + */ +#define RF_TIMER1COEF_TIMER1COEFFICIENT 0xF5 // Default + +/*! + * RegTimer2Coef + */ +#define RF_TIMER2COEF_TIMER2COEFFICIENT 0x20 // Default + +/*! + * RegImageCal + */ +#define RF_IMAGECAL_AUTOIMAGECAL_MASK 0x7F +#define RF_IMAGECAL_AUTOIMAGECAL_ON 0x80 +#define RF_IMAGECAL_AUTOIMAGECAL_OFF 0x00 // Default + +#define RF_IMAGECAL_IMAGECAL_MASK 0xBF +#define RF_IMAGECAL_IMAGECAL_START 0x40 + +#define RF_IMAGECAL_IMAGECAL_RUNNING 0x20 +#define RF_IMAGECAL_IMAGECAL_DONE 0x00 // Default + +#define RF_IMAGECAL_TEMPCHANGE_HIGHER 0x08 +#define RF_IMAGECAL_TEMPCHANGE_LOWER 0x00 + +#define RF_IMAGECAL_TEMPTHRESHOLD_MASK 0xF9 +#define RF_IMAGECAL_TEMPTHRESHOLD_05 0x00 +#define RF_IMAGECAL_TEMPTHRESHOLD_10 0x02 // Default +#define RF_IMAGECAL_TEMPTHRESHOLD_15 0x04 +#define RF_IMAGECAL_TEMPTHRESHOLD_20 0x06 + +#define RF_IMAGECAL_TEMPMONITOR_MASK 0xFE +#define RF_IMAGECAL_TEMPMONITOR_ON 0x00 // Default +#define RF_IMAGECAL_TEMPMONITOR_OFF 0x01 + +/*! + * RegTemp (Read Only) + */ + +/*! + * RegLowBat + */ +#define RF_LOWBAT_MASK 0xF7 +#define RF_LOWBAT_ON 0x08 +#define RF_LOWBAT_OFF 0x00 // Default + +#define RF_LOWBAT_TRIM_MASK 0xF8 +#define RF_LOWBAT_TRIM_1695 0x00 +#define RF_LOWBAT_TRIM_1764 0x01 +#define RF_LOWBAT_TRIM_1835 0x02 // Default +#define RF_LOWBAT_TRIM_1905 0x03 +#define RF_LOWBAT_TRIM_1976 0x04 +#define RF_LOWBAT_TRIM_2045 0x05 +#define RF_LOWBAT_TRIM_2116 0x06 +#define RF_LOWBAT_TRIM_2185 0x07 + +/*! + * RegIrqFlags1 + */ +#define RF_IRQFLAGS1_MODEREADY 0x80 + +#define RF_IRQFLAGS1_RXREADY 0x40 + +#define RF_IRQFLAGS1_TXREADY 0x20 + +#define RF_IRQFLAGS1_PLLLOCK 0x10 + +#define RF_IRQFLAGS1_RSSI 0x08 + +#define RF_IRQFLAGS1_TIMEOUT 0x04 + +#define RF_IRQFLAGS1_PREAMBLEDETECT 0x02 + +#define RF_IRQFLAGS1_SYNCADDRESSMATCH 0x01 + +/*! + * RegIrqFlags2 + */ +#define RF_IRQFLAGS2_FIFOFULL 0x80 + +#define RF_IRQFLAGS2_FIFOEMPTY 0x40 + +#define RF_IRQFLAGS2_FIFOLEVEL 0x20 + +#define RF_IRQFLAGS2_FIFOOVERRUN 0x10 + +#define RF_IRQFLAGS2_PACKETSENT 0x08 + +#define RF_IRQFLAGS2_PAYLOADREADY 0x04 + +#define RF_IRQFLAGS2_CRCOK 0x02 + +#define RF_IRQFLAGS2_LOWBAT 0x01 + +/*! + * RegDioMapping1 + */ +#define RF_DIOMAPPING1_DIO0_MASK 0x3F +#define RF_DIOMAPPING1_DIO0_00 0x00 // Default +#define RF_DIOMAPPING1_DIO0_01 0x40 +#define RF_DIOMAPPING1_DIO0_10 0x80 +#define RF_DIOMAPPING1_DIO0_11 0xC0 + +#define RF_DIOMAPPING1_DIO1_MASK 0xCF +#define RF_DIOMAPPING1_DIO1_00 0x00 // Default +#define RF_DIOMAPPING1_DIO1_01 0x10 +#define RF_DIOMAPPING1_DIO1_10 0x20 +#define RF_DIOMAPPING1_DIO1_11 0x30 + +#define RF_DIOMAPPING1_DIO2_MASK 0xF3 +#define RF_DIOMAPPING1_DIO2_00 0x00 // Default +#define RF_DIOMAPPING1_DIO2_01 0x04 +#define RF_DIOMAPPING1_DIO2_10 0x08 +#define RF_DIOMAPPING1_DIO2_11 0x0C + +#define RF_DIOMAPPING1_DIO3_MASK 0xFC +#define RF_DIOMAPPING1_DIO3_00 0x00 // Default +#define RF_DIOMAPPING1_DIO3_01 0x01 +#define RF_DIOMAPPING1_DIO3_10 0x02 +#define RF_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RF_DIOMAPPING2_DIO4_MASK 0x3F +#define RF_DIOMAPPING2_DIO4_00 0x00 // Default +#define RF_DIOMAPPING2_DIO4_01 0x40 +#define RF_DIOMAPPING2_DIO4_10 0x80 +#define RF_DIOMAPPING2_DIO4_11 0xC0 + +#define RF_DIOMAPPING2_DIO5_MASK 0xCF +#define RF_DIOMAPPING2_DIO5_00 0x00 // Default +#define RF_DIOMAPPING2_DIO5_01 0x10 +#define RF_DIOMAPPING2_DIO5_10 0x20 +#define RF_DIOMAPPING2_DIO5_11 0x30 + +#define RF_DIOMAPPING2_MAP_MASK 0xFE +#define RF_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RF_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegPllHop + */ +#define RF_PLLHOP_FASTHOP_MASK 0x7F +#define RF_PLLHOP_FASTHOP_ON 0x80 +#define RF_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RF_TCXO_TCXOINPUT_MASK 0xEF +#define RF_TCXO_TCXOINPUT_ON 0x10 +#define RF_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RF_PADAC_20DBM_MASK 0xF8 +#define RF_PADAC_20DBM_ON 0x07 +#define RF_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegPll + */ +#define RF_PLL_BANDWIDTH_MASK 0x3F +#define RF_PLL_BANDWIDTH_75 0x00 +#define RF_PLL_BANDWIDTH_150 0x40 +#define RF_PLL_BANDWIDTH_225 0x80 +#define RF_PLL_BANDWIDTH_300 0xC0 // Default + +/*! + * RegPllLowPn + */ +#define RF_PLLLOWPN_BANDWIDTH_MASK 0x3F +#define RF_PLLLOWPN_BANDWIDTH_75 0x00 +#define RF_PLLLOWPN_BANDWIDTH_150 0x40 +#define RF_PLLLOWPN_BANDWIDTH_225 0x80 +#define RF_PLLLOWPN_BANDWIDTH_300 0xC0 // Default + +/*! + * RegFormerTemp + */ + +/*! + * RegBitrateFrac + */ +#define RF_BITRATEFRAC_MASK 0xF0 + +#endif // __SX1272_REGS_FSK_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/registers/sx1272Regs-LoRa.h Tue Jan 05 16:43:48 2016 +0000 @@ -0,0 +1,545 @@ +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C) 2015 Semtech + +Description: SX1272 LoRa modem registers and bits definitions + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis and Gregory Cristian +*/ +#ifndef __SX1272_REGS_LORA_H__ +#define __SX1272_REGS_LORA_H__ + +/*! + * ============================================================================ + * SX1272 Internal registers Address + * ============================================================================ + */ +#define REG_LR_FIFO 0x00 +// Common settings +#define REG_LR_OPMODE 0x01 +#define REG_LR_FRFMSB 0x06 +#define REG_LR_FRFMID 0x07 +#define REG_LR_FRFLSB 0x08 +// Tx settings +#define REG_LR_PACONFIG 0x09 +#define REG_LR_PARAMP 0x0A +#define REG_LR_OCP 0x0B +// Rx settings +#define REG_LR_LNA 0x0C +// LoRa registers +#define REG_LR_FIFOADDRPTR 0x0D +#define REG_LR_FIFOTXBASEADDR 0x0E +#define REG_LR_FIFORXBASEADDR 0x0F +#define REG_LR_FIFORXCURRENTADDR 0x10 +#define REG_LR_IRQFLAGSMASK 0x11 +#define REG_LR_IRQFLAGS 0x12 +#define REG_LR_RXNBBYTES 0x13 +#define REG_LR_RXHEADERCNTVALUEMSB 0x14 +#define REG_LR_RXHEADERCNTVALUELSB 0x15 +#define REG_LR_RXPACKETCNTVALUEMSB 0x16 +#define REG_LR_RXPACKETCNTVALUELSB 0x17 +#define REG_LR_MODEMSTAT 0x18 +#define REG_LR_PKTSNRVALUE 0x19 +#define REG_LR_PKTRSSIVALUE 0x1A +#define REG_LR_RSSIVALUE 0x1B +#define REG_LR_HOPCHANNEL 0x1C +#define REG_LR_MODEMCONFIG1 0x1D +#define REG_LR_MODEMCONFIG2 0x1E +#define REG_LR_SYMBTIMEOUTLSB 0x1F +#define REG_LR_PREAMBLEMSB 0x20 +#define REG_LR_PREAMBLELSB 0x21 +#define REG_LR_PAYLOADLENGTH 0x22 +#define REG_LR_PAYLOADMAXLENGTH 0x23 +#define REG_LR_HOPPERIOD 0x24 +#define REG_LR_FIFORXBYTEADDR 0x25 +#define REG_LR_FEIMSB 0x28 +#define REG_LR_FEIMID 0x29 +#define REG_LR_FEILSB 0x2A +#define REG_LR_RSSIWIDEBAND 0x2C +#define REG_LR_DETECTOPTIMIZE 0x31 +#define REG_LR_INVERTIQ 0x33 +#define REG_LR_DETECTIONTHRESHOLD 0x37 +#define REG_LR_SYNCWORD 0x39 +#define REG_LR_INVERTIQ2 0x3B + +// end of documented register in datasheet +// I/O settings +#define REG_LR_DIOMAPPING1 0x40 +#define REG_LR_DIOMAPPING2 0x41 +// Version +#define REG_LR_VERSION 0x42 +// Additional settings +#define REG_LR_AGCREF 0x43 +#define REG_LR_AGCTHRESH1 0x44 +#define REG_LR_AGCTHRESH2 0x45 +#define REG_LR_AGCTHRESH3 0x46 +#define REG_LR_PLLHOP 0x4B +#define REG_LR_TCXO 0x58 +#define REG_LR_PADAC 0x5A +#define REG_LR_PLL 0x5C +#define REG_LR_PLLLOWPN 0x5E +#define REG_LR_FORMERTEMP 0x6C + +/*! + * ============================================================================ + * SX1272 LoRa bits control definition + * ============================================================================ + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default +#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF +#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 +#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default + +#define RFLR_OPMODE_MASK 0xF8 +#define RFLR_OPMODE_SLEEP 0x00 +#define RFLR_OPMODE_STANDBY 0x01 // Default +#define RFLR_OPMODE_SYNTHESIZER_TX 0x02 +#define RFLR_OPMODE_TRANSMITTER 0x03 +#define RFLR_OPMODE_SYNTHESIZER_RX 0x04 +#define RFLR_OPMODE_RECEIVER 0x05 +// LoRa specific modes +#define RFLR_OPMODE_RECEIVER_SINGLE 0x06 +#define RFLR_OPMODE_CAD 0x07 + +/*! + * RegFrf (MHz) + */ +#define RFLR_FRFMSB_915_MHZ 0xE4 // Default +#define RFLR_FRFMID_915_MHZ 0xC0 // Default +#define RFLR_FRFLSB_915_MHZ 0x00 // Default + +/*! + * RegPaConfig + */ +#define RFLR_PACONFIG_PASELECT_MASK 0x7F +#define RFLR_PACONFIG_PASELECT_PABOOST 0x80 +#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RFLR_PARAMP_LOWPNTXPLL_MASK 0xE0 +#define RFLR_PARAMP_LOWPNTXPLL_OFF 0x10 // Default +#define RFLR_PARAMP_LOWPNTXPLL_ON 0x00 + +#define RFLR_PARAMP_MASK 0xF0 +#define RFLR_PARAMP_3400_US 0x00 +#define RFLR_PARAMP_2000_US 0x01 +#define RFLR_PARAMP_1000_US 0x02 +#define RFLR_PARAMP_0500_US 0x03 +#define RFLR_PARAMP_0250_US 0x04 +#define RFLR_PARAMP_0125_US 0x05 +#define RFLR_PARAMP_0100_US 0x06 +#define RFLR_PARAMP_0062_US 0x07 +#define RFLR_PARAMP_0050_US 0x08 +#define RFLR_PARAMP_0040_US 0x09 // Default +#define RFLR_PARAMP_0031_US 0x0A +#define RFLR_PARAMP_0025_US 0x0B +#define RFLR_PARAMP_0020_US 0x0C +#define RFLR_PARAMP_0015_US 0x0D +#define RFLR_PARAMP_0012_US 0x0E +#define RFLR_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RFLR_OCP_MASK 0xDF +#define RFLR_OCP_ON 0x20 // Default +#define RFLR_OCP_OFF 0x00 + +#define RFLR_OCP_TRIM_MASK 0xE0 +#define RFLR_OCP_TRIM_045_MA 0x00 +#define RFLR_OCP_TRIM_050_MA 0x01 +#define RFLR_OCP_TRIM_055_MA 0x02 +#define RFLR_OCP_TRIM_060_MA 0x03 +#define RFLR_OCP_TRIM_065_MA 0x04 +#define RFLR_OCP_TRIM_070_MA 0x05 +#define RFLR_OCP_TRIM_075_MA 0x06 +#define RFLR_OCP_TRIM_080_MA 0x07 +#define RFLR_OCP_TRIM_085_MA 0x08 +#define RFLR_OCP_TRIM_090_MA 0x09 +#define RFLR_OCP_TRIM_095_MA 0x0A +#define RFLR_OCP_TRIM_100_MA 0x0B // Default +#define RFLR_OCP_TRIM_105_MA 0x0C +#define RFLR_OCP_TRIM_110_MA 0x0D +#define RFLR_OCP_TRIM_115_MA 0x0E +#define RFLR_OCP_TRIM_120_MA 0x0F +#define RFLR_OCP_TRIM_130_MA 0x10 +#define RFLR_OCP_TRIM_140_MA 0x11 +#define RFLR_OCP_TRIM_150_MA 0x12 +#define RFLR_OCP_TRIM_160_MA 0x13 +#define RFLR_OCP_TRIM_170_MA 0x14 +#define RFLR_OCP_TRIM_180_MA 0x15 +#define RFLR_OCP_TRIM_190_MA 0x16 +#define RFLR_OCP_TRIM_200_MA 0x17 +#define RFLR_OCP_TRIM_210_MA 0x18 +#define RFLR_OCP_TRIM_220_MA 0x19 +#define RFLR_OCP_TRIM_230_MA 0x1A +#define RFLR_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RFLR_LNA_GAIN_MASK 0x1F +#define RFLR_LNA_GAIN_G1 0x20 // Default +#define RFLR_LNA_GAIN_G2 0x40 +#define RFLR_LNA_GAIN_G3 0x60 +#define RFLR_LNA_GAIN_G4 0x80 +#define RFLR_LNA_GAIN_G5 0xA0 +#define RFLR_LNA_GAIN_G6 0xC0 + +#define RFLR_LNA_BOOST_MASK 0xFC +#define RFLR_LNA_BOOST_OFF 0x00 // Default +#define RFLR_LNA_BOOST_ON 0x03 + +/*! + * RegFifoAddrPtr + */ +#define RFLR_FIFOADDRPTR 0x00 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFOTXBASEADDR 0x80 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFORXBASEADDR 0x00 // Default + +/*! + * RegFifoRxCurrentAddr (Read Only) + */ + +/*! + * RegIrqFlagsMask + */ +#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 +#define RFLR_IRQFLAGS_RXDONE_MASK 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 +#define RFLR_IRQFLAGS_TXDONE_MASK 0x08 +#define RFLR_IRQFLAGS_CADDONE_MASK 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 +#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 + +/*! + * RegIrqFlags + */ +#define RFLR_IRQFLAGS_RXTIMEOUT 0x80 +#define RFLR_IRQFLAGS_RXDONE 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER 0x10 +#define RFLR_IRQFLAGS_TXDONE 0x08 +#define RFLR_IRQFLAGS_CADDONE 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 +#define RFLR_IRQFLAGS_CADDETECTED 0x01 + +/*! + * RegFifoRxNbBytes (Read Only) + */ + +/*! + * RegRxHeaderCntValueMsb (Read Only) + */ + +/*! + * RegRxHeaderCntValueLsb (Read Only) + */ + +/*! + * RegRxPacketCntValueMsb (Read Only) + */ + +/*! + * RegRxPacketCntValueLsb (Read Only) + */ + +/*! + * RegModemStat (Read Only) + */ +#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F +#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 + +/*! + * RegPktSnrValue (Read Only) + */ + +/*! + * RegPktRssiValue (Read Only) + */ + +/*! + * RegRssiValue (Read Only) + */ + +/*! + * RegHopChannel (Read Only) + */ +#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F +#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 +#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default + +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40 +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default + +#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F + +/*! + * RegModemConfig1 + */ +#define RFLR_MODEMCONFIG1_BW_MASK 0x3F +#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x00 // Default +#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x40 +#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x80 + +#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xC7 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x08 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x10 // Default +#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x18 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x20 + +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFB +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x04 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK 0xFD +#define RFLR_MODEMCONFIG1_RXPAYLOADCRC_ON 0x02 +#define RFLR_MODEMCONFIG1_RXPAYLOADCRC_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK 0xFE +#define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_ON 0x01 +#define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_OFF 0x00 // Default + +/*! + * RegModemConfig2 + */ +#define RFLR_MODEMCONFIG2_SF_MASK 0x0F +#define RFLR_MODEMCONFIG2_SF_6 0x60 +#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default +#define RFLR_MODEMCONFIG2_SF_8 0x80 +#define RFLR_MODEMCONFIG2_SF_9 0x90 +#define RFLR_MODEMCONFIG2_SF_10 0xA0 +#define RFLR_MODEMCONFIG2_SF_11 0xB0 +#define RFLR_MODEMCONFIG2_SF_12 0xC0 + +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 + +#define RFLR_MODEMCONFIG2_AGCAUTO_MASK 0xFB +#define RFLR_MODEMCONFIG2_AGCAUTO_ON 0x04 // Default +#define RFLR_MODEMCONFIG2_AGCAUTO_OFF 0x00 + +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default + +/*! + * RegSymbTimeoutLsb + */ +#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default + +/*! + * RegPreambleLengthMsb + */ +#define RFLR_PREAMBLELENGTHMSB 0x00 // Default + +/*! + * RegPreambleLengthLsb + */ +#define RFLR_PREAMBLELENGTHLSB 0x08 // Default + +/*! + * RegPayloadLength + */ +#define RFLR_PAYLOADLENGTH 0x0E // Default + +/*! + * RegPayloadMaxLength + */ +#define RFLR_PAYLOADMAXLENGTH 0xFF // Default + +/*! + * RegHopPeriod + */ +#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default + +/*! + * RegFifoRxByteAddr (Read Only) + */ + +/*! + * RegFeiMsb (Read Only) + */ + +/*! + * RegFeiMid (Read Only) + */ + +/*! + * RegFeiLsb (Read Only) + */ + +/*! + * RegRssiWideband (Read Only) + */ + +/*! + * RegDetectOptimize + */ +#define RFLR_DETECTIONOPTIMIZE_MASK 0xF8 +#define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default +#define RFLR_DETECTIONOPTIMIZE_SF6 0x05 + +/*! + * RegInvertIQ + */ +#define RFLR_INVERTIQ_RX_MASK 0xBF +#define RFLR_INVERTIQ_RX_OFF 0x00 +#define RFLR_INVERTIQ_RX_ON 0x40 +#define RFLR_INVERTIQ_TX_MASK 0xFE +#define RFLR_INVERTIQ_TX_OFF 0x01 +#define RFLR_INVERTIQ_TX_ON 0x00 + +/*! + * RegDetectionThreshold + */ +#define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default +#define RFLR_DETECTIONTHRESH_SF6 0x0C + +/*! + * RegInvertIQ2 + */ +#define RFLR_INVERTIQ2_ON 0x19 +#define RFLR_INVERTIQ2_OFF 0x1D + +/*! + * RegDioMapping1 + */ +#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F +#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO0_01 0x40 +#define RFLR_DIOMAPPING1_DIO0_10 0x80 +#define RFLR_DIOMAPPING1_DIO0_11 0xC0 + +#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF +#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO1_01 0x10 +#define RFLR_DIOMAPPING1_DIO1_10 0x20 +#define RFLR_DIOMAPPING1_DIO1_11 0x30 + +#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 +#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO2_01 0x04 +#define RFLR_DIOMAPPING1_DIO2_10 0x08 +#define RFLR_DIOMAPPING1_DIO2_11 0x0C + +#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC +#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO3_01 0x01 +#define RFLR_DIOMAPPING1_DIO3_10 0x02 +#define RFLR_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F +#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO4_01 0x40 +#define RFLR_DIOMAPPING2_DIO4_10 0x80 +#define RFLR_DIOMAPPING2_DIO4_11 0xC0 + +#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF +#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO5_01 0x10 +#define RFLR_DIOMAPPING2_DIO5_10 0x20 +#define RFLR_DIOMAPPING2_DIO5_11 0x30 + +#define RFLR_DIOMAPPING2_MAP_MASK 0xFE +#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegPllHop + */ +#define RFLR_PLLHOP_FASTHOP_MASK 0x7F +#define RFLR_PLLHOP_FASTHOP_ON 0x80 +#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RFLR_TCXO_TCXOINPUT_MASK 0xEF +#define RFLR_TCXO_TCXOINPUT_ON 0x10 +#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RFLR_PADAC_20DBM_MASK 0xF8 +#define RFLR_PADAC_20DBM_ON 0x07 +#define RFLR_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegPll + */ +#define RFLR_PLL_BANDWIDTH_MASK 0x3F +#define RFLR_PLL_BANDWIDTH_75 0x00 +#define RFLR_PLL_BANDWIDTH_150 0x40 +#define RFLR_PLL_BANDWIDTH_225 0x80 +#define RFLR_PLL_BANDWIDTH_300 0xC0 // Default + +/*! + * RegPllLowPn + */ +#define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F +#define RFLR_PLLLOWPN_BANDWIDTH_75 0x00 +#define RFLR_PLLLOWPN_BANDWIDTH_150 0x40 +#define RFLR_PLLLOWPN_BANDWIDTH_225 0x80 +#define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default + +/*! + * RegFormerTemp + */ + +#endif // __SX1272_REGS_LORA_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sx1272/sx1272-hal.cpp Tue Jan 05 16:43:48 2016 +0000
@@ -0,0 +1,336 @@
+/*
+ / _____) _ | |
+( (____ _____ ____ _| |_ _____ ____| |__
+ \____ \| ___ | (_ _) ___ |/ ___) _ \
+ _____) ) ____| | | || |_| ____( (___| | | |
+(______/|_____)_|_|_| \__)_____)\____)_| |_|
+ (C) 2015 Semtech
+
+Description: -
+
+License: Revised BSD License, see LICENSE.TXT file include in the project
+
+Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
+*/
+#include "sx1272-hal.h"
+
+const RadioRegisters_t SX1272MB1DxS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
+
+SX1272MB1DxS::SX1272MB1DxS( RadioEvents_t *events,
+ PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
+ PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
+#if defined ( TARGET_MOTE_L152RC )
+ PinName rfSwitchCntr1, PinName rfSwitchCntr2 )
+#else
+ PinName antSwitch )
+#endif
+ : SX1272( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
+#if defined ( TARGET_MOTE_L152RC )
+ RfSwitchCntr1( rfSwitchCntr1 ),
+ RfSwitchCntr2( rfSwitchCntr2 ),
+ PwrAmpCntr( PD_2 )
+#else
+ AntSwitch( antSwitch ),
+ #if( defined ( TARGET_NUCLEO_L152RE ) )
+ Fake( D8 )
+ #else
+ Fake( A3 )
+ #endif
+#endif
+{
+ this->RadioEvents = events;
+
+ Reset( );
+
+ IoInit( );
+
+ SetOpMode( RF_OPMODE_SLEEP );
+
+ IoIrqInit( dioIrq );
+
+ RadioRegistersInit( );
+
+ SetModem( MODEM_FSK );
+
+ this->settings.State = RF_IDLE ;
+}
+
+SX1272MB1DxS::SX1272MB1DxS( RadioEvents_t *events )
+ #if defined ( TARGET_NUCLEO_L152RE )
+ : SX1272( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
+ AntSwitch( A4 ),
+ Fake( D8 )
+ #elif defined ( TARGET_MOTE_L152RC )
+ : SX1272( events, PB_15, PB_14, PB_13, PB_12, PC_2, PC_6, PC_10, PC_11, PC_8, PC_9, PC_12 ),
+ RfSwitchCntr1( PC_4 ),
+ RfSwitchCntr2( PC_13 ),
+ PwrAmpCntr( PD_2 )
+ #else
+ : SX1272( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
+ AntSwitch( A4 ),
+ Fake( A3 )
+ #endif
+{
+ this->RadioEvents = events;
+
+ Reset( );
+
+ boardConnected = UNKNOWN;
+
+ DetectBoardType( );
+
+ IoInit( );
+
+ SetOpMode( RF_OPMODE_SLEEP );
+ IoIrqInit( dioIrq );
+
+ RadioRegistersInit( );
+
+ SetModem( MODEM_FSK );
+
+ this->settings.State = RF_IDLE ;
+}
+
+//-------------------------------------------------------------------------
+// Board relative functions
+//-------------------------------------------------------------------------
+uint8_t SX1272MB1DxS::DetectBoardType( void )
+{
+ if( boardConnected == UNKNOWN )
+ {
+#if defined ( TARGET_MOTE_L152RC )
+ boardConnected = NA_MOTE_72;
+#else
+ this->AntSwitch.input( );
+ wait_ms( 1 );
+ if( this->AntSwitch == 1 )
+ {
+ boardConnected = SX1272MB1DCS;
+ }
+ else
+ {
+ boardConnected = SX1272MB1DAS;
+ }
+ this->AntSwitch.output( );
+ wait_ms( 1 );
+#endif
+ }
+ return ( boardConnected );
+}
+
+void SX1272MB1DxS::IoInit( void )
+{
+ AntSwInit( );
+ SpiInit( );
+}
+
+void SX1272MB1DxS::RadioRegistersInit( )
+{
+ uint8_t i = 0;
+ for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
+ {
+ SetModem( RadioRegsInit[i].Modem );
+ Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
+ }
+}
+
+void SX1272MB1DxS::SpiInit( void )
+{
+ nss = 1;
+ spi.format( 8,0 );
+ uint32_t frequencyToSet = 8000000;
+ #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_LPC11U6X ) )
+ spi.frequency( frequencyToSet );
+ #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
+ spi.frequency( frequencyToSet * 2 );
+ #else
+ #warning "Check the board's SPI frequency"
+ #endif
+ wait(0.1);
+}
+
+void SX1272MB1DxS::IoIrqInit( DioIrqHandler *irqHandlers )
+{
+#if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_LPC11U6X ) )
+ dio0.mode( PullDown );
+ dio1.mode( PullDown );
+ dio2.mode( PullDown );
+ dio3.mode( PullDown );
+ dio4.mode( PullDown );
+#endif
+ dio0.rise( this, static_cast< TriggerMB1DxS > ( irqHandlers[0] ) );
+ dio1.rise( this, static_cast< TriggerMB1DxS > ( irqHandlers[1] ) );
+ dio2.rise( this, static_cast< TriggerMB1DxS > ( irqHandlers[2] ) );
+ dio3.rise( this, static_cast< TriggerMB1DxS > ( irqHandlers[3] ) );
+ dio4.rise( this, static_cast< TriggerMB1DxS > ( irqHandlers[4] ) );
+}
+
+void SX1272MB1DxS::IoDeInit( void )
+{
+ //nothing
+}
+
+uint8_t SX1272MB1DxS::GetPaSelect( uint32_t channel )
+{
+ if( boardConnected == SX1272MB1DCS )
+ {
+ return RF_PACONFIG_PASELECT_PABOOST;
+ }
+ else
+ {
+ return RF_PACONFIG_PASELECT_RFO;
+ }
+}
+
+void SX1272MB1DxS::SetAntSwLowPower( bool status )
+{
+ if( isRadioActive != status )
+ {
+ isRadioActive = status;
+
+ if( status == false )
+ {
+ AntSwInit( );
+ }
+ else
+ {
+ AntSwDeInit( );
+ }
+ }
+}
+
+void SX1272MB1DxS::AntSwInit( void )
+{
+#if defined ( TARGET_MOTE_L152RC )
+ this->RfSwitchCntr1 = 0;
+ this->RfSwitchCntr2 = 0;
+ this->PwrAmpCntr = 0;
+#else
+ this->AntSwitch = 0;
+#endif
+}
+
+void SX1272MB1DxS::AntSwDeInit( void )
+{
+#if defined ( TARGET_MOTE_L152RC )
+ this->RfSwitchCntr1 = 0;
+ this->RfSwitchCntr2 = 0;
+ this->PwrAmpCntr = 0;
+#else
+ this->AntSwitch = 0;
+#endif
+}
+
+void SX1272MB1DxS::SetAntSw( uint8_t rxTx )
+{
+#if defined ( TARGET_MOTE_L152RC )
+ switch( this->currentOpMode )
+ {
+ case RFLR_OPMODE_TRANSMITTER:
+ if( ( Read( REG_PACONFIG ) & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
+ {
+ this->RfSwitchCntr1 = 1;
+ this->RfSwitchCntr2 = 0;
+ }
+ else
+ {
+ this->RfSwitchCntr1 = 0;
+ this->RfSwitchCntr2 = 1;
+ }
+ break;
+ case RFLR_OPMODE_RECEIVER:
+ case RFLR_OPMODE_RECEIVER_SINGLE:
+ case RFLR_OPMODE_CAD:
+ this->RfSwitchCntr1 = 1;
+ this->RfSwitchCntr2 = 1;
+ break;
+ default:
+ this->RfSwitchCntr1 = 0;
+ this->RfSwitchCntr2 = 0;
+ this->PwrAmpCntr = 0;
+ break;
+ }
+#else
+ if( this->rxTx == rxTx )
+ {
+ //no need to go further
+ return;
+ }
+
+ this->rxTx = rxTx;
+
+ // 1: Tx, 0: Rx
+ if( rxTx != 0 )
+ {
+ this->AntSwitch = 1;
+ }
+ else
+ {
+ this->AntSwitch = 0;
+ }
+#endif
+}
+
+bool SX1272MB1DxS::CheckRfFrequency( uint32_t frequency )
+{
+ //TODO: Implement check, currently all frequencies are supported
+ return true;
+}
+
+
+void SX1272MB1DxS::Reset( void )
+{
+ reset.output();
+ reset = 0;
+ wait_ms( 1 );
+ reset.input();
+ wait_ms( 6 );
+}
+
+void SX1272MB1DxS::Write( uint8_t addr, uint8_t data )
+{
+ Write( addr, &data, 1 );
+}
+
+uint8_t SX1272MB1DxS::Read( uint8_t addr )
+{
+ uint8_t data;
+ Read( addr, &data, 1 );
+ return data;
+}
+
+void SX1272MB1DxS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
+{
+ uint8_t i;
+
+ nss = 0;
+ spi.write( addr | 0x80 );
+ for( i = 0; i < size; i++ )
+ {
+ spi.write( buffer[i] );
+ }
+ nss = 1;
+}
+
+void SX1272MB1DxS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
+{
+ uint8_t i;
+
+ nss = 0;
+ spi.write( addr & 0x7F );
+ for( i = 0; i < size; i++ )
+ {
+ buffer[i] = spi.write( 0 );
+ }
+ nss = 1;
+}
+
+void SX1272MB1DxS::WriteFifo( uint8_t *buffer, uint8_t size )
+{
+ Write( 0, buffer, size );
+}
+
+void SX1272MB1DxS::ReadFifo( uint8_t *buffer, uint8_t size )
+{
+ Read( 0, buffer, size );
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sx1272/sx1272-hal.h Tue Jan 05 16:43:48 2016 +0000
@@ -0,0 +1,215 @@
+/*
+ / _____) _ | |
+( (____ _____ ____ _| |_ _____ ____| |__
+ \____ \| ___ | (_ _) ___ |/ ___) _ \
+ _____) ) ____| | | || |_| ____( (___| | | |
+(______/|_____)_|_|_| \__)_____)\____)_| |_|
+ (C) 2015 Semtech
+
+Description: -
+
+License: Revised BSD License, see LICENSE.TXT file include in the project
+
+Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
+*/
+#ifndef __SX1272_HAL_H__
+#define __SX1272_HAL_H__
+#include "sx1272.h"
+
+/*!
+ * \brief Radio hardware registers initialization definition
+ *
+ * \remark Can be automatically generated by the SX1272 GUI (not yet implemented)
+ */
+#define RADIO_INIT_REGISTERS_VALUE \
+{ \
+ { MODEM_FSK , REG_LNA , 0x23 },\
+ { MODEM_FSK , REG_RXCONFIG , 0x1E },\
+ { MODEM_FSK , REG_RSSICONFIG , 0xD2 },\
+ { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },\
+ { MODEM_FSK , REG_OSC , 0x07 },\
+ { MODEM_FSK , REG_SYNCCONFIG , 0x12 },\
+ { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },\
+ { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },\
+ { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },\
+ { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },\
+ { MODEM_FSK , REG_FIFOTHRESH , 0x8F },\
+ { MODEM_FSK , REG_IMAGECAL , 0x02 },\
+ { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },\
+ { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },\
+ { MODEM_LORA, REG_LR_DETECTOPTIMIZE , 0x43 },\
+ { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },\
+} \
+
+/*!
+ * Actual implementation of a SX1272 radio, includes some modifications to make it compatible with the MB1 LAS board
+ */
+class SX1272MB1DxS : public SX1272
+{
+protected:
+ /*!
+ * Antenna switch GPIO pins objects
+ */
+#if defined ( TARGET_MOTE_L152RC )
+ DigitalOut RfSwitchCntr1;
+ DigitalOut RfSwitchCntr2;
+ DigitalOut PwrAmpCntr;
+#else
+ DigitalInOut AntSwitch;
+ DigitalIn Fake;
+#endif
+
+private:
+ static const RadioRegisters_t RadioRegsInit[];
+
+public:
+ SX1272MB1DxS( RadioEvents_t *events,
+ PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
+ PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
+#if defined ( TARGET_MOTE_L152RC )
+ PinName rfSwitchCntr1, PinName rfSwitchCntr2 );
+#else
+ PinName antSwitch );
+#endif
+
+ SX1272MB1DxS( RadioEvents_t *events );
+
+ virtual ~SX1272MB1DxS( ) { };
+
+ protected:
+ /*!
+ * @brief Initializes the radio I/Os pins interface
+ */
+ virtual void IoInit( void );
+
+ /*!
+ * @brief Initializes the radio registers
+ */
+ virtual void RadioRegistersInit( );
+
+ /*!
+ * @brief Initializes the radio SPI
+ */
+ virtual void SpiInit( void );
+
+ /*!
+ * @brief Initializes DIO IRQ handlers
+ *
+ * @param [IN] irqHandlers Array containing the IRQ callback functions
+ */
+ virtual void IoIrqInit( DioIrqHandler *irqHandlers );
+
+ /*!
+ * @brief De-initializes the radio I/Os pins interface.
+ *
+ * \remark Useful when going in MCU lowpower modes
+ */
+ virtual void IoDeInit( void );
+
+ /*!
+ * @brief Gets the board PA selection configuration
+ *
+ * @param [IN] channel Channel frequency in Hz
+ * @retval PaSelect RegPaConfig PaSelect value
+ */
+ virtual uint8_t GetPaSelect( uint32_t channel );
+
+ /*!
+ * @brief Set the RF Switch I/Os pins in Low Power mode
+ *
+ * @param [IN] status enable or disable
+ */
+ virtual void SetAntSwLowPower( bool status );
+
+ /*!
+ * @brief Initializes the RF Switch I/Os pins interface
+ */
+ virtual void AntSwInit( void );
+
+ /*!
+ * @brief De-initializes the RF Switch I/Os pins interface
+ *
+ * \remark Needed to decrease the power consumption in MCU lowpower modes
+ */
+ virtual void AntSwDeInit( void );
+
+ /*!
+ * @brief Controls the antena switch if necessary.
+ *
+ * \remark see errata note
+ *
+ * @param [IN] rxTx [1: Tx, 0: Rx]
+ */
+ virtual void SetAntSw( uint8_t rxTx );
+
+ public:
+ /*!
+ * @brief Detect the board connected by reading the value of the antenna switch pin
+ */
+ virtual uint8_t DetectBoardType( void );
+
+ /*!
+ * @brief Checks if the given RF frequency is supported by the hardware
+ *
+ * @param [IN] frequency RF frequency to be checked
+ * @retval isSupported [true: supported, false: unsupported]
+ */
+ virtual bool CheckRfFrequency( uint32_t frequency );
+
+ /*!
+ * @brief Writes the radio register at the specified address
+ *
+ * @param [IN]: addr Register address
+ * @param [IN]: data New register value
+ */
+ virtual void Write ( uint8_t addr, uint8_t data ) ;
+
+ /*!
+ * @brief Reads the radio register at the specified address
+ *
+ * @param [IN]: addr Register address
+ * @retval data Register value
+ */
+ virtual uint8_t Read ( uint8_t addr ) ;
+
+ /*!
+ * @brief Writes multiple radio registers starting at address
+ *
+ * @param [IN] addr First Radio register address
+ * @param [IN] buffer Buffer containing the new register's values
+ * @param [IN] size Number of registers to be written
+ */
+ virtual void Write( uint8_t addr, uint8_t *buffer, uint8_t size ) ;
+
+ /*!
+ * @brief Reads multiple radio registers starting at address
+ *
+ * @param [IN] addr First Radio register address
+ * @param [OUT] buffer Buffer where to copy the registers data
+ * @param [IN] size Number of registers to be read
+ */
+ virtual void Read ( uint8_t addr, uint8_t *buffer, uint8_t size ) ;
+
+ /*!
+ * @brief Writes the buffer contents to the SX1272 FIFO
+ *
+ * @param [IN] buffer Buffer containing data to be put on the FIFO.
+ * @param [IN] size Number of bytes to be written to the FIFO
+ */
+ virtual void WriteFifo( uint8_t *buffer, uint8_t size ) ;
+
+ /*!
+ * @brief Reads the contents of the SX1272 FIFO
+ *
+ * @param [OUT] buffer Buffer where to copy the FIFO read data.
+ * @param [IN] size Number of bytes to be read from the FIFO
+ */
+ virtual void ReadFifo( uint8_t *buffer, uint8_t size ) ;
+
+ /*!
+ * @brief Reset the SX1272
+ */
+ virtual void Reset( void );
+};
+
+#endif // __SX1272_HAL_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sx1272/sx1272.cpp Tue Jan 05 16:43:48 2016 +0000
@@ -0,0 +1,1418 @@
+/*
+ / _____) _ | |
+( (____ _____ ____ _| |_ _____ ____| |__
+ \____ \| ___ | (_ _) ___ |/ ___) _ \
+ _____) ) ____| | | || |_| ____( (___| | | |
+(______/|_____)_|_|_| \__)_____)\____)_| |_|
+ (C) 2015 Semtech
+
+Description: Actual implementation of a SX1272 radio, inherits Radio
+
+License: Revised BSD License, see LICENSE.TXT file include in the project
+
+Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
+*/
+#include "sx1272.h"
+
+const FskBandwidth_t SX1272::FskBandwidths[] =
+{
+ { 2600 , 0x17 },
+ { 3100 , 0x0F },
+ { 3900 , 0x07 },
+ { 5200 , 0x16 },
+ { 6300 , 0x0E },
+ { 7800 , 0x06 },
+ { 10400 , 0x15 },
+ { 12500 , 0x0D },
+ { 15600 , 0x05 },
+ { 20800 , 0x14 },
+ { 25000 , 0x0C },
+ { 31300 , 0x04 },
+ { 41700 , 0x13 },
+ { 50000 , 0x0B },
+ { 62500 , 0x03 },
+ { 83333 , 0x12 },
+ { 100000, 0x0A },
+ { 125000, 0x02 },
+ { 166700, 0x11 },
+ { 200000, 0x09 },
+ { 250000, 0x01 },
+ { 300000, 0x00 }, // Invalid Badwidth
+};
+
+
+SX1272::SX1272( RadioEvents_t *events,
+ PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
+ PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
+ : Radio( events ),
+ spi( mosi, miso, sclk ),
+ nss( nss ),
+ reset( reset ),
+ dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
+ isRadioActive( false )
+{
+ wait_ms( 10 );
+ this->rxTx = 0;
+ this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
+ currentOpMode = RF_OPMODE_STANDBY;
+
+ this->RadioEvents = events;
+
+ this->dioIrq = new DioIrqHandler[6];
+
+ this->dioIrq[0] = &SX1272::OnDio0Irq;
+ this->dioIrq[1] = &SX1272::OnDio1Irq;
+ this->dioIrq[2] = &SX1272::OnDio2Irq;
+ this->dioIrq[3] = &SX1272::OnDio3Irq;
+ this->dioIrq[4] = &SX1272::OnDio4Irq;
+ this->dioIrq[5] = NULL;
+
+ this->settings.State = RF_IDLE;
+}
+
+SX1272::~SX1272( )
+{
+ delete this->rxBuffer;
+ delete this->dioIrq;
+}
+
+void SX1272::Init( RadioEvents_t *events )
+{
+ this->RadioEvents = events;
+}
+
+RadioState SX1272::GetStatus( void )
+{
+ return this->settings.State;
+}
+
+void SX1272::SetChannel( uint32_t freq )
+{
+ this->settings.Channel = freq;
+ freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
+ Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
+ Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
+ Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
+}
+
+bool SX1272::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
+{
+ int16_t rssi = 0;
+
+ SetModem( modem );
+
+ SetChannel( freq );
+
+ SetOpMode( RF_OPMODE_RECEIVER );
+
+ wait_ms( 1 );
+
+ rssi = GetRssi( modem );
+
+ Sleep( );
+
+ if( rssi > rssiThresh )
+ {
+ return false;
+ }
+ return true;
+}
+
+uint32_t SX1272::Random( void )
+{
+ uint8_t i;
+ uint32_t rnd = 0;
+
+ /*
+ * Radio setup for random number generation
+ */
+ // Set LoRa modem ON
+ SetModem( MODEM_LORA );
+
+ // Disable LoRa modem interrupts
+ Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+ RFLR_IRQFLAGS_CADDETECTED );
+
+ // Set radio in continuous reception
+ SetOpMode( RF_OPMODE_RECEIVER );
+
+ for( i = 0; i < 32; i++ )
+ {
+ wait_ms( 1 );
+ // Unfiltered RSSI value reading. Only takes the LSB value
+ rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
+ }
+
+ Sleep( );
+
+ return rnd;
+}
+
+/*!
+ * Returns the known FSK bandwidth registers value
+ *
+ * \param [IN] bandwidth Bandwidth value in Hz
+ * \retval regValue Bandwidth register value.
+ */
+uint8_t SX1272::GetFskBandwidthRegValue( uint32_t bandwidth )
+{
+ uint8_t i;
+
+ for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
+ {
+ if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
+ {
+ return FskBandwidths[i].RegValue;
+ }
+ }
+ // ERROR: Value not found
+ while( 1 );
+}
+
+void SX1272::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
+ uint32_t datarate, uint8_t coderate,
+ uint32_t bandwidthAfc, uint16_t preambleLen,
+ uint16_t symbTimeout, bool fixLen,
+ uint8_t payloadLen,
+ bool crcOn, bool freqHopOn, uint8_t hopPeriod,
+ bool iqInverted, bool rxContinuous )
+{
+ SetModem( modem );
+
+ switch( modem )
+ {
+ case MODEM_FSK:
+ {
+ this->settings.Fsk.Bandwidth = bandwidth;
+ this->settings.Fsk.Datarate = datarate;
+ this->settings.Fsk.BandwidthAfc = bandwidthAfc;
+ this->settings.Fsk.FixLen = fixLen;
+ this->settings.Fsk.PayloadLen = payloadLen;
+ this->settings.Fsk.CrcOn = crcOn;
+ this->settings.Fsk.IqInverted = iqInverted;
+ this->settings.Fsk.RxContinuous = rxContinuous;
+ this->settings.Fsk.PreambleLen = preambleLen;
+
+ datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
+ Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
+ Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
+
+ Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
+ Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
+
+ Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
+ Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
+
+ if( fixLen == 1 )
+ {
+ Write( REG_PAYLOADLENGTH, payloadLen );
+ }
+
+ Write( REG_PACKETCONFIG1,
+ ( Read( REG_PACKETCONFIG1 ) &
+ RF_PACKETCONFIG1_CRC_MASK &
+ RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
+ ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
+ ( crcOn << 4 ) );
+ }
+ break;
+ case MODEM_LORA:
+ {
+ this->settings.LoRa.Bandwidth = bandwidth;
+ this->settings.LoRa.Datarate = datarate;
+ this->settings.LoRa.Coderate = coderate;
+ this->settings.LoRa.PreambleLen = preambleLen;
+ this->settings.LoRa.FixLen = fixLen;
+ this->settings.LoRa.PayloadLen = payloadLen;
+ this->settings.LoRa.CrcOn = crcOn;
+ this->settings.LoRa.FreqHopOn = freqHopOn;
+ this->settings.LoRa.HopPeriod = hopPeriod;
+ this->settings.LoRa.IqInverted = iqInverted;
+ this->settings.LoRa.RxContinuous = rxContinuous;
+
+ if( datarate > 12 )
+ {
+ datarate = 12;
+ }
+ else if( datarate < 6 )
+ {
+ datarate = 6;
+ }
+
+ if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
+ ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
+ {
+ this->settings.LoRa.LowDatarateOptimize = 0x01;
+ }
+ else
+ {
+ this->settings.LoRa.LowDatarateOptimize = 0x00;
+ }
+
+ Write( REG_LR_MODEMCONFIG1,
+ ( Read( REG_LR_MODEMCONFIG1 ) &
+ RFLR_MODEMCONFIG1_BW_MASK &
+ RFLR_MODEMCONFIG1_CODINGRATE_MASK &
+ RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
+ RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
+ RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
+ ( bandwidth << 6 ) | ( coderate << 3 ) |
+ ( fixLen << 2 ) | ( crcOn << 1 ) |
+ this->settings.LoRa.LowDatarateOptimize );
+
+ Write( REG_LR_MODEMCONFIG2,
+ ( Read( REG_LR_MODEMCONFIG2 ) &
+ RFLR_MODEMCONFIG2_SF_MASK &
+ RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
+ ( datarate << 4 ) |
+ ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
+
+ Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
+
+ Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
+ Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
+
+ if( fixLen == 1 )
+ {
+ Write( REG_LR_PAYLOADLENGTH, payloadLen );
+ }
+
+ if( this->settings.LoRa.FreqHopOn == true )
+ {
+ Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
+ Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
+ }
+
+ if( datarate == 6 )
+ {
+ Write( REG_LR_DETECTOPTIMIZE,
+ ( Read( REG_LR_DETECTOPTIMIZE ) &
+ RFLR_DETECTIONOPTIMIZE_MASK ) |
+ RFLR_DETECTIONOPTIMIZE_SF6 );
+ Write( REG_LR_DETECTIONTHRESHOLD,
+ RFLR_DETECTIONTHRESH_SF6 );
+ }
+ else
+ {
+ Write( REG_LR_DETECTOPTIMIZE,
+ ( Read( REG_LR_DETECTOPTIMIZE ) &
+ RFLR_DETECTIONOPTIMIZE_MASK ) |
+ RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
+ Write( REG_LR_DETECTIONTHRESHOLD,
+ RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
+ }
+ }
+ break;
+ }
+}
+#if defined ( TARGET_MOTE_L152RC )
+/* PD_2=0 PD_2=1
+op PaB rfo rfo
+0 4.6 18.5 27.0
+1 5.6 21.1 28.1
+2 6.7 23.3 29.1
+3 7.7 25.3 30.1
+4 8.8 26.2 30.7
+5 9.8 27.3 31.2
+6 10.7 28.1 31.6
+7 11.7 28.6 32.2
+8 12.8 29.2 32.4
+9 13.7 29.9 32.9
+10 14.7 30.5 33.1
+11 15.6 30.8 33.4
+12 16.4 30.9 33.6
+13 17.1 31.0 33.7
+14 17.8 31.1 33.7
+15 18.4 31.1 33.7
+*/
+// txpow: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
+static const uint8_t PaBTable[20] = { 0, 0, 0, 0, 0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15 };
+
+// txpow: 20 21 22 23 24 25 26 27 28 29 30
+static const uint8_t RfoTable[11] = { 1, 1, 1, 2, 2, 3, 4, 5, 6, 8, 9 };
+#endif
+
+void SX1272::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
+ uint32_t bandwidth, uint32_t datarate,
+ uint8_t coderate, uint16_t preambleLen,
+ bool fixLen, bool crcOn, bool freqHopOn,
+ uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
+{
+ uint8_t paConfig = 0;
+ uint8_t paDac = 0;
+
+ SetModem( modem );
+
+ paConfig = Read( REG_PACONFIG );
+ paDac = Read( REG_PADAC );
+
+#if defined ( TARGET_MOTE_L152RC )
+ if( power > 19 )
+ {
+ paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | RF_PACONFIG_PASELECT_RFO;
+ paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | RfoTable[power - 20];
+ }
+ else
+ {
+ paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | RF_PACONFIG_PASELECT_PABOOST;
+ paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | PaBTable[power];
+ }
+#else
+ paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
+
+ if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
+ {
+ if( power > 17 )
+ {
+ paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
+ }
+ else
+ {
+ paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
+ }
+ if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
+ {
+ if( power < 5 )
+ {
+ power = 5;
+ }
+ if( power > 20 )
+ {
+ power = 20;
+ }
+ paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
+ }
+ else
+ {
+ if( power < 2 )
+ {
+ power = 2;
+ }
+ if( power > 17 )
+ {
+ power = 17;
+ }
+ paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
+ }
+ }
+ else
+ {
+ if( power < -1 )
+ {
+ power = -1;
+ }
+ if( power > 14 )
+ {
+ power = 14;
+ }
+ paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
+ }
+#endif
+
+ Write( REG_PACONFIG, paConfig );
+ Write( REG_PADAC, paDac );
+
+ switch( modem )
+ {
+ case MODEM_FSK:
+ {
+ this->settings.Fsk.Power = power;
+ this->settings.Fsk.Fdev = fdev;
+ this->settings.Fsk.Bandwidth = bandwidth;
+ this->settings.Fsk.Datarate = datarate;
+ this->settings.Fsk.PreambleLen = preambleLen;
+ this->settings.Fsk.FixLen = fixLen;
+ this->settings.Fsk.CrcOn = crcOn;
+ this->settings.Fsk.IqInverted = iqInverted;
+ this->settings.Fsk.TxTimeout = timeout;
+
+ fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
+ Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
+ Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
+
+ datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
+ Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
+ Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
+
+ Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
+ Write( REG_PREAMBLELSB, preambleLen & 0xFF );
+
+ Write( REG_PACKETCONFIG1,
+ ( Read( REG_PACKETCONFIG1 ) &
+ RF_PACKETCONFIG1_CRC_MASK &
+ RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
+ ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
+ ( crcOn << 4 ) );
+
+ }
+ break;
+ case MODEM_LORA:
+ {
+ this->settings.LoRa.Power = power;
+ this->settings.LoRa.Bandwidth = bandwidth;
+ this->settings.LoRa.Datarate = datarate;
+ this->settings.LoRa.Coderate = coderate;
+ this->settings.LoRa.PreambleLen = preambleLen;
+ this->settings.LoRa.FixLen = fixLen;
+ this->settings.LoRa.FreqHopOn = freqHopOn;
+ this->settings.LoRa.HopPeriod = hopPeriod;
+ this->settings.LoRa.CrcOn = crcOn;
+ this->settings.LoRa.IqInverted = iqInverted;
+ this->settings.LoRa.TxTimeout = timeout;
+
+ if( datarate > 12 )
+ {
+ datarate = 12;
+ }
+ else if( datarate < 6 )
+ {
+ datarate = 6;
+ }
+ if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
+ ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
+ {
+ this->settings.LoRa.LowDatarateOptimize = 0x01;
+ }
+ else
+ {
+ this->settings.LoRa.LowDatarateOptimize = 0x00;
+ }
+
+ if( this->settings.LoRa.FreqHopOn == true )
+ {
+ Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
+ Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
+ }
+
+ Write( REG_LR_MODEMCONFIG1,
+ ( Read( REG_LR_MODEMCONFIG1 ) &
+ RFLR_MODEMCONFIG1_BW_MASK &
+ RFLR_MODEMCONFIG1_CODINGRATE_MASK &
+ RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
+ RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
+ RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
+ ( bandwidth << 6 ) | ( coderate << 3 ) |
+ ( fixLen << 2 ) | ( crcOn << 1 ) |
+ this->settings.LoRa.LowDatarateOptimize );
+
+ Write( REG_LR_MODEMCONFIG2,
+ ( Read( REG_LR_MODEMCONFIG2 ) &
+ RFLR_MODEMCONFIG2_SF_MASK ) |
+ ( datarate << 4 ) );
+
+
+ Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
+ Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
+
+ if( datarate == 6 )
+ {
+ Write( REG_LR_DETECTOPTIMIZE,
+ ( Read( REG_LR_DETECTOPTIMIZE ) &
+ RFLR_DETECTIONOPTIMIZE_MASK ) |
+ RFLR_DETECTIONOPTIMIZE_SF6 );
+ Write( REG_LR_DETECTIONTHRESHOLD,
+ RFLR_DETECTIONTHRESH_SF6 );
+ }
+ else
+ {
+ Write( REG_LR_DETECTOPTIMIZE,
+ ( Read( REG_LR_DETECTOPTIMIZE ) &
+ RFLR_DETECTIONOPTIMIZE_MASK ) |
+ RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
+ Write( REG_LR_DETECTIONTHRESHOLD,
+ RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
+ }
+ }
+ break;
+ }
+}
+
+double SX1272::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
+{
+ uint32_t airTime = 0;
+
+ switch( modem )
+ {
+ case MODEM_FSK:
+ {
+ airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
+ ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
+ ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
+ ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
+ pktLen +
+ ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
+ this->settings.Fsk.Datarate ) * 1e6 );
+ }
+ break;
+ case MODEM_LORA:
+ {
+ double bw = 0.0;
+ switch( this->settings.LoRa.Bandwidth )
+ {
+ case 0: // 125 kHz
+ bw = 125e3;
+ break;
+ case 1: // 250 kHz
+ bw = 250e3;
+ break;
+ case 2: // 500 kHz
+ bw = 500e3;
+ break;
+ }
+
+ // Symbol rate : time for one symbol (secs)
+ double rs = bw / ( 1 << this->settings.LoRa.Datarate );
+ double ts = 1 / rs;
+ // time of preamble
+ double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
+ // Symbol length of payload and time
+ double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
+ 28 + 16 * this->settings.LoRa.CrcOn -
+ ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
+ ( double )( 4 * this->settings.LoRa.Datarate -
+ ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) *
+ ( this->settings.LoRa.Coderate + 4 );
+ double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
+ double tPayload = nPayload * ts;
+ // Time on air
+ double tOnAir = tPreamble + tPayload;
+ // return us secs
+ airTime = floor( tOnAir * 1e6 + 0.999 );
+ }
+ break;
+ }
+ return airTime;
+}
+
+void SX1272::Send( uint8_t *buffer, uint8_t size )
+{
+ uint32_t txTimeout = 0;
+
+ switch( this->settings.Modem )
+ {
+ case MODEM_FSK:
+ {
+ this->settings.FskPacketHandler.NbBytes = 0;
+ this->settings.FskPacketHandler.Size = size;
+
+ if( this->settings.Fsk.FixLen == false )
+ {
+ WriteFifo( ( uint8_t* )&size, 1 );
+ }
+ else
+ {
+ Write( REG_PAYLOADLENGTH, size );
+ }
+
+ if( ( size > 0 ) && ( size <= 64 ) )
+ {
+ this->settings.FskPacketHandler.ChunkSize = size;
+ }
+ else
+ {
+ this->settings.FskPacketHandler.ChunkSize = 32;
+ }
+
+ // Write payload buffer
+ WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
+ this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
+ txTimeout = this->settings.Fsk.TxTimeout;
+ }
+ break;
+ case MODEM_LORA:
+ {
+ if( this->settings.LoRa.IqInverted == true )
+ {
+ Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
+ Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
+ }
+ else
+ {
+ Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
+ Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
+ }
+
+ this->settings.LoRaPacketHandler.Size = size;
+
+ // Initializes the payload size
+ Write( REG_LR_PAYLOADLENGTH, size );
+
+ // Full buffer used for Tx
+ Write( REG_LR_FIFOTXBASEADDR, 0 );
+ Write( REG_LR_FIFOADDRPTR, 0 );
+
+ // FIFO operations can not take place in Sleep mode
+ if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
+ {
+ Standby( );
+ wait_ms( 1 );
+ }
+ // Write payload buffer
+ WriteFifo( buffer, size );
+ txTimeout = this->settings.LoRa.TxTimeout;
+ }
+ break;
+ }
+
+ Tx( txTimeout );
+}
+
+void SX1272::Sleep( void )
+{
+ txTimeoutTimer.detach( );
+ rxTimeoutTimer.detach( );
+
+ SetOpMode( RF_OPMODE_SLEEP );
+ this->settings.State = RF_IDLE;
+}
+
+void SX1272::Standby( void )
+{
+ txTimeoutTimer.detach( );
+ rxTimeoutTimer.detach( );
+
+ SetOpMode( RF_OPMODE_STANDBY );
+ this->settings.State = RF_IDLE;
+}
+
+void SX1272::Rx( uint32_t timeout )
+{
+ bool rxContinuous = false;
+
+ switch( this->settings.Modem )
+ {
+ case MODEM_FSK:
+ {
+ rxContinuous = this->settings.Fsk.RxContinuous;
+
+ // DIO0=PayloadReady
+ // DIO1=FifoLevel
+ // DIO2=SyncAddr
+ // DIO3=FifoEmpty
+ // DIO4=Preamble
+ // DIO5=ModeReady
+ Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
+ RF_DIOMAPPING1_DIO2_MASK ) |
+ RF_DIOMAPPING1_DIO0_00 |
+ RF_DIOMAPPING1_DIO2_11 );
+
+ Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
+ RF_DIOMAPPING2_MAP_MASK ) |
+ RF_DIOMAPPING2_DIO4_11 |
+ RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
+
+ this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
+
+ this->settings.FskPacketHandler.PreambleDetected = false;
+ this->settings.FskPacketHandler.SyncWordDetected = false;
+ this->settings.FskPacketHandler.NbBytes = 0;
+ this->settings.FskPacketHandler.Size = 0;
+ }
+ break;
+ case MODEM_LORA:
+ {
+ if( this->settings.LoRa.IqInverted == true )
+ {
+ Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
+ Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
+ }
+ else
+ {
+ Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
+ Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
+ }
+
+ rxContinuous = this->settings.LoRa.RxContinuous;
+
+ if( this->settings.LoRa.FreqHopOn == true )
+ {
+ Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
+ //RFLR_IRQFLAGS_RXDONE |
+ //RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_CADDONE |
+ //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+ RFLR_IRQFLAGS_CADDETECTED );
+
+ // DIO0=RxDone, DIO2=FhssChangeChannel
+ Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
+ }
+ else
+ {
+ Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
+ //RFLR_IRQFLAGS_RXDONE |
+ //RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+ RFLR_IRQFLAGS_CADDETECTED );
+
+ // DIO0=RxDone
+ Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
+ }
+ Write( REG_LR_FIFORXBASEADDR, 0 );
+ Write( REG_LR_FIFOADDRPTR, 0 );
+ }
+ break;
+ }
+
+ memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
+
+ this->settings.State = RF_RX_RUNNING;
+ if( timeout != 0 )
+ {
+ rxTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
+ }
+
+ if( this->settings.Modem == MODEM_FSK )
+ {
+ SetOpMode( RF_OPMODE_RECEIVER );
+
+ if( rxContinuous == false )
+ {
+ rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
+ ( ( Read( REG_SYNCCONFIG ) &
+ ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
+ 1.0 ) + 10.0 ) /
+ ( double )this->settings.Fsk.Datarate ) * 1e6 );
+ }
+ }
+ else
+ {
+ if( rxContinuous == true )
+ {
+ SetOpMode( RFLR_OPMODE_RECEIVER );
+ }
+ else
+ {
+ SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
+ }
+ }
+}
+
+void SX1272::Tx( uint32_t timeout )
+{
+
+ switch( this->settings.Modem )
+ {
+ case MODEM_FSK:
+ {
+ // DIO0=PacketSent
+ // DIO1=FifoLevel
+ // DIO2=FifoFull
+ // DIO3=FifoEmpty
+ // DIO4=LowBat
+ // DIO5=ModeReady
+ Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
+ RF_DIOMAPPING1_DIO2_MASK ) );
+
+ Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
+ RF_DIOMAPPING2_MAP_MASK ) );
+ this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
+ }
+ break;
+ case MODEM_LORA:
+ {
+ if( this->settings.LoRa.FreqHopOn == true )
+ {
+ Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ //RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_CADDONE |
+ //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+ RFLR_IRQFLAGS_CADDETECTED );
+
+ // DIO0=TxDone, DIO2=FhssChangeChannel
+ Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
+ }
+ else
+ {
+ Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ //RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+ RFLR_IRQFLAGS_CADDETECTED );
+
+ // DIO0=TxDone
+ Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
+ }
+ }
+ break;
+ }
+
+ this->settings.State = RF_TX_RUNNING;
+ txTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
+ SetOpMode( RF_OPMODE_TRANSMITTER );
+}
+
+void SX1272::StartCad( void )
+{
+ switch( this->settings.Modem )
+ {
+ case MODEM_FSK:
+ {
+
+ }
+ break;
+ case MODEM_LORA:
+ {
+ Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_TXDONE |
+ //RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
+ //RFLR_IRQFLAGS_CADDETECTED
+ );
+
+ // DIO3=CADDone
+ Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
+
+ this->settings.State = RF_CAD;
+ SetOpMode( RFLR_OPMODE_CAD );
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+int16_t SX1272::GetRssi( RadioModems_t modem )
+{
+ int16_t rssi = 0;
+
+ switch( modem )
+ {
+ case MODEM_FSK:
+ rssi = -( Read( REG_RSSIVALUE ) >> 1 );
+ break;
+ case MODEM_LORA:
+ rssi = RSSI_OFFSET + Read( REG_LR_RSSIVALUE );
+ break;
+ default:
+ rssi = -1;
+ break;
+ }
+ return rssi;
+}
+
+void SX1272::SetOpMode( uint8_t opMode )
+{
+ if( opMode != currentOpMode )
+ {
+ currentOpMode = opMode;
+ if( opMode == RF_OPMODE_SLEEP )
+ {
+ SetAntSwLowPower( true );
+ }
+ else
+ {
+ SetAntSwLowPower( false );
+ if( opMode == RF_OPMODE_TRANSMITTER )
+ {
+ SetAntSw( 1 );
+ }
+ else
+ {
+ SetAntSw( 0 );
+ }
+ }
+ Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
+ }
+}
+
+void SX1272::SetModem( RadioModems_t modem )
+{
+ if( this->settings.Modem == modem )
+ {
+ return;
+ }
+
+ this->settings.Modem = modem;
+ switch( this->settings.Modem )
+ {
+ default:
+ case MODEM_FSK:
+ SetOpMode( RF_OPMODE_SLEEP );
+ Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
+
+ Write( REG_DIOMAPPING1, 0x00 );
+ Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
+ break;
+ case MODEM_LORA:
+ SetOpMode( RF_OPMODE_SLEEP );
+ Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
+
+ Write( REG_DIOMAPPING1, 0x00 );
+ Write( REG_DIOMAPPING2, 0x00 );
+ break;
+ }
+}
+
+void SX1272::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
+{
+ this->SetModem( modem );
+
+ switch( modem )
+ {
+ case MODEM_FSK:
+ if( this->settings.Fsk.FixLen == false )
+ {
+ this->Write( REG_PAYLOADLENGTH, max );
+ }
+ break;
+ case MODEM_LORA:
+ this->Write( REG_LR_PAYLOADMAXLENGTH, max );
+ break;
+ }
+}
+
+void SX1272::OnTimeoutIrq( void )
+{
+ switch( this->settings.State )
+ {
+ case RF_RX_RUNNING:
+ if( this->settings.Modem == MODEM_FSK )
+ {
+ this->settings.FskPacketHandler.PreambleDetected = false;
+ this->settings.FskPacketHandler.SyncWordDetected = false;
+ this->settings.FskPacketHandler.NbBytes = 0;
+ this->settings.FskPacketHandler.Size = 0;
+
+ // Clear Irqs
+ Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
+ RF_IRQFLAGS1_PREAMBLEDETECT |
+ RF_IRQFLAGS1_SYNCADDRESSMATCH );
+ Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
+
+ if( this->settings.Fsk.RxContinuous == true )
+ {
+ // Continuous mode restart Rx chain
+ Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
+ }
+ else
+ {
+ this->settings.State = RF_IDLE;
+ rxTimeoutSyncWord.detach( );
+ }
+ }
+ if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
+ {
+ this->RadioEvents->RxTimeout( );
+ }
+ break;
+ case RF_TX_RUNNING:
+ this->settings.State = RF_IDLE;
+ if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
+ {
+ this->RadioEvents->TxTimeout( );
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1272::OnDio0Irq( void )
+{
+ volatile uint8_t irqFlags = 0;
+
+ switch( this->settings.State )
+ {
+ case RF_RX_RUNNING:
+ //TimerStop( &RxTimeoutTimer );
+ // RxDone interrupt
+ switch( this->settings.Modem )
+ {
+ case MODEM_FSK:
+ if( this->settings.Fsk.CrcOn == true )
+ {
+ irqFlags = Read( REG_IRQFLAGS2 );
+ if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
+ {
+ // Clear Irqs
+ Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
+ RF_IRQFLAGS1_PREAMBLEDETECT |
+ RF_IRQFLAGS1_SYNCADDRESSMATCH );
+ Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
+
+ if( this->settings.Fsk.RxContinuous == false )
+ {
+ this->settings.State = RF_IDLE;
+ rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
+ ( ( Read( REG_SYNCCONFIG ) &
+ ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
+ 1.0 ) + 10.0 ) /
+ ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
+ }
+ else
+ {
+ // Continuous mode restart Rx chain
+ Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
+ }
+ rxTimeoutTimer.detach( );
+
+ if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
+ {
+ this->RadioEvents->RxError( );
+ }
+ this->settings.FskPacketHandler.PreambleDetected = false;
+ this->settings.FskPacketHandler.SyncWordDetected = false;
+ this->settings.FskPacketHandler.NbBytes = 0;
+ this->settings.FskPacketHandler.Size = 0;
+ break;
+ }
+ }
+
+ // Read received packet size
+ if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
+ {
+ if( this->settings.Fsk.FixLen == false )
+ {
+ ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
+ }
+ else
+ {
+ this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
+ }
+ ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
+ this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
+ }
+ else
+ {
+ ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
+ this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
+ }
+
+ if( this->settings.Fsk.RxContinuous == false )
+ {
+ this->settings.State = RF_IDLE;
+ rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
+ ( ( Read( REG_SYNCCONFIG ) &
+ ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
+ 1.0 ) + 10.0 ) /
+ ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
+ }
+ else
+ {
+ // Continuous mode restart Rx chain
+ Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
+ }
+ rxTimeoutTimer.detach( );
+
+ if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
+ {
+ this->RadioEvents->RxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
+ }
+ this->settings.FskPacketHandler.PreambleDetected = false;
+ this->settings.FskPacketHandler.SyncWordDetected = false;
+ this->settings.FskPacketHandler.NbBytes = 0;
+ this->settings.FskPacketHandler.Size = 0;
+ break;
+ case MODEM_LORA:
+ {
+ int8_t snr = 0;
+
+ // Clear Irq
+ Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
+
+ irqFlags = Read( REG_LR_IRQFLAGS );
+ if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
+ {
+ // Clear Irq
+ Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
+
+ if( this->settings.LoRa.RxContinuous == false )
+ {
+ this->settings.State = RF_IDLE;
+ }
+ rxTimeoutTimer.detach( );
+
+ if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
+ {
+ this->RadioEvents->RxError( );
+ }
+ break;
+ }
+
+ this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
+ if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
+ {
+ // Invert and divide by 4
+ snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
+ snr = -snr;
+ }
+ else
+ {
+ // Divide by 4
+ snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
+ }
+
+ int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
+ if( snr < 0 )
+ {
+ this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 ) +
+ snr;
+ }
+ else
+ {
+ this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 );
+ }
+
+ this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
+ ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
+
+ if( this->settings.LoRa.RxContinuous == false )
+ {
+ this->settings.State = RF_IDLE;
+ }
+ rxTimeoutTimer.detach( );
+
+ if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
+ {
+ this->RadioEvents->RxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case RF_TX_RUNNING:
+ txTimeoutTimer.detach( );
+ // TxDone interrupt
+ switch( this->settings.Modem )
+ {
+ case MODEM_LORA:
+ // Clear Irq
+ Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
+ // Intentional fall through
+ case MODEM_FSK:
+ default:
+ this->settings.State = RF_IDLE;
+ if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
+ {
+ this->RadioEvents->TxDone( );
+ }
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1272::OnDio1Irq( void )
+{
+ switch( this->settings.State )
+ {
+ case RF_RX_RUNNING:
+ switch( this->settings.Modem )
+ {
+ case MODEM_FSK:
+ // FifoLevel interrupt
+ // Read received packet size
+ if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
+ {
+ if( this->settings.Fsk.FixLen == false )
+ {
+ ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
+ }
+ else
+ {
+ this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
+ }
+ }
+
+ if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
+ {
+ ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
+ this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
+ }
+ else
+ {
+ ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
+ this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
+ }
+ break;
+ case MODEM_LORA:
+ // Sync time out
+ rxTimeoutTimer.detach( );
+ this->settings.State = RF_IDLE;
+ if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
+ {
+ this->RadioEvents->RxTimeout( );
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case RF_TX_RUNNING:
+ switch( this->settings.Modem )
+ {
+ case MODEM_FSK:
+ // FifoLevel interrupt
+ if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
+ {
+ WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
+ this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
+ }
+ else
+ {
+ // Write the last chunk of data
+ WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
+ this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
+ }
+ break;
+ case MODEM_LORA:
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1272::OnDio2Irq( void )
+{
+ switch( this->settings.State )
+ {
+ case RF_RX_RUNNING:
+ switch( this->settings.Modem )
+ {
+ case MODEM_FSK:
+ if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
+ {
+ rxTimeoutSyncWord.detach( );
+
+ this->settings.FskPacketHandler.SyncWordDetected = true;
+
+ this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
+
+ this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
+ ( uint16_t )Read( REG_AFCLSB ) ) *
+ ( double )FREQ_STEP;
+ this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
+ }
+ break;
+ case MODEM_LORA:
+ if( this->settings.LoRa.FreqHopOn == true )
+ {
+ // Clear Irq
+ Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
+
+ if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
+ {
+ this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case RF_TX_RUNNING:
+ switch( this->settings.Modem )
+ {
+ case MODEM_FSK:
+ break;
+ case MODEM_LORA:
+ if( this->settings.LoRa.FreqHopOn == true )
+ {
+ // Clear Irq
+ Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
+
+ if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
+ {
+ this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1272::OnDio3Irq( void )
+{
+ switch( this->settings.Modem )
+ {
+ case MODEM_FSK:
+ break;
+ case MODEM_LORA:
+ if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
+ {
+ // Clear Irq
+ Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
+ if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
+ {
+ this->RadioEvents->CadDone( true );
+ }
+ }
+ else
+ {
+ // Clear Irq
+ Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
+ if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
+ {
+ this->RadioEvents->CadDone( false );
+ }
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1272::OnDio4Irq( void )
+{
+ switch( this->settings.Modem )
+ {
+ case MODEM_FSK:
+ {
+ if( this->settings.FskPacketHandler.PreambleDetected == false )
+ {
+ this->settings.FskPacketHandler.PreambleDetected = true;
+ }
+ }
+ break;
+ case MODEM_LORA:
+ break;
+ default:
+ break;
+ }
+}
+
+void SX1272::OnDio5Irq( void )
+{
+ switch( this->settings.Modem )
+ {
+ case MODEM_FSK:
+ break;
+ case MODEM_LORA:
+ break;
+ default:
+ break;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sx1272/sx1272.h Tue Jan 05 16:43:48 2016 +0000
@@ -0,0 +1,496 @@
+/*
+ / _____) _ | |
+( (____ _____ ____ _| |_ _____ ____| |__
+ \____ \| ___ | (_ _) ___ |/ ___) _ \
+ _____) ) ____| | | || |_| ____( (___| | | |
+(______/|_____)_|_|_| \__)_____)\____)_| |_|
+ (C) 2015 Semtech
+
+Description: Actual implementation of a SX1272 radio, inherits Radio
+
+License: Revised BSD License, see LICENSE.TXT file include in the project
+
+Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
+*/
+#ifndef __SX1272_H__
+#define __SX1272_H__
+
+#include "radio.h"
+#include "./registers/sx1272Regs-Fsk.h"
+#include "./registers/sx1272Regs-LoRa.h"
+#include "./typedefs/typedefs.h"
+
+/*!
+ * Radio wakeup time from SLEEP mode
+ */
+#define RADIO_WAKEUP_TIME 1000 // [us]
+
+/*!
+ * SX1272 definitions
+ */
+#define XTAL_FREQ 32000000
+#define FREQ_STEP 61.03515625
+
+#define RX_BUFFER_SIZE 256
+
+/*!
+ * Constant values need to compute the RSSI value
+ */
+#define RSSI_OFFSET -139
+
+/*!
+ * Actual implementation of a SX1272 radio, inherits Radio
+ */
+class SX1272 : public Radio
+{
+protected:
+ /*!
+ * SPI Interface
+ */
+ SPI spi; // mosi, miso, sclk
+ DigitalOut nss;
+
+ /*!
+ * SX1272 Reset pin
+ */
+ DigitalInOut reset;
+
+ /*!
+ * SX1272 DIO pins
+ */
+ InterruptIn dio0;
+ InterruptIn dio1;
+ InterruptIn dio2;
+ InterruptIn dio3;
+ InterruptIn dio4;
+ DigitalIn dio5;
+
+ bool isRadioActive;
+
+ uint8_t boardConnected; //1 = SX1272MB1DCS; 0 = SX1272MB1DAS
+
+ uint8_t *rxBuffer;
+
+ uint8_t currentOpMode;
+
+ /*!
+ * Hardware DIO IRQ functions
+ */
+ DioIrqHandler *dioIrq;
+
+ /*!
+ * Tx and Rx timers
+ */
+ Timeout txTimeoutTimer;
+ Timeout rxTimeoutTimer;
+ Timeout rxTimeoutSyncWord;
+
+ /*!
+ * rxTx: [1: Tx, 0: Rx]
+ */
+ uint8_t rxTx;
+
+ RadioSettings_t settings;
+
+ static const FskBandwidth_t FskBandwidths[] ;
+protected:
+
+ /*!
+ * Performs the Rx chain calibration for LF and HF bands
+ * \remark Must be called just after the reset so all registers are at their
+ * default values
+ */
+ void RxChainCalibration( void );
+
+public:
+ SX1272( RadioEvents_t *events,
+ PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
+ PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 );
+ SX1272( RadioEvents_t *events );
+ virtual ~SX1272( );
+
+ //-------------------------------------------------------------------------
+ // Redefined Radio functions
+ //-------------------------------------------------------------------------
+ /*!
+ * @brief Initializes the radio
+ *
+ * @param [IN] events Structure containing the driver callback functions
+ */
+ virtual void Init( RadioEvents_t *events );
+ /*!
+ * Return current radio status
+ *
+ * @param status Radio status. [RF_IDLE, RX_RUNNING, TX_RUNNING]
+ */
+ virtual RadioState GetStatus( void );
+
+ /*!
+ * @brief Configures the SX1272 with the given modem
+ *
+ * @param [IN] modem Modem to be used [0: FSK, 1: LoRa]
+ */
+ virtual void SetModem( RadioModems_t modem );
+
+ /*!
+ * @brief Sets the channel frequency
+ *
+ * @param [IN] freq Channel RF frequency
+ */
+ virtual void SetChannel( uint32_t freq );
+
+ /*!
+ * @brief Sets the channels configuration
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] freq Channel RF frequency
+ * @param [IN] rssiThresh RSSI threshold
+ *
+ * @retval isFree [true: Channel is free, false: Channel is not free]
+ */
+ virtual bool IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh );
+
+ /*!
+ * @brief Generates a 32 bits random value based on the RSSI readings
+ *
+ * \remark This function sets the radio in LoRa modem mode and disables
+ * all interrupts.
+ * After calling this function either Radio.SetRxConfig or
+ * Radio.SetTxConfig functions must be called.
+ *
+ * @retval randomValue 32 bits random value
+ */
+ virtual uint32_t Random( void );
+
+ /*!
+ * @brief Sets the reception parameters
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] bandwidth Sets the bandwidth
+ * FSK : >= 2600 and <= 250000 Hz
+ * LoRa: [0: 125 kHz, 1: 250 kHz,
+ * 2: 500 kHz, 3: Reserved]
+ * @param [IN] datarate Sets the Datarate
+ * FSK : 600..300000 bits/s
+ * LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ * 10: 1024, 11: 2048, 12: 4096 chips]
+ * @param [IN] coderate Sets the coding rate ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * @param [IN] bandwidthAfc Sets the AFC Bandwidth ( FSK only )
+ * FSK : >= 2600 and <= 250000 Hz
+ * LoRa: N/A ( set to 0 )
+ * @param [IN] preambleLen Sets the Preamble length ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: Length in symbols ( the hardware adds 4 more symbols )
+ * @param [IN] symbTimeout Sets the RxSingle timeout value ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: timeout in symbols
+ * @param [IN] fixLen Fixed length packets [0: variable, 1: fixed]
+ * @param [IN] payloadLen Sets payload length when fixed lenght is used
+ * @param [IN] crcOn Enables/Disables the CRC [0: OFF, 1: ON]
+ * @param [IN] freqHopOn Enables disables the intra-packet frequency hopping [0: OFF, 1: ON] (LoRa only)
+ * @param [IN] hopPeriod Number of symbols bewteen each hop (LoRa only)
+ * @param [IN] iqInverted Inverts IQ signals ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [0: not inverted, 1: inverted]
+ * @param [IN] rxContinuous Sets the reception in continuous mode
+ * [false: single mode, true: continuous mode]
+ */
+ virtual void SetRxConfig ( RadioModems_t modem, uint32_t bandwidth,
+ uint32_t datarate, uint8_t coderate,
+ uint32_t bandwidthAfc, uint16_t preambleLen,
+ uint16_t symbTimeout, bool fixLen,
+ uint8_t payloadLen,
+ bool crcOn, bool freqHopOn, uint8_t hopPeriod,
+ bool iqInverted, bool rxContinuous );
+
+ /*!
+ * @brief Sets the transmission parameters
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] power Sets the output power [dBm]
+ * @param [IN] fdev Sets the frequency deviation ( FSK only )
+ * FSK : [Hz]
+ * LoRa: 0
+ * @param [IN] bandwidth Sets the bandwidth ( LoRa only )
+ * FSK : 0
+ * LoRa: [0: 125 kHz, 1: 250 kHz,
+ * 2: 500 kHz, 3: Reserved]
+ * @param [IN] datarate Sets the Datarate
+ * FSK : 600..300000 bits/s
+ * LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ * 10: 1024, 11: 2048, 12: 4096 chips]
+ * @param [IN] coderate Sets the coding rate ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * @param [IN] preambleLen Sets the preamble length
+ * @param [IN] fixLen Fixed length packets [0: variable, 1: fixed]
+ * @param [IN] crcOn Enables disables the CRC [0: OFF, 1: ON]
+ * @param [IN] freqHopOn Enables disables the intra-packet frequency hopping [0: OFF, 1: ON] (LoRa only)
+ * @param [IN] hopPeriod Number of symbols bewteen each hop (LoRa only)
+ * @param [IN] iqInverted Inverts IQ signals ( LoRa only )
+ * FSK : N/A ( set to 0 )
+ * LoRa: [0: not inverted, 1: inverted]
+ * @param [IN] timeout Transmission timeout [us]
+ */
+ virtual void SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
+ uint32_t bandwidth, uint32_t datarate,
+ uint8_t coderate, uint16_t preambleLen,
+ bool fixLen, bool crcOn, bool freqHopOn,
+ uint8_t hopPeriod, bool iqInverted, uint32_t timeout );
+
+ /*!
+ * @brief Computes the packet time on air for the given payload
+ *
+ * \Remark Can only be called once SetRxConfig or SetTxConfig have been called
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] pktLen Packet payload length
+ *
+ * @retval airTime Computed airTime for the given packet payload length
+ */
+ virtual double TimeOnAir ( RadioModems_t modem, uint8_t pktLen );
+
+ /*!
+ * @brief Sends the buffer of size. Prepares the packet to be sent and sets
+ * the radio in transmission
+ *
+ * @param [IN]: buffer Buffer pointer
+ * @param [IN]: size Buffer size
+ */
+ virtual void Send( uint8_t *buffer, uint8_t size );
+
+ /*!
+ * @brief Sets the radio in sleep mode
+ */
+ virtual void Sleep( void );
+
+ /*!
+ * @brief Sets the radio in standby mode
+ */
+ virtual void Standby( void );
+
+ /*!
+ * @brief Sets the radio in reception mode for the given time
+ * @param [IN] timeout Reception timeout [us]
+ * [0: continuous, others timeout]
+ */
+ virtual void Rx( uint32_t timeout );
+
+ /*!
+ * @brief Sets the radio in transmission mode for the given time
+ * @param [IN] timeout Transmission timeout [us]
+ * [0: continuous, others timeout]
+ */
+ virtual void Tx( uint32_t timeout );
+
+ /*!
+ * @brief Start a Channel Activity Detection
+ */
+ virtual void StartCad( void );
+
+ /*!
+ * @brief Reads the current RSSI value
+ *
+ * @retval rssiValue Current RSSI value in [dBm]
+ */
+ virtual int16_t GetRssi ( RadioModems_t modem );
+
+ /*!
+ * @brief Writes the radio register at the specified address
+ *
+ * @param [IN]: addr Register address
+ * @param [IN]: data New register value
+ */
+ virtual void Write ( uint8_t addr, uint8_t data ) = 0;
+
+ /*!
+ * @brief Reads the radio register at the specified address
+ *
+ * @param [IN]: addr Register address
+ * @retval data Register value
+ */
+ virtual uint8_t Read ( uint8_t addr ) = 0;
+
+ /*!
+ * @brief Writes multiple radio registers starting at address
+ *
+ * @param [IN] addr First Radio register address
+ * @param [IN] buffer Buffer containing the new register's values
+ * @param [IN] size Number of registers to be written
+ */
+ virtual void Write( uint8_t addr, uint8_t *buffer, uint8_t size ) = 0;
+
+ /*!
+ * @brief Reads multiple radio registers starting at address
+ *
+ * @param [IN] addr First Radio register address
+ * @param [OUT] buffer Buffer where to copy the registers data
+ * @param [IN] size Number of registers to be read
+ */
+ virtual void Read ( uint8_t addr, uint8_t *buffer, uint8_t size ) = 0;
+
+ /*!
+ * @brief Writes the buffer contents to the SX1272 FIFO
+ *
+ * @param [IN] buffer Buffer containing data to be put on the FIFO.
+ * @param [IN] size Number of bytes to be written to the FIFO
+ */
+ virtual void WriteFifo( uint8_t *buffer, uint8_t size ) = 0;
+
+ /*!
+ * @brief Reads the contents of the SX1272 FIFO
+ *
+ * @param [OUT] buffer Buffer where to copy the FIFO read data.
+ * @param [IN] size Number of bytes to be read from the FIFO
+ */
+ virtual void ReadFifo( uint8_t *buffer, uint8_t size ) = 0;
+ /*!
+ * @brief Resets the SX1272
+ */
+ virtual void Reset( void ) = 0;
+
+ /*!
+ * @brief Sets the maximum payload length.
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] max Maximum payload length in bytes
+ */
+ virtual void SetMaxPayloadLength( RadioModems_t modem, uint8_t max );
+
+ //-------------------------------------------------------------------------
+ // Board relative functions
+ //-------------------------------------------------------------------------
+
+protected:
+ /*!
+ * @brief Initializes the radio I/Os pins interface
+ */
+ virtual void IoInit( void ) = 0;
+
+ /*!
+ * @brief Initializes the radio registers
+ */
+ virtual void RadioRegistersInit( ) = 0;
+
+ /*!
+ * @brief Initializes the radio SPI
+ */
+ virtual void SpiInit( void ) = 0;
+
+ /*!
+ * @brief Initializes DIO IRQ handlers
+ *
+ * @param [IN] irqHandlers Array containing the IRQ callback functions
+ */
+ virtual void IoIrqInit( DioIrqHandler *irqHandlers ) = 0;
+
+ /*!
+ * @brief De-initializes the radio I/Os pins interface.
+ *
+ * \remark Useful when going in MCU lowpower modes
+ */
+ virtual void IoDeInit( void ) = 0;
+
+ /*!
+ * @brief Gets the board PA selection configuration
+ *
+ * @param [IN] channel Channel frequency in Hz
+ * @retval PaSelect RegPaConfig PaSelect value
+ */
+ virtual uint8_t GetPaSelect( uint32_t channel ) = 0;
+
+ /*!
+ * @brief Set the RF Switch I/Os pins in Low Power mode
+ *
+ * @param [IN] status enable or disable
+ */
+ virtual void SetAntSwLowPower( bool status ) = 0;
+
+ /*!
+ * @brief Initializes the RF Switch I/Os pins interface
+ */
+ virtual void AntSwInit( void ) = 0;
+
+ /*!
+ * @brief De-initializes the RF Switch I/Os pins interface
+ *
+ * \remark Needed to decrease the power consumption in MCU lowpower modes
+ */
+ virtual void AntSwDeInit( void ) = 0;
+
+ /*!
+ * @brief Controls the antena switch if necessary.
+ *
+ * \remark see errata note
+ *
+ * @param [IN] rxTx [1: Tx, 0: Rx]
+ */
+ virtual void SetAntSw( uint8_t rxTx ) = 0;
+
+ /*!
+ * @brief Checks if the given RF frequency is supported by the hardware
+ *
+ * @param [IN] frequency RF frequency to be checked
+ * @retval isSupported [true: supported, false: unsupported]
+ */
+ virtual bool CheckRfFrequency( uint32_t frequency ) = 0;
+protected:
+
+ /*!
+ * @brief Sets the SX1272 operating mode
+ *
+ * @param [IN] opMode New operating mode
+ */
+ virtual void SetOpMode( uint8_t opMode );
+
+ /*
+ * SX1272 DIO IRQ callback functions prototype
+ */
+
+ /*!
+ * @brief DIO 0 IRQ callback
+ */
+ virtual void OnDio0Irq( void );
+
+ /*!
+ * @brief DIO 1 IRQ callback
+ */
+ virtual void OnDio1Irq( void );
+
+ /*!
+ * @brief DIO 2 IRQ callback
+ */
+ virtual void OnDio2Irq( void );
+
+ /*!
+ * @brief DIO 3 IRQ callback
+ */
+ virtual void OnDio3Irq( void );
+
+ /*!
+ * @brief DIO 4 IRQ callback
+ */
+ virtual void OnDio4Irq( void );
+
+ /*!
+ * @brief DIO 5 IRQ callback
+ */
+ virtual void OnDio5Irq( void );
+
+ /*!
+ * @brief Tx & Rx timeout timer callback
+ */
+ virtual void OnTimeoutIrq( void );
+
+ /*!
+ * Returns the known FSK bandwidth registers value
+ *
+ * \param [IN] bandwidth Bandwidth value in Hz
+ * \retval regValue Bandwidth register value.
+ */
+ static uint8_t GetFskBandwidthRegValue( uint32_t bandwidth );
+};
+
+#endif // __SX1272_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/typedefs/typedefs.h Tue Jan 05 16:43:48 2016 +0000
@@ -0,0 +1,53 @@
+/*
+ / _____) _ | |
+( (____ _____ ____ _| |_ _____ ____| |__
+ \____ \| ___ | (_ _) ___ |/ ___) _ \
+ _____) ) ____| | | || |_| ____( (___| | | |
+(______/|_____)_|_|_| \__)_____)\____)_| |_|
+ (C) 2015 Semtech
+
+Description: -
+
+License: Revised BSD License, see LICENSE.TXT file include in the project
+
+Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
+*/
+#ifndef __TYPEDEFS_H__
+#define __TYPEDEFS_H__
+
+#include "mbed.h"
+#include "./enums/enums.h"
+
+class SX1272;
+class SX1272MB1DxS;
+/*!
+ * Hardware IO IRQ callback function definition
+ */
+typedef void ( SX1272::*DioIrqHandler )( void );
+
+/*!
+ * triggers definition
+ */
+typedef void ( SX1272::*Trigger )( void );
+typedef void ( SX1272MB1DxS::*TriggerMB1DxS )( void );
+
+/*!
+ * FSK bandwidth definition
+ */
+typedef struct
+{
+ uint32_t bandwidth;
+ uint8_t RegValue;
+}FskBandwidth_t;
+
+/*!
+ * Radio registers definition
+ */
+typedef struct
+{
+ ModemType Modem;
+ uint8_t Addr;
+ uint8_t Value;
+}RadioRegisters_t;
+
+#endif //__TYPEDEFS_H__
Repository toolbox
| Export to desktop IDE |
Repository details
| Type: | Library |
|---|---|
| Created: | 27 Nov 2015 |
| Imports: | 874 |
| Forks: | 14 |
| Commits: | 8 |
| Dependents: | 54 |
| Dependencies: | 0 |
| Followers: | 122 |
Components
SX1272MB2xAS / SX1272MB2DAS