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mbed library sources for GR-PEACH rev.B.
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mbed-src
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mbed official
Revision 462:e03396e14338, committed 2015-02-03
- Comitter:
- mbed_official
- Date:
- Tue Feb 03 13:15:07 2015 +0000
- Parent:
- 461:b90c5392bbcd
- Child:
- 463:5c73c3744533
- Commit message:
- Synchronized with git revision ae7e2e76ed57b9ca11dc05f51f097df1de144fe2
Full URL: https://github.com/mbedmicro/mbed/commit/ae7e2e76ed57b9ca11dc05f51f097df1de144fe2/
Add support for EA LPC4088_DM
Changed in this revision
--- a/targets/hal/TARGET_NXP/TARGET_LPC408X/PeripheralNames.h Mon Feb 02 16:00:07 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,119 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- UART_0 = (int)LPC_UART0_BASE,
- UART_1 = (int)LPC_UART1_BASE,
- UART_2 = (int)LPC_UART2_BASE,
- UART_3 = (int)LPC_UART3_BASE,
- UART_4 = (int)LPC_UART4_BASE
-} UARTName;
-
-typedef enum {
- ADC0_0 = 0,
- ADC0_1,
- ADC0_2,
- ADC0_3,
- ADC0_4,
- ADC0_5,
- ADC0_6,
- ADC0_7
-} ADCName;
-
-typedef enum {
- DAC_0 = 0
-} DACName;
-
-typedef enum {
- SPI_0 = (int)LPC_SSP0_BASE,
- SPI_1 = (int)LPC_SSP1_BASE,
- SPI_2 = (int)LPC_SSP2_BASE
-} SPIName;
-
-typedef enum {
- I2C_0 = (int)LPC_I2C0_BASE,
- I2C_1 = (int)LPC_I2C1_BASE,
- I2C_2 = (int)LPC_I2C2_BASE
-} I2CName;
-
-typedef enum {
- PWM0_1 = 1,
- PWM0_2,
- PWM0_3,
- PWM0_4,
- PWM0_5,
- PWM0_6,
- PWM1_1,
- PWM1_2,
- PWM1_3,
- PWM1_4,
- PWM1_5,
- PWM1_6
-} PWMName;
-
-typedef enum {
- CAN_1 = (int)LPC_CAN1_BASE,
- CAN_2 = (int)LPC_CAN2_BASE
-} CANName;
-
-#define STDIO_UART_TX USBTX
-#define STDIO_UART_RX USBRX
-#define STDIO_UART UART_0
-
-// Default peripherals
-#define MBED_SPI0 p5, p6, p7
-#define MBED_SPI1 p11, p12, p13, p14
-#define MBED_SPI2 p39, p38, p32, p31
-
-#define MBED_UART3 p9, p10
-#define MBED_UART4 p37, p31
-#define MBED_UARTUSB USBTX, USBRX
-
-#define MBED_I2C0 p32, p31
-#define MBED_I2C1 p9, p10
-
-#define MBED_CAN1 p9, p10
-#define MBED_CAN2 p34, p33
-
-#define MBED_ANALOGOUT0 p18
-
-#define MBED_ANALOGIN0 p15
-#define MBED_ANALOGIN1 p16
-#define MBED_ANALOGIN2 p17
-#define MBED_ANALOGIN3 p18
-#define MBED_ANALOGIN4 p19
-#define MBED_ANALOGIN5 p20
-
-#define MBED_PWMOUT0 p30
-#define MBED_PWMOUT1 p29
-#define MBED_PWMOUT2 p28
-#define MBED_PWMOUT3 p27
-#define MBED_PWMOUT4 p26
-#define MBED_PWMOUT5 p25
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/hal/TARGET_NXP/TARGET_LPC408X/PinNames.h Mon Feb 02 16:00:07 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,130 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT 5
-
-typedef enum {
- // LPC Pin Names
- P0_0 = /*LPC_GPIO0_BASE*/0,
- P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
- P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
- P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
- P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
- P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
- P5_0, P5_1, P5_2, P5_3, P5_4,
-
- // mbed DIP Pin Names
- p5 = P1_24,
- p6 = P1_23,
- p7 = P1_20,
- p8 = P0_21,
- p9 = P0_0,
- p10 = P0_1,
- p11 = P0_9,
- p12 = P0_8,
- p13 = P0_7,
- p14 = P0_6,
- p15 = P0_23,
- p16 = P0_24,
- p17 = P0_25,
- p18 = P0_26,
- p19 = P1_30,
- p20 = P1_31,
-
- p23 = P2_10,
- p24 = P1_12,
- p25 = P1_11,
- p26 = P1_7,
- p27 = P1_6,
- p28 = P1_5,
- p29 = P1_3,
- p30 = P1_2,
- p31 = P5_3,
- p32 = P5_2,
- p33 = P0_5,
- p34 = P0_4,
-
- p37 = P5_4,
- p38 = P5_1,
- p39 = P5_0,
-
- // Other mbed Pin Names
- LED1 = P1_18,
- LED2 = P0_13,
- LED3 = P1_13,
- LED4 = P2_19,
-
- USBTX = P0_2,
- USBRX = P0_3,
-
- // QSB baseboard Arduino shield pins
- D0 = p10,
- D1 = p9,
- D2 = p31,
- D3 = p32,
- D4 = p33,
- D5 = p37,
- D6 = p38,
- D7 = p34,
- D8 = p8,
- D9 = p39,
- D10 = p14,
- D11 = p11,
- D12 = p12,
- D13 = p13,
- D14 = p19,
- D15 = p20,
-
- A0 = p15,
- A1 = p16,
- A2 = p17,
- A3 = p18,
- A4 = p19,
- A5 = p20,
-
-
- // Not connected
- NC = (int)0xFFFFFFFF
-} PinName;
-
-typedef enum {
- PullUp = 2,
- PullDown = 1,
- PullNone = 0,
- OpenDrain = 4,
- PullDefault = PullDown
-} PinMode;
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/PeripheralNames.h Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,119 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_UART0_BASE,
+ UART_1 = (int)LPC_UART1_BASE,
+ UART_2 = (int)LPC_UART2_BASE,
+ UART_3 = (int)LPC_UART3_BASE,
+ UART_4 = (int)LPC_UART4_BASE
+} UARTName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0
+} DACName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE,
+ SPI_2 = (int)LPC_SSP2_BASE
+} SPIName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C0_BASE,
+ I2C_1 = (int)LPC_I2C1_BASE,
+ I2C_2 = (int)LPC_I2C2_BASE
+} I2CName;
+
+typedef enum {
+ PWM0_1 = 1,
+ PWM0_2,
+ PWM0_3,
+ PWM0_4,
+ PWM0_5,
+ PWM0_6,
+ PWM1_1,
+ PWM1_2,
+ PWM1_3,
+ PWM1_4,
+ PWM1_5,
+ PWM1_6
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)LPC_CAN1_BASE,
+ CAN_2 = (int)LPC_CAN2_BASE
+} CANName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+// Default peripherals
+#define MBED_SPI0 p5, p6, p7
+#define MBED_SPI1 p11, p12, p13, p14
+#define MBED_SPI2 p39, p38, p32, p31
+
+#define MBED_UART3 p9, p10
+#define MBED_UART4 p37, p31
+#define MBED_UARTUSB USBTX, USBRX
+
+#define MBED_I2C0 p32, p31
+#define MBED_I2C1 p9, p10
+
+#define MBED_CAN1 p9, p10
+#define MBED_CAN2 p34, p33
+
+#define MBED_ANALOGOUT0 p18
+
+#define MBED_ANALOGIN0 p15
+#define MBED_ANALOGIN1 p16
+#define MBED_ANALOGIN2 p17
+#define MBED_ANALOGIN3 p18
+#define MBED_ANALOGIN4 p19
+#define MBED_ANALOGIN5 p20
+
+#define MBED_PWMOUT0 p30
+#define MBED_PWMOUT1 p29
+#define MBED_PWMOUT2 p28
+#define MBED_PWMOUT3 p27
+#define MBED_PWMOUT4 p26
+#define MBED_PWMOUT5 p25
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/PinNames.h Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,130 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 5
+
+typedef enum {
+ // LPC Pin Names
+ P0_0 = /*LPC_GPIO0_BASE*/0,
+ P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
+ P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
+ P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
+ P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
+ P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
+ P5_0, P5_1, P5_2, P5_3, P5_4,
+
+ // mbed DIP Pin Names
+ p5 = P1_24,
+ p6 = P1_23,
+ p7 = P1_20,
+ p8 = P0_21,
+ p9 = P0_0,
+ p10 = P0_1,
+ p11 = P0_9,
+ p12 = P0_8,
+ p13 = P0_7,
+ p14 = P0_6,
+ p15 = P0_23,
+ p16 = P0_24,
+ p17 = P0_25,
+ p18 = P0_26,
+ p19 = P1_30,
+ p20 = P1_31,
+
+ p23 = P2_10,
+ p24 = P1_12,
+ p25 = P1_11,
+ p26 = P1_7,
+ p27 = P1_6,
+ p28 = P1_5,
+ p29 = P1_3,
+ p30 = P1_2,
+ p31 = P5_3,
+ p32 = P5_2,
+ p33 = P0_5,
+ p34 = P0_4,
+
+ p37 = P5_4,
+ p38 = P5_1,
+ p39 = P5_0,
+
+ // Other mbed Pin Names
+ LED1 = P1_18,
+ LED2 = P0_13,
+ LED3 = P1_13,
+ LED4 = P2_19,
+
+ USBTX = P0_2,
+ USBRX = P0_3,
+
+ // QSB baseboard Arduino shield pins
+ D0 = p10,
+ D1 = p9,
+ D2 = p31,
+ D3 = p32,
+ D4 = p33,
+ D5 = p37,
+ D6 = p38,
+ D7 = p34,
+ D8 = p8,
+ D9 = p39,
+ D10 = p14,
+ D11 = p11,
+ D12 = p12,
+ D13 = p13,
+ D14 = p19,
+ D15 = p20,
+
+ A0 = p15,
+ A1 = p16,
+ A2 = p17,
+ A3 = p18,
+ A4 = p19,
+ A5 = p20,
+
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
+ OpenDrain = 4,
+ PullDefault = PullDown
+} PinMode;
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/analogin_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,125 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#define ANALOGIN_MEDIAN_FILTER 1
+
+#define ADC_10BIT_RANGE 0x3FF
+#define ADC_12BIT_RANGE 0xFFF
+
+static inline int div_round_up(int x, int y) {
+ return (x + (y - 1)) / y;
+}
+
+static const PinMap PinMap_ADC[] = {
+ {P0_23, ADC0_0, 0x01},
+ {P0_24, ADC0_1, 0x01},
+ {P0_25, ADC0_2, 0x01},
+ {P0_26, ADC0_3, 0x01},
+ {P1_30, ADC0_4, 0x03},
+ {P1_31, ADC0_5, 0x03},
+ {P0_12, ADC0_6, 0x03},
+ {P0_13, ADC0_7, 0x03},
+ {NC , NC , 0 }
+};
+
+#define ADC_RANGE ADC_12BIT_RANGE
+
+void analogin_init(analogin_t *obj, PinName pin) {
+ obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj->adc != (ADCName)NC);
+
+ // ensure power is turned on
+ LPC_SC->PCONP |= (1 << 12);
+
+ uint32_t PCLK = PeripheralClock;
+
+ // calculate minimum clock divider
+ // clkdiv = divider - 1
+ uint32_t MAX_ADC_CLK = 12400000;
+ uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
+
+ // Set the generic software-controlled ADC settings
+ LPC_ADC->CR = (0 << 0) // SEL: 0 = no channels selected
+ | (clkdiv << 8) // CLKDIV:
+ | (0 << 16) // BURST: 0 = software control
+ | (1 << 21) // PDN: 1 = operational
+ | (0 << 24) // START: 0 = no start
+ | (0 << 27); // EDGE: not applicable
+
+ // must enable analog mode (ADMODE = 0)
+ __IO uint32_t *reg = (__IO uint32_t*) (LPC_IOCON_BASE + 4 * pin);
+ *reg &= ~(1 << 7);
+
+ pinmap_pinout(pin, PinMap_ADC);
+}
+
+static inline uint32_t adc_read(analogin_t *obj) {
+ // Select the appropriate channel and start conversion
+ LPC_ADC->CR &= ~0xFF;
+ LPC_ADC->CR |= 1 << (int)obj->adc;
+ LPC_ADC->CR |= 1 << 24;
+
+ // Repeatedly get the sample data until DONE bit
+ unsigned int data;
+ do {
+ data = LPC_ADC->GDR;
+ } while ((data & ((unsigned int)1 << 31)) == 0);
+
+ // Stop conversion
+ LPC_ADC->CR &= ~(1 << 24);
+
+ return (data >> 4) & ADC_RANGE; // 12 bit
+}
+
+static inline void order(uint32_t *a, uint32_t *b) {
+ if (*a > *b) {
+ uint32_t t = *a;
+ *a = *b;
+ *b = t;
+ }
+}
+
+static inline uint32_t adc_read_u32(analogin_t *obj) {
+ uint32_t value;
+#if ANALOGIN_MEDIAN_FILTER
+ uint32_t v1 = adc_read(obj);
+ uint32_t v2 = adc_read(obj);
+ uint32_t v3 = adc_read(obj);
+ order(&v1, &v2);
+ order(&v2, &v3);
+ order(&v1, &v2);
+ value = v2;
+#else
+ value = adc_read(obj);
+#endif
+ return value;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+ uint32_t value = adc_read_u32(obj);
+
+ return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
+}
+
+float analogin_read(analogin_t *obj) {
+ uint32_t value = adc_read_u32(obj);
+ return (float)value * (1.0f / (float)ADC_RANGE);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/can_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,391 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "can_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+
+#include <math.h>
+#include <string.h>
+
+#define CAN_NUM 2
+
+/* Acceptance filter mode in AFMR register */
+#define ACCF_OFF 0x01
+#define ACCF_BYPASS 0x02
+#define ACCF_ON 0x00
+#define ACCF_FULLCAN 0x04
+
+/* There are several bit timing calculators on the internet.
+http://www.port.de/engl/canprod/sv_req_form.html
+http://www.kvaser.com/can/index.htm
+*/
+
+static const PinMap PinMap_CAN_RD[] = {
+ {P0_0 , CAN_1, 1},
+ {P0_4 , CAN_2, 2},
+ {P0_21, CAN_1, 4},
+ {P2_7 , CAN_2, 1},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_CAN_TD[] = {
+ {P0_1 , CAN_1, 1},
+ {P0_5 , CAN_2, 2},
+ {P0_22, CAN_1, 4},
+ {P2_8 , CAN_2, 1},
+ {NC , NC , 0}
+};
+
+// Type definition to hold a CAN message
+struct CANMsg {
+ unsigned int reserved1 : 16;
+ unsigned int dlc : 4; // Bits 16..19: DLC - Data Length Counter
+ unsigned int reserved0 : 10;
+ unsigned int rtr : 1; // Bit 30: Set if this is a RTR message
+ unsigned int type : 1; // Bit 31: Set if this is a 29-bit ID message
+ unsigned int id; // CAN Message ID (11-bit or 29-bit)
+ unsigned char data[8]; // CAN Message Data Bytes 0-7
+};
+typedef struct CANMsg CANMsg;
+
+static uint32_t can_irq_ids[CAN_NUM] = {0};
+static can_irq_handler irq_handler;
+
+static uint32_t can_disable(can_t *obj) {
+ uint32_t sm = obj->dev->MOD;
+ obj->dev->MOD |= 1;
+ return sm;
+}
+
+static inline void can_enable(can_t *obj) {
+ if (obj->dev->MOD & 1) {
+ obj->dev->MOD &= ~(1);
+ }
+}
+
+int can_mode(can_t *obj, CanMode mode)
+{
+ return 0; // not implemented
+}
+
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
+ return 0; // not implemented
+}
+
+static inline void can_irq(uint32_t icr, uint32_t index) {
+ uint32_t i;
+
+ for(i = 0; i < 8; i++)
+ {
+ if((can_irq_ids[index] != 0) && (icr & (1 << i)))
+ {
+ switch (i) {
+ case 0: irq_handler(can_irq_ids[index], IRQ_RX); break;
+ case 1: irq_handler(can_irq_ids[index], IRQ_TX); break;
+ case 2: irq_handler(can_irq_ids[index], IRQ_ERROR); break;
+ case 3: irq_handler(can_irq_ids[index], IRQ_OVERRUN); break;
+ case 4: irq_handler(can_irq_ids[index], IRQ_WAKEUP); break;
+ case 5: irq_handler(can_irq_ids[index], IRQ_PASSIVE); break;
+ case 6: irq_handler(can_irq_ids[index], IRQ_ARB); break;
+ case 7: irq_handler(can_irq_ids[index], IRQ_BUS); break;
+ case 8: irq_handler(can_irq_ids[index], IRQ_READY); break;
+ }
+ }
+ }
+}
+
+// Have to check that the CAN block is active before reading the Interrupt
+// Control Register, or the mbed hangs
+void can_irq_n() {
+ uint32_t icr;
+
+ if(LPC_SC->PCONP & (1 << 13)) {
+ icr = LPC_CAN1->ICR & 0x1FF;
+ can_irq(icr, 0);
+ }
+
+ if(LPC_SC->PCONP & (1 << 14)) {
+ icr = LPC_CAN2->ICR & 0x1FF;
+ can_irq(icr, 1);
+ }
+}
+
+// Register CAN object's irq handler
+void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
+ irq_handler = handler;
+ can_irq_ids[obj->index] = id;
+}
+
+// Unregister CAN object's irq handler
+void can_irq_free(can_t *obj) {
+ obj->dev->IER &= ~(1);
+ can_irq_ids[obj->index] = 0;
+
+ if ((can_irq_ids[0] == 0) && (can_irq_ids[1] == 0)) {
+ NVIC_DisableIRQ(CAN_IRQn);
+ }
+}
+
+// Clear or set a irq
+void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
+ uint32_t ier;
+
+ switch (type) {
+ case IRQ_RX: ier = (1 << 0); break;
+ case IRQ_TX: ier = (1 << 1); break;
+ case IRQ_ERROR: ier = (1 << 2); break;
+ case IRQ_OVERRUN: ier = (1 << 3); break;
+ case IRQ_WAKEUP: ier = (1 << 4); break;
+ case IRQ_PASSIVE: ier = (1 << 5); break;
+ case IRQ_ARB: ier = (1 << 6); break;
+ case IRQ_BUS: ier = (1 << 7); break;
+ case IRQ_READY: ier = (1 << 8); break;
+ default: return;
+ }
+
+ obj->dev->MOD |= 1;
+ if(enable == 0) {
+ obj->dev->IER &= ~ier;
+ }
+ else {
+ obj->dev->IER |= ier;
+ }
+ obj->dev->MOD &= ~(1);
+
+ // Enable NVIC if at least 1 interrupt is active
+ if(((LPC_SC->PCONP & (1 << 13)) && LPC_CAN1->IER) || ((LPC_SC->PCONP & (1 << 14)) && LPC_CAN2->IER)) {
+ NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq_n);
+ NVIC_EnableIRQ(CAN_IRQn);
+ }
+ else {
+ NVIC_DisableIRQ(CAN_IRQn);
+ }
+}
+
+// This table has the sampling points as close to 75% as possible. The first
+// value is TSEG1, the second TSEG2.
+static const int timing_pts[23][2] = {
+ {0x0, 0x0}, // 2, 50%
+ {0x1, 0x0}, // 3, 67%
+ {0x2, 0x0}, // 4, 75%
+ {0x3, 0x0}, // 5, 80%
+ {0x3, 0x1}, // 6, 67%
+ {0x4, 0x1}, // 7, 71%
+ {0x5, 0x1}, // 8, 75%
+ {0x6, 0x1}, // 9, 78%
+ {0x6, 0x2}, // 10, 70%
+ {0x7, 0x2}, // 11, 73%
+ {0x8, 0x2}, // 12, 75%
+ {0x9, 0x2}, // 13, 77%
+ {0x9, 0x3}, // 14, 71%
+ {0xA, 0x3}, // 15, 73%
+ {0xB, 0x3}, // 16, 75%
+ {0xC, 0x3}, // 17, 76%
+ {0xD, 0x3}, // 18, 78%
+ {0xD, 0x4}, // 19, 74%
+ {0xE, 0x4}, // 20, 75%
+ {0xF, 0x4}, // 21, 76%
+ {0xF, 0x5}, // 22, 73%
+ {0xF, 0x6}, // 23, 70%
+ {0xF, 0x7}, // 24, 67%
+};
+
+static unsigned int can_speed(unsigned int pclk, unsigned int cclk, unsigned char psjw) {
+ uint32_t btr;
+ uint16_t brp = 0;
+ uint32_t calcbit;
+ uint32_t bitwidth;
+ int hit = 0;
+ int bits;
+
+ bitwidth = (pclk / cclk);
+
+ brp = bitwidth / 0x18;
+ while ((!hit) && (brp < bitwidth / 4)) {
+ brp++;
+ for (bits = 22; bits > 0; bits--) {
+ calcbit = (bits + 3) * (brp + 1);
+ if (calcbit == bitwidth) {
+ hit = 1;
+ break;
+ }
+ }
+ }
+
+ if (hit) {
+ btr = ((timing_pts[bits][1] << 20) & 0x00700000)
+ | ((timing_pts[bits][0] << 16) & 0x000F0000)
+ | ((psjw << 14) & 0x0000C000)
+ | ((brp << 0) & 0x000003FF);
+ } else {
+ btr = 0xFFFFFFFF;
+ }
+
+ return btr;
+
+}
+
+void can_init(can_t *obj, PinName rd, PinName td) {
+ CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
+ CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
+ obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
+ MBED_ASSERT((int)obj->dev != NC);
+
+ switch ((int)obj->dev) {
+ case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
+ case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
+ }
+
+ pinmap_pinout(rd, PinMap_CAN_RD);
+ pinmap_pinout(td, PinMap_CAN_TD);
+
+ switch ((int)obj->dev) {
+ case CAN_1: obj->index = 0; break;
+ case CAN_2: obj->index = 1; break;
+ }
+
+ can_reset(obj);
+ obj->dev->IER = 0; // Disable Interrupts
+ can_frequency(obj, 100000);
+
+ LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
+}
+
+void can_free(can_t *obj) {
+ switch ((int)obj->dev) {
+ case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break;
+ case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break;
+ }
+}
+
+int can_frequency(can_t *obj, int f) {
+ int pclk = PeripheralClock;
+
+ int btr = can_speed(pclk, (unsigned int)f, 1);
+
+ if (btr > 0) {
+ uint32_t modmask = can_disable(obj);
+ obj->dev->BTR = btr;
+ obj->dev->MOD = modmask;
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc) {
+ unsigned int CANStatus;
+ CANMsg m;
+
+ can_enable(obj);
+
+ m.id = msg.id ;
+ m.dlc = msg.len & 0xF;
+ m.rtr = msg.type;
+ m.type = msg.format;
+ memcpy(m.data, msg.data, msg.len);
+ const unsigned int *buf = (const unsigned int *)&m;
+
+ CANStatus = obj->dev->SR;
+ if (CANStatus & 0x00000004) {
+ obj->dev->TFI1 = buf[0] & 0xC00F0000;
+ obj->dev->TID1 = buf[1];
+ obj->dev->TDA1 = buf[2];
+ obj->dev->TDB1 = buf[3];
+ if(cc) {
+ obj->dev->CMR = 0x30;
+ } else {
+ obj->dev->CMR = 0x21;
+ }
+ return 1;
+
+ } else if (CANStatus & 0x00000400) {
+ obj->dev->TFI2 = buf[0] & 0xC00F0000;
+ obj->dev->TID2 = buf[1];
+ obj->dev->TDA2 = buf[2];
+ obj->dev->TDB2 = buf[3];
+ if (cc) {
+ obj->dev->CMR = 0x50;
+ } else {
+ obj->dev->CMR = 0x41;
+ }
+ return 1;
+
+ } else if (CANStatus & 0x00040000) {
+ obj->dev->TFI3 = buf[0] & 0xC00F0000;
+ obj->dev->TID3 = buf[1];
+ obj->dev->TDA3 = buf[2];
+ obj->dev->TDB3 = buf[3];
+ if (cc) {
+ obj->dev->CMR = 0x90;
+ } else {
+ obj->dev->CMR = 0x81;
+ }
+ return 1;
+ }
+
+ return 0;
+}
+
+int can_read(can_t *obj, CAN_Message *msg, int handle) {
+ CANMsg x;
+ unsigned int *i = (unsigned int *)&x;
+
+ can_enable(obj);
+
+ if (obj->dev->GSR & 0x1) {
+ *i++ = obj->dev->RFS; // Frame
+ *i++ = obj->dev->RID; // ID
+ *i++ = obj->dev->RDA; // Data A
+ *i++ = obj->dev->RDB; // Data B
+ obj->dev->CMR = 0x04; // release receive buffer
+
+ msg->id = x.id;
+ msg->len = x.dlc;
+ msg->format = (x.type)? CANExtended : CANStandard;
+ msg->type = (x.rtr)? CANRemote: CANData;
+ memcpy(msg->data,x.data,x.dlc);
+ return 1;
+ }
+
+ return 0;
+}
+
+void can_reset(can_t *obj) {
+ can_disable(obj);
+ obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
+}
+
+unsigned char can_rderror(can_t *obj) {
+ return (obj->dev->GSR >> 16) & 0xFF;
+}
+
+unsigned char can_tderror(can_t *obj) {
+ return (obj->dev->GSR >> 24) & 0xFF;
+}
+
+void can_monitor(can_t *obj, int silent) {
+ uint32_t mod_mask = can_disable(obj);
+ if (silent) {
+ obj->dev->MOD |= (1 << 1);
+ } else {
+ obj->dev->MOD &= ~(1 << 1);
+ }
+ if (!(mod_mask & 1)) {
+ can_enable(obj);
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,1008 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+
+#include "ethernet_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "toolchain.h"
+#include "mbed_error.h"
+
+#define NEW_LOGIC 0
+#define NEW_ETH_BUFFER 0
+
+#if NEW_ETH_BUFFER
+
+#define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets)
+#define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets)
+
+#define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size
+#define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length)
+
+#else
+
+// Memfree calculation:
+// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
+// (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
+#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
+#define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
+//#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
+
+//#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
+#define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */
+#define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */
+
+const int ethernet_MTU_SIZE = 0x300;
+
+#endif
+
+#define ETHERNET_ADDR_SIZE 6
+
+PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */
+ unsigned int Packet;
+ unsigned int Ctrl;
+};
+typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
+
+PACKED struct RX_STAT_TypeDef { /* RX Status struct */
+ unsigned int Info;
+ unsigned int HashCRC;
+};
+typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
+
+PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */
+ unsigned int Packet;
+ unsigned int Ctrl;
+};
+typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
+
+PACKED struct TX_STAT_TypeDef { /* TX Status struct */
+ unsigned int Info;
+};
+typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
+
+/* MAC Configuration Register 1 */
+#define MAC1_REC_EN 0x00000001 /* Receive Enable */
+#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
+#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
+#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
+#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
+#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
+#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
+#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
+#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
+#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
+#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
+
+/* MAC Configuration Register 2 */
+#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
+#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
+#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
+#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
+#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
+#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
+#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
+#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
+#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
+#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
+#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
+#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
+#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
+
+/* Back-to-Back Inter-Packet-Gap Register */
+#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
+#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
+
+/* Non Back-to-Back Inter-Packet-Gap Register */
+#define IPGR_DEF 0x00000012 /* Recommended value */
+
+/* Collision Window/Retry Register */
+#define CLRT_DEF 0x0000370F /* Default value */
+
+/* PHY Support Register */
+#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
+//#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
+#define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
+
+/* Test Register */
+#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
+#define TEST_TST_PAUSE 0x00000002 /* Test Pause */
+#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
+
+/* MII Management Configuration Register */
+#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
+#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
+#define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */
+#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
+
+/* MII Management Command Register */
+#define MCMD_READ 0x00000001 /* MII Read */
+#define MCMD_SCAN 0x00000002 /* MII Scan continuously */
+
+#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
+#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
+
+/* MII Management Address Register */
+#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
+#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
+
+/* MII Management Indicators Register */
+#define MIND_BUSY 0x00000001 /* MII is Busy */
+#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
+#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
+#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
+
+/* Command Register */
+#define CR_RX_EN 0x00000001 /* Enable Receive */
+#define CR_TX_EN 0x00000002 /* Enable Transmit */
+#define CR_REG_RES 0x00000008 /* Reset Host Registers */
+#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
+#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
+#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
+#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
+#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
+#define CR_RMII 0x00000200 /* Reduced MII Interface */
+#define CR_FULL_DUP 0x00000400 /* Full Duplex */
+
+/* Status Register */
+#define SR_RX_EN 0x00000001 /* Enable Receive */
+#define SR_TX_EN 0x00000002 /* Enable Transmit */
+
+/* Transmit Status Vector 0 Register */
+#define TSV0_CRC_ERR 0x00000001 /* CRC error */
+#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
+#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
+#define TSV0_DONE 0x00000008 /* Tramsmission Completed */
+#define TSV0_MCAST 0x00000010 /* Multicast Destination */
+#define TSV0_BCAST 0x00000020 /* Broadcast Destination */
+#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
+#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
+#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
+#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
+#define TSV0_GIANT 0x00000400 /* Giant Frame */
+#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
+#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
+#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
+#define TSV0_PAUSE 0x20000000 /* Pause Frame */
+#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
+#define TSV0_VLAN 0x80000000 /* VLAN Frame */
+
+/* Transmit Status Vector 1 Register */
+#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
+#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
+
+/* Receive Status Vector Register */
+#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
+#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
+#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
+#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
+#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
+#define RSV_CRC_ERR 0x00100000 /* CRC Error */
+#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
+#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
+#define RSV_REC_OK 0x00800000 /* Frame Received OK */
+#define RSV_MCAST 0x01000000 /* Multicast Frame */
+#define RSV_BCAST 0x02000000 /* Broadcast Frame */
+#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
+#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
+#define RSV_PAUSE 0x10000000 /* Pause Frame */
+#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
+#define RSV_VLAN 0x40000000 /* VLAN Frame */
+
+/* Flow Control Counter Register */
+#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
+#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
+
+/* Flow Control Status Register */
+#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
+
+/* Receive Filter Control Register */
+#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
+#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
+#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
+#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
+#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
+#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
+#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
+#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
+
+/* Receive Filter WoL Status/Clear Registers */
+#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
+#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
+#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
+#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
+#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
+#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
+#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
+#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
+
+/* Interrupt Status/Enable/Clear/Set Registers */
+#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
+#define INT_RX_ERR 0x00000002 /* Receive Error */
+#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
+#define INT_RX_DONE 0x00000008 /* Receive Done */
+#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
+#define INT_TX_ERR 0x00000020 /* Transmit Error */
+#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
+#define INT_TX_DONE 0x00000080 /* Transmit Done */
+#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
+#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
+
+/* Power Down Register */
+#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
+
+/* RX Descriptor Control Word */
+#define RCTRL_SIZE 0x000007FF /* Buffer size mask */
+#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
+
+/* RX Status Hash CRC Word */
+#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
+#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
+
+/* RX Status Information Word */
+#define RINFO_SIZE 0x000007FF /* Data size in bytes */
+#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
+#define RINFO_VLAN 0x00080000 /* VLAN Frame */
+#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
+#define RINFO_MCAST 0x00200000 /* Multicast Frame */
+#define RINFO_BCAST 0x00400000 /* Broadcast Frame */
+#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
+#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
+#define RINFO_LEN_ERR 0x02000000 /* Length Error */
+#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
+#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
+#define RINFO_OVERRUN 0x10000000 /* Receive overrun */
+#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
+#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
+#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
+
+//#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
+ RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+
+
+/* TX Descriptor Control Word */
+#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
+#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
+#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
+#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
+#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
+#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
+#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
+
+/* TX Status Information Word */
+#define TINFO_COL_CNT 0x01E00000 /* Collision Count */
+#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
+#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
+#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
+#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
+#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
+#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
+#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
+
+/* ENET Device Revision ID */
+#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
+
+/* DP83848C PHY Registers */
+#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
+#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
+#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
+#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
+#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
+#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
+#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
+#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
+
+/* PHY Extended Registers */
+#define PHY_REG_STS 0x10 /* Status Register */
+#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
+#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
+#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
+#define PHY_REG_RECR 0x15 /* Receive Error Counter */
+#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
+#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
+#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
+#define PHY_REG_PHYCR 0x19 /* PHY Control Register */
+#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
+#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
+#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
+
+#define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
+
+#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
+#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
+#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
+#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
+#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
+
+#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
+#define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */
+
+#define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */
+
+#define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */
+#define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */
+#define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */
+
+#define PHY_BMCR_RESET 0x8000 /* PHY Reset */
+
+#define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */
+
+#define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */
+#define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */
+
+
+static int phy_read(unsigned int PhyReg);
+static int phy_write(unsigned int PhyReg, unsigned short Data);
+
+static void txdscr_init(void);
+static void rxdscr_init(void);
+
+#if defined (__ICCARM__)
+# define AHBSRAM1
+#elif defined(TOOLCHAIN_GCC_CR)
+# define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
+#else
+# define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned))
+#endif
+
+AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
+AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
+AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
+AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
+AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
+AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
+
+
+#if NEW_LOGIC
+static int rx_consume_offset = -1;
+static int tx_produce_offset = -1;
+#else
+static int send_doff = 0;
+static int send_idx = -1;
+static int send_size = 0;
+
+static int receive_soff = 0;
+static int receive_idx = -1;
+#endif
+
+static uint32_t phy_id = 0;
+
+static inline int rinc(int idx, int mod) {
+ ++idx;
+ idx %= mod;
+ return idx;
+}
+
+//extern unsigned int SystemFrequency;
+static inline unsigned int clockselect() {
+ if(SystemCoreClock < 10000000) {
+ return 1;
+ } else if(SystemCoreClock < 15000000) {
+ return 2;
+ } else if(SystemCoreClock < 20000000) {
+ return 3;
+ } else if(SystemCoreClock < 25000000) {
+ return 4;
+ } else if(SystemCoreClock < 35000000) {
+ return 5;
+ } else if(SystemCoreClock < 50000000) {
+ return 6;
+ } else if(SystemCoreClock < 70000000) {
+ return 7;
+ } else if(SystemCoreClock < 80000000) {
+ return 8;
+ } else if(SystemCoreClock < 90000000) {
+ return 9;
+ } else if(SystemCoreClock < 100000000) {
+ return 10;
+ } else if(SystemCoreClock < 120000000) {
+ return 11;
+ } else if(SystemCoreClock < 130000000) {
+ return 12;
+ } else if(SystemCoreClock < 140000000) {
+ return 13;
+ } else if(SystemCoreClock < 150000000) {
+ return 15;
+ } else if(SystemCoreClock < 160000000) {
+ return 16;
+ } else {
+ return 0;
+ }
+}
+
+#ifndef min
+#define min(x, y) (((x)<(y))?(x):(y))
+#endif
+
+/*----------------------------------------------------------------------------
+ Ethernet Device initialize
+ *----------------------------------------------------------------------------*/
+int ethernet_init() {
+ int regv, tout;
+ char mac[ETHERNET_ADDR_SIZE];
+ unsigned int clock = clockselect();
+
+ LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */
+
+ LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */
+ LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */
+ LPC_IOCON->P1_1 &= ~0x07;
+ LPC_IOCON->P1_1 |= 0x01; /* ENET_TXD1 */
+ LPC_IOCON->P1_4 &= ~0x07;
+ LPC_IOCON->P1_4 |= 0x01; /* ENET_TXEN */
+ LPC_IOCON->P1_8 &= ~0x07;
+ LPC_IOCON->P1_8 |= 0x01; /* ENET_CRS */
+ LPC_IOCON->P1_9 &= ~0x07;
+ LPC_IOCON->P1_9 |= 0x01; /* ENET_RXD0 */
+ LPC_IOCON->P1_10 &= ~0x07;
+ LPC_IOCON->P1_10 |= 0x01; /* ENET_RXD1 */
+ LPC_IOCON->P1_14 &= ~0x07;
+ LPC_IOCON->P1_14 |= 0x01; /* ENET_RX_ER */
+ LPC_IOCON->P1_15 &= ~0x07;
+ LPC_IOCON->P1_15 |= 0x01; /* ENET_REF_CLK */
+ LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */
+ LPC_IOCON->P1_16 |= 0x01; /* ENET_MDC */
+ LPC_IOCON->P1_17 &= ~0x07;
+ LPC_IOCON->P1_17 |= 0x01; /* ENET_MDIO */
+
+ /* Reset all EMAC internal modules. */
+ LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
+ MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
+ LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
+
+ for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */
+
+ LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */
+ LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
+ LPC_EMAC->MAXF = ETH_MAX_FLEN;
+ LPC_EMAC->CLRT = CLRT_DEF;
+ LPC_EMAC->IPGR = IPGR_DEF;
+
+ LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */
+
+ LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */
+ LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */
+
+ for(tout = 100; tout; tout--) __NOP(); /* A short delay */
+
+ LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
+ LPC_EMAC->MCMD = 0;
+
+ LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */
+
+ for (tout = 100; tout; tout--) __NOP(); /* A short delay */
+
+ LPC_EMAC->SUPP = 0;
+
+ phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */
+ for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */
+ regv = phy_read(PHY_REG_BMCR);
+ if(regv < 0 || tout == 0) {
+ return -1; /* Error */
+ }
+ if(!(regv & PHY_BMCR_RESET)) {
+ break; /* Reset complete. */
+ }
+ }
+
+ phy_id = (phy_read(PHY_REG_IDR1) << 16);
+ phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
+
+ if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
+ error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
+ }
+
+ ethernet_set_link(-1, 0);
+
+ /* Set the Ethernet MAC Address registers */
+ ethernet_address(mac);
+ LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
+ LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
+ LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
+
+ txdscr_init(); /* initialize DMA TX Descriptor */
+ rxdscr_init(); /* initialize DMA RX Descriptor */
+
+ LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
+ /* Receive Broadcast, Perfect Match Packets */
+
+ LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */
+ LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */
+
+ LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */
+ LPC_EMAC->MAC1 |= MAC1_REC_EN;
+
+#if NEW_LOGIC
+ rx_consume_offset = -1;
+ tx_produce_offset = -1;
+#else
+ send_doff = 0;
+ send_idx = -1;
+ send_size = 0;
+
+ receive_soff = 0;
+ receive_idx = -1;
+#endif
+
+ return 0;
+}
+
+/*----------------------------------------------------------------------------
+ Ethernet Device Uninitialize
+ *----------------------------------------------------------------------------*/
+void ethernet_free() {
+ LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
+ LPC_EMAC->IntClear = 0xFFFF;
+
+ LPC_SC->PCONP &= ~0x40000000; /* Power down the EMAC controller. */
+
+ LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */
+ LPC_IOCON->P1_1 &= ~0x07;
+ LPC_IOCON->P1_4 &= ~0x07;
+ LPC_IOCON->P1_8 &= ~0x07;
+ LPC_IOCON->P1_9 &= ~0x07;
+ LPC_IOCON->P1_10 &= ~0x07;
+ LPC_IOCON->P1_14 &= ~0x07;
+ LPC_IOCON->P1_15 &= ~0x07;
+ LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */
+ LPC_IOCON->P1_17 &= ~0x07;
+}
+
+// if(TxProduceIndex == TxConsumeIndex) buffer array is empty
+// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
+// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
+// TxConsumeIndex - The buffer that will/is beign sent by hardware
+
+int ethernet_write(const char *data, int slen) {
+
+#if NEW_LOGIC
+
+ if(tx_produce_offset < 0) { // mark as active if not already
+ tx_produce_offset = 0;
+ }
+
+ int index = LPC_EMAC->TxProduceIndex;
+
+ int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
+ int requested = slen;
+ int ncopy = min(remaining, requested);
+
+ void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
+ void *psrc = (void *)(data);
+
+ if(ncopy > 0 ){
+ if(data != NULL) {
+ memcpy(pdst, psrc, ncopy);
+ } else {
+ memset(pdst, 0, ncopy);
+ }
+ }
+
+ tx_produce_offset += ncopy;
+
+ return ncopy;
+
+#else
+ void *pdst, *psrc;
+ const int dlen = ETH_FRAG_SIZE;
+ int copy = 0;
+ int soff = 0;
+
+ if(send_idx == -1) {
+ send_idx = LPC_EMAC->TxProduceIndex;
+ }
+
+ if(slen + send_doff > ethernet_MTU_SIZE) {
+ return -1;
+ }
+
+ do {
+ copy = min(slen - soff, dlen - send_doff);
+ pdst = (void *)(txdesc[send_idx].Packet + send_doff);
+ psrc = (void *)(data + soff);
+ if(send_doff + copy > ETH_FRAG_SIZE) {
+ txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
+ send_idx = rinc(send_idx, NUM_TX_FRAG);
+ send_doff = 0;
+ }
+
+ if(data != NULL) {
+ memcpy(pdst, psrc, copy);
+ } else {
+ memset(pdst, 0, copy);
+ }
+
+ soff += copy;
+ send_doff += copy;
+ send_size += copy;
+ } while(soff != slen);
+
+ return soff;
+#endif
+}
+
+int ethernet_send() {
+
+#if NEW_LOGIC
+ if(tx_produce_offset < 0) { // no buffer active
+ return -1;
+ }
+
+ // ensure there is a link
+ if(!ethernet_link()) {
+ return -2;
+ }
+
+ // we have been writing in to a buffer, so finalise it
+ int size = tx_produce_offset;
+ int index = LPC_EMAC->TxProduceIndex;
+ txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
+
+ // Increment ProduceIndex to allow it to be sent
+ // We can only do this if the next slot is free
+ int next = rinc(index, NUM_TX_FRAG);
+ while(next == LPC_EMAC->TxConsumeIndex) {
+ for(int i=0; i<1000; i++) { __NOP(); }
+ }
+
+ LPC_EMAC->TxProduceIndex = next;
+ tx_produce_offset = -1;
+ return size;
+
+#else
+ int s = send_size;
+ txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
+ send_idx = rinc(send_idx, NUM_TX_FRAG);
+ LPC_EMAC->TxProduceIndex = send_idx;
+ send_doff = 0;
+ send_idx = -1;
+ send_size = 0;
+ return s;
+#endif
+}
+
+// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
+// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
+//
+// if(RxConsumeIndex == RxProduceIndex) buffer array is empty
+// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
+
+// Recevies an arrived ethernet packet.
+// Receiving an ethernet packet will drop the last received ethernet packet
+// and make a new ethernet packet ready to read.
+// Returns size of packet, else 0 if nothing to receive
+
+// We read from RxConsumeIndex from position rx_consume_offset
+// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
+// rx_consume_offset = -1 // no frame
+// rx_consume_offset = 0 // start of frame
+// Assumption: A fragment should alway be a whole frame
+
+int ethernet_receive() {
+#if NEW_LOGIC
+
+ // if we are currently reading a valid RxConsume buffer, increment to the next one
+ if(rx_consume_offset >= 0) {
+ LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
+ }
+
+ // if the buffer is empty, mark it as no valid buffer
+ if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
+ rx_consume_offset = -1;
+ return 0;
+ }
+
+ uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
+ rx_consume_offset = 0;
+
+ // check if it is not marked as last or for errors
+ if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
+ return -1;
+ }
+
+ int size = (info & RINFO_SIZE) + 1;
+ return size - 4; // don't include checksum bytes
+
+#else
+ if(receive_idx == -1) {
+ receive_idx = LPC_EMAC->RxConsumeIndex;
+ } else {
+ while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && ((uint32_t)receive_idx != LPC_EMAC->RxProduceIndex)) {
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ }
+ unsigned int info = rxstat[receive_idx].Info;
+ int slen = (info & RINFO_SIZE) + 1;
+
+ if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
+ /* Invalid frame, ignore it and free buffer. */
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ }
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ receive_soff = 0;
+
+ LPC_EMAC->RxConsumeIndex = receive_idx;
+ }
+
+ if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex) {
+ receive_idx = -1;
+ return 0;
+ }
+
+ return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
+#endif
+}
+
+// Read from an recevied ethernet packet.
+// After receive returnd a number bigger than 0 it is
+// possible to read bytes from this packet.
+// Read will write up to size bytes into data.
+// It is possible to use read multible times.
+// Each time read will start reading after the last read byte before.
+
+int ethernet_read(char *data, int dlen) {
+#if NEW_LOGIC
+ // Check we have a valid buffer to read
+ if(rx_consume_offset < 0) {
+ return 0;
+ }
+
+ // Assume 1 fragment block
+ uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
+ int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
+
+ int remaining = size - rx_consume_offset;
+ int requested = dlen;
+ int ncopy = min(remaining, requested);
+
+ void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
+ void *pdst = (void *)(data);
+
+ if(data != NULL && ncopy > 0) {
+ memcpy(pdst, psrc, ncopy);
+ }
+
+ rx_consume_offset += ncopy;
+
+ return ncopy;
+#else
+ int slen;
+ int copy = 0;
+ unsigned int more;
+ unsigned int info;
+ void *pdst, *psrc;
+ int doff = 0;
+
+ if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
+ return 0;
+ }
+
+ do {
+ info = rxstat[receive_idx].Info;
+ more = !(info & RINFO_LAST_FLAG);
+ slen = (info & RINFO_SIZE) + 1;
+
+ if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
+ /* Invalid frame, ignore it and free buffer. */
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ } else {
+
+ copy = min(slen - receive_soff, dlen - doff);
+ psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
+ pdst = (void *)(data + doff);
+
+ if(data != NULL) {
+ /* check if Buffer available */
+ memcpy(pdst, psrc, copy);
+ }
+
+ receive_soff += copy;
+ doff += copy;
+
+ if((more && (receive_soff == slen))) {
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ receive_soff = 0;
+ }
+ }
+ } while(more && !(doff == dlen) && !receive_soff);
+
+ return doff;
+#endif
+}
+
+int ethernet_link(void) {
+
+ if (phy_id == DP83848C_ID) {
+ return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
+ }
+ else { // LAN8720_ID
+ return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
+ }
+}
+
+static int phy_write(unsigned int PhyReg, unsigned short Data) {
+ unsigned int timeOut;
+
+ LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+ LPC_EMAC->MWTD = Data;
+
+ for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) { /* Wait until operation completed */
+ if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+
+static int phy_read(unsigned int PhyReg) {
+ unsigned int timeOut;
+
+ LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+ LPC_EMAC->MCMD = MCMD_READ;
+
+ for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */
+ if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+ LPC_EMAC->MCMD = 0;
+ return LPC_EMAC->MRDD; /* Return a 16-bit value. */
+ }
+ }
+
+ return -1;
+}
+
+
+static void txdscr_init() {
+ int i;
+
+ for(i = 0; i < NUM_TX_FRAG; i++) {
+ txdesc[i].Packet = (uint32_t)&txbuf[i];
+ txdesc[i].Ctrl = 0;
+ txstat[i].Info = 0;
+ }
+
+ LPC_EMAC->TxDescriptor = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */
+ LPC_EMAC->TxStatus = (uint32_t)txstat;
+ LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
+
+ LPC_EMAC->TxProduceIndex = 0; /* Tx Descriptors Point to 0 */
+}
+
+
+static void rxdscr_init() {
+ int i;
+
+ for(i = 0; i < NUM_RX_FRAG; i++) {
+ rxdesc[i].Packet = (uint32_t)&rxbuf[i];
+ rxdesc[i].Ctrl = RCTRL_INT | (ETH_FRAG_SIZE-1);
+ rxstat[i].Info = 0;
+ rxstat[i].HashCRC = 0;
+ }
+
+ LPC_EMAC->RxDescriptor = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */
+ LPC_EMAC->RxStatus = (uint32_t)rxstat;
+ LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
+
+ LPC_EMAC->RxConsumeIndex = 0; /* Rx Descriptors Point to 0 */
+}
+
+void ethernet_address(char *mac) {
+ mbed_mac_address(mac);
+}
+
+void ethernet_set_link(int speed, int duplex) {
+ unsigned short phy_data;
+ int tout;
+
+ if((speed < 0) || (speed > 1)) {
+ phy_data = PHY_AUTO_NEG;
+ } else {
+ phy_data = (((unsigned short) speed << 13) |
+ ((unsigned short) duplex << 8));
+ }
+
+ phy_write(PHY_REG_BMCR, phy_data);
+
+ for (tout = 100; tout; tout--) { __NOP(); } /* A short delay */
+
+ switch(phy_id) {
+ case DP83848C_ID:
+ phy_data = phy_read(PHY_REG_STS);
+
+ if(phy_data & PHY_STS_DUPLEX) {
+ LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
+ LPC_EMAC->Command |= CR_FULL_DUP;
+ LPC_EMAC->IPGT = IPGT_FULL_DUP;
+ } else {
+ LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
+ LPC_EMAC->Command &= ~CR_FULL_DUP;
+ LPC_EMAC->IPGT = IPGT_HALF_DUP;
+ }
+
+ if(phy_data & PHY_STS_SPEED) {
+ LPC_EMAC->SUPP &= ~SUPP_SPEED;
+ } else {
+ LPC_EMAC->SUPP |= SUPP_SPEED;
+ }
+ break;
+
+ case LAN8720_ID:
+ phy_data = phy_read(PHY_REG_SCSR);
+
+ if (phy_data & PHY_SCSR_DUPLEX) {
+ LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
+ LPC_EMAC->Command |= CR_FULL_DUP;
+ LPC_EMAC->IPGT = IPGT_FULL_DUP;
+ } else {
+ LPC_EMAC->Command &= ~CR_FULL_DUP;
+ LPC_EMAC->IPGT = IPGT_HALF_DUP;
+ }
+
+ if(phy_data & PHY_SCSR_100MBIT) {
+ LPC_EMAC->SUPP |= SUPP_SPEED;
+ } else {
+ LPC_EMAC->SUPP &= ~SUPP_SPEED;
+ }
+
+ break;
+ }
+}
+
+/*
+ * The Embedded Artists LPC4088 QuickStart Board has an eeprom with a unique
+ * 48 bit ID. This ID is used as MAC address.
+ */
+
+#include "i2c_api.h"
+
+static int _macRetrieved = 0;
+static char _macAddr[6] = {0x00,0x02,0xF7,0xF0,0x00,0x00};
+#define EEPROM_24AA02E48_ADDR (0xA0)
+
+void mbed_mac_address(char *mac) {
+
+ if (_macRetrieved == 0) {
+ char tmp[6];
+ i2c_t i2cObj;
+
+ i2c_init(&i2cObj, P0_27, P0_28);
+
+ do {
+ // the unique ID is at offset 0xFA
+ tmp[0] = 0xFA;
+ if (i2c_write(&i2cObj, EEPROM_24AA02E48_ADDR, tmp, 1, 1) != 1) {
+ break; // failed to write
+ }
+
+
+ if (i2c_read(&i2cObj, EEPROM_24AA02E48_ADDR, tmp, 6, 1) != 6) {
+ break; // failed to read
+ }
+
+ memcpy(_macAddr, tmp, 6);
+
+ } while(0);
+
+ // We always consider the MAC address to be retrieved even though
+ // reading from the eeprom failed. If it wasn't possible to read
+ // from eeprom the default address will be used.
+ _macRetrieved = 1;
+ }
+
+ memcpy(mac, _macAddr, 6);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,416 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+
+static const PinMap PinMap_I2C_SDA[] = {
+ {P0_0 , I2C_1, 3},
+ {P0_10, I2C_2, 2},
+ {P0_19, I2C_1, 3},
+ {P0_27, I2C_0, 1},
+ {P1_15, I2C_2, 3},
+ {P1_30, I2C_0, 4},
+ {P2_14, I2C_1, 2},
+ {P2_30, I2C_2, 2},
+ {P4_20, I2C_2, 4},
+ {P5_2, I2C_0, 5},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+ {P0_1 , I2C_1, 3},
+ {P0_11, I2C_2, 2},
+ {P0_20, I2C_1, 3},
+ {P0_28, I2C_0, 1},
+ {P1_31, I2C_0, 4},
+ {P2_15, I2C_1, 2},
+ {P2_31, I2C_2, 2},
+ {P4_21, I2C_2, 2},
+ {P4_29, I2C_2, 4},
+ {P5_3, I2C_0, 5},
+ {NC , NC, 0}
+};
+
+#define I2C_CONSET(x) (x->i2c->CONSET)
+#define I2C_CONCLR(x) (x->i2c->CONCLR)
+#define I2C_STAT(x) (x->i2c->STAT)
+#define I2C_DAT(x) (x->i2c->DAT)
+#define I2C_SCLL(x, val) (x->i2c->SCLL = val)
+#define I2C_SCLH(x, val) (x->i2c->SCLH = val)
+
+static const uint32_t I2C_addr_offset[2][4] = {
+ {0x0C, 0x20, 0x24, 0x28},
+ {0x30, 0x34, 0x38, 0x3C}
+};
+
+static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+ I2C_CONCLR(obj) = (start << 5)
+ | (stop << 4)
+ | (interrupt << 3)
+ | (acknowledge << 2);
+}
+
+static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+ I2C_CONSET(obj) = (start << 5)
+ | (stop << 4)
+ | (interrupt << 3)
+ | (acknowledge << 2);
+}
+
+// Clear the Serial Interrupt (SI)
+static inline void i2c_clear_SI(i2c_t *obj) {
+ i2c_conclr(obj, 0, 0, 1, 0);
+}
+
+static inline int i2c_status(i2c_t *obj) {
+ return I2C_STAT(obj);
+}
+
+// Wait until the Serial Interrupt (SI) is set
+static int i2c_wait_SI(i2c_t *obj) {
+ int timeout = 0;
+ while (!(I2C_CONSET(obj) & (1 << 3))) {
+ timeout++;
+ if (timeout > 100000) return -1;
+ }
+ return 0;
+}
+
+static inline void i2c_interface_enable(i2c_t *obj) {
+ I2C_CONSET(obj) = 0x40;
+}
+
+static inline void i2c_power_enable(i2c_t *obj) {
+ switch ((int)obj->i2c) {
+ case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
+ case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
+ case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
+ }
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+ // determine the SPI to use
+ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+ obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
+ MBED_ASSERT((int)obj->i2c != NC);
+
+ // enable power
+ i2c_power_enable(obj);
+
+ // set default frequency at 100k
+ i2c_frequency(obj, 100000);
+ i2c_conclr(obj, 1, 1, 1, 1);
+ i2c_interface_enable(obj);
+
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+
+ // OpenDrain must explicitly be enabled for p0.0 and p0.1
+ if (sda == P0_0) {
+ pin_mode(sda, OpenDrain);
+ }
+ if (scl == P0_1) {
+ pin_mode(scl, OpenDrain);
+ }
+
+}
+
+inline int i2c_start(i2c_t *obj) {
+ int status = 0;
+ // 8.1 Before master mode can be entered, I2CON must be initialised to:
+ // - I2EN STA STO SI AA - -
+ // - 1 0 0 0 x - -
+ // if AA = 0, it can't enter slave mode
+ i2c_conclr(obj, 1, 1, 1, 1);
+
+ // The master mode may now be entered by setting the STA bit
+ // this will generate a start condition when the bus becomes free
+ i2c_conset(obj, 1, 0, 0, 1);
+
+ i2c_wait_SI(obj);
+ status = i2c_status(obj);
+
+ // Clear start bit now transmitted, and interrupt bit
+ i2c_conclr(obj, 1, 0, 0, 0);
+ return status;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+ int timeout = 0;
+
+ // write the stop bit
+ i2c_conset(obj, 0, 1, 0, 0);
+ i2c_clear_SI(obj);
+
+ // wait for STO bit to reset
+ while(I2C_CONSET(obj) & (1 << 4)) {
+ timeout ++;
+ if (timeout > 100000) return 1;
+ }
+
+ return 0;
+}
+
+
+static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
+ // write the data
+ I2C_DAT(obj) = value;
+
+ // clear SI to init a send
+ i2c_clear_SI(obj);
+
+ // wait and return status
+ i2c_wait_SI(obj);
+ return i2c_status(obj);
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+ // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
+ if(last) {
+ i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
+ } else {
+ i2c_conset(obj, 0, 0, 0, 1); // send a ACK
+ }
+
+ // accept byte
+ i2c_clear_SI(obj);
+
+ // wait for it to arrive
+ i2c_wait_SI(obj);
+
+ // return the data
+ return (I2C_DAT(obj) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+ uint32_t PCLK = PeripheralClock;
+ uint32_t pulse = PCLK / (hz * 2);
+
+ // I2C Rate
+ I2C_SCLL(obj, pulse);
+ I2C_SCLH(obj, pulse);
+}
+
+// The I2C does a read or a write as a whole operation
+// There are two types of error conditions it can encounter
+// 1) it can not obtain the bus
+// 2) it gets error responses at part of the transmission
+//
+// We tackle them as follows:
+// 1) we retry until we get the bus. we could have a "timeout" if we can not get it
+// which basically turns it in to a 2)
+// 2) on error, we use the standard error mechanisms to report/debug
+//
+// Therefore an I2C transaction should always complete. If it doesn't it is usually
+// because something is setup wrong (e.g. wiring), and we don't need to programatically
+// check for that
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+ int count, status;
+
+ status = i2c_start(obj);
+
+ if ((status != 0x10) && (status != 0x08)) {
+ i2c_stop(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+
+ status = i2c_do_write(obj, (address | 0x01), 1);
+ if (status != 0x40) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ // Read in all except last byte
+ for (count = 0; count < (length - 1); count++) {
+ int value = i2c_do_read(obj, 0);
+ status = i2c_status(obj);
+ if (status != 0x50) {
+ i2c_stop(obj);
+ return count;
+ }
+ data[count] = (char) value;
+ }
+
+ // read in last byte
+ int value = i2c_do_read(obj, 1);
+ status = i2c_status(obj);
+ if (status != 0x58) {
+ i2c_stop(obj);
+ return length - 1;
+ }
+
+ data[count] = (char) value;
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ }
+
+ return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+ int i, status;
+
+ status = i2c_start(obj);
+
+ if ((status != 0x10) && (status != 0x08)) {
+ i2c_stop(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+
+ status = i2c_do_write(obj, (address & 0xFE), 1);
+ if (status != 0x18) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ for (i=0; i<length; i++) {
+ status = i2c_do_write(obj, data[i], 0);
+ if (status != 0x28) {
+ i2c_stop(obj);
+ return i;
+ }
+ }
+
+ // clearing the serial interrupt here might cause an unintended rewrite of the last byte
+ // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
+ // i2c_clear_SI(obj);
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ }
+
+ return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+ i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+ return (i2c_do_read(obj, last) & 0xFF);
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+ int ack;
+ int status = i2c_do_write(obj, (data & 0xFF), 0);
+
+ switch(status) {
+ case 0x18: case 0x28: // Master transmit ACKs
+ ack = 1;
+ break;
+
+ case 0x40: // Master receive address transmitted ACK
+ ack = 1;
+ break;
+
+ case 0xB8: // Slave transmit ACK
+ ack = 1;
+ break;
+
+ default:
+ ack = 0;
+ break;
+ }
+
+ return ack;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+ if (enable_slave != 0) {
+ i2c_conclr(obj, 1, 1, 1, 0);
+ i2c_conset(obj, 0, 0, 0, 1);
+ } else {
+ i2c_conclr(obj, 1, 1, 1, 1);
+ }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+ int status;
+ int retval;
+
+ status = i2c_status(obj);
+ switch(status) {
+ case 0x60: retval = 3; break;
+ case 0x70: retval = 2; break;
+ case 0xA8: retval = 1; break;
+ default : retval = 0; break;
+ }
+
+ return(retval);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+ int count = 0;
+ int status;
+
+ do {
+ i2c_clear_SI(obj);
+ i2c_wait_SI(obj);
+ status = i2c_status(obj);
+ if((status == 0x80) || (status == 0x90)) {
+ data[count] = I2C_DAT(obj) & 0xFF;
+ }
+ count++;
+ } while (((status == 0x80) || (status == 0x90) ||
+ (status == 0x060) || (status == 0x70)) && (count < length));
+
+ if(status != 0xA0) {
+ i2c_stop(obj);
+ }
+
+ i2c_clear_SI(obj);
+
+ return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+ int count = 0;
+ int status;
+
+ if(length <= 0) {
+ return(0);
+ }
+
+ do {
+ status = i2c_do_write(obj, data[count], 0);
+ count++;
+ } while ((count < length) && (status == 0xB8));
+
+ if((status != 0xC0) && (status != 0xC8)) {
+ i2c_stop(obj);
+ }
+
+ i2c_clear_SI(obj);
+
+ return(count);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+ uint32_t addr;
+
+ if ((idx >= 0) && (idx <= 3)) {
+ addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
+ *((uint32_t *) addr) = address & 0xFF;
+ addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
+ *((uint32_t *) addr) = mask & 0xFE;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/pwmout_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,189 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+
+#define TCR_CNT_EN 0x00000001
+#define TCR_RESET 0x00000002
+
+// PORT ID, PWM ID, Pin function
+static const PinMap PinMap_PWM[] = {
+ {P1_2, PWM0_1, 3},
+ {P1_3, PWM0_2, 3},
+ {P1_5, PWM0_3, 3},
+ {P1_6, PWM0_4, 3},
+ {P1_7, PWM0_5, 3},
+ {P1_11, PWM0_6, 3},
+ {P1_18, PWM1_1, 2},
+ {P1_20, PWM1_2, 2},
+ {P1_21, PWM1_3, 2},
+ {P1_23, PWM1_4, 2},
+ {P1_24, PWM1_5, 2},
+ {P1_26, PWM1_6, 2},
+ {P2_0, PWM1_1, 1},
+ {P2_1, PWM1_2, 1},
+ {P2_2, PWM1_3, 1},
+ {P2_3, PWM1_4, 1},
+ {P2_4, PWM1_5, 1},
+ {P2_5, PWM1_6, 1},
+ {P3_16, PWM0_1, 2},
+ {P3_17, PWM0_2, 2},
+ {P3_18, PWM0_3, 2},
+ {P3_19, PWM0_4, 2},
+ {P3_20, PWM0_5, 2},
+ {P3_21, PWM0_6, 2},
+ {P3_24, PWM1_1, 2},
+ {P3_25, PWM1_2, 2},
+ {P3_26, PWM1_3, 2},
+ {P3_27, PWM1_4, 2},
+ {P3_28, PWM1_5, 2},
+ {P3_29, PWM1_6, 2},
+ {NC, NC, 0}
+};
+
+static const uint32_t PWM_mr_offset[7] = {
+ 0x18, 0x1C, 0x20, 0x24, 0x40, 0x44, 0x48
+};
+
+#define TCR_PWM_EN 0x00000008
+static unsigned int pwm_clock_mhz;
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+ // determine the channel
+ PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+ MBED_ASSERT(pwm != (PWMName)NC);
+
+ obj->channel = pwm;
+ obj->pwm = LPC_PWM0;
+
+ if (obj->channel > 6) { // PWM1 is used if pwm > 6
+ obj->channel -= 6;
+ obj->pwm = LPC_PWM1;
+ }
+
+ obj->MR = (__IO uint32_t *)((uint32_t)obj->pwm + PWM_mr_offset[obj->channel]);
+
+ // ensure the power is on
+ if (obj->pwm == LPC_PWM0) {
+ LPC_SC->PCONP |= 1 << 5;
+ } else {
+ LPC_SC->PCONP |= 1 << 6;
+ }
+
+ obj->pwm->PR = 0; // no pre-scale
+
+ // ensure single PWM mode
+ obj->pwm->MCR = 1 << 1; // reset TC on match 0
+
+ // enable the specific PWM output
+ obj->pwm->PCR |= 1 << (8 + obj->channel);
+
+ pwm_clock_mhz = PeripheralClock / 1000000;
+
+ // default to 20ms: standard for servos, and fine for e.g. brightness control
+ pwmout_period_ms(obj, 20);
+ pwmout_write (obj, 0);
+
+ // Wire pinout
+ pinmap_pinout(pin, PinMap_PWM);
+}
+
+void pwmout_free(pwmout_t* obj) {
+ // [TODO]
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+ if (value < 0.0f) {
+ value = 0.0;
+ } else if (value > 1.0f) {
+ value = 1.0;
+ }
+
+ // set channel match to percentage
+ uint32_t v = (uint32_t)((float)(obj->pwm->MR0) * value);
+
+ // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
+ if (v == obj->pwm->MR0) {
+ v++;
+ }
+
+ *obj->MR = v;
+
+ // accept on next period start
+ obj->pwm->LER |= 1 << obj->channel;
+}
+
+float pwmout_read(pwmout_t* obj) {
+ float v = (float)(*obj->MR) / (float)(obj->pwm->MR0);
+ return (v > 1.0f) ? (1.0f) : (v);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+ pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+ pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us) {
+ // calculate number of ticks
+ uint32_t ticks = pwm_clock_mhz * us;
+
+ // set reset
+ obj->pwm->TCR = TCR_RESET;
+
+ // set the global match register
+ obj->pwm->MR0 = ticks;
+
+ // Scale the pulse width to preserve the duty ratio
+ if (obj->pwm->MR0 > 0) {
+ *obj->MR = (*obj->MR * ticks) / obj->pwm->MR0;
+ }
+
+ // set the channel latch to update value at next period start
+ obj->pwm->LER |= 1 << 0;
+
+ // enable counter and pwm, clear reset
+ obj->pwm->TCR = TCR_CNT_EN | TCR_PWM_EN;
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+ pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+ pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+ // calculate number of ticks
+ uint32_t v = pwm_clock_mhz * us;
+
+ // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
+ if (v == obj->pwm->MR0) {
+ v++;
+ }
+
+ // set the match register value
+ *obj->MR = v;
+
+ // set the channel latch to update value at next period start
+ obj->pwm->LER |= 1 << obj->channel;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/serial_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,330 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+static const PinMap PinMap_UART_TX[] = {
+ {P0_0, UART_3, 2},
+ {P0_2, UART_0, 1},
+ {P0_10, UART_2, 1},
+ {P0_15, UART_1, 1},
+ {P1_29, UART_4, 5},
+ {P0_25, UART_3, 3},
+ {P2_0 , UART_1, 2},
+ {P2_8 , UART_2, 2},
+ {P3_16, UART_1, 3},
+ {P4_22, UART_2, 2},
+ {P4_28, UART_3, 2},
+ {P5_4, UART_4, 4},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+ {P0_1 , UART_3, 2},
+ {P0_3 , UART_0, 1},
+ {P0_11, UART_2, 1},
+ {P0_16, UART_1, 1},
+ {P0_26, UART_3, 3},
+ {P2_1 , UART_1, 2},
+ {P2_9 , UART_2, 2},
+ {P3_17, UART_1, 3},
+ {P4_23, UART_2, 2},
+ {P4_29, UART_3, 2},
+ {P5_3, UART_4, 4},
+ {NC , NC , 0}
+};
+
+#define UART_NUM 5
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+ int is_stdio_uart = 0;
+
+ // determine the UART to use
+ UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+ UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+ UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+ MBED_ASSERT((int)uart != NC);
+
+ obj->uart = (LPC_UART_TypeDef *)uart;
+ // enable power
+ switch (uart) {
+ case UART_0: LPC_SC->PCONP |= 1 << 3; break;
+ case UART_1: LPC_SC->PCONP |= 1 << 4; break;
+ case UART_2: LPC_SC->PCONP |= 1 << 24; break;
+ case UART_3: LPC_SC->PCONP |= 1 << 25; break;
+ case UART_4: LPC_SC->PCONP |= 1 << 8; break;
+ }
+
+ // enable fifos and default rx trigger level
+ obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
+ | 0 << 1 // Rx Fifo Reset
+ | 0 << 2 // Tx Fifo Reset
+ | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
+
+ // disable irqs
+ obj->uart->IER = 0 << 0 // Rx Data available irq enable
+ | 0 << 1 // Tx Fifo empty irq enable
+ | 0 << 2; // Rx Line Status irq enable
+
+ // set default baud rate and format
+ serial_baud (obj, 9600);
+ serial_format(obj, 8, ParityNone, 1);
+
+ // pinout the chosen uart
+ pinmap_pinout(tx, PinMap_UART_TX);
+ pinmap_pinout(rx, PinMap_UART_RX);
+
+ // set rx/tx pins in PullUp mode
+ if (tx != NC) {
+ pin_mode(tx, PullUp);
+ }
+ if (rx != NC) {
+ pin_mode(rx, PullUp);
+ }
+
+ switch (uart) {
+ case UART_0: obj->index = 0; break;
+ case UART_1: obj->index = 1; break;
+ case UART_2: obj->index = 2; break;
+ case UART_3: obj->index = 3; break;
+ case UART_4: obj->index = 4; break;
+ }
+
+ is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+
+ if (is_stdio_uart) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj) {
+ serial_irq_ids[obj->index] = 0;
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+ uint32_t PCLK = PeripheralClock;
+
+ // First we check to see if the basic divide with no DivAddVal/MulVal
+ // ratio gives us an integer result. If it does, we set DivAddVal = 0,
+ // MulVal = 1. Otherwise, we search the valid ratio value range to find
+ // the closest match. This could be more elegant, using search methods
+ // and/or lookup tables, but the brute force method is not that much
+ // slower, and is more maintainable.
+ uint16_t DL = PCLK / (16 * baudrate);
+
+ uint8_t DivAddVal = 0;
+ uint8_t MulVal = 1;
+ int hit = 0;
+ uint16_t dlv;
+ uint8_t mv, dav;
+ if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder
+ int err_best = baudrate, b;
+ for (mv = 1; mv < 16 && !hit; mv++)
+ {
+ for (dav = 0; dav < mv; dav++)
+ {
+ // baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul))
+ // solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul))
+ // mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding
+ // for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision
+ // note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding
+
+ if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom
+ dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2;
+ else // 2 bits headroom, use more precision
+ dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2;
+
+ // datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood
+ if (dlv == 0)
+ dlv = 1;
+
+ // datasheet says if dav > 0 then DL must be >= 2
+ if ((dav > 0) && (dlv < 2))
+ dlv = 2;
+
+ // integer rearrangement of the baudrate equation (with rounding)
+ b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2;
+
+ // check to see how we went
+ b = abs(b - baudrate);
+ if (b < err_best)
+ {
+ err_best = b;
+
+ DL = dlv;
+ MulVal = mv;
+ DivAddVal = dav;
+
+ if (b == baudrate)
+ {
+ hit = 1;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ // set LCR[DLAB] to enable writing to divider registers
+ obj->uart->LCR |= (1 << 7);
+
+ // set divider values
+ obj->uart->DLM = (DL >> 8) & 0xFF;
+ obj->uart->DLL = (DL >> 0) & 0xFF;
+ obj->uart->FDR = (uint32_t) DivAddVal << 0
+ | (uint32_t) MulVal << 4;
+
+ // clear LCR[DLAB]
+ obj->uart->LCR &= ~(1 << 7);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+ MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
+ MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
+ MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
+ (parity == ParityForced1) || (parity == ParityForced0));
+
+ stop_bits -= 1;
+ data_bits -= 5;
+
+ int parity_enable, parity_select;
+ switch (parity) {
+ case ParityNone: parity_enable = 0; parity_select = 0; break;
+ case ParityOdd : parity_enable = 1; parity_select = 0; break;
+ case ParityEven: parity_enable = 1; parity_select = 1; break;
+ case ParityForced1: parity_enable = 1; parity_select = 2; break;
+ case ParityForced0: parity_enable = 1; parity_select = 3; break;
+ default:
+ break;
+ }
+
+ obj->uart->LCR = data_bits << 0
+ | stop_bits << 2
+ | parity_enable << 3
+ | parity_select << 4;
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t iir, uint32_t index) {
+ // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
+ SerialIrq irq_type;
+ switch (iir) {
+ case 1: irq_type = TxIrq; break;
+ case 2: irq_type = RxIrq; break;
+ default: return;
+ }
+
+ if (serial_irq_ids[index] != 0)
+ irq_handler(serial_irq_ids[index], irq_type);
+}
+
+void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0);}
+void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1);}
+void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2);}
+void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3);}
+void uart4_irq() {uart_irq((LPC_UART4->IIR >> 1) & 0x7, 4);}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+ irq_handler = handler;
+ serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+ switch ((int)obj->uart) {
+ case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
+ case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
+ case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
+ case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break;
+ case UART_4: irq_n=UART4_IRQn; vector = (uint32_t)&uart4_irq; break;
+ }
+
+ if (enable) {
+ obj->uart->IER |= 1 << irq;
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+ } else { // disable
+ int all_disabled = 0;
+ SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+ obj->uart->IER &= ~(1 << irq);
+ all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
+ if (all_disabled)
+ NVIC_DisableIRQ(irq_n);
+ }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+ while (!serial_readable(obj));
+ return obj->uart->RBR;
+}
+
+void serial_putc(serial_t *obj, int c) {
+ while (!serial_writable(obj));
+ obj->uart->THR = c;
+}
+
+int serial_readable(serial_t *obj) {
+ return obj->uart->LSR & 0x01;
+}
+
+int serial_writable(serial_t *obj) {
+ return obj->uart->LSR & 0x20;
+}
+
+void serial_clear(serial_t *obj) {
+ obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
+ | 1 << 1 // rx FIFO reset
+ | 1 << 2 // tx FIFO reset
+ | 0 << 6; // interrupt depth
+}
+
+void serial_pinout_tx(PinName tx) {
+ pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+ obj->uart->LCR |= (1 << 6);
+}
+
+void serial_break_clear(serial_t *obj) {
+ obj->uart->LCR &= ~(1 << 6);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,226 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+
+#include "spi_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+static const PinMap PinMap_SPI_SCLK[] = {
+ {P0_7 , SPI_1, 2},
+ {P0_15, SPI_0, 2},
+ {P1_0, SPI_2, 4},
+ {P1_19, SPI_1, 5},
+ {P1_20, SPI_0, 5},
+ {P1_31, SPI_1, 2},
+ {P2_22, SPI_0, 2},
+ {P4_20, SPI_1, 3},
+ {P5_2, SPI_2, 2},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+ {P0_9 , SPI_1, 2},
+ {P0_13, SPI_1, 2},
+ {P0_18, SPI_0, 2},
+ {P1_1, SPI_2, 4},
+ {P1_22, SPI_1, 5},
+ {P1_24, SPI_0, 5},
+ {P2_27, SPI_0, 2},
+ {P4_23, SPI_1, 3},
+ {P5_0, SPI_2, 2},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+ {P0_8 , SPI_1, 2},
+ {P0_12, SPI_1, 2},
+ {P0_17, SPI_0, 2},
+ {P1_4, SPI_2, 4},
+ {P1_18, SPI_1, 5},
+ {P1_23, SPI_0, 5},
+ {P2_26, SPI_0, 2},
+ {P4_22, SPI_1, 3},
+ {P5_1, SPI_2, 2},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+ {P0_6 , SPI_1, 2},
+ {P0_14, SPI_1, 2},
+ {P0_16, SPI_0, 2},
+ {P1_8, SPI_2, 4},
+ {P1_21, SPI_0, 3},
+ {P1_26, SPI_1, 5},
+ {P1_28, SPI_0, 5},
+ {P2_23, SPI_0, 2},
+ {P4_21, SPI_1, 3},
+ {NC , NC , 0}
+};
+
+static inline int ssp_disable(spi_t *obj);
+static inline int ssp_enable(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+ // determine the SPI to use
+ SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+ SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+ SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+ SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+ obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
+ MBED_ASSERT((int)obj->spi != NC);
+
+ // enable power and clocking
+ switch ((int)obj->spi) {
+ case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
+ case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
+ case SPI_2: LPC_SC->PCONP |= 1 << 20; break;
+ }
+
+ // set default format and frequency
+ if (ssel == NC) {
+ spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
+ } else {
+ spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
+ }
+ spi_frequency(obj, 1000000);
+
+ // enable the ssp channel
+ ssp_enable(obj);
+
+ // pin out the spi pins
+ pinmap_pinout(mosi, PinMap_SPI_MOSI);
+ pinmap_pinout(miso, PinMap_SPI_MISO);
+ pinmap_pinout(sclk, PinMap_SPI_SCLK);
+ if (ssel != NC) {
+ pinmap_pinout(ssel, PinMap_SPI_SSEL);
+ }
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+ MBED_ASSERT(((bits >= 4) && (bits <= 16)) && ((mode >= 0) && (mode <= 3)));
+ ssp_disable(obj);
+
+ int polarity = (mode & 0x2) ? 1 : 0;
+ int phase = (mode & 0x1) ? 1 : 0;
+
+ // set it up
+ int DSS = bits - 1; // DSS (data select size)
+ int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
+ int SPH = (phase) ? 1 : 0; // SPH - clock out phase
+
+ int FRF = 0; // FRF (frame format) = SPI
+ uint32_t tmp = obj->spi->CR0;
+ tmp &= ~(0xFFFF);
+ tmp |= DSS << 0
+ | FRF << 4
+ | SPO << 6
+ | SPH << 7;
+ obj->spi->CR0 = tmp;
+
+ tmp = obj->spi->CR1;
+ tmp &= ~(0xD);
+ tmp |= 0 << 0 // LBM - loop back mode - off
+ | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
+ | 0 << 3; // SOD - slave output disable - na
+ obj->spi->CR1 = tmp;
+ ssp_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+ ssp_disable(obj);
+
+ uint32_t PCLK = PeripheralClock;
+
+ int prescaler;
+
+ for (prescaler = 2; prescaler <= 254; prescaler += 2) {
+ int prescale_hz = PCLK / prescaler;
+
+ // calculate the divider
+ int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
+
+ // check we can support the divider
+ if (divider < 256) {
+ // prescaler
+ obj->spi->CPSR = prescaler;
+
+ // divider
+ obj->spi->CR0 &= ~(0xFFFF << 8);
+ obj->spi->CR0 |= (divider - 1) << 8;
+ ssp_enable(obj);
+ return;
+ }
+ }
+ error("Couldn't setup requested SPI frequency");
+}
+
+static inline int ssp_disable(spi_t *obj) {
+ return obj->spi->CR1 &= ~(1 << 1);
+}
+
+static inline int ssp_enable(spi_t *obj) {
+ return obj->spi->CR1 |= (1 << 1);
+}
+
+static inline int ssp_readable(spi_t *obj) {
+ return obj->spi->SR & (1 << 2);
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+ return obj->spi->SR & (1 << 1);
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+ while (!ssp_writeable(obj));
+ obj->spi->DR = value;
+}
+
+static inline int ssp_read(spi_t *obj) {
+ while (!ssp_readable(obj));
+ return obj->spi->DR;
+}
+
+static inline int ssp_busy(spi_t *obj) {
+ return (obj->spi->SR & (1 << 4)) ? (1) : (0);
+}
+
+int spi_master_write(spi_t *obj, int value) {
+ ssp_write(obj, value);
+ return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj) {
+ return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+}
+
+int spi_slave_read(spi_t *obj) {
+ return obj->spi->DR;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+ while (ssp_writeable(obj) == 0) ;
+ obj->spi->DR = value;
+}
+
+int spi_busy(spi_t *obj) {
+ return ssp_busy(obj);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PeripheralNames.h Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,111 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_UART0_BASE,
+ UART_1 = (int)LPC_UART1_BASE,
+ UART_2 = (int)LPC_UART2_BASE,
+ UART_3 = (int)LPC_UART3_BASE,
+ UART_4 = (int)LPC_UART4_BASE
+} UARTName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0
+} DACName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE,
+ SPI_2 = (int)LPC_SSP2_BASE
+} SPIName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C0_BASE,
+ I2C_1 = (int)LPC_I2C1_BASE,
+ I2C_2 = (int)LPC_I2C2_BASE
+} I2CName;
+
+typedef enum {
+ PWM0_1 = 1,
+ PWM0_2,
+ PWM0_3,
+ PWM0_4,
+ PWM0_5,
+ PWM0_6,
+ PWM1_1,
+ PWM1_2,
+ PWM1_3,
+ PWM1_4,
+ PWM1_5,
+ PWM1_6
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)LPC_CAN1_BASE,
+ CAN_2 = (int)LPC_CAN2_BASE
+} CANName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+// Default peripherals
+#define MBED_SPI0 p7, p8, p9
+#define MBED_SPI1 p46, p44, p42, p45
+#define MBED_SPI2 p15, p16, p17, p18
+
+#define MBED_UART3 p29, p30
+#define MBED_UART4 p19, p18
+#define MBED_UARTUSB USBTX, USBRX
+
+#define MBED_I2C1 p12, p13
+
+#define MBED_CAN1 p12, p13
+#define MBED_CAN2 p41, p43
+
+#define MBED_ANALOGOUT0 p30
+
+#define MBED_ANALOGIN2 p29
+#define MBED_ANALOGIN3 p30
+
+#define MBED_PWMOUT0 p9
+#define MBED_PWMOUT1 p8
+#define MBED_PWMOUT2 p7
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PinNames.h Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,106 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 5
+
+typedef enum {
+ // LPC Pin Names
+ P0_0 = /*LPC_GPIO0_BASE*/0,
+ P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
+ P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
+ P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
+ P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
+ P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
+ P5_0, P5_1, P5_2, P5_3, P5_4,
+
+ // mbed DIP Pin Names
+ p1 = P0_30,
+ p2 = P2_14,
+ p3 = P0_29,
+ p4 = P2_15,
+
+ p7 = P1_24,
+ p8 = P1_23,
+ p9 = P1_20,
+ p10 = P1_19,
+ p11 = P0_21,
+ p12 = P0_0,
+ p13 = P0_1,
+ p14 = P2_10,
+ p15 = P5_0,
+ p16 = P5_1,
+ p17 = P5_2,
+ p18 = P5_3,
+ p19 = P5_4,
+ p20 = P2_22,
+ p21 = P2_23,
+ p22 = P2_25,
+ p23 = P2_26,
+ p24 = P2_27,
+ p25 = P0_2,
+ p26 = P0_3,
+
+ p29 = P0_25,
+ p30 = P0_26,
+
+ p41 = P0_4,
+ p42 = P0_7,
+ p43 = P0_5,
+ p44 = P0_8,
+ p45 = P0_6,
+ p46 = P0_9,
+
+ // Other mbed Pin Names
+ LED1 = P1_18,
+ LED2 = P0_13,
+ LED3 = P1_13,
+ LED4 = P2_19,
+
+ USBTX = P0_2,
+ USBRX = P0_3,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
+ OpenDrain = 4,
+ PullDefault = PullDown
+} PinMode;
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/analogin_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,119 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#define ANALOGIN_MEDIAN_FILTER 1
+
+#define ADC_10BIT_RANGE 0x3FF
+#define ADC_12BIT_RANGE 0xFFF
+
+static inline int div_round_up(int x, int y) {
+ return (x + (y - 1)) / y;
+}
+
+static const PinMap PinMap_ADC[] = {
+ {P0_25, ADC0_2, 0x01},
+ {P0_26, ADC0_3, 0x01},
+ {NC , NC , 0 }
+};
+
+#define ADC_RANGE ADC_12BIT_RANGE
+
+void analogin_init(analogin_t *obj, PinName pin) {
+ obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj->adc != (ADCName)NC);
+
+ // ensure power is turned on
+ LPC_SC->PCONP |= (1 << 12);
+
+ uint32_t PCLK = PeripheralClock;
+
+ // calculate minimum clock divider
+ // clkdiv = divider - 1
+ uint32_t MAX_ADC_CLK = 12400000;
+ uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
+
+ // Set the generic software-controlled ADC settings
+ LPC_ADC->CR = (0 << 0) // SEL: 0 = no channels selected
+ | (clkdiv << 8) // CLKDIV:
+ | (0 << 16) // BURST: 0 = software control
+ | (1 << 21) // PDN: 1 = operational
+ | (0 << 24) // START: 0 = no start
+ | (0 << 27); // EDGE: not applicable
+
+ // must enable analog mode (ADMODE = 0)
+ __IO uint32_t *reg = (__IO uint32_t*) (LPC_IOCON_BASE + 4 * pin);
+ *reg &= ~(1 << 7);
+
+ pinmap_pinout(pin, PinMap_ADC);
+}
+
+static inline uint32_t adc_read(analogin_t *obj) {
+ // Select the appropriate channel and start conversion
+ LPC_ADC->CR &= ~0xFF;
+ LPC_ADC->CR |= 1 << (int)obj->adc;
+ LPC_ADC->CR |= 1 << 24;
+
+ // Repeatedly get the sample data until DONE bit
+ unsigned int data;
+ do {
+ data = LPC_ADC->GDR;
+ } while ((data & ((unsigned int)1 << 31)) == 0);
+
+ // Stop conversion
+ LPC_ADC->CR &= ~(1 << 24);
+
+ return (data >> 4) & ADC_RANGE; // 12 bit
+}
+
+static inline void order(uint32_t *a, uint32_t *b) {
+ if (*a > *b) {
+ uint32_t t = *a;
+ *a = *b;
+ *b = t;
+ }
+}
+
+static inline uint32_t adc_read_u32(analogin_t *obj) {
+ uint32_t value;
+#if ANALOGIN_MEDIAN_FILTER
+ uint32_t v1 = adc_read(obj);
+ uint32_t v2 = adc_read(obj);
+ uint32_t v3 = adc_read(obj);
+ order(&v1, &v2);
+ order(&v2, &v3);
+ order(&v1, &v2);
+ value = v2;
+#else
+ value = adc_read(obj);
+#endif
+ return value;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+ uint32_t value = adc_read_u32(obj);
+
+ return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
+}
+
+float analogin_read(analogin_t *obj) {
+ uint32_t value = adc_read_u32(obj);
+ return (float)value * (1.0f / (float)ADC_RANGE);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/can_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,388 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "can_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+
+#include <math.h>
+#include <string.h>
+
+#define CAN_NUM 2
+
+/* Acceptance filter mode in AFMR register */
+#define ACCF_OFF 0x01
+#define ACCF_BYPASS 0x02
+#define ACCF_ON 0x00
+#define ACCF_FULLCAN 0x04
+
+/* There are several bit timing calculators on the internet.
+http://www.port.de/engl/canprod/sv_req_form.html
+http://www.kvaser.com/can/index.htm
+*/
+
+static const PinMap PinMap_CAN_RD[] = {
+ {P0_0 , CAN_1, 1},
+ {P0_4 , CAN_2, 2},
+ {P0_21, CAN_1, 4},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_CAN_TD[] = {
+ {P0_1 , CAN_1, 1},
+ {P0_5 , CAN_2, 2},
+ {NC , NC , 0}
+};
+
+// Type definition to hold a CAN message
+struct CANMsg {
+ unsigned int reserved1 : 16;
+ unsigned int dlc : 4; // Bits 16..19: DLC - Data Length Counter
+ unsigned int reserved0 : 10;
+ unsigned int rtr : 1; // Bit 30: Set if this is a RTR message
+ unsigned int type : 1; // Bit 31: Set if this is a 29-bit ID message
+ unsigned int id; // CAN Message ID (11-bit or 29-bit)
+ unsigned char data[8]; // CAN Message Data Bytes 0-7
+};
+typedef struct CANMsg CANMsg;
+
+static uint32_t can_irq_ids[CAN_NUM] = {0};
+static can_irq_handler irq_handler;
+
+static uint32_t can_disable(can_t *obj) {
+ uint32_t sm = obj->dev->MOD;
+ obj->dev->MOD |= 1;
+ return sm;
+}
+
+static inline void can_enable(can_t *obj) {
+ if (obj->dev->MOD & 1) {
+ obj->dev->MOD &= ~(1);
+ }
+}
+
+int can_mode(can_t *obj, CanMode mode)
+{
+ return 0; // not implemented
+}
+
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
+ return 0; // not implemented
+}
+
+static inline void can_irq(uint32_t icr, uint32_t index) {
+ uint32_t i;
+
+ for(i = 0; i < 8; i++)
+ {
+ if((can_irq_ids[index] != 0) && (icr & (1 << i)))
+ {
+ switch (i) {
+ case 0: irq_handler(can_irq_ids[index], IRQ_RX); break;
+ case 1: irq_handler(can_irq_ids[index], IRQ_TX); break;
+ case 2: irq_handler(can_irq_ids[index], IRQ_ERROR); break;
+ case 3: irq_handler(can_irq_ids[index], IRQ_OVERRUN); break;
+ case 4: irq_handler(can_irq_ids[index], IRQ_WAKEUP); break;
+ case 5: irq_handler(can_irq_ids[index], IRQ_PASSIVE); break;
+ case 6: irq_handler(can_irq_ids[index], IRQ_ARB); break;
+ case 7: irq_handler(can_irq_ids[index], IRQ_BUS); break;
+ case 8: irq_handler(can_irq_ids[index], IRQ_READY); break;
+ }
+ }
+ }
+}
+
+// Have to check that the CAN block is active before reading the Interrupt
+// Control Register, or the mbed hangs
+void can_irq_n() {
+ uint32_t icr;
+
+ if(LPC_SC->PCONP & (1 << 13)) {
+ icr = LPC_CAN1->ICR & 0x1FF;
+ can_irq(icr, 0);
+ }
+
+ if(LPC_SC->PCONP & (1 << 14)) {
+ icr = LPC_CAN2->ICR & 0x1FF;
+ can_irq(icr, 1);
+ }
+}
+
+// Register CAN object's irq handler
+void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
+ irq_handler = handler;
+ can_irq_ids[obj->index] = id;
+}
+
+// Unregister CAN object's irq handler
+void can_irq_free(can_t *obj) {
+ obj->dev->IER &= ~(1);
+ can_irq_ids[obj->index] = 0;
+
+ if ((can_irq_ids[0] == 0) && (can_irq_ids[1] == 0)) {
+ NVIC_DisableIRQ(CAN_IRQn);
+ }
+}
+
+// Clear or set a irq
+void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
+ uint32_t ier;
+
+ switch (type) {
+ case IRQ_RX: ier = (1 << 0); break;
+ case IRQ_TX: ier = (1 << 1); break;
+ case IRQ_ERROR: ier = (1 << 2); break;
+ case IRQ_OVERRUN: ier = (1 << 3); break;
+ case IRQ_WAKEUP: ier = (1 << 4); break;
+ case IRQ_PASSIVE: ier = (1 << 5); break;
+ case IRQ_ARB: ier = (1 << 6); break;
+ case IRQ_BUS: ier = (1 << 7); break;
+ case IRQ_READY: ier = (1 << 8); break;
+ default: return;
+ }
+
+ obj->dev->MOD |= 1;
+ if(enable == 0) {
+ obj->dev->IER &= ~ier;
+ }
+ else {
+ obj->dev->IER |= ier;
+ }
+ obj->dev->MOD &= ~(1);
+
+ // Enable NVIC if at least 1 interrupt is active
+ if(((LPC_SC->PCONP & (1 << 13)) && LPC_CAN1->IER) || ((LPC_SC->PCONP & (1 << 14)) && LPC_CAN2->IER)) {
+ NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq_n);
+ NVIC_EnableIRQ(CAN_IRQn);
+ }
+ else {
+ NVIC_DisableIRQ(CAN_IRQn);
+ }
+}
+
+// This table has the sampling points as close to 75% as possible. The first
+// value is TSEG1, the second TSEG2.
+static const int timing_pts[23][2] = {
+ {0x0, 0x0}, // 2, 50%
+ {0x1, 0x0}, // 3, 67%
+ {0x2, 0x0}, // 4, 75%
+ {0x3, 0x0}, // 5, 80%
+ {0x3, 0x1}, // 6, 67%
+ {0x4, 0x1}, // 7, 71%
+ {0x5, 0x1}, // 8, 75%
+ {0x6, 0x1}, // 9, 78%
+ {0x6, 0x2}, // 10, 70%
+ {0x7, 0x2}, // 11, 73%
+ {0x8, 0x2}, // 12, 75%
+ {0x9, 0x2}, // 13, 77%
+ {0x9, 0x3}, // 14, 71%
+ {0xA, 0x3}, // 15, 73%
+ {0xB, 0x3}, // 16, 75%
+ {0xC, 0x3}, // 17, 76%
+ {0xD, 0x3}, // 18, 78%
+ {0xD, 0x4}, // 19, 74%
+ {0xE, 0x4}, // 20, 75%
+ {0xF, 0x4}, // 21, 76%
+ {0xF, 0x5}, // 22, 73%
+ {0xF, 0x6}, // 23, 70%
+ {0xF, 0x7}, // 24, 67%
+};
+
+static unsigned int can_speed(unsigned int pclk, unsigned int cclk, unsigned char psjw) {
+ uint32_t btr;
+ uint16_t brp = 0;
+ uint32_t calcbit;
+ uint32_t bitwidth;
+ int hit = 0;
+ int bits;
+
+ bitwidth = (pclk / cclk);
+
+ brp = bitwidth / 0x18;
+ while ((!hit) && (brp < bitwidth / 4)) {
+ brp++;
+ for (bits = 22; bits > 0; bits--) {
+ calcbit = (bits + 3) * (brp + 1);
+ if (calcbit == bitwidth) {
+ hit = 1;
+ break;
+ }
+ }
+ }
+
+ if (hit) {
+ btr = ((timing_pts[bits][1] << 20) & 0x00700000)
+ | ((timing_pts[bits][0] << 16) & 0x000F0000)
+ | ((psjw << 14) & 0x0000C000)
+ | ((brp << 0) & 0x000003FF);
+ } else {
+ btr = 0xFFFFFFFF;
+ }
+
+ return btr;
+
+}
+
+void can_init(can_t *obj, PinName rd, PinName td) {
+ CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
+ CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
+ obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
+ MBED_ASSERT((int)obj->dev != NC);
+
+ switch ((int)obj->dev) {
+ case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
+ case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
+ }
+
+ pinmap_pinout(rd, PinMap_CAN_RD);
+ pinmap_pinout(td, PinMap_CAN_TD);
+
+ switch ((int)obj->dev) {
+ case CAN_1: obj->index = 0; break;
+ case CAN_2: obj->index = 1; break;
+ }
+
+ can_reset(obj);
+ obj->dev->IER = 0; // Disable Interrupts
+ can_frequency(obj, 100000);
+
+ LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
+}
+
+void can_free(can_t *obj) {
+ switch ((int)obj->dev) {
+ case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break;
+ case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break;
+ }
+}
+
+int can_frequency(can_t *obj, int f) {
+ int pclk = PeripheralClock;
+
+ int btr = can_speed(pclk, (unsigned int)f, 1);
+
+ if (btr > 0) {
+ uint32_t modmask = can_disable(obj);
+ obj->dev->BTR = btr;
+ obj->dev->MOD = modmask;
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc) {
+ unsigned int CANStatus;
+ CANMsg m;
+
+ can_enable(obj);
+
+ m.id = msg.id ;
+ m.dlc = msg.len & 0xF;
+ m.rtr = msg.type;
+ m.type = msg.format;
+ memcpy(m.data, msg.data, msg.len);
+ const unsigned int *buf = (const unsigned int *)&m;
+
+ CANStatus = obj->dev->SR;
+ if (CANStatus & 0x00000004) {
+ obj->dev->TFI1 = buf[0] & 0xC00F0000;
+ obj->dev->TID1 = buf[1];
+ obj->dev->TDA1 = buf[2];
+ obj->dev->TDB1 = buf[3];
+ if(cc) {
+ obj->dev->CMR = 0x30;
+ } else {
+ obj->dev->CMR = 0x21;
+ }
+ return 1;
+
+ } else if (CANStatus & 0x00000400) {
+ obj->dev->TFI2 = buf[0] & 0xC00F0000;
+ obj->dev->TID2 = buf[1];
+ obj->dev->TDA2 = buf[2];
+ obj->dev->TDB2 = buf[3];
+ if (cc) {
+ obj->dev->CMR = 0x50;
+ } else {
+ obj->dev->CMR = 0x41;
+ }
+ return 1;
+
+ } else if (CANStatus & 0x00040000) {
+ obj->dev->TFI3 = buf[0] & 0xC00F0000;
+ obj->dev->TID3 = buf[1];
+ obj->dev->TDA3 = buf[2];
+ obj->dev->TDB3 = buf[3];
+ if (cc) {
+ obj->dev->CMR = 0x90;
+ } else {
+ obj->dev->CMR = 0x81;
+ }
+ return 1;
+ }
+
+ return 0;
+}
+
+int can_read(can_t *obj, CAN_Message *msg, int handle) {
+ CANMsg x;
+ unsigned int *i = (unsigned int *)&x;
+
+ can_enable(obj);
+
+ if (obj->dev->GSR & 0x1) {
+ *i++ = obj->dev->RFS; // Frame
+ *i++ = obj->dev->RID; // ID
+ *i++ = obj->dev->RDA; // Data A
+ *i++ = obj->dev->RDB; // Data B
+ obj->dev->CMR = 0x04; // release receive buffer
+
+ msg->id = x.id;
+ msg->len = x.dlc;
+ msg->format = (x.type)? CANExtended : CANStandard;
+ msg->type = (x.rtr)? CANRemote: CANData;
+ memcpy(msg->data,x.data,x.dlc);
+ return 1;
+ }
+
+ return 0;
+}
+
+void can_reset(can_t *obj) {
+ can_disable(obj);
+ obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
+}
+
+unsigned char can_rderror(can_t *obj) {
+ return (obj->dev->GSR >> 16) & 0xFF;
+}
+
+unsigned char can_tderror(can_t *obj) {
+ return (obj->dev->GSR >> 24) & 0xFF;
+}
+
+void can_monitor(can_t *obj, int silent) {
+ uint32_t mod_mask = can_disable(obj);
+ if (silent) {
+ obj->dev->MOD |= (1 << 1);
+ } else {
+ obj->dev->MOD &= ~(1 << 1);
+ }
+ if (!(mod_mask & 1)) {
+ can_enable(obj);
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,964 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+
+#include "ethernet_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "toolchain.h"
+#include "mbed_error.h"
+
+#define NEW_LOGIC 0
+#define NEW_ETH_BUFFER 0
+
+#if NEW_ETH_BUFFER
+
+#define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets)
+#define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets)
+
+#define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size
+#define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length)
+
+#else
+
+// Memfree calculation:
+// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
+// (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
+#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
+#define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
+//#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
+
+//#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
+#define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */
+#define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */
+
+const int ethernet_MTU_SIZE = 0x300;
+
+#endif
+
+#define ETHERNET_ADDR_SIZE 6
+
+PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */
+ unsigned int Packet;
+ unsigned int Ctrl;
+};
+typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
+
+PACKED struct RX_STAT_TypeDef { /* RX Status struct */
+ unsigned int Info;
+ unsigned int HashCRC;
+};
+typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
+
+PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */
+ unsigned int Packet;
+ unsigned int Ctrl;
+};
+typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
+
+PACKED struct TX_STAT_TypeDef { /* TX Status struct */
+ unsigned int Info;
+};
+typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
+
+/* MAC Configuration Register 1 */
+#define MAC1_REC_EN 0x00000001 /* Receive Enable */
+#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
+#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
+#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
+#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
+#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
+#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
+#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
+#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
+#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
+#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
+
+/* MAC Configuration Register 2 */
+#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
+#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
+#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
+#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
+#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
+#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
+#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
+#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
+#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
+#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
+#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
+#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
+#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
+
+/* Back-to-Back Inter-Packet-Gap Register */
+#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
+#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
+
+/* Non Back-to-Back Inter-Packet-Gap Register */
+#define IPGR_DEF 0x00000012 /* Recommended value */
+
+/* Collision Window/Retry Register */
+#define CLRT_DEF 0x0000370F /* Default value */
+
+/* PHY Support Register */
+#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
+//#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
+#define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
+
+/* Test Register */
+#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
+#define TEST_TST_PAUSE 0x00000002 /* Test Pause */
+#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
+
+/* MII Management Configuration Register */
+#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
+#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
+#define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */
+#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
+
+/* MII Management Command Register */
+#define MCMD_READ 0x00000001 /* MII Read */
+#define MCMD_SCAN 0x00000002 /* MII Scan continuously */
+
+#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
+#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
+
+/* MII Management Address Register */
+#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
+#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
+
+/* MII Management Indicators Register */
+#define MIND_BUSY 0x00000001 /* MII is Busy */
+#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
+#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
+#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
+
+/* Command Register */
+#define CR_RX_EN 0x00000001 /* Enable Receive */
+#define CR_TX_EN 0x00000002 /* Enable Transmit */
+#define CR_REG_RES 0x00000008 /* Reset Host Registers */
+#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
+#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
+#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
+#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
+#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
+#define CR_RMII 0x00000200 /* Reduced MII Interface */
+#define CR_FULL_DUP 0x00000400 /* Full Duplex */
+
+/* Status Register */
+#define SR_RX_EN 0x00000001 /* Enable Receive */
+#define SR_TX_EN 0x00000002 /* Enable Transmit */
+
+/* Transmit Status Vector 0 Register */
+#define TSV0_CRC_ERR 0x00000001 /* CRC error */
+#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
+#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
+#define TSV0_DONE 0x00000008 /* Tramsmission Completed */
+#define TSV0_MCAST 0x00000010 /* Multicast Destination */
+#define TSV0_BCAST 0x00000020 /* Broadcast Destination */
+#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
+#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
+#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
+#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
+#define TSV0_GIANT 0x00000400 /* Giant Frame */
+#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
+#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
+#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
+#define TSV0_PAUSE 0x20000000 /* Pause Frame */
+#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
+#define TSV0_VLAN 0x80000000 /* VLAN Frame */
+
+/* Transmit Status Vector 1 Register */
+#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
+#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
+
+/* Receive Status Vector Register */
+#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
+#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
+#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
+#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
+#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
+#define RSV_CRC_ERR 0x00100000 /* CRC Error */
+#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
+#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
+#define RSV_REC_OK 0x00800000 /* Frame Received OK */
+#define RSV_MCAST 0x01000000 /* Multicast Frame */
+#define RSV_BCAST 0x02000000 /* Broadcast Frame */
+#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
+#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
+#define RSV_PAUSE 0x10000000 /* Pause Frame */
+#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
+#define RSV_VLAN 0x40000000 /* VLAN Frame */
+
+/* Flow Control Counter Register */
+#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
+#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
+
+/* Flow Control Status Register */
+#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
+
+/* Receive Filter Control Register */
+#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
+#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
+#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
+#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
+#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
+#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
+#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
+#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
+
+/* Receive Filter WoL Status/Clear Registers */
+#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
+#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
+#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
+#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
+#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
+#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
+#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
+#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
+
+/* Interrupt Status/Enable/Clear/Set Registers */
+#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
+#define INT_RX_ERR 0x00000002 /* Receive Error */
+#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
+#define INT_RX_DONE 0x00000008 /* Receive Done */
+#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
+#define INT_TX_ERR 0x00000020 /* Transmit Error */
+#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
+#define INT_TX_DONE 0x00000080 /* Transmit Done */
+#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
+#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
+
+/* Power Down Register */
+#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
+
+/* RX Descriptor Control Word */
+#define RCTRL_SIZE 0x000007FF /* Buffer size mask */
+#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
+
+/* RX Status Hash CRC Word */
+#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
+#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
+
+/* RX Status Information Word */
+#define RINFO_SIZE 0x000007FF /* Data size in bytes */
+#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
+#define RINFO_VLAN 0x00080000 /* VLAN Frame */
+#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
+#define RINFO_MCAST 0x00200000 /* Multicast Frame */
+#define RINFO_BCAST 0x00400000 /* Broadcast Frame */
+#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
+#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
+#define RINFO_LEN_ERR 0x02000000 /* Length Error */
+#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
+#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
+#define RINFO_OVERRUN 0x10000000 /* Receive overrun */
+#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
+#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
+#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
+
+//#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
+ RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+
+
+/* TX Descriptor Control Word */
+#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
+#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
+#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
+#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
+#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
+#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
+#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
+
+/* TX Status Information Word */
+#define TINFO_COL_CNT 0x01E00000 /* Collision Count */
+#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
+#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
+#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
+#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
+#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
+#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
+#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
+
+/* ENET Device Revision ID */
+#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
+
+/* DP83848C PHY Registers */
+#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
+#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
+#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
+#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
+#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
+#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
+#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
+#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
+
+/* PHY Extended Registers */
+#define PHY_REG_STS 0x10 /* Status Register */
+#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
+#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
+#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
+#define PHY_REG_RECR 0x15 /* Receive Error Counter */
+#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
+#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
+#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
+#define PHY_REG_PHYCR 0x19 /* PHY Control Register */
+#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
+#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
+#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
+
+#define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
+
+#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
+#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
+#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
+#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
+#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
+
+#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
+#define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */
+
+#define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */
+
+#define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */
+#define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */
+#define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */
+
+#define PHY_BMCR_RESET 0x8000 /* PHY Reset */
+
+#define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */
+
+#define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */
+#define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */
+
+
+static int phy_read(unsigned int PhyReg);
+static int phy_write(unsigned int PhyReg, unsigned short Data);
+
+static void txdscr_init(void);
+static void rxdscr_init(void);
+
+#if defined (__ICCARM__)
+# define AHBSRAM1
+#elif defined(TOOLCHAIN_GCC_CR)
+# define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
+#else
+# define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned))
+#endif
+
+AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
+AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
+AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
+AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
+AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
+AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
+
+
+#if NEW_LOGIC
+static int rx_consume_offset = -1;
+static int tx_produce_offset = -1;
+#else
+static int send_doff = 0;
+static int send_idx = -1;
+static int send_size = 0;
+
+static int receive_soff = 0;
+static int receive_idx = -1;
+#endif
+
+static uint32_t phy_id = 0;
+
+static inline int rinc(int idx, int mod) {
+ ++idx;
+ idx %= mod;
+ return idx;
+}
+
+//extern unsigned int SystemFrequency;
+static inline unsigned int clockselect() {
+ if(SystemCoreClock < 10000000) {
+ return 1;
+ } else if(SystemCoreClock < 15000000) {
+ return 2;
+ } else if(SystemCoreClock < 20000000) {
+ return 3;
+ } else if(SystemCoreClock < 25000000) {
+ return 4;
+ } else if(SystemCoreClock < 35000000) {
+ return 5;
+ } else if(SystemCoreClock < 50000000) {
+ return 6;
+ } else if(SystemCoreClock < 70000000) {
+ return 7;
+ } else if(SystemCoreClock < 80000000) {
+ return 8;
+ } else if(SystemCoreClock < 90000000) {
+ return 9;
+ } else if(SystemCoreClock < 100000000) {
+ return 10;
+ } else if(SystemCoreClock < 120000000) {
+ return 11;
+ } else if(SystemCoreClock < 130000000) {
+ return 12;
+ } else if(SystemCoreClock < 140000000) {
+ return 13;
+ } else if(SystemCoreClock < 150000000) {
+ return 15;
+ } else if(SystemCoreClock < 160000000) {
+ return 16;
+ } else {
+ return 0;
+ }
+}
+
+#ifndef min
+#define min(x, y) (((x)<(y))?(x):(y))
+#endif
+
+/*----------------------------------------------------------------------------
+ Ethernet Device initialize
+ *----------------------------------------------------------------------------*/
+int ethernet_init() {
+ int regv, tout;
+ char mac[ETHERNET_ADDR_SIZE];
+ unsigned int clock = clockselect();
+
+ LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */
+
+ LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */
+ LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */
+ LPC_IOCON->P1_1 &= ~0x07;
+ LPC_IOCON->P1_1 |= 0x01; /* ENET_TXD1 */
+ LPC_IOCON->P1_4 &= ~0x07;
+ LPC_IOCON->P1_4 |= 0x01; /* ENET_TXEN */
+ LPC_IOCON->P1_8 &= ~0x07;
+ LPC_IOCON->P1_8 |= 0x01; /* ENET_CRS */
+ LPC_IOCON->P1_9 &= ~0x07;
+ LPC_IOCON->P1_9 |= 0x01; /* ENET_RXD0 */
+ LPC_IOCON->P1_10 &= ~0x07;
+ LPC_IOCON->P1_10 |= 0x01; /* ENET_RXD1 */
+ LPC_IOCON->P1_14 &= ~0x07;
+ LPC_IOCON->P1_14 |= 0x01; /* ENET_RX_ER */
+ LPC_IOCON->P1_15 &= ~0x07;
+ LPC_IOCON->P1_15 |= 0x01; /* ENET_REF_CLK */
+ LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */
+ LPC_IOCON->P1_16 |= 0x01; /* ENET_MDC */
+ LPC_IOCON->P1_17 &= ~0x07;
+ LPC_IOCON->P1_17 |= 0x01; /* ENET_MDIO */
+
+ /* Reset all EMAC internal modules. */
+ LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
+ MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
+ LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
+
+ for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */
+
+ LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */
+ LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
+ LPC_EMAC->MAXF = ETH_MAX_FLEN;
+ LPC_EMAC->CLRT = CLRT_DEF;
+ LPC_EMAC->IPGR = IPGR_DEF;
+
+ LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */
+
+ LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */
+ LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */
+
+ for(tout = 100; tout; tout--) __NOP(); /* A short delay */
+
+ LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
+ LPC_EMAC->MCMD = 0;
+
+ LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */
+
+ for (tout = 100; tout; tout--) __NOP(); /* A short delay */
+
+ LPC_EMAC->SUPP = 0;
+
+ phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */
+ for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */
+ regv = phy_read(PHY_REG_BMCR);
+ if(regv < 0 || tout == 0) {
+ return -1; /* Error */
+ }
+ if(!(regv & PHY_BMCR_RESET)) {
+ break; /* Reset complete. */
+ }
+ }
+
+ phy_id = (phy_read(PHY_REG_IDR1) << 16);
+ phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
+
+ if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
+ error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
+ }
+
+ ethernet_set_link(-1, 0);
+
+ /* Set the Ethernet MAC Address registers */
+ ethernet_address(mac);
+ LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
+ LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
+ LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
+
+ txdscr_init(); /* initialize DMA TX Descriptor */
+ rxdscr_init(); /* initialize DMA RX Descriptor */
+
+ LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
+ /* Receive Broadcast, Perfect Match Packets */
+
+ LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */
+ LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */
+
+ LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */
+ LPC_EMAC->MAC1 |= MAC1_REC_EN;
+
+#if NEW_LOGIC
+ rx_consume_offset = -1;
+ tx_produce_offset = -1;
+#else
+ send_doff = 0;
+ send_idx = -1;
+ send_size = 0;
+
+ receive_soff = 0;
+ receive_idx = -1;
+#endif
+
+ return 0;
+}
+
+/*----------------------------------------------------------------------------
+ Ethernet Device Uninitialize
+ *----------------------------------------------------------------------------*/
+void ethernet_free() {
+ LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
+ LPC_EMAC->IntClear = 0xFFFF;
+
+ LPC_SC->PCONP &= ~0x40000000; /* Power down the EMAC controller. */
+
+ LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */
+ LPC_IOCON->P1_1 &= ~0x07;
+ LPC_IOCON->P1_4 &= ~0x07;
+ LPC_IOCON->P1_8 &= ~0x07;
+ LPC_IOCON->P1_9 &= ~0x07;
+ LPC_IOCON->P1_10 &= ~0x07;
+ LPC_IOCON->P1_14 &= ~0x07;
+ LPC_IOCON->P1_15 &= ~0x07;
+ LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */
+ LPC_IOCON->P1_17 &= ~0x07;
+}
+
+// if(TxProduceIndex == TxConsumeIndex) buffer array is empty
+// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
+// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
+// TxConsumeIndex - The buffer that will/is beign sent by hardware
+
+int ethernet_write(const char *data, int slen) {
+
+#if NEW_LOGIC
+
+ if(tx_produce_offset < 0) { // mark as active if not already
+ tx_produce_offset = 0;
+ }
+
+ int index = LPC_EMAC->TxProduceIndex;
+
+ int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
+ int requested = slen;
+ int ncopy = min(remaining, requested);
+
+ void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
+ void *psrc = (void *)(data);
+
+ if(ncopy > 0 ){
+ if(data != NULL) {
+ memcpy(pdst, psrc, ncopy);
+ } else {
+ memset(pdst, 0, ncopy);
+ }
+ }
+
+ tx_produce_offset += ncopy;
+
+ return ncopy;
+
+#else
+ void *pdst, *psrc;
+ const int dlen = ETH_FRAG_SIZE;
+ int copy = 0;
+ int soff = 0;
+
+ if(send_idx == -1) {
+ send_idx = LPC_EMAC->TxProduceIndex;
+ }
+
+ if(slen + send_doff > ethernet_MTU_SIZE) {
+ return -1;
+ }
+
+ do {
+ copy = min(slen - soff, dlen - send_doff);
+ pdst = (void *)(txdesc[send_idx].Packet + send_doff);
+ psrc = (void *)(data + soff);
+ if(send_doff + copy > ETH_FRAG_SIZE) {
+ txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
+ send_idx = rinc(send_idx, NUM_TX_FRAG);
+ send_doff = 0;
+ }
+
+ if(data != NULL) {
+ memcpy(pdst, psrc, copy);
+ } else {
+ memset(pdst, 0, copy);
+ }
+
+ soff += copy;
+ send_doff += copy;
+ send_size += copy;
+ } while(soff != slen);
+
+ return soff;
+#endif
+}
+
+int ethernet_send() {
+
+#if NEW_LOGIC
+ if(tx_produce_offset < 0) { // no buffer active
+ return -1;
+ }
+
+ // ensure there is a link
+ if(!ethernet_link()) {
+ return -2;
+ }
+
+ // we have been writing in to a buffer, so finalise it
+ int size = tx_produce_offset;
+ int index = LPC_EMAC->TxProduceIndex;
+ txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
+
+ // Increment ProduceIndex to allow it to be sent
+ // We can only do this if the next slot is free
+ int next = rinc(index, NUM_TX_FRAG);
+ while(next == LPC_EMAC->TxConsumeIndex) {
+ for(int i=0; i<1000; i++) { __NOP(); }
+ }
+
+ LPC_EMAC->TxProduceIndex = next;
+ tx_produce_offset = -1;
+ return size;
+
+#else
+ int s = send_size;
+ txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
+ send_idx = rinc(send_idx, NUM_TX_FRAG);
+ LPC_EMAC->TxProduceIndex = send_idx;
+ send_doff = 0;
+ send_idx = -1;
+ send_size = 0;
+ return s;
+#endif
+}
+
+// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
+// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
+//
+// if(RxConsumeIndex == RxProduceIndex) buffer array is empty
+// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
+
+// Recevies an arrived ethernet packet.
+// Receiving an ethernet packet will drop the last received ethernet packet
+// and make a new ethernet packet ready to read.
+// Returns size of packet, else 0 if nothing to receive
+
+// We read from RxConsumeIndex from position rx_consume_offset
+// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
+// rx_consume_offset = -1 // no frame
+// rx_consume_offset = 0 // start of frame
+// Assumption: A fragment should alway be a whole frame
+
+int ethernet_receive() {
+#if NEW_LOGIC
+
+ // if we are currently reading a valid RxConsume buffer, increment to the next one
+ if(rx_consume_offset >= 0) {
+ LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
+ }
+
+ // if the buffer is empty, mark it as no valid buffer
+ if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
+ rx_consume_offset = -1;
+ return 0;
+ }
+
+ uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
+ rx_consume_offset = 0;
+
+ // check if it is not marked as last or for errors
+ if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
+ return -1;
+ }
+
+ int size = (info & RINFO_SIZE) + 1;
+ return size - 4; // don't include checksum bytes
+
+#else
+ if(receive_idx == -1) {
+ receive_idx = LPC_EMAC->RxConsumeIndex;
+ } else {
+ while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && ((uint32_t)receive_idx != LPC_EMAC->RxProduceIndex)) {
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ }
+ unsigned int info = rxstat[receive_idx].Info;
+ int slen = (info & RINFO_SIZE) + 1;
+
+ if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
+ /* Invalid frame, ignore it and free buffer. */
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ }
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ receive_soff = 0;
+
+ LPC_EMAC->RxConsumeIndex = receive_idx;
+ }
+
+ if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex) {
+ receive_idx = -1;
+ return 0;
+ }
+
+ return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
+#endif
+}
+
+// Read from an recevied ethernet packet.
+// After receive returnd a number bigger than 0 it is
+// possible to read bytes from this packet.
+// Read will write up to size bytes into data.
+// It is possible to use read multible times.
+// Each time read will start reading after the last read byte before.
+
+int ethernet_read(char *data, int dlen) {
+#if NEW_LOGIC
+ // Check we have a valid buffer to read
+ if(rx_consume_offset < 0) {
+ return 0;
+ }
+
+ // Assume 1 fragment block
+ uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
+ int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
+
+ int remaining = size - rx_consume_offset;
+ int requested = dlen;
+ int ncopy = min(remaining, requested);
+
+ void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
+ void *pdst = (void *)(data);
+
+ if(data != NULL && ncopy > 0) {
+ memcpy(pdst, psrc, ncopy);
+ }
+
+ rx_consume_offset += ncopy;
+
+ return ncopy;
+#else
+ int slen;
+ int copy = 0;
+ unsigned int more;
+ unsigned int info;
+ void *pdst, *psrc;
+ int doff = 0;
+
+ if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
+ return 0;
+ }
+
+ do {
+ info = rxstat[receive_idx].Info;
+ more = !(info & RINFO_LAST_FLAG);
+ slen = (info & RINFO_SIZE) + 1;
+
+ if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
+ /* Invalid frame, ignore it and free buffer. */
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ } else {
+
+ copy = min(slen - receive_soff, dlen - doff);
+ psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
+ pdst = (void *)(data + doff);
+
+ if(data != NULL) {
+ /* check if Buffer available */
+ memcpy(pdst, psrc, copy);
+ }
+
+ receive_soff += copy;
+ doff += copy;
+
+ if((more && (receive_soff == slen))) {
+ receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+ receive_soff = 0;
+ }
+ }
+ } while(more && !(doff == dlen) && !receive_soff);
+
+ return doff;
+#endif
+}
+
+int ethernet_link(void) {
+
+ if (phy_id == DP83848C_ID) {
+ return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
+ }
+ else { // LAN8720_ID
+ return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
+ }
+}
+
+static int phy_write(unsigned int PhyReg, unsigned short Data) {
+ unsigned int timeOut;
+
+ LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+ LPC_EMAC->MWTD = Data;
+
+ for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) { /* Wait until operation completed */
+ if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+
+static int phy_read(unsigned int PhyReg) {
+ unsigned int timeOut;
+
+ LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+ LPC_EMAC->MCMD = MCMD_READ;
+
+ for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */
+ if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+ LPC_EMAC->MCMD = 0;
+ return LPC_EMAC->MRDD; /* Return a 16-bit value. */
+ }
+ }
+
+ return -1;
+}
+
+
+static void txdscr_init() {
+ int i;
+
+ for(i = 0; i < NUM_TX_FRAG; i++) {
+ txdesc[i].Packet = (uint32_t)&txbuf[i];
+ txdesc[i].Ctrl = 0;
+ txstat[i].Info = 0;
+ }
+
+ LPC_EMAC->TxDescriptor = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */
+ LPC_EMAC->TxStatus = (uint32_t)txstat;
+ LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
+
+ LPC_EMAC->TxProduceIndex = 0; /* Tx Descriptors Point to 0 */
+}
+
+
+static void rxdscr_init() {
+ int i;
+
+ for(i = 0; i < NUM_RX_FRAG; i++) {
+ rxdesc[i].Packet = (uint32_t)&rxbuf[i];
+ rxdesc[i].Ctrl = RCTRL_INT | (ETH_FRAG_SIZE-1);
+ rxstat[i].Info = 0;
+ rxstat[i].HashCRC = 0;
+ }
+
+ LPC_EMAC->RxDescriptor = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */
+ LPC_EMAC->RxStatus = (uint32_t)rxstat;
+ LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
+
+ LPC_EMAC->RxConsumeIndex = 0; /* Rx Descriptors Point to 0 */
+}
+
+void ethernet_address(char *mac) {
+ mbed_mac_address(mac);
+}
+
+void ethernet_set_link(int speed, int duplex) {
+ unsigned short phy_data;
+ int tout;
+
+ if((speed < 0) || (speed > 1)) {
+ phy_data = PHY_AUTO_NEG;
+ } else {
+ phy_data = (((unsigned short) speed << 13) |
+ ((unsigned short) duplex << 8));
+ }
+
+ phy_write(PHY_REG_BMCR, phy_data);
+
+ for (tout = 100; tout; tout--) { __NOP(); } /* A short delay */
+
+ switch(phy_id) {
+ case DP83848C_ID:
+ phy_data = phy_read(PHY_REG_STS);
+
+ if(phy_data & PHY_STS_DUPLEX) {
+ LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
+ LPC_EMAC->Command |= CR_FULL_DUP;
+ LPC_EMAC->IPGT = IPGT_FULL_DUP;
+ } else {
+ LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
+ LPC_EMAC->Command &= ~CR_FULL_DUP;
+ LPC_EMAC->IPGT = IPGT_HALF_DUP;
+ }
+
+ if(phy_data & PHY_STS_SPEED) {
+ LPC_EMAC->SUPP &= ~SUPP_SPEED;
+ } else {
+ LPC_EMAC->SUPP |= SUPP_SPEED;
+ }
+ break;
+
+ case LAN8720_ID:
+ phy_data = phy_read(PHY_REG_SCSR);
+
+ if (phy_data & PHY_SCSR_DUPLEX) {
+ LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
+ LPC_EMAC->Command |= CR_FULL_DUP;
+ LPC_EMAC->IPGT = IPGT_FULL_DUP;
+ } else {
+ LPC_EMAC->Command &= ~CR_FULL_DUP;
+ LPC_EMAC->IPGT = IPGT_HALF_DUP;
+ }
+
+ if(phy_data & PHY_SCSR_100MBIT) {
+ LPC_EMAC->SUPP |= SUPP_SPEED;
+ } else {
+ LPC_EMAC->SUPP &= ~SUPP_SPEED;
+ }
+
+ break;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,402 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+
+static const PinMap PinMap_I2C_SDA[] = {
+ {P0_0 , I2C_1, 3},
+ {P0_27, I2C_0, 1},
+ {P2_14, I2C_1, 2},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+ {P0_1 , I2C_1, 3},
+ {P0_28, I2C_0, 1},
+ {P2_15, I2C_1, 2},
+ {NC , NC, 0}
+};
+
+#define I2C_CONSET(x) (x->i2c->CONSET)
+#define I2C_CONCLR(x) (x->i2c->CONCLR)
+#define I2C_STAT(x) (x->i2c->STAT)
+#define I2C_DAT(x) (x->i2c->DAT)
+#define I2C_SCLL(x, val) (x->i2c->SCLL = val)
+#define I2C_SCLH(x, val) (x->i2c->SCLH = val)
+
+static const uint32_t I2C_addr_offset[2][4] = {
+ {0x0C, 0x20, 0x24, 0x28},
+ {0x30, 0x34, 0x38, 0x3C}
+};
+
+static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+ I2C_CONCLR(obj) = (start << 5)
+ | (stop << 4)
+ | (interrupt << 3)
+ | (acknowledge << 2);
+}
+
+static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+ I2C_CONSET(obj) = (start << 5)
+ | (stop << 4)
+ | (interrupt << 3)
+ | (acknowledge << 2);
+}
+
+// Clear the Serial Interrupt (SI)
+static inline void i2c_clear_SI(i2c_t *obj) {
+ i2c_conclr(obj, 0, 0, 1, 0);
+}
+
+static inline int i2c_status(i2c_t *obj) {
+ return I2C_STAT(obj);
+}
+
+// Wait until the Serial Interrupt (SI) is set
+static int i2c_wait_SI(i2c_t *obj) {
+ int timeout = 0;
+ while (!(I2C_CONSET(obj) & (1 << 3))) {
+ timeout++;
+ if (timeout > 100000) return -1;
+ }
+ return 0;
+}
+
+static inline void i2c_interface_enable(i2c_t *obj) {
+ I2C_CONSET(obj) = 0x40;
+}
+
+static inline void i2c_power_enable(i2c_t *obj) {
+ switch ((int)obj->i2c) {
+ case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
+ case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
+ case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
+ }
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+ // determine the SPI to use
+ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+ obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
+ MBED_ASSERT((int)obj->i2c != NC);
+
+ // enable power
+ i2c_power_enable(obj);
+
+ // set default frequency at 100k
+ i2c_frequency(obj, 100000);
+ i2c_conclr(obj, 1, 1, 1, 1);
+ i2c_interface_enable(obj);
+
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+
+ // OpenDrain must explicitly be enabled for p0.0 and p0.1
+ if (sda == P0_0) {
+ pin_mode(sda, OpenDrain);
+ }
+ if (scl == P0_1) {
+ pin_mode(scl, OpenDrain);
+ }
+
+}
+
+inline int i2c_start(i2c_t *obj) {
+ int status = 0;
+ // 8.1 Before master mode can be entered, I2CON must be initialised to:
+ // - I2EN STA STO SI AA - -
+ // - 1 0 0 0 x - -
+ // if AA = 0, it can't enter slave mode
+ i2c_conclr(obj, 1, 1, 1, 1);
+
+ // The master mode may now be entered by setting the STA bit
+ // this will generate a start condition when the bus becomes free
+ i2c_conset(obj, 1, 0, 0, 1);
+
+ i2c_wait_SI(obj);
+ status = i2c_status(obj);
+
+ // Clear start bit now transmitted, and interrupt bit
+ i2c_conclr(obj, 1, 0, 0, 0);
+ return status;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+ int timeout = 0;
+
+ // write the stop bit
+ i2c_conset(obj, 0, 1, 0, 0);
+ i2c_clear_SI(obj);
+
+ // wait for STO bit to reset
+ while(I2C_CONSET(obj) & (1 << 4)) {
+ timeout ++;
+ if (timeout > 100000) return 1;
+ }
+
+ return 0;
+}
+
+
+static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
+ // write the data
+ I2C_DAT(obj) = value;
+
+ // clear SI to init a send
+ i2c_clear_SI(obj);
+
+ // wait and return status
+ i2c_wait_SI(obj);
+ return i2c_status(obj);
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+ // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
+ if(last) {
+ i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
+ } else {
+ i2c_conset(obj, 0, 0, 0, 1); // send a ACK
+ }
+
+ // accept byte
+ i2c_clear_SI(obj);
+
+ // wait for it to arrive
+ i2c_wait_SI(obj);
+
+ // return the data
+ return (I2C_DAT(obj) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+ uint32_t PCLK = PeripheralClock;
+ uint32_t pulse = PCLK / (hz * 2);
+
+ // I2C Rate
+ I2C_SCLL(obj, pulse);
+ I2C_SCLH(obj, pulse);
+}
+
+// The I2C does a read or a write as a whole operation
+// There are two types of error conditions it can encounter
+// 1) it can not obtain the bus
+// 2) it gets error responses at part of the transmission
+//
+// We tackle them as follows:
+// 1) we retry until we get the bus. we could have a "timeout" if we can not get it
+// which basically turns it in to a 2)
+// 2) on error, we use the standard error mechanisms to report/debug
+//
+// Therefore an I2C transaction should always complete. If it doesn't it is usually
+// because something is setup wrong (e.g. wiring), and we don't need to programatically
+// check for that
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+ int count, status;
+
+ status = i2c_start(obj);
+
+ if ((status != 0x10) && (status != 0x08)) {
+ i2c_stop(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+
+ status = i2c_do_write(obj, (address | 0x01), 1);
+ if (status != 0x40) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ // Read in all except last byte
+ for (count = 0; count < (length - 1); count++) {
+ int value = i2c_do_read(obj, 0);
+ status = i2c_status(obj);
+ if (status != 0x50) {
+ i2c_stop(obj);
+ return count;
+ }
+ data[count] = (char) value;
+ }
+
+ // read in last byte
+ int value = i2c_do_read(obj, 1);
+ status = i2c_status(obj);
+ if (status != 0x58) {
+ i2c_stop(obj);
+ return length - 1;
+ }
+
+ data[count] = (char) value;
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ }
+
+ return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+ int i, status;
+
+ status = i2c_start(obj);
+
+ if ((status != 0x10) && (status != 0x08)) {
+ i2c_stop(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+
+ status = i2c_do_write(obj, (address & 0xFE), 1);
+ if (status != 0x18) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ for (i=0; i<length; i++) {
+ status = i2c_do_write(obj, data[i], 0);
+ if (status != 0x28) {
+ i2c_stop(obj);
+ return i;
+ }
+ }
+
+ // clearing the serial interrupt here might cause an unintended rewrite of the last byte
+ // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
+ // i2c_clear_SI(obj);
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ }
+
+ return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+ i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+ return (i2c_do_read(obj, last) & 0xFF);
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+ int ack;
+ int status = i2c_do_write(obj, (data & 0xFF), 0);
+
+ switch(status) {
+ case 0x18: case 0x28: // Master transmit ACKs
+ ack = 1;
+ break;
+
+ case 0x40: // Master receive address transmitted ACK
+ ack = 1;
+ break;
+
+ case 0xB8: // Slave transmit ACK
+ ack = 1;
+ break;
+
+ default:
+ ack = 0;
+ break;
+ }
+
+ return ack;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+ if (enable_slave != 0) {
+ i2c_conclr(obj, 1, 1, 1, 0);
+ i2c_conset(obj, 0, 0, 0, 1);
+ } else {
+ i2c_conclr(obj, 1, 1, 1, 1);
+ }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+ int status;
+ int retval;
+
+ status = i2c_status(obj);
+ switch(status) {
+ case 0x60: retval = 3; break;
+ case 0x70: retval = 2; break;
+ case 0xA8: retval = 1; break;
+ default : retval = 0; break;
+ }
+
+ return(retval);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+ int count = 0;
+ int status;
+
+ do {
+ i2c_clear_SI(obj);
+ i2c_wait_SI(obj);
+ status = i2c_status(obj);
+ if((status == 0x80) || (status == 0x90)) {
+ data[count] = I2C_DAT(obj) & 0xFF;
+ }
+ count++;
+ } while (((status == 0x80) || (status == 0x90) ||
+ (status == 0x060) || (status == 0x70)) && (count < length));
+
+ if(status != 0xA0) {
+ i2c_stop(obj);
+ }
+
+ i2c_clear_SI(obj);
+
+ return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+ int count = 0;
+ int status;
+
+ if(length <= 0) {
+ return(0);
+ }
+
+ do {
+ status = i2c_do_write(obj, data[count], 0);
+ count++;
+ } while ((count < length) && (status == 0xB8));
+
+ if((status != 0xC0) && (status != 0xC8)) {
+ i2c_stop(obj);
+ }
+
+ i2c_clear_SI(obj);
+
+ return(count);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+ uint32_t addr;
+
+ if ((idx >= 0) && (idx <= 3)) {
+ addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
+ *((uint32_t *) addr) = address & 0xFF;
+ addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
+ *((uint32_t *) addr) = mask & 0xFE;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/pwmout_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,163 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+
+#define TCR_CNT_EN 0x00000001
+#define TCR_RESET 0x00000002
+
+// PORT ID, PWM ID, Pin function
+static const PinMap PinMap_PWM[] = {
+ {P1_5, PWM0_3, 3},
+ {P1_20, PWM1_2, 2},
+ {P1_23, PWM1_4, 2},
+ {P1_24, PWM1_5, 2},
+ {NC, NC, 0}
+};
+
+static const uint32_t PWM_mr_offset[7] = {
+ 0x18, 0x1C, 0x20, 0x24, 0x40, 0x44, 0x48
+};
+
+#define TCR_PWM_EN 0x00000008
+static unsigned int pwm_clock_mhz;
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+ // determine the channel
+ PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+ MBED_ASSERT(pwm != (PWMName)NC);
+
+ obj->channel = pwm;
+ obj->pwm = LPC_PWM0;
+
+ if (obj->channel > 6) { // PWM1 is used if pwm > 6
+ obj->channel -= 6;
+ obj->pwm = LPC_PWM1;
+ }
+
+ obj->MR = (__IO uint32_t *)((uint32_t)obj->pwm + PWM_mr_offset[obj->channel]);
+
+ // ensure the power is on
+ if (obj->pwm == LPC_PWM0) {
+ LPC_SC->PCONP |= 1 << 5;
+ } else {
+ LPC_SC->PCONP |= 1 << 6;
+ }
+
+ obj->pwm->PR = 0; // no pre-scale
+
+ // ensure single PWM mode
+ obj->pwm->MCR = 1 << 1; // reset TC on match 0
+
+ // enable the specific PWM output
+ obj->pwm->PCR |= 1 << (8 + obj->channel);
+
+ pwm_clock_mhz = PeripheralClock / 1000000;
+
+ // default to 20ms: standard for servos, and fine for e.g. brightness control
+ pwmout_period_ms(obj, 20);
+ pwmout_write (obj, 0);
+
+ // Wire pinout
+ pinmap_pinout(pin, PinMap_PWM);
+}
+
+void pwmout_free(pwmout_t* obj) {
+ // [TODO]
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+ if (value < 0.0f) {
+ value = 0.0;
+ } else if (value > 1.0f) {
+ value = 1.0;
+ }
+
+ // set channel match to percentage
+ uint32_t v = (uint32_t)((float)(obj->pwm->MR0) * value);
+
+ // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
+ if (v == obj->pwm->MR0) {
+ v++;
+ }
+
+ *obj->MR = v;
+
+ // accept on next period start
+ obj->pwm->LER |= 1 << obj->channel;
+}
+
+float pwmout_read(pwmout_t* obj) {
+ float v = (float)(*obj->MR) / (float)(obj->pwm->MR0);
+ return (v > 1.0f) ? (1.0f) : (v);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+ pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+ pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us) {
+ // calculate number of ticks
+ uint32_t ticks = pwm_clock_mhz * us;
+
+ // set reset
+ obj->pwm->TCR = TCR_RESET;
+
+ // set the global match register
+ obj->pwm->MR0 = ticks;
+
+ // Scale the pulse width to preserve the duty ratio
+ if (obj->pwm->MR0 > 0) {
+ *obj->MR = (*obj->MR * ticks) / obj->pwm->MR0;
+ }
+
+ // set the channel latch to update value at next period start
+ obj->pwm->LER |= 1 << 0;
+
+ // enable counter and pwm, clear reset
+ obj->pwm->TCR = TCR_CNT_EN | TCR_PWM_EN;
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+ pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+ pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+ // calculate number of ticks
+ uint32_t v = pwm_clock_mhz * us;
+
+ // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
+ if (v == obj->pwm->MR0) {
+ v++;
+ }
+
+ // set the match register value
+ *obj->MR = v;
+
+ // set the channel latch to update value at next period start
+ obj->pwm->LER |= 1 << obj->channel;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/serial_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,317 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+static const PinMap PinMap_UART_TX[] = {
+ {P0_0, UART_3, 2},
+ {P0_2, UART_0, 1},
+ {P0_25, UART_3, 3},
+ {P4_22, UART_2, 2},
+ {P5_4, UART_4, 4},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+ {P0_1 , UART_3, 2},
+ {P0_3 , UART_0, 1},
+ {P0_26, UART_3, 3},
+ {P4_23, UART_2, 2},
+ {P5_3, UART_4, 4},
+ {NC , NC , 0}
+};
+
+#define UART_NUM 5
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+ int is_stdio_uart = 0;
+
+ // determine the UART to use
+ UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+ UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+ UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+ MBED_ASSERT((int)uart != NC);
+
+ obj->uart = (LPC_UART_TypeDef *)uart;
+ // enable power
+ switch (uart) {
+ case UART_0: LPC_SC->PCONP |= 1 << 3; break;
+ case UART_1: LPC_SC->PCONP |= 1 << 4; break;
+ case UART_2: LPC_SC->PCONP |= 1 << 24; break;
+ case UART_3: LPC_SC->PCONP |= 1 << 25; break;
+ case UART_4: LPC_SC->PCONP |= 1 << 8; break;
+ }
+
+ // enable fifos and default rx trigger level
+ obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
+ | 0 << 1 // Rx Fifo Reset
+ | 0 << 2 // Tx Fifo Reset
+ | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
+
+ // disable irqs
+ obj->uart->IER = 0 << 0 // Rx Data available irq enable
+ | 0 << 1 // Tx Fifo empty irq enable
+ | 0 << 2; // Rx Line Status irq enable
+
+ // set default baud rate and format
+ serial_baud (obj, 9600);
+ serial_format(obj, 8, ParityNone, 1);
+
+ // pinout the chosen uart
+ pinmap_pinout(tx, PinMap_UART_TX);
+ pinmap_pinout(rx, PinMap_UART_RX);
+
+ // set rx/tx pins in PullUp mode
+ if (tx != NC) {
+ pin_mode(tx, PullUp);
+ }
+ if (rx != NC) {
+ pin_mode(rx, PullUp);
+ }
+
+ switch (uart) {
+ case UART_0: obj->index = 0; break;
+ case UART_1: obj->index = 1; break;
+ case UART_2: obj->index = 2; break;
+ case UART_3: obj->index = 3; break;
+ case UART_4: obj->index = 4; break;
+ }
+
+ is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+
+ if (is_stdio_uart) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj) {
+ serial_irq_ids[obj->index] = 0;
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+ uint32_t PCLK = PeripheralClock;
+
+ // First we check to see if the basic divide with no DivAddVal/MulVal
+ // ratio gives us an integer result. If it does, we set DivAddVal = 0,
+ // MulVal = 1. Otherwise, we search the valid ratio value range to find
+ // the closest match. This could be more elegant, using search methods
+ // and/or lookup tables, but the brute force method is not that much
+ // slower, and is more maintainable.
+ uint16_t DL = PCLK / (16 * baudrate);
+
+ uint8_t DivAddVal = 0;
+ uint8_t MulVal = 1;
+ int hit = 0;
+ uint16_t dlv;
+ uint8_t mv, dav;
+ if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder
+ int err_best = baudrate, b;
+ for (mv = 1; mv < 16 && !hit; mv++)
+ {
+ for (dav = 0; dav < mv; dav++)
+ {
+ // baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul))
+ // solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul))
+ // mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding
+ // for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision
+ // note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding
+
+ if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom
+ dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2;
+ else // 2 bits headroom, use more precision
+ dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2;
+
+ // datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood
+ if (dlv == 0)
+ dlv = 1;
+
+ // datasheet says if dav > 0 then DL must be >= 2
+ if ((dav > 0) && (dlv < 2))
+ dlv = 2;
+
+ // integer rearrangement of the baudrate equation (with rounding)
+ b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2;
+
+ // check to see how we went
+ b = abs(b - baudrate);
+ if (b < err_best)
+ {
+ err_best = b;
+
+ DL = dlv;
+ MulVal = mv;
+ DivAddVal = dav;
+
+ if (b == baudrate)
+ {
+ hit = 1;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ // set LCR[DLAB] to enable writing to divider registers
+ obj->uart->LCR |= (1 << 7);
+
+ // set divider values
+ obj->uart->DLM = (DL >> 8) & 0xFF;
+ obj->uart->DLL = (DL >> 0) & 0xFF;
+ obj->uart->FDR = (uint32_t) DivAddVal << 0
+ | (uint32_t) MulVal << 4;
+
+ // clear LCR[DLAB]
+ obj->uart->LCR &= ~(1 << 7);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+ MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
+ MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
+ MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
+ (parity == ParityForced1) || (parity == ParityForced0));
+
+ stop_bits -= 1;
+ data_bits -= 5;
+
+ int parity_enable, parity_select;
+ switch (parity) {
+ case ParityNone: parity_enable = 0; parity_select = 0; break;
+ case ParityOdd : parity_enable = 1; parity_select = 0; break;
+ case ParityEven: parity_enable = 1; parity_select = 1; break;
+ case ParityForced1: parity_enable = 1; parity_select = 2; break;
+ case ParityForced0: parity_enable = 1; parity_select = 3; break;
+ default:
+ break;
+ }
+
+ obj->uart->LCR = data_bits << 0
+ | stop_bits << 2
+ | parity_enable << 3
+ | parity_select << 4;
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t iir, uint32_t index) {
+ // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
+ SerialIrq irq_type;
+ switch (iir) {
+ case 1: irq_type = TxIrq; break;
+ case 2: irq_type = RxIrq; break;
+ default: return;
+ }
+
+ if (serial_irq_ids[index] != 0)
+ irq_handler(serial_irq_ids[index], irq_type);
+}
+
+void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0);}
+void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1);}
+void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2);}
+void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3);}
+void uart4_irq() {uart_irq((LPC_UART4->IIR >> 1) & 0x7, 4);}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+ irq_handler = handler;
+ serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+ switch ((int)obj->uart) {
+ case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
+ case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
+ case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
+ case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break;
+ case UART_4: irq_n=UART4_IRQn; vector = (uint32_t)&uart4_irq; break;
+ }
+
+ if (enable) {
+ obj->uart->IER |= 1 << irq;
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+ } else { // disable
+ int all_disabled = 0;
+ SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+ obj->uart->IER &= ~(1 << irq);
+ all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
+ if (all_disabled)
+ NVIC_DisableIRQ(irq_n);
+ }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+ while (!serial_readable(obj));
+ return obj->uart->RBR;
+}
+
+void serial_putc(serial_t *obj, int c) {
+ while (!serial_writable(obj));
+ obj->uart->THR = c;
+}
+
+int serial_readable(serial_t *obj) {
+ return obj->uart->LSR & 0x01;
+}
+
+int serial_writable(serial_t *obj) {
+ return obj->uart->LSR & 0x20;
+}
+
+void serial_clear(serial_t *obj) {
+ obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
+ | 1 << 1 // rx FIFO reset
+ | 1 << 2 // tx FIFO reset
+ | 0 << 6; // interrupt depth
+}
+
+void serial_pinout_tx(PinName tx) {
+ pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+ obj->uart->LCR |= (1 << 6);
+}
+
+void serial_break_clear(serial_t *obj) {
+ obj->uart->LCR &= ~(1 << 6);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -0,0 +1,206 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+
+#include "spi_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+static const PinMap PinMap_SPI_SCLK[] = {
+ {P0_7 , SPI_1, 2},
+ {P1_19, SPI_1, 5},
+ {P1_20, SPI_0, 5},
+ {P2_22, SPI_0, 2},
+ {P5_2, SPI_2, 2},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+ {P0_9 , SPI_1, 2},
+ {P1_24, SPI_0, 5},
+ {P2_27, SPI_0, 2},
+ {P5_0, SPI_2, 2},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+ {P0_8 , SPI_1, 2},
+ {P1_23, SPI_0, 5},
+ {P2_26, SPI_0, 2},
+ {P5_1, SPI_2, 2},
+ {NC , NC , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+ {P0_6 , SPI_1, 2},
+ {P2_23, SPI_0, 2},
+ {P5_3, SPI_2, 2},
+ {NC , NC , 0}
+};
+
+static inline int ssp_disable(spi_t *obj);
+static inline int ssp_enable(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+ // determine the SPI to use
+ SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+ SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+ SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+ SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+ obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
+ MBED_ASSERT((int)obj->spi != NC);
+
+ // enable power and clocking
+ switch ((int)obj->spi) {
+ case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
+ case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
+ case SPI_2: LPC_SC->PCONP |= 1 << 20; break;
+ }
+
+ // set default format and frequency
+ if (ssel == NC) {
+ spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
+ } else {
+ spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
+ }
+ spi_frequency(obj, 1000000);
+
+ // enable the ssp channel
+ ssp_enable(obj);
+
+ // pin out the spi pins
+ pinmap_pinout(mosi, PinMap_SPI_MOSI);
+ pinmap_pinout(miso, PinMap_SPI_MISO);
+ pinmap_pinout(sclk, PinMap_SPI_SCLK);
+ if (ssel != NC) {
+ pinmap_pinout(ssel, PinMap_SPI_SSEL);
+ }
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+ MBED_ASSERT(((bits >= 4) && (bits <= 16)) && ((mode >= 0) && (mode <= 3)));
+ ssp_disable(obj);
+
+ int polarity = (mode & 0x2) ? 1 : 0;
+ int phase = (mode & 0x1) ? 1 : 0;
+
+ // set it up
+ int DSS = bits - 1; // DSS (data select size)
+ int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
+ int SPH = (phase) ? 1 : 0; // SPH - clock out phase
+
+ int FRF = 0; // FRF (frame format) = SPI
+ uint32_t tmp = obj->spi->CR0;
+ tmp &= ~(0xFFFF);
+ tmp |= DSS << 0
+ | FRF << 4
+ | SPO << 6
+ | SPH << 7;
+ obj->spi->CR0 = tmp;
+
+ tmp = obj->spi->CR1;
+ tmp &= ~(0xD);
+ tmp |= 0 << 0 // LBM - loop back mode - off
+ | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
+ | 0 << 3; // SOD - slave output disable - na
+ obj->spi->CR1 = tmp;
+ ssp_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+ ssp_disable(obj);
+
+ uint32_t PCLK = PeripheralClock;
+
+ int prescaler;
+
+ for (prescaler = 2; prescaler <= 254; prescaler += 2) {
+ int prescale_hz = PCLK / prescaler;
+
+ // calculate the divider
+ int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
+
+ // check we can support the divider
+ if (divider < 256) {
+ // prescaler
+ obj->spi->CPSR = prescaler;
+
+ // divider
+ obj->spi->CR0 &= ~(0xFFFF << 8);
+ obj->spi->CR0 |= (divider - 1) << 8;
+ ssp_enable(obj);
+ return;
+ }
+ }
+ error("Couldn't setup requested SPI frequency");
+}
+
+static inline int ssp_disable(spi_t *obj) {
+ return obj->spi->CR1 &= ~(1 << 1);
+}
+
+static inline int ssp_enable(spi_t *obj) {
+ return obj->spi->CR1 |= (1 << 1);
+}
+
+static inline int ssp_readable(spi_t *obj) {
+ return obj->spi->SR & (1 << 2);
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+ return obj->spi->SR & (1 << 1);
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+ while (!ssp_writeable(obj));
+ obj->spi->DR = value;
+}
+
+static inline int ssp_read(spi_t *obj) {
+ while (!ssp_readable(obj));
+ return obj->spi->DR;
+}
+
+static inline int ssp_busy(spi_t *obj) {
+ return (obj->spi->SR & (1 << 4)) ? (1) : (0);
+}
+
+int spi_master_write(spi_t *obj, int value) {
+ ssp_write(obj, value);
+ return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj) {
+ return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+}
+
+int spi_slave_read(spi_t *obj) {
+ return obj->spi->DR;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+ while (ssp_writeable(obj) == 0) ;
+ obj->spi->DR = value;
+}
+
+int spi_busy(spi_t *obj) {
+ return ssp_busy(obj);
+}
--- a/targets/hal/TARGET_NXP/TARGET_LPC408X/analogin_api.c Mon Feb 02 16:00:07 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,125 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "mbed_assert.h"
-#include "analogin_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-#define ANALOGIN_MEDIAN_FILTER 1
-
-#define ADC_10BIT_RANGE 0x3FF
-#define ADC_12BIT_RANGE 0xFFF
-
-static inline int div_round_up(int x, int y) {
- return (x + (y - 1)) / y;
-}
-
-static const PinMap PinMap_ADC[] = {
- {P0_23, ADC0_0, 0x01},
- {P0_24, ADC0_1, 0x01},
- {P0_25, ADC0_2, 0x01},
- {P0_26, ADC0_3, 0x01},
- {P1_30, ADC0_4, 0x03},
- {P1_31, ADC0_5, 0x03},
- {P0_12, ADC0_6, 0x03},
- {P0_13, ADC0_7, 0x03},
- {NC , NC , 0 }
-};
-
-#define ADC_RANGE ADC_12BIT_RANGE
-
-void analogin_init(analogin_t *obj, PinName pin) {
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
- MBED_ASSERT(obj->adc != (ADCName)NC);
-
- // ensure power is turned on
- LPC_SC->PCONP |= (1 << 12);
-
- uint32_t PCLK = PeripheralClock;
-
- // calculate minimum clock divider
- // clkdiv = divider - 1
- uint32_t MAX_ADC_CLK = 12400000;
- uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
-
- // Set the generic software-controlled ADC settings
- LPC_ADC->CR = (0 << 0) // SEL: 0 = no channels selected
- | (clkdiv << 8) // CLKDIV:
- | (0 << 16) // BURST: 0 = software control
- | (1 << 21) // PDN: 1 = operational
- | (0 << 24) // START: 0 = no start
- | (0 << 27); // EDGE: not applicable
-
- // must enable analog mode (ADMODE = 0)
- __IO uint32_t *reg = (__IO uint32_t*) (LPC_IOCON_BASE + 4 * pin);
- *reg &= ~(1 << 7);
-
- pinmap_pinout(pin, PinMap_ADC);
-}
-
-static inline uint32_t adc_read(analogin_t *obj) {
- // Select the appropriate channel and start conversion
- LPC_ADC->CR &= ~0xFF;
- LPC_ADC->CR |= 1 << (int)obj->adc;
- LPC_ADC->CR |= 1 << 24;
-
- // Repeatedly get the sample data until DONE bit
- unsigned int data;
- do {
- data = LPC_ADC->GDR;
- } while ((data & ((unsigned int)1 << 31)) == 0);
-
- // Stop conversion
- LPC_ADC->CR &= ~(1 << 24);
-
- return (data >> 4) & ADC_RANGE; // 12 bit
-}
-
-static inline void order(uint32_t *a, uint32_t *b) {
- if (*a > *b) {
- uint32_t t = *a;
- *a = *b;
- *b = t;
- }
-}
-
-static inline uint32_t adc_read_u32(analogin_t *obj) {
- uint32_t value;
-#if ANALOGIN_MEDIAN_FILTER
- uint32_t v1 = adc_read(obj);
- uint32_t v2 = adc_read(obj);
- uint32_t v3 = adc_read(obj);
- order(&v1, &v2);
- order(&v2, &v3);
- order(&v1, &v2);
- value = v2;
-#else
- value = adc_read(obj);
-#endif
- return value;
-}
-
-uint16_t analogin_read_u16(analogin_t *obj) {
- uint32_t value = adc_read_u32(obj);
-
- return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
-}
-
-float analogin_read(analogin_t *obj) {
- uint32_t value = adc_read_u32(obj);
- return (float)value * (1.0f / (float)ADC_RANGE);
-}
--- a/targets/hal/TARGET_NXP/TARGET_LPC408X/can_api.c Mon Feb 02 16:00:07 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,391 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "can_api.h"
-
-#include "cmsis.h"
-#include "pinmap.h"
-
-#include <math.h>
-#include <string.h>
-
-#define CAN_NUM 2
-
-/* Acceptance filter mode in AFMR register */
-#define ACCF_OFF 0x01
-#define ACCF_BYPASS 0x02
-#define ACCF_ON 0x00
-#define ACCF_FULLCAN 0x04
-
-/* There are several bit timing calculators on the internet.
-http://www.port.de/engl/canprod/sv_req_form.html
-http://www.kvaser.com/can/index.htm
-*/
-
-static const PinMap PinMap_CAN_RD[] = {
- {P0_0 , CAN_1, 1},
- {P0_4 , CAN_2, 2},
- {P0_21, CAN_1, 4},
- {P2_7 , CAN_2, 1},
- {NC , NC , 0}
-};
-
-static const PinMap PinMap_CAN_TD[] = {
- {P0_1 , CAN_1, 1},
- {P0_5 , CAN_2, 2},
- {P0_22, CAN_1, 4},
- {P2_8 , CAN_2, 1},
- {NC , NC , 0}
-};
-
-// Type definition to hold a CAN message
-struct CANMsg {
- unsigned int reserved1 : 16;
- unsigned int dlc : 4; // Bits 16..19: DLC - Data Length Counter
- unsigned int reserved0 : 10;
- unsigned int rtr : 1; // Bit 30: Set if this is a RTR message
- unsigned int type : 1; // Bit 31: Set if this is a 29-bit ID message
- unsigned int id; // CAN Message ID (11-bit or 29-bit)
- unsigned char data[8]; // CAN Message Data Bytes 0-7
-};
-typedef struct CANMsg CANMsg;
-
-static uint32_t can_irq_ids[CAN_NUM] = {0};
-static can_irq_handler irq_handler;
-
-static uint32_t can_disable(can_t *obj) {
- uint32_t sm = obj->dev->MOD;
- obj->dev->MOD |= 1;
- return sm;
-}
-
-static inline void can_enable(can_t *obj) {
- if (obj->dev->MOD & 1) {
- obj->dev->MOD &= ~(1);
- }
-}
-
-int can_mode(can_t *obj, CanMode mode)
-{
- return 0; // not implemented
-}
-
-int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
- return 0; // not implemented
-}
-
-static inline void can_irq(uint32_t icr, uint32_t index) {
- uint32_t i;
-
- for(i = 0; i < 8; i++)
- {
- if((can_irq_ids[index] != 0) && (icr & (1 << i)))
- {
- switch (i) {
- case 0: irq_handler(can_irq_ids[index], IRQ_RX); break;
- case 1: irq_handler(can_irq_ids[index], IRQ_TX); break;
- case 2: irq_handler(can_irq_ids[index], IRQ_ERROR); break;
- case 3: irq_handler(can_irq_ids[index], IRQ_OVERRUN); break;
- case 4: irq_handler(can_irq_ids[index], IRQ_WAKEUP); break;
- case 5: irq_handler(can_irq_ids[index], IRQ_PASSIVE); break;
- case 6: irq_handler(can_irq_ids[index], IRQ_ARB); break;
- case 7: irq_handler(can_irq_ids[index], IRQ_BUS); break;
- case 8: irq_handler(can_irq_ids[index], IRQ_READY); break;
- }
- }
- }
-}
-
-// Have to check that the CAN block is active before reading the Interrupt
-// Control Register, or the mbed hangs
-void can_irq_n() {
- uint32_t icr;
-
- if(LPC_SC->PCONP & (1 << 13)) {
- icr = LPC_CAN1->ICR & 0x1FF;
- can_irq(icr, 0);
- }
-
- if(LPC_SC->PCONP & (1 << 14)) {
- icr = LPC_CAN2->ICR & 0x1FF;
- can_irq(icr, 1);
- }
-}
-
-// Register CAN object's irq handler
-void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
- irq_handler = handler;
- can_irq_ids[obj->index] = id;
-}
-
-// Unregister CAN object's irq handler
-void can_irq_free(can_t *obj) {
- obj->dev->IER &= ~(1);
- can_irq_ids[obj->index] = 0;
-
- if ((can_irq_ids[0] == 0) && (can_irq_ids[1] == 0)) {
- NVIC_DisableIRQ(CAN_IRQn);
- }
-}
-
-// Clear or set a irq
-void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
- uint32_t ier;
-
- switch (type) {
- case IRQ_RX: ier = (1 << 0); break;
- case IRQ_TX: ier = (1 << 1); break;
- case IRQ_ERROR: ier = (1 << 2); break;
- case IRQ_OVERRUN: ier = (1 << 3); break;
- case IRQ_WAKEUP: ier = (1 << 4); break;
- case IRQ_PASSIVE: ier = (1 << 5); break;
- case IRQ_ARB: ier = (1 << 6); break;
- case IRQ_BUS: ier = (1 << 7); break;
- case IRQ_READY: ier = (1 << 8); break;
- default: return;
- }
-
- obj->dev->MOD |= 1;
- if(enable == 0) {
- obj->dev->IER &= ~ier;
- }
- else {
- obj->dev->IER |= ier;
- }
- obj->dev->MOD &= ~(1);
-
- // Enable NVIC if at least 1 interrupt is active
- if(((LPC_SC->PCONP & (1 << 13)) && LPC_CAN1->IER) || ((LPC_SC->PCONP & (1 << 14)) && LPC_CAN2->IER)) {
- NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq_n);
- NVIC_EnableIRQ(CAN_IRQn);
- }
- else {
- NVIC_DisableIRQ(CAN_IRQn);
- }
-}
-
-// This table has the sampling points as close to 75% as possible. The first
-// value is TSEG1, the second TSEG2.
-static const int timing_pts[23][2] = {
- {0x0, 0x0}, // 2, 50%
- {0x1, 0x0}, // 3, 67%
- {0x2, 0x0}, // 4, 75%
- {0x3, 0x0}, // 5, 80%
- {0x3, 0x1}, // 6, 67%
- {0x4, 0x1}, // 7, 71%
- {0x5, 0x1}, // 8, 75%
- {0x6, 0x1}, // 9, 78%
- {0x6, 0x2}, // 10, 70%
- {0x7, 0x2}, // 11, 73%
- {0x8, 0x2}, // 12, 75%
- {0x9, 0x2}, // 13, 77%
- {0x9, 0x3}, // 14, 71%
- {0xA, 0x3}, // 15, 73%
- {0xB, 0x3}, // 16, 75%
- {0xC, 0x3}, // 17, 76%
- {0xD, 0x3}, // 18, 78%
- {0xD, 0x4}, // 19, 74%
- {0xE, 0x4}, // 20, 75%
- {0xF, 0x4}, // 21, 76%
- {0xF, 0x5}, // 22, 73%
- {0xF, 0x6}, // 23, 70%
- {0xF, 0x7}, // 24, 67%
-};
-
-static unsigned int can_speed(unsigned int pclk, unsigned int cclk, unsigned char psjw) {
- uint32_t btr;
- uint16_t brp = 0;
- uint32_t calcbit;
- uint32_t bitwidth;
- int hit = 0;
- int bits;
-
- bitwidth = (pclk / cclk);
-
- brp = bitwidth / 0x18;
- while ((!hit) && (brp < bitwidth / 4)) {
- brp++;
- for (bits = 22; bits > 0; bits--) {
- calcbit = (bits + 3) * (brp + 1);
- if (calcbit == bitwidth) {
- hit = 1;
- break;
- }
- }
- }
-
- if (hit) {
- btr = ((timing_pts[bits][1] << 20) & 0x00700000)
- | ((timing_pts[bits][0] << 16) & 0x000F0000)
- | ((psjw << 14) & 0x0000C000)
- | ((brp << 0) & 0x000003FF);
- } else {
- btr = 0xFFFFFFFF;
- }
-
- return btr;
-
-}
-
-void can_init(can_t *obj, PinName rd, PinName td) {
- CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
- CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
- obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
- MBED_ASSERT((int)obj->dev != NC);
-
- switch ((int)obj->dev) {
- case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
- case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
- }
-
- pinmap_pinout(rd, PinMap_CAN_RD);
- pinmap_pinout(td, PinMap_CAN_TD);
-
- switch ((int)obj->dev) {
- case CAN_1: obj->index = 0; break;
- case CAN_2: obj->index = 1; break;
- }
-
- can_reset(obj);
- obj->dev->IER = 0; // Disable Interrupts
- can_frequency(obj, 100000);
-
- LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
-}
-
-void can_free(can_t *obj) {
- switch ((int)obj->dev) {
- case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break;
- case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break;
- }
-}
-
-int can_frequency(can_t *obj, int f) {
- int pclk = PeripheralClock;
-
- int btr = can_speed(pclk, (unsigned int)f, 1);
-
- if (btr > 0) {
- uint32_t modmask = can_disable(obj);
- obj->dev->BTR = btr;
- obj->dev->MOD = modmask;
- return 1;
- } else {
- return 0;
- }
-}
-
-int can_write(can_t *obj, CAN_Message msg, int cc) {
- unsigned int CANStatus;
- CANMsg m;
-
- can_enable(obj);
-
- m.id = msg.id ;
- m.dlc = msg.len & 0xF;
- m.rtr = msg.type;
- m.type = msg.format;
- memcpy(m.data, msg.data, msg.len);
- const unsigned int *buf = (const unsigned int *)&m;
-
- CANStatus = obj->dev->SR;
- if (CANStatus & 0x00000004) {
- obj->dev->TFI1 = buf[0] & 0xC00F0000;
- obj->dev->TID1 = buf[1];
- obj->dev->TDA1 = buf[2];
- obj->dev->TDB1 = buf[3];
- if(cc) {
- obj->dev->CMR = 0x30;
- } else {
- obj->dev->CMR = 0x21;
- }
- return 1;
-
- } else if (CANStatus & 0x00000400) {
- obj->dev->TFI2 = buf[0] & 0xC00F0000;
- obj->dev->TID2 = buf[1];
- obj->dev->TDA2 = buf[2];
- obj->dev->TDB2 = buf[3];
- if (cc) {
- obj->dev->CMR = 0x50;
- } else {
- obj->dev->CMR = 0x41;
- }
- return 1;
-
- } else if (CANStatus & 0x00040000) {
- obj->dev->TFI3 = buf[0] & 0xC00F0000;
- obj->dev->TID3 = buf[1];
- obj->dev->TDA3 = buf[2];
- obj->dev->TDB3 = buf[3];
- if (cc) {
- obj->dev->CMR = 0x90;
- } else {
- obj->dev->CMR = 0x81;
- }
- return 1;
- }
-
- return 0;
-}
-
-int can_read(can_t *obj, CAN_Message *msg, int handle) {
- CANMsg x;
- unsigned int *i = (unsigned int *)&x;
-
- can_enable(obj);
-
- if (obj->dev->GSR & 0x1) {
- *i++ = obj->dev->RFS; // Frame
- *i++ = obj->dev->RID; // ID
- *i++ = obj->dev->RDA; // Data A
- *i++ = obj->dev->RDB; // Data B
- obj->dev->CMR = 0x04; // release receive buffer
-
- msg->id = x.id;
- msg->len = x.dlc;
- msg->format = (x.type)? CANExtended : CANStandard;
- msg->type = (x.rtr)? CANRemote: CANData;
- memcpy(msg->data,x.data,x.dlc);
- return 1;
- }
-
- return 0;
-}
-
-void can_reset(can_t *obj) {
- can_disable(obj);
- obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
-}
-
-unsigned char can_rderror(can_t *obj) {
- return (obj->dev->GSR >> 16) & 0xFF;
-}
-
-unsigned char can_tderror(can_t *obj) {
- return (obj->dev->GSR >> 24) & 0xFF;
-}
-
-void can_monitor(can_t *obj, int silent) {
- uint32_t mod_mask = can_disable(obj);
- if (silent) {
- obj->dev->MOD |= (1 << 1);
- } else {
- obj->dev->MOD &= ~(1 << 1);
- }
- if (!(mod_mask & 1)) {
- can_enable(obj);
- }
-}
--- a/targets/hal/TARGET_NXP/TARGET_LPC408X/ethernet_api.c Mon Feb 02 16:00:07 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1008 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <string.h>
-
-#include "ethernet_api.h"
-#include "cmsis.h"
-#include "mbed_interface.h"
-#include "toolchain.h"
-#include "mbed_error.h"
-
-#define NEW_LOGIC 0
-#define NEW_ETH_BUFFER 0
-
-#if NEW_ETH_BUFFER
-
-#define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets)
-#define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets)
-
-#define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size
-#define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length)
-
-#else
-
-// Memfree calculation:
-// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
-// (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
-/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
-#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
-#define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
-//#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
-
-//#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
-#define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */
-#define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */
-
-const int ethernet_MTU_SIZE = 0x300;
-
-#endif
-
-#define ETHERNET_ADDR_SIZE 6
-
-PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */
- unsigned int Packet;
- unsigned int Ctrl;
-};
-typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
-
-PACKED struct RX_STAT_TypeDef { /* RX Status struct */
- unsigned int Info;
- unsigned int HashCRC;
-};
-typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
-
-PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */
- unsigned int Packet;
- unsigned int Ctrl;
-};
-typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
-
-PACKED struct TX_STAT_TypeDef { /* TX Status struct */
- unsigned int Info;
-};
-typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
-
-/* MAC Configuration Register 1 */
-#define MAC1_REC_EN 0x00000001 /* Receive Enable */
-#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
-#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
-#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
-#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
-#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
-#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
-#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
-#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
-#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
-#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
-
-/* MAC Configuration Register 2 */
-#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
-#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
-#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
-#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
-#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
-#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
-#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
-#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
-#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
-#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
-#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
-#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
-#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
-
-/* Back-to-Back Inter-Packet-Gap Register */
-#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
-#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
-
-/* Non Back-to-Back Inter-Packet-Gap Register */
-#define IPGR_DEF 0x00000012 /* Recommended value */
-
-/* Collision Window/Retry Register */
-#define CLRT_DEF 0x0000370F /* Default value */
-
-/* PHY Support Register */
-#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
-//#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
-#define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
-
-/* Test Register */
-#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
-#define TEST_TST_PAUSE 0x00000002 /* Test Pause */
-#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
-
-/* MII Management Configuration Register */
-#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
-#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
-#define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */
-#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
-
-/* MII Management Command Register */
-#define MCMD_READ 0x00000001 /* MII Read */
-#define MCMD_SCAN 0x00000002 /* MII Scan continuously */
-
-#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
-#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
-
-/* MII Management Address Register */
-#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
-#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
-
-/* MII Management Indicators Register */
-#define MIND_BUSY 0x00000001 /* MII is Busy */
-#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
-#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
-#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
-
-/* Command Register */
-#define CR_RX_EN 0x00000001 /* Enable Receive */
-#define CR_TX_EN 0x00000002 /* Enable Transmit */
-#define CR_REG_RES 0x00000008 /* Reset Host Registers */
-#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
-#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
-#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
-#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
-#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
-#define CR_RMII 0x00000200 /* Reduced MII Interface */
-#define CR_FULL_DUP 0x00000400 /* Full Duplex */
-
-/* Status Register */
-#define SR_RX_EN 0x00000001 /* Enable Receive */
-#define SR_TX_EN 0x00000002 /* Enable Transmit */
-
-/* Transmit Status Vector 0 Register */
-#define TSV0_CRC_ERR 0x00000001 /* CRC error */
-#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
-#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
-#define TSV0_DONE 0x00000008 /* Tramsmission Completed */
-#define TSV0_MCAST 0x00000010 /* Multicast Destination */
-#define TSV0_BCAST 0x00000020 /* Broadcast Destination */
-#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
-#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
-#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
-#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
-#define TSV0_GIANT 0x00000400 /* Giant Frame */
-#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
-#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
-#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
-#define TSV0_PAUSE 0x20000000 /* Pause Frame */
-#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
-#define TSV0_VLAN 0x80000000 /* VLAN Frame */
-
-/* Transmit Status Vector 1 Register */
-#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
-#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
-
-/* Receive Status Vector Register */
-#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
-#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
-#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
-#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
-#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
-#define RSV_CRC_ERR 0x00100000 /* CRC Error */
-#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
-#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
-#define RSV_REC_OK 0x00800000 /* Frame Received OK */
-#define RSV_MCAST 0x01000000 /* Multicast Frame */
-#define RSV_BCAST 0x02000000 /* Broadcast Frame */
-#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
-#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
-#define RSV_PAUSE 0x10000000 /* Pause Frame */
-#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
-#define RSV_VLAN 0x40000000 /* VLAN Frame */
-
-/* Flow Control Counter Register */
-#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
-#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
-
-/* Flow Control Status Register */
-#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
-
-/* Receive Filter Control Register */
-#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
-#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
-#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
-#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
-#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
-#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
-#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
-#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
-
-/* Receive Filter WoL Status/Clear Registers */
-#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
-#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
-#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
-#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
-#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
-#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
-#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
-#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
-
-/* Interrupt Status/Enable/Clear/Set Registers */
-#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
-#define INT_RX_ERR 0x00000002 /* Receive Error */
-#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
-#define INT_RX_DONE 0x00000008 /* Receive Done */
-#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
-#define INT_TX_ERR 0x00000020 /* Transmit Error */
-#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
-#define INT_TX_DONE 0x00000080 /* Transmit Done */
-#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
-#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
-
-/* Power Down Register */
-#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
-
-/* RX Descriptor Control Word */
-#define RCTRL_SIZE 0x000007FF /* Buffer size mask */
-#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
-
-/* RX Status Hash CRC Word */
-#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
-#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
-
-/* RX Status Information Word */
-#define RINFO_SIZE 0x000007FF /* Data size in bytes */
-#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
-#define RINFO_VLAN 0x00080000 /* VLAN Frame */
-#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
-#define RINFO_MCAST 0x00200000 /* Multicast Frame */
-#define RINFO_BCAST 0x00400000 /* Broadcast Frame */
-#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
-#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
-#define RINFO_LEN_ERR 0x02000000 /* Length Error */
-#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
-#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
-#define RINFO_OVERRUN 0x10000000 /* Receive overrun */
-#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
-#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
-#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
-
-//#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
-#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
- RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
-
-
-/* TX Descriptor Control Word */
-#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
-#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
-#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
-#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
-#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
-#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
-#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
-
-/* TX Status Information Word */
-#define TINFO_COL_CNT 0x01E00000 /* Collision Count */
-#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
-#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
-#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
-#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
-#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
-#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
-#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
-
-/* ENET Device Revision ID */
-#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
-
-/* DP83848C PHY Registers */
-#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
-#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
-#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
-#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
-#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
-#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
-#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
-#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
-
-/* PHY Extended Registers */
-#define PHY_REG_STS 0x10 /* Status Register */
-#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
-#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
-#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
-#define PHY_REG_RECR 0x15 /* Receive Error Counter */
-#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
-#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
-#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
-#define PHY_REG_PHYCR 0x19 /* PHY Control Register */
-#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
-#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
-#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
-
-#define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
-
-#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
-#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
-#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
-#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
-#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
-
-#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
-#define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */
-
-#define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */
-
-#define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */
-#define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */
-#define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */
-
-#define PHY_BMCR_RESET 0x8000 /* PHY Reset */
-
-#define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */
-
-#define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */
-#define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */
-
-
-static int phy_read(unsigned int PhyReg);
-static int phy_write(unsigned int PhyReg, unsigned short Data);
-
-static void txdscr_init(void);
-static void rxdscr_init(void);
-
-#if defined (__ICCARM__)
-# define AHBSRAM1
-#elif defined(TOOLCHAIN_GCC_CR)
-# define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
-#else
-# define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned))
-#endif
-
-AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
-AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
-AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
-AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
-AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
-AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
-
-
-#if NEW_LOGIC
-static int rx_consume_offset = -1;
-static int tx_produce_offset = -1;
-#else
-static int send_doff = 0;
-static int send_idx = -1;
-static int send_size = 0;
-
-static int receive_soff = 0;
-static int receive_idx = -1;
-#endif
-
-static uint32_t phy_id = 0;
-
-static inline int rinc(int idx, int mod) {
- ++idx;
- idx %= mod;
- return idx;
-}
-
-//extern unsigned int SystemFrequency;
-static inline unsigned int clockselect() {
- if(SystemCoreClock < 10000000) {
- return 1;
- } else if(SystemCoreClock < 15000000) {
- return 2;
- } else if(SystemCoreClock < 20000000) {
- return 3;
- } else if(SystemCoreClock < 25000000) {
- return 4;
- } else if(SystemCoreClock < 35000000) {
- return 5;
- } else if(SystemCoreClock < 50000000) {
- return 6;
- } else if(SystemCoreClock < 70000000) {
- return 7;
- } else if(SystemCoreClock < 80000000) {
- return 8;
- } else if(SystemCoreClock < 90000000) {
- return 9;
- } else if(SystemCoreClock < 100000000) {
- return 10;
- } else if(SystemCoreClock < 120000000) {
- return 11;
- } else if(SystemCoreClock < 130000000) {
- return 12;
- } else if(SystemCoreClock < 140000000) {
- return 13;
- } else if(SystemCoreClock < 150000000) {
- return 15;
- } else if(SystemCoreClock < 160000000) {
- return 16;
- } else {
- return 0;
- }
-}
-
-#ifndef min
-#define min(x, y) (((x)<(y))?(x):(y))
-#endif
-
-/*----------------------------------------------------------------------------
- Ethernet Device initialize
- *----------------------------------------------------------------------------*/
-int ethernet_init() {
- int regv, tout;
- char mac[ETHERNET_ADDR_SIZE];
- unsigned int clock = clockselect();
-
- LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */
-
- LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */
- LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */
- LPC_IOCON->P1_1 &= ~0x07;
- LPC_IOCON->P1_1 |= 0x01; /* ENET_TXD1 */
- LPC_IOCON->P1_4 &= ~0x07;
- LPC_IOCON->P1_4 |= 0x01; /* ENET_TXEN */
- LPC_IOCON->P1_8 &= ~0x07;
- LPC_IOCON->P1_8 |= 0x01; /* ENET_CRS */
- LPC_IOCON->P1_9 &= ~0x07;
- LPC_IOCON->P1_9 |= 0x01; /* ENET_RXD0 */
- LPC_IOCON->P1_10 &= ~0x07;
- LPC_IOCON->P1_10 |= 0x01; /* ENET_RXD1 */
- LPC_IOCON->P1_14 &= ~0x07;
- LPC_IOCON->P1_14 |= 0x01; /* ENET_RX_ER */
- LPC_IOCON->P1_15 &= ~0x07;
- LPC_IOCON->P1_15 |= 0x01; /* ENET_REF_CLK */
- LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */
- LPC_IOCON->P1_16 |= 0x01; /* ENET_MDC */
- LPC_IOCON->P1_17 &= ~0x07;
- LPC_IOCON->P1_17 |= 0x01; /* ENET_MDIO */
-
- /* Reset all EMAC internal modules. */
- LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
- MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
- LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
-
- for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */
-
- LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */
- LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
- LPC_EMAC->MAXF = ETH_MAX_FLEN;
- LPC_EMAC->CLRT = CLRT_DEF;
- LPC_EMAC->IPGR = IPGR_DEF;
-
- LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */
-
- LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */
- LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */
-
- for(tout = 100; tout; tout--) __NOP(); /* A short delay */
-
- LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
- LPC_EMAC->MCMD = 0;
-
- LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */
-
- for (tout = 100; tout; tout--) __NOP(); /* A short delay */
-
- LPC_EMAC->SUPP = 0;
-
- phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */
- for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */
- regv = phy_read(PHY_REG_BMCR);
- if(regv < 0 || tout == 0) {
- return -1; /* Error */
- }
- if(!(regv & PHY_BMCR_RESET)) {
- break; /* Reset complete. */
- }
- }
-
- phy_id = (phy_read(PHY_REG_IDR1) << 16);
- phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
-
- if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
- error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
- }
-
- ethernet_set_link(-1, 0);
-
- /* Set the Ethernet MAC Address registers */
- ethernet_address(mac);
- LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
- LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
- LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
-
- txdscr_init(); /* initialize DMA TX Descriptor */
- rxdscr_init(); /* initialize DMA RX Descriptor */
-
- LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
- /* Receive Broadcast, Perfect Match Packets */
-
- LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */
- LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */
-
- LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */
- LPC_EMAC->MAC1 |= MAC1_REC_EN;
-
-#if NEW_LOGIC
- rx_consume_offset = -1;
- tx_produce_offset = -1;
-#else
- send_doff = 0;
- send_idx = -1;
- send_size = 0;
-
- receive_soff = 0;
- receive_idx = -1;
-#endif
-
- return 0;
-}
-
-/*----------------------------------------------------------------------------
- Ethernet Device Uninitialize
- *----------------------------------------------------------------------------*/
-void ethernet_free() {
- LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
- LPC_EMAC->IntClear = 0xFFFF;
-
- LPC_SC->PCONP &= ~0x40000000; /* Power down the EMAC controller. */
-
- LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */
- LPC_IOCON->P1_1 &= ~0x07;
- LPC_IOCON->P1_4 &= ~0x07;
- LPC_IOCON->P1_8 &= ~0x07;
- LPC_IOCON->P1_9 &= ~0x07;
- LPC_IOCON->P1_10 &= ~0x07;
- LPC_IOCON->P1_14 &= ~0x07;
- LPC_IOCON->P1_15 &= ~0x07;
- LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */
- LPC_IOCON->P1_17 &= ~0x07;
-}
-
-// if(TxProduceIndex == TxConsumeIndex) buffer array is empty
-// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
-// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
-// TxConsumeIndex - The buffer that will/is beign sent by hardware
-
-int ethernet_write(const char *data, int slen) {
-
-#if NEW_LOGIC
-
- if(tx_produce_offset < 0) { // mark as active if not already
- tx_produce_offset = 0;
- }
-
- int index = LPC_EMAC->TxProduceIndex;
-
- int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
- int requested = slen;
- int ncopy = min(remaining, requested);
-
- void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
- void *psrc = (void *)(data);
-
- if(ncopy > 0 ){
- if(data != NULL) {
- memcpy(pdst, psrc, ncopy);
- } else {
- memset(pdst, 0, ncopy);
- }
- }
-
- tx_produce_offset += ncopy;
-
- return ncopy;
-
-#else
- void *pdst, *psrc;
- const int dlen = ETH_FRAG_SIZE;
- int copy = 0;
- int soff = 0;
-
- if(send_idx == -1) {
- send_idx = LPC_EMAC->TxProduceIndex;
- }
-
- if(slen + send_doff > ethernet_MTU_SIZE) {
- return -1;
- }
-
- do {
- copy = min(slen - soff, dlen - send_doff);
- pdst = (void *)(txdesc[send_idx].Packet + send_doff);
- psrc = (void *)(data + soff);
- if(send_doff + copy > ETH_FRAG_SIZE) {
- txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
- send_idx = rinc(send_idx, NUM_TX_FRAG);
- send_doff = 0;
- }
-
- if(data != NULL) {
- memcpy(pdst, psrc, copy);
- } else {
- memset(pdst, 0, copy);
- }
-
- soff += copy;
- send_doff += copy;
- send_size += copy;
- } while(soff != slen);
-
- return soff;
-#endif
-}
-
-int ethernet_send() {
-
-#if NEW_LOGIC
- if(tx_produce_offset < 0) { // no buffer active
- return -1;
- }
-
- // ensure there is a link
- if(!ethernet_link()) {
- return -2;
- }
-
- // we have been writing in to a buffer, so finalise it
- int size = tx_produce_offset;
- int index = LPC_EMAC->TxProduceIndex;
- txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
-
- // Increment ProduceIndex to allow it to be sent
- // We can only do this if the next slot is free
- int next = rinc(index, NUM_TX_FRAG);
- while(next == LPC_EMAC->TxConsumeIndex) {
- for(int i=0; i<1000; i++) { __NOP(); }
- }
-
- LPC_EMAC->TxProduceIndex = next;
- tx_produce_offset = -1;
- return size;
-
-#else
- int s = send_size;
- txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
- send_idx = rinc(send_idx, NUM_TX_FRAG);
- LPC_EMAC->TxProduceIndex = send_idx;
- send_doff = 0;
- send_idx = -1;
- send_size = 0;
- return s;
-#endif
-}
-
-// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
-// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
-//
-// if(RxConsumeIndex == RxProduceIndex) buffer array is empty
-// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
-
-// Recevies an arrived ethernet packet.
-// Receiving an ethernet packet will drop the last received ethernet packet
-// and make a new ethernet packet ready to read.
-// Returns size of packet, else 0 if nothing to receive
-
-// We read from RxConsumeIndex from position rx_consume_offset
-// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
-// rx_consume_offset = -1 // no frame
-// rx_consume_offset = 0 // start of frame
-// Assumption: A fragment should alway be a whole frame
-
-int ethernet_receive() {
-#if NEW_LOGIC
-
- // if we are currently reading a valid RxConsume buffer, increment to the next one
- if(rx_consume_offset >= 0) {
- LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
- }
-
- // if the buffer is empty, mark it as no valid buffer
- if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
- rx_consume_offset = -1;
- return 0;
- }
-
- uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
- rx_consume_offset = 0;
-
- // check if it is not marked as last or for errors
- if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
- return -1;
- }
-
- int size = (info & RINFO_SIZE) + 1;
- return size - 4; // don't include checksum bytes
-
-#else
- if(receive_idx == -1) {
- receive_idx = LPC_EMAC->RxConsumeIndex;
- } else {
- while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && ((uint32_t)receive_idx != LPC_EMAC->RxProduceIndex)) {
- receive_idx = rinc(receive_idx, NUM_RX_FRAG);
- }
- unsigned int info = rxstat[receive_idx].Info;
- int slen = (info & RINFO_SIZE) + 1;
-
- if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
- /* Invalid frame, ignore it and free buffer. */
- receive_idx = rinc(receive_idx, NUM_RX_FRAG);
- }
- receive_idx = rinc(receive_idx, NUM_RX_FRAG);
- receive_soff = 0;
-
- LPC_EMAC->RxConsumeIndex = receive_idx;
- }
-
- if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex) {
- receive_idx = -1;
- return 0;
- }
-
- return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
-#endif
-}
-
-// Read from an recevied ethernet packet.
-// After receive returnd a number bigger than 0 it is
-// possible to read bytes from this packet.
-// Read will write up to size bytes into data.
-// It is possible to use read multible times.
-// Each time read will start reading after the last read byte before.
-
-int ethernet_read(char *data, int dlen) {
-#if NEW_LOGIC
- // Check we have a valid buffer to read
- if(rx_consume_offset < 0) {
- return 0;
- }
-
- // Assume 1 fragment block
- uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
- int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
-
- int remaining = size - rx_consume_offset;
- int requested = dlen;
- int ncopy = min(remaining, requested);
-
- void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
- void *pdst = (void *)(data);
-
- if(data != NULL && ncopy > 0) {
- memcpy(pdst, psrc, ncopy);
- }
-
- rx_consume_offset += ncopy;
-
- return ncopy;
-#else
- int slen;
- int copy = 0;
- unsigned int more;
- unsigned int info;
- void *pdst, *psrc;
- int doff = 0;
-
- if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
- return 0;
- }
-
- do {
- info = rxstat[receive_idx].Info;
- more = !(info & RINFO_LAST_FLAG);
- slen = (info & RINFO_SIZE) + 1;
-
- if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
- /* Invalid frame, ignore it and free buffer. */
- receive_idx = rinc(receive_idx, NUM_RX_FRAG);
- } else {
-
- copy = min(slen - receive_soff, dlen - doff);
- psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
- pdst = (void *)(data + doff);
-
- if(data != NULL) {
- /* check if Buffer available */
- memcpy(pdst, psrc, copy);
- }
-
- receive_soff += copy;
- doff += copy;
-
- if((more && (receive_soff == slen))) {
- receive_idx = rinc(receive_idx, NUM_RX_FRAG);
- receive_soff = 0;
- }
- }
- } while(more && !(doff == dlen) && !receive_soff);
-
- return doff;
-#endif
-}
-
-int ethernet_link(void) {
-
- if (phy_id == DP83848C_ID) {
- return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
- }
- else { // LAN8720_ID
- return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
- }
-}
-
-static int phy_write(unsigned int PhyReg, unsigned short Data) {
- unsigned int timeOut;
-
- LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
- LPC_EMAC->MWTD = Data;
-
- for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) { /* Wait until operation completed */
- if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
- return 0;
- }
- }
-
- return -1;
-}
-
-
-static int phy_read(unsigned int PhyReg) {
- unsigned int timeOut;
-
- LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
- LPC_EMAC->MCMD = MCMD_READ;
-
- for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */
- if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
- LPC_EMAC->MCMD = 0;
- return LPC_EMAC->MRDD; /* Return a 16-bit value. */
- }
- }
-
- return -1;
-}
-
-
-static void txdscr_init() {
- int i;
-
- for(i = 0; i < NUM_TX_FRAG; i++) {
- txdesc[i].Packet = (uint32_t)&txbuf[i];
- txdesc[i].Ctrl = 0;
- txstat[i].Info = 0;
- }
-
- LPC_EMAC->TxDescriptor = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */
- LPC_EMAC->TxStatus = (uint32_t)txstat;
- LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
-
- LPC_EMAC->TxProduceIndex = 0; /* Tx Descriptors Point to 0 */
-}
-
-
-static void rxdscr_init() {
- int i;
-
- for(i = 0; i < NUM_RX_FRAG; i++) {
- rxdesc[i].Packet = (uint32_t)&rxbuf[i];
- rxdesc[i].Ctrl = RCTRL_INT | (ETH_FRAG_SIZE-1);
- rxstat[i].Info = 0;
- rxstat[i].HashCRC = 0;
- }
-
- LPC_EMAC->RxDescriptor = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */
- LPC_EMAC->RxStatus = (uint32_t)rxstat;
- LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
-
- LPC_EMAC->RxConsumeIndex = 0; /* Rx Descriptors Point to 0 */
-}
-
-void ethernet_address(char *mac) {
- mbed_mac_address(mac);
-}
-
-void ethernet_set_link(int speed, int duplex) {
- unsigned short phy_data;
- int tout;
-
- if((speed < 0) || (speed > 1)) {
- phy_data = PHY_AUTO_NEG;
- } else {
- phy_data = (((unsigned short) speed << 13) |
- ((unsigned short) duplex << 8));
- }
-
- phy_write(PHY_REG_BMCR, phy_data);
-
- for (tout = 100; tout; tout--) { __NOP(); } /* A short delay */
-
- switch(phy_id) {
- case DP83848C_ID:
- phy_data = phy_read(PHY_REG_STS);
-
- if(phy_data & PHY_STS_DUPLEX) {
- LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
- LPC_EMAC->Command |= CR_FULL_DUP;
- LPC_EMAC->IPGT = IPGT_FULL_DUP;
- } else {
- LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
- LPC_EMAC->Command &= ~CR_FULL_DUP;
- LPC_EMAC->IPGT = IPGT_HALF_DUP;
- }
-
- if(phy_data & PHY_STS_SPEED) {
- LPC_EMAC->SUPP &= ~SUPP_SPEED;
- } else {
- LPC_EMAC->SUPP |= SUPP_SPEED;
- }
- break;
-
- case LAN8720_ID:
- phy_data = phy_read(PHY_REG_SCSR);
-
- if (phy_data & PHY_SCSR_DUPLEX) {
- LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
- LPC_EMAC->Command |= CR_FULL_DUP;
- LPC_EMAC->IPGT = IPGT_FULL_DUP;
- } else {
- LPC_EMAC->Command &= ~CR_FULL_DUP;
- LPC_EMAC->IPGT = IPGT_HALF_DUP;
- }
-
- if(phy_data & PHY_SCSR_100MBIT) {
- LPC_EMAC->SUPP |= SUPP_SPEED;
- } else {
- LPC_EMAC->SUPP &= ~SUPP_SPEED;
- }
-
- break;
- }
-}
-
-/*
- * The Embedded Artists LPC4088 QuickStart Board has an eeprom with a unique
- * 48 bit ID. This ID is used as MAC address.
- */
-
-#include "i2c_api.h"
-
-static int _macRetrieved = 0;
-static char _macAddr[6] = {0x00,0x02,0xF7,0xF0,0x00,0x00};
-#define EEPROM_24AA02E48_ADDR (0xA0)
-
-void mbed_mac_address(char *mac) {
-
- if (_macRetrieved == 0) {
- char tmp[6];
- i2c_t i2cObj;
-
- i2c_init(&i2cObj, P0_27, P0_28);
-
- do {
- // the unique ID is at offset 0xFA
- tmp[0] = 0xFA;
- if (i2c_write(&i2cObj, EEPROM_24AA02E48_ADDR, tmp, 1, 1) != 1) {
- break; // failed to write
- }
-
-
- if (i2c_read(&i2cObj, EEPROM_24AA02E48_ADDR, tmp, 6, 1) != 6) {
- break; // failed to read
- }
-
- memcpy(_macAddr, tmp, 6);
-
- } while(0);
-
- // We always consider the MAC address to be retrieved even though
- // reading from the eeprom failed. If it wasn't possible to read
- // from eeprom the default address will be used.
- _macRetrieved = 1;
- }
-
- memcpy(mac, _macAddr, 6);
-}
--- a/targets/hal/TARGET_NXP/TARGET_LPC408X/i2c_api.c Mon Feb 02 16:00:07 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,416 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "mbed_assert.h"
-#include "i2c_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-
-static const PinMap PinMap_I2C_SDA[] = {
- {P0_0 , I2C_1, 3},
- {P0_10, I2C_2, 2},
- {P0_19, I2C_1, 3},
- {P0_27, I2C_0, 1},
- {P1_15, I2C_2, 3},
- {P1_30, I2C_0, 4},
- {P2_14, I2C_1, 2},
- {P2_30, I2C_2, 2},
- {P4_20, I2C_2, 4},
- {P5_2, I2C_0, 5},
- {NC , NC , 0}
-};
-
-static const PinMap PinMap_I2C_SCL[] = {
- {P0_1 , I2C_1, 3},
- {P0_11, I2C_2, 2},
- {P0_20, I2C_1, 3},
- {P0_28, I2C_0, 1},
- {P1_31, I2C_0, 4},
- {P2_15, I2C_1, 2},
- {P2_31, I2C_2, 2},
- {P4_21, I2C_2, 2},
- {P4_29, I2C_2, 4},
- {P5_3, I2C_0, 5},
- {NC , NC, 0}
-};
-
-#define I2C_CONSET(x) (x->i2c->CONSET)
-#define I2C_CONCLR(x) (x->i2c->CONCLR)
-#define I2C_STAT(x) (x->i2c->STAT)
-#define I2C_DAT(x) (x->i2c->DAT)
-#define I2C_SCLL(x, val) (x->i2c->SCLL = val)
-#define I2C_SCLH(x, val) (x->i2c->SCLH = val)
-
-static const uint32_t I2C_addr_offset[2][4] = {
- {0x0C, 0x20, 0x24, 0x28},
- {0x30, 0x34, 0x38, 0x3C}
-};
-
-static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
- I2C_CONCLR(obj) = (start << 5)
- | (stop << 4)
- | (interrupt << 3)
- | (acknowledge << 2);
-}
-
-static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
- I2C_CONSET(obj) = (start << 5)
- | (stop << 4)
- | (interrupt << 3)
- | (acknowledge << 2);
-}
-
-// Clear the Serial Interrupt (SI)
-static inline void i2c_clear_SI(i2c_t *obj) {
- i2c_conclr(obj, 0, 0, 1, 0);
-}
-
-static inline int i2c_status(i2c_t *obj) {
- return I2C_STAT(obj);
-}
-
-// Wait until the Serial Interrupt (SI) is set
-static int i2c_wait_SI(i2c_t *obj) {
- int timeout = 0;
- while (!(I2C_CONSET(obj) & (1 << 3))) {
- timeout++;
- if (timeout > 100000) return -1;
- }
- return 0;
-}
-
-static inline void i2c_interface_enable(i2c_t *obj) {
- I2C_CONSET(obj) = 0x40;
-}
-
-static inline void i2c_power_enable(i2c_t *obj) {
- switch ((int)obj->i2c) {
- case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
- case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
- case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
- }
-}
-
-void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
- // determine the SPI to use
- I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
- I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
- obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
- MBED_ASSERT((int)obj->i2c != NC);
-
- // enable power
- i2c_power_enable(obj);
-
- // set default frequency at 100k
- i2c_frequency(obj, 100000);
- i2c_conclr(obj, 1, 1, 1, 1);
- i2c_interface_enable(obj);
-
- pinmap_pinout(sda, PinMap_I2C_SDA);
- pinmap_pinout(scl, PinMap_I2C_SCL);
-
- // OpenDrain must explicitly be enabled for p0.0 and p0.1
- if (sda == P0_0) {
- pin_mode(sda, OpenDrain);
- }
- if (scl == P0_1) {
- pin_mode(scl, OpenDrain);
- }
-
-}
-
-inline int i2c_start(i2c_t *obj) {
- int status = 0;
- // 8.1 Before master mode can be entered, I2CON must be initialised to:
- // - I2EN STA STO SI AA - -
- // - 1 0 0 0 x - -
- // if AA = 0, it can't enter slave mode
- i2c_conclr(obj, 1, 1, 1, 1);
-
- // The master mode may now be entered by setting the STA bit
- // this will generate a start condition when the bus becomes free
- i2c_conset(obj, 1, 0, 0, 1);
-
- i2c_wait_SI(obj);
- status = i2c_status(obj);
-
- // Clear start bit now transmitted, and interrupt bit
- i2c_conclr(obj, 1, 0, 0, 0);
- return status;
-}
-
-inline int i2c_stop(i2c_t *obj) {
- int timeout = 0;
-
- // write the stop bit
- i2c_conset(obj, 0, 1, 0, 0);
- i2c_clear_SI(obj);
-
- // wait for STO bit to reset
- while(I2C_CONSET(obj) & (1 << 4)) {
- timeout ++;
- if (timeout > 100000) return 1;
- }
-
- return 0;
-}
-
-
-static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
- // write the data
- I2C_DAT(obj) = value;
-
- // clear SI to init a send
- i2c_clear_SI(obj);
-
- // wait and return status
- i2c_wait_SI(obj);
- return i2c_status(obj);
-}
-
-static inline int i2c_do_read(i2c_t *obj, int last) {
- // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
- if(last) {
- i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
- } else {
- i2c_conset(obj, 0, 0, 0, 1); // send a ACK
- }
-
- // accept byte
- i2c_clear_SI(obj);
-
- // wait for it to arrive
- i2c_wait_SI(obj);
-
- // return the data
- return (I2C_DAT(obj) & 0xFF);
-}
-
-void i2c_frequency(i2c_t *obj, int hz) {
- uint32_t PCLK = PeripheralClock;
- uint32_t pulse = PCLK / (hz * 2);
-
- // I2C Rate
- I2C_SCLL(obj, pulse);
- I2C_SCLH(obj, pulse);
-}
-
-// The I2C does a read or a write as a whole operation
-// There are two types of error conditions it can encounter
-// 1) it can not obtain the bus
-// 2) it gets error responses at part of the transmission
-//
-// We tackle them as follows:
-// 1) we retry until we get the bus. we could have a "timeout" if we can not get it
-// which basically turns it in to a 2)
-// 2) on error, we use the standard error mechanisms to report/debug
-//
-// Therefore an I2C transaction should always complete. If it doesn't it is usually
-// because something is setup wrong (e.g. wiring), and we don't need to programatically
-// check for that
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
- int count, status;
-
- status = i2c_start(obj);
-
- if ((status != 0x10) && (status != 0x08)) {
- i2c_stop(obj);
- return I2C_ERROR_BUS_BUSY;
- }
-
- status = i2c_do_write(obj, (address | 0x01), 1);
- if (status != 0x40) {
- i2c_stop(obj);
- return I2C_ERROR_NO_SLAVE;
- }
-
- // Read in all except last byte
- for (count = 0; count < (length - 1); count++) {
- int value = i2c_do_read(obj, 0);
- status = i2c_status(obj);
- if (status != 0x50) {
- i2c_stop(obj);
- return count;
- }
- data[count] = (char) value;
- }
-
- // read in last byte
- int value = i2c_do_read(obj, 1);
- status = i2c_status(obj);
- if (status != 0x58) {
- i2c_stop(obj);
- return length - 1;
- }
-
- data[count] = (char) value;
-
- // If not repeated start, send stop.
- if (stop) {
- i2c_stop(obj);
- }
-
- return length;
-}
-
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
- int i, status;
-
- status = i2c_start(obj);
-
- if ((status != 0x10) && (status != 0x08)) {
- i2c_stop(obj);
- return I2C_ERROR_BUS_BUSY;
- }
-
- status = i2c_do_write(obj, (address & 0xFE), 1);
- if (status != 0x18) {
- i2c_stop(obj);
- return I2C_ERROR_NO_SLAVE;
- }
-
- for (i=0; i<length; i++) {
- status = i2c_do_write(obj, data[i], 0);
- if (status != 0x28) {
- i2c_stop(obj);
- return i;
- }
- }
-
- // clearing the serial interrupt here might cause an unintended rewrite of the last byte
- // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
- // i2c_clear_SI(obj);
-
- // If not repeated start, send stop.
- if (stop) {
- i2c_stop(obj);
- }
-
- return length;
-}
-
-void i2c_reset(i2c_t *obj) {
- i2c_stop(obj);
-}
-
-int i2c_byte_read(i2c_t *obj, int last) {
- return (i2c_do_read(obj, last) & 0xFF);
-}
-
-int i2c_byte_write(i2c_t *obj, int data) {
- int ack;
- int status = i2c_do_write(obj, (data & 0xFF), 0);
-
- switch(status) {
- case 0x18: case 0x28: // Master transmit ACKs
- ack = 1;
- break;
-
- case 0x40: // Master receive address transmitted ACK
- ack = 1;
- break;
-
- case 0xB8: // Slave transmit ACK
- ack = 1;
- break;
-
- default:
- ack = 0;
- break;
- }
-
- return ack;
-}
-
-void i2c_slave_mode(i2c_t *obj, int enable_slave) {
- if (enable_slave != 0) {
- i2c_conclr(obj, 1, 1, 1, 0);
- i2c_conset(obj, 0, 0, 0, 1);
- } else {
- i2c_conclr(obj, 1, 1, 1, 1);
- }
-}
-
-int i2c_slave_receive(i2c_t *obj) {
- int status;
- int retval;
-
- status = i2c_status(obj);
- switch(status) {
- case 0x60: retval = 3; break;
- case 0x70: retval = 2; break;
- case 0xA8: retval = 1; break;
- default : retval = 0; break;
- }
-
- return(retval);
-}
-
-int i2c_slave_read(i2c_t *obj, char *data, int length) {
- int count = 0;
- int status;
-
- do {
- i2c_clear_SI(obj);
- i2c_wait_SI(obj);
- status = i2c_status(obj);
- if((status == 0x80) || (status == 0x90)) {
- data[count] = I2C_DAT(obj) & 0xFF;
- }
- count++;
- } while (((status == 0x80) || (status == 0x90) ||
- (status == 0x060) || (status == 0x70)) && (count < length));
-
- if(status != 0xA0) {
- i2c_stop(obj);
- }
-
- i2c_clear_SI(obj);
-
- return count;
-}
-
-int i2c_slave_write(i2c_t *obj, const char *data, int length) {
- int count = 0;
- int status;
-
- if(length <= 0) {
- return(0);
- }
-
- do {
- status = i2c_do_write(obj, data[count], 0);
- count++;
- } while ((count < length) && (status == 0xB8));
-
- if((status != 0xC0) && (status != 0xC8)) {
- i2c_stop(obj);
- }
-
- i2c_clear_SI(obj);
-
- return(count);
-}
-
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
- uint32_t addr;
-
- if ((idx >= 0) && (idx <= 3)) {
- addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
- *((uint32_t *) addr) = address & 0xFF;
- addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
- *((uint32_t *) addr) = mask & 0xFE;
- }
-}
--- a/targets/hal/TARGET_NXP/TARGET_LPC408X/pwmout_api.c Mon Feb 02 16:00:07 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,189 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "mbed_assert.h"
-#include "pwmout_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-
-#define TCR_CNT_EN 0x00000001
-#define TCR_RESET 0x00000002
-
-// PORT ID, PWM ID, Pin function
-static const PinMap PinMap_PWM[] = {
- {P1_2, PWM0_1, 3},
- {P1_3, PWM0_2, 3},
- {P1_5, PWM0_3, 3},
- {P1_6, PWM0_4, 3},
- {P1_7, PWM0_5, 3},
- {P1_11, PWM0_6, 3},
- {P1_18, PWM1_1, 2},
- {P1_20, PWM1_2, 2},
- {P1_21, PWM1_3, 2},
- {P1_23, PWM1_4, 2},
- {P1_24, PWM1_5, 2},
- {P1_26, PWM1_6, 2},
- {P2_0, PWM1_1, 1},
- {P2_1, PWM1_2, 1},
- {P2_2, PWM1_3, 1},
- {P2_3, PWM1_4, 1},
- {P2_4, PWM1_5, 1},
- {P2_5, PWM1_6, 1},
- {P3_16, PWM0_1, 2},
- {P3_17, PWM0_2, 2},
- {P3_18, PWM0_3, 2},
- {P3_19, PWM0_4, 2},
- {P3_20, PWM0_5, 2},
- {P3_21, PWM0_6, 2},
- {P3_24, PWM1_1, 2},
- {P3_25, PWM1_2, 2},
- {P3_26, PWM1_3, 2},
- {P3_27, PWM1_4, 2},
- {P3_28, PWM1_5, 2},
- {P3_29, PWM1_6, 2},
- {NC, NC, 0}
-};
-
-static const uint32_t PWM_mr_offset[7] = {
- 0x18, 0x1C, 0x20, 0x24, 0x40, 0x44, 0x48
-};
-
-#define TCR_PWM_EN 0x00000008
-static unsigned int pwm_clock_mhz;
-
-void pwmout_init(pwmout_t* obj, PinName pin) {
- // determine the channel
- PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
- MBED_ASSERT(pwm != (PWMName)NC);
-
- obj->channel = pwm;
- obj->pwm = LPC_PWM0;
-
- if (obj->channel > 6) { // PWM1 is used if pwm > 6
- obj->channel -= 6;
- obj->pwm = LPC_PWM1;
- }
-
- obj->MR = (__IO uint32_t *)((uint32_t)obj->pwm + PWM_mr_offset[obj->channel]);
-
- // ensure the power is on
- if (obj->pwm == LPC_PWM0) {
- LPC_SC->PCONP |= 1 << 5;
- } else {
- LPC_SC->PCONP |= 1 << 6;
- }
-
- obj->pwm->PR = 0; // no pre-scale
-
- // ensure single PWM mode
- obj->pwm->MCR = 1 << 1; // reset TC on match 0
-
- // enable the specific PWM output
- obj->pwm->PCR |= 1 << (8 + obj->channel);
-
- pwm_clock_mhz = PeripheralClock / 1000000;
-
- // default to 20ms: standard for servos, and fine for e.g. brightness control
- pwmout_period_ms(obj, 20);
- pwmout_write (obj, 0);
-
- // Wire pinout
- pinmap_pinout(pin, PinMap_PWM);
-}
-
-void pwmout_free(pwmout_t* obj) {
- // [TODO]
-}
-
-void pwmout_write(pwmout_t* obj, float value) {
- if (value < 0.0f) {
- value = 0.0;
- } else if (value > 1.0f) {
- value = 1.0;
- }
-
- // set channel match to percentage
- uint32_t v = (uint32_t)((float)(obj->pwm->MR0) * value);
-
- // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
- if (v == obj->pwm->MR0) {
- v++;
- }
-
- *obj->MR = v;
-
- // accept on next period start
- obj->pwm->LER |= 1 << obj->channel;
-}
-
-float pwmout_read(pwmout_t* obj) {
- float v = (float)(*obj->MR) / (float)(obj->pwm->MR0);
- return (v > 1.0f) ? (1.0f) : (v);
-}
-
-void pwmout_period(pwmout_t* obj, float seconds) {
- pwmout_period_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_period_ms(pwmout_t* obj, int ms) {
- pwmout_period_us(obj, ms * 1000);
-}
-
-// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
- // calculate number of ticks
- uint32_t ticks = pwm_clock_mhz * us;
-
- // set reset
- obj->pwm->TCR = TCR_RESET;
-
- // set the global match register
- obj->pwm->MR0 = ticks;
-
- // Scale the pulse width to preserve the duty ratio
- if (obj->pwm->MR0 > 0) {
- *obj->MR = (*obj->MR * ticks) / obj->pwm->MR0;
- }
-
- // set the channel latch to update value at next period start
- obj->pwm->LER |= 1 << 0;
-
- // enable counter and pwm, clear reset
- obj->pwm->TCR = TCR_CNT_EN | TCR_PWM_EN;
-}
-
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
- pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
- pwmout_pulsewidth_us(obj, ms * 1000);
-}
-
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
- // calculate number of ticks
- uint32_t v = pwm_clock_mhz * us;
-
- // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
- if (v == obj->pwm->MR0) {
- v++;
- }
-
- // set the match register value
- *obj->MR = v;
-
- // set the channel latch to update value at next period start
- obj->pwm->LER |= 1 << obj->channel;
-}
--- a/targets/hal/TARGET_NXP/TARGET_LPC408X/rtc_api.c Mon Feb 02 16:00:07 2015 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC408X/rtc_api.c Tue Feb 03 13:15:07 2015 +0000
@@ -28,7 +28,6 @@
* Clock Control Register
* RTC_CCR[0] : Enable - 0 = Disabled, 1 = Enabled
* RTC_CCR[1] : Reset - 0 = Normal, 1 = Reset
- * RTC_CCR[4] : Clock Source - 0 = Prescaler, 1 = 32k Xtal
*
* The RTC may already be running, so we should set it up
* without impacting if it is the case
@@ -37,7 +36,6 @@
LPC_SC->PCONP |= 0x200; // Ensure power is on
LPC_RTC->CCR = 0x00;
-// clock source on 2368 is special test mode on 1768!
LPC_RTC->CCR |= 1 << 0; // Ensure the RTC is enabled
}
--- a/targets/hal/TARGET_NXP/TARGET_LPC408X/serial_api.c Mon Feb 02 16:00:07 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,330 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// math.h required for floating point operations for baud rate calculation
-#include <math.h>
-#include <string.h>
-#include <stdlib.h>
-
-#include "serial_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-/******************************************************************************
- * INITIALIZATION
- ******************************************************************************/
-static const PinMap PinMap_UART_TX[] = {
- {P0_0, UART_3, 2},
- {P0_2, UART_0, 1},
- {P0_10, UART_2, 1},
- {P0_15, UART_1, 1},
- {P1_29, UART_4, 5},
- {P0_25, UART_3, 3},
- {P2_0 , UART_1, 2},
- {P2_8 , UART_2, 2},
- {P3_16, UART_1, 3},
- {P4_22, UART_2, 2},
- {P4_28, UART_3, 2},
- {P5_4, UART_4, 4},
- {NC , NC , 0}
-};
-
-static const PinMap PinMap_UART_RX[] = {
- {P0_1 , UART_3, 2},
- {P0_3 , UART_0, 1},
- {P0_11, UART_2, 1},
- {P0_16, UART_1, 1},
- {P0_26, UART_3, 3},
- {P2_1 , UART_1, 2},
- {P2_9 , UART_2, 2},
- {P3_17, UART_1, 3},
- {P4_23, UART_2, 2},
- {P4_29, UART_3, 2},
- {P5_3, UART_4, 4},
- {NC , NC , 0}
-};
-
-#define UART_NUM 5
-
-static uint32_t serial_irq_ids[UART_NUM] = {0};
-static uart_irq_handler irq_handler;
-
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
- int is_stdio_uart = 0;
-
- // determine the UART to use
- UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
- UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
- UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
- MBED_ASSERT((int)uart != NC);
-
- obj->uart = (LPC_UART_TypeDef *)uart;
- // enable power
- switch (uart) {
- case UART_0: LPC_SC->PCONP |= 1 << 3; break;
- case UART_1: LPC_SC->PCONP |= 1 << 4; break;
- case UART_2: LPC_SC->PCONP |= 1 << 24; break;
- case UART_3: LPC_SC->PCONP |= 1 << 25; break;
- case UART_4: LPC_SC->PCONP |= 1 << 8; break;
- }
-
- // enable fifos and default rx trigger level
- obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
- | 0 << 1 // Rx Fifo Reset
- | 0 << 2 // Tx Fifo Reset
- | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
-
- // disable irqs
- obj->uart->IER = 0 << 0 // Rx Data available irq enable
- | 0 << 1 // Tx Fifo empty irq enable
- | 0 << 2; // Rx Line Status irq enable
-
- // set default baud rate and format
- serial_baud (obj, 9600);
- serial_format(obj, 8, ParityNone, 1);
-
- // pinout the chosen uart
- pinmap_pinout(tx, PinMap_UART_TX);
- pinmap_pinout(rx, PinMap_UART_RX);
-
- // set rx/tx pins in PullUp mode
- if (tx != NC) {
- pin_mode(tx, PullUp);
- }
- if (rx != NC) {
- pin_mode(rx, PullUp);
- }
-
- switch (uart) {
- case UART_0: obj->index = 0; break;
- case UART_1: obj->index = 1; break;
- case UART_2: obj->index = 2; break;
- case UART_3: obj->index = 3; break;
- case UART_4: obj->index = 4; break;
- }
-
- is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
-
- if (is_stdio_uart) {
- stdio_uart_inited = 1;
- memcpy(&stdio_uart, obj, sizeof(serial_t));
- }
-}
-
-void serial_free(serial_t *obj) {
- serial_irq_ids[obj->index] = 0;
-}
-
-// serial_baud
-// set the baud rate, taking in to account the current SystemFrequency
-void serial_baud(serial_t *obj, int baudrate) {
- uint32_t PCLK = PeripheralClock;
-
- // First we check to see if the basic divide with no DivAddVal/MulVal
- // ratio gives us an integer result. If it does, we set DivAddVal = 0,
- // MulVal = 1. Otherwise, we search the valid ratio value range to find
- // the closest match. This could be more elegant, using search methods
- // and/or lookup tables, but the brute force method is not that much
- // slower, and is more maintainable.
- uint16_t DL = PCLK / (16 * baudrate);
-
- uint8_t DivAddVal = 0;
- uint8_t MulVal = 1;
- int hit = 0;
- uint16_t dlv;
- uint8_t mv, dav;
- if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder
- int err_best = baudrate, b;
- for (mv = 1; mv < 16 && !hit; mv++)
- {
- for (dav = 0; dav < mv; dav++)
- {
- // baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul))
- // solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul))
- // mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding
- // for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision
- // note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding
-
- if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom
- dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2;
- else // 2 bits headroom, use more precision
- dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2;
-
- // datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood
- if (dlv == 0)
- dlv = 1;
-
- // datasheet says if dav > 0 then DL must be >= 2
- if ((dav > 0) && (dlv < 2))
- dlv = 2;
-
- // integer rearrangement of the baudrate equation (with rounding)
- b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2;
-
- // check to see how we went
- b = abs(b - baudrate);
- if (b < err_best)
- {
- err_best = b;
-
- DL = dlv;
- MulVal = mv;
- DivAddVal = dav;
-
- if (b == baudrate)
- {
- hit = 1;
- break;
- }
- }
- }
- }
- }
-
- // set LCR[DLAB] to enable writing to divider registers
- obj->uart->LCR |= (1 << 7);
-
- // set divider values
- obj->uart->DLM = (DL >> 8) & 0xFF;
- obj->uart->DLL = (DL >> 0) & 0xFF;
- obj->uart->FDR = (uint32_t) DivAddVal << 0
- | (uint32_t) MulVal << 4;
-
- // clear LCR[DLAB]
- obj->uart->LCR &= ~(1 << 7);
-}
-
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
- MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
- MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
- MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
- (parity == ParityForced1) || (parity == ParityForced0));
-
- stop_bits -= 1;
- data_bits -= 5;
-
- int parity_enable, parity_select;
- switch (parity) {
- case ParityNone: parity_enable = 0; parity_select = 0; break;
- case ParityOdd : parity_enable = 1; parity_select = 0; break;
- case ParityEven: parity_enable = 1; parity_select = 1; break;
- case ParityForced1: parity_enable = 1; parity_select = 2; break;
- case ParityForced0: parity_enable = 1; parity_select = 3; break;
- default:
- break;
- }
-
- obj->uart->LCR = data_bits << 0
- | stop_bits << 2
- | parity_enable << 3
- | parity_select << 4;
-}
-
-/******************************************************************************
- * INTERRUPTS HANDLING
- ******************************************************************************/
-static inline void uart_irq(uint32_t iir, uint32_t index) {
- // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
- SerialIrq irq_type;
- switch (iir) {
- case 1: irq_type = TxIrq; break;
- case 2: irq_type = RxIrq; break;
- default: return;
- }
-
- if (serial_irq_ids[index] != 0)
- irq_handler(serial_irq_ids[index], irq_type);
-}
-
-void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0);}
-void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1);}
-void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2);}
-void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3);}
-void uart4_irq() {uart_irq((LPC_UART4->IIR >> 1) & 0x7, 4);}
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
- irq_handler = handler;
- serial_irq_ids[obj->index] = id;
-}
-
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
- IRQn_Type irq_n = (IRQn_Type)0;
- uint32_t vector = 0;
- switch ((int)obj->uart) {
- case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
- case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
- case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
- case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break;
- case UART_4: irq_n=UART4_IRQn; vector = (uint32_t)&uart4_irq; break;
- }
-
- if (enable) {
- obj->uart->IER |= 1 << irq;
- NVIC_SetVector(irq_n, vector);
- NVIC_EnableIRQ(irq_n);
- } else { // disable
- int all_disabled = 0;
- SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
- obj->uart->IER &= ~(1 << irq);
- all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
- if (all_disabled)
- NVIC_DisableIRQ(irq_n);
- }
-}
-
-/******************************************************************************
- * READ/WRITE
- ******************************************************************************/
-int serial_getc(serial_t *obj) {
- while (!serial_readable(obj));
- return obj->uart->RBR;
-}
-
-void serial_putc(serial_t *obj, int c) {
- while (!serial_writable(obj));
- obj->uart->THR = c;
-}
-
-int serial_readable(serial_t *obj) {
- return obj->uart->LSR & 0x01;
-}
-
-int serial_writable(serial_t *obj) {
- return obj->uart->LSR & 0x20;
-}
-
-void serial_clear(serial_t *obj) {
- obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
- | 1 << 1 // rx FIFO reset
- | 1 << 2 // tx FIFO reset
- | 0 << 6; // interrupt depth
-}
-
-void serial_pinout_tx(PinName tx) {
- pinmap_pinout(tx, PinMap_UART_TX);
-}
-
-void serial_break_set(serial_t *obj) {
- obj->uart->LCR |= (1 << 6);
-}
-
-void serial_break_clear(serial_t *obj) {
- obj->uart->LCR &= ~(1 << 6);
-}
-
--- a/targets/hal/TARGET_NXP/TARGET_LPC408X/spi_api.c Mon Feb 02 16:00:07 2015 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,226 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <math.h>
-
-#include "spi_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-static const PinMap PinMap_SPI_SCLK[] = {
- {P0_7 , SPI_1, 2},
- {P0_15, SPI_0, 2},
- {P1_0, SPI_2, 4},
- {P1_19, SPI_1, 5},
- {P1_20, SPI_0, 5},
- {P1_31, SPI_1, 2},
- {P2_22, SPI_0, 2},
- {P4_20, SPI_1, 3},
- {P5_2, SPI_2, 2},
- {NC , NC , 0}
-};
-
-static const PinMap PinMap_SPI_MOSI[] = {
- {P0_9 , SPI_1, 2},
- {P0_13, SPI_1, 2},
- {P0_18, SPI_0, 2},
- {P1_1, SPI_2, 4},
- {P1_22, SPI_1, 5},
- {P1_24, SPI_0, 5},
- {P2_27, SPI_0, 2},
- {P4_23, SPI_1, 3},
- {P5_0, SPI_2, 2},
- {NC , NC , 0}
-};
-
-static const PinMap PinMap_SPI_MISO[] = {
- {P0_8 , SPI_1, 2},
- {P0_12, SPI_1, 2},
- {P0_17, SPI_0, 2},
- {P1_4, SPI_2, 4},
- {P1_18, SPI_1, 5},
- {P1_23, SPI_0, 5},
- {P2_26, SPI_0, 2},
- {P4_22, SPI_1, 3},
- {P5_1, SPI_2, 2},
- {NC , NC , 0}
-};
-
-static const PinMap PinMap_SPI_SSEL[] = {
- {P0_6 , SPI_1, 2},
- {P0_14, SPI_1, 2},
- {P0_16, SPI_0, 2},
- {P1_8, SPI_2, 4},
- {P1_21, SPI_0, 3},
- {P1_26, SPI_1, 5},
- {P1_28, SPI_0, 5},
- {P2_23, SPI_0, 2},
- {P4_21, SPI_1, 3},
- {NC , NC , 0}
-};
-
-static inline int ssp_disable(spi_t *obj);
-static inline int ssp_enable(spi_t *obj);
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
- // determine the SPI to use
- SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
- SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
- SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
- SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
- SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
- SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
- obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
- MBED_ASSERT((int)obj->spi != NC);
-
- // enable power and clocking
- switch ((int)obj->spi) {
- case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
- case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
- case SPI_2: LPC_SC->PCONP |= 1 << 20; break;
- }
-
- // set default format and frequency
- if (ssel == NC) {
- spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
- } else {
- spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
- }
- spi_frequency(obj, 1000000);
-
- // enable the ssp channel
- ssp_enable(obj);
-
- // pin out the spi pins
- pinmap_pinout(mosi, PinMap_SPI_MOSI);
- pinmap_pinout(miso, PinMap_SPI_MISO);
- pinmap_pinout(sclk, PinMap_SPI_SCLK);
- if (ssel != NC) {
- pinmap_pinout(ssel, PinMap_SPI_SSEL);
- }
-}
-
-void spi_free(spi_t *obj) {}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
- MBED_ASSERT(((bits >= 4) && (bits <= 16)) && ((mode >= 0) && (mode <= 3)));
- ssp_disable(obj);
-
- int polarity = (mode & 0x2) ? 1 : 0;
- int phase = (mode & 0x1) ? 1 : 0;
-
- // set it up
- int DSS = bits - 1; // DSS (data select size)
- int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
- int SPH = (phase) ? 1 : 0; // SPH - clock out phase
-
- int FRF = 0; // FRF (frame format) = SPI
- uint32_t tmp = obj->spi->CR0;
- tmp &= ~(0xFFFF);
- tmp |= DSS << 0
- | FRF << 4
- | SPO << 6
- | SPH << 7;
- obj->spi->CR0 = tmp;
-
- tmp = obj->spi->CR1;
- tmp &= ~(0xD);
- tmp |= 0 << 0 // LBM - loop back mode - off
- | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
- | 0 << 3; // SOD - slave output disable - na
- obj->spi->CR1 = tmp;
- ssp_enable(obj);
-}
-
-void spi_frequency(spi_t *obj, int hz) {
- ssp_disable(obj);
-
- uint32_t PCLK = PeripheralClock;
-
- int prescaler;
-
- for (prescaler = 2; prescaler <= 254; prescaler += 2) {
- int prescale_hz = PCLK / prescaler;
-
- // calculate the divider
- int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
-
- // check we can support the divider
- if (divider < 256) {
- // prescaler
- obj->spi->CPSR = prescaler;
-
- // divider
- obj->spi->CR0 &= ~(0xFFFF << 8);
- obj->spi->CR0 |= (divider - 1) << 8;
- ssp_enable(obj);
- return;
- }
- }
- error("Couldn't setup requested SPI frequency");
-}
-
-static inline int ssp_disable(spi_t *obj) {
- return obj->spi->CR1 &= ~(1 << 1);
-}
-
-static inline int ssp_enable(spi_t *obj) {
- return obj->spi->CR1 |= (1 << 1);
-}
-
-static inline int ssp_readable(spi_t *obj) {
- return obj->spi->SR & (1 << 2);
-}
-
-static inline int ssp_writeable(spi_t *obj) {
- return obj->spi->SR & (1 << 1);
-}
-
-static inline void ssp_write(spi_t *obj, int value) {
- while (!ssp_writeable(obj));
- obj->spi->DR = value;
-}
-
-static inline int ssp_read(spi_t *obj) {
- while (!ssp_readable(obj));
- return obj->spi->DR;
-}
-
-static inline int ssp_busy(spi_t *obj) {
- return (obj->spi->SR & (1 << 4)) ? (1) : (0);
-}
-
-int spi_master_write(spi_t *obj, int value) {
- ssp_write(obj, value);
- return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj) {
- return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
-}
-
-int spi_slave_read(spi_t *obj) {
- return obj->spi->DR;
-}
-
-void spi_slave_write(spi_t *obj, int value) {
- while (ssp_writeable(obj) == 0) ;
- obj->spi->DR = value;
-}
-
-int spi_busy(spi_t *obj) {
- return ssp_busy(obj);
-}