Maxim Integrated
MAX77655 Low IQ SIMO PMIC with 4-Outputs Delivering up to 700mA Total Output Current Mbed Driver
Revision 0:08f763822dd3, committed 21 months ago
- Comitter:
- Okan Sahin
- Date:
- Tue Aug 23 18:11:21 2022 +0300
- Commit message:
- Initial Commit
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MAX77655.cpp Tue Aug 23 18:11:21 2022 +0300
@@ -0,0 +1,668 @@
+/*******************************************************************************
+ * Copyright(C) Analog Devices Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Analog Devices Inc.
+ * shall not be used except as stated in the Analog Devices Inc.
+ * Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Analog Devices Inc.retains all ownership rights.
+ *******************************************************************************
+ */
+
+#include <Thread.h>
+#include "MAX77655.h"
+#include <math.h>
+
+#define POST_INTR_WORK_SIGNAL_ID 0x1
+#define TO_UINT8 0xFF
+#define TO_UINT16 0xFFFF
+
+MAX77655::MAX77655(I2C *i2c, PinName IRQPin):interrupt_handler_list{NULL}
+{
+ if (i2c == NULL)
+ return;
+
+ i2c_handler = i2c;
+
+ if (IRQPin != NC) {
+ irq_disable_all();
+ post_intr_work_thread = new Thread();
+ post_intr_work_thread->start(Callback<void()>(this, &MAX77655::post_interrupt_work));
+
+ this->irq_pin = new InterruptIn(IRQPin);
+ this->irq_pin->fall(Callback<void()>(this, &MAX77655::interrupt_handler));
+ this->irq_pin->enable_irq();
+ } else {
+ this->irq_pin = NULL;
+ }
+}
+
+MAX77655::~MAX77655()
+{
+ if (post_intr_work_thread)
+ delete post_intr_work_thread;
+
+ if (irq_pin)
+ delete irq_pin;
+}
+
+int MAX77655::read_register(uint8_t reg, uint8_t *value)
+{
+ int rtn_val;
+
+ if (value == NULL)
+ return MAX77655_VALUE_NULL;
+
+ rtn_val = i2c_handler->write(MAX77655_I2C_ADDRESS, (const char *)®, 1, true);
+ if (rtn_val != 0)
+ return MAX77655_WRITE_DATA_FAILED;
+
+ rtn_val = i2c_handler->read(MAX77655_I2C_ADDRESS, (char *) value, 1, false);
+ if (rtn_val < 0)
+ return MAX77655_READ_DATA_FAILED;
+
+ return MAX77655_NO_ERROR;
+}
+
+int MAX77655::write_register(uint8_t reg, const uint8_t *value)
+{
+ int rtn_val;
+ unsigned char local_data[2];
+
+ if (value == NULL)
+ return MAX77655_VALUE_NULL;
+
+ local_data[0] = reg;
+
+ memcpy(&local_data[1], value, 1);
+
+ rtn_val = i2c_handler->write(MAX77655_I2C_ADDRESS, (const char *)local_data, sizeof(local_data));
+ if (rtn_val != MAX77655_NO_ERROR)
+ return MAX77655_WRITE_DATA_FAILED;
+
+ return MAX77655_NO_ERROR;
+}
+
+#define SET_BIT_FIELD(address, reg_name, bit_field_name, value) \
+ int ret_val; \
+ ret_val = read_register(address, (uint8_t *)&(reg_name)); \
+ if (ret_val) { \
+ return ret_val; \
+ } \
+ bit_field_name = value; \
+ ret_val = write_register(address, (uint8_t *)&(reg_name)); \
+ if (ret_val) { \
+ return ret_val; \
+ }
+
+int MAX77655::set_cnfg_glbl_a(reg_bit_cnfg_glbl_a_t bit_field, uint8_t config)
+{
+ int ret;
+ reg_cnfg_glbl_a_t reg_cnfg_glbl_a;
+
+ ret = read_register(CNFG_GLBL_A, (uint8_t *)&(reg_cnfg_glbl_a));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case CNFG_GLBL_A_DBEN_nEN:
+ reg_cnfg_glbl_a.bits.dben_nen = config;
+ break;
+ case CNFG_GLBL_A_nEN_MODE:
+ reg_cnfg_glbl_a.bits.nen_mode = config;
+ break;
+ case CNFG_GLBL_A_MRT:
+ reg_cnfg_glbl_a.bits.mrt = config;
+ break;
+ case CNFG_GLBL_A_BIAS_LPM:
+ reg_cnfg_glbl_a.bits.bias_lpm = config;
+ break;
+ case CNFG_GLBL_A_PU_DIS:
+ reg_cnfg_glbl_a.bits.pu_dis = config;
+ break;
+ default:
+ return MAX77655_INVALID_DATA;
+ break;
+ }
+
+ return write_register(CNFG_GLBL_A, (uint8_t *)&(reg_cnfg_glbl_a));
+}
+
+int MAX77655::get_cnfg_glbl_a(reg_bit_cnfg_glbl_a_t bit_field, uint8_t *config)
+{
+ int ret;
+ reg_cnfg_glbl_a_t reg_cnfg_glbl_a = {0};
+
+ ret = read_register(CNFG_GLBL_A, (uint8_t *)&(reg_cnfg_glbl_a));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case CNFG_GLBL_A_DBEN_nEN:
+ *config = (uint8_t)reg_cnfg_glbl_a.bits.dben_nen;
+ break;
+ case CNFG_GLBL_A_nEN_MODE:
+ *config = (uint8_t)reg_cnfg_glbl_a.bits.nen_mode;
+ break;
+ case CNFG_GLBL_A_MRT:
+ *config = (uint8_t)reg_cnfg_glbl_a.bits.mrt;
+ break;
+ case CNFG_GLBL_A_BIAS_LPM:
+ *config = (uint8_t)reg_cnfg_glbl_a.bits.bias_lpm;
+ break;
+ case CNFG_GLBL_A_PU_DIS:
+ *config = (uint8_t)reg_cnfg_glbl_a.bits.pu_dis;
+ break;
+ default:
+ return MAX77655_INVALID_DATA;
+ break;
+ }
+
+ return MAX77655_NO_ERROR;
+}
+
+int MAX77655::set_sft_ctrl(decode_sft_ctrl_t config)
+{
+ reg_cnfg_glbl_b_t reg_cnfg_glbl_b;
+
+ SET_BIT_FIELD(CNFG_GLBL_B, reg_cnfg_glbl_b, reg_cnfg_glbl_b.bits.sft_ctrl, config);
+
+ return MAX77655_NO_ERROR;
+}
+
+int MAX77655::get_sft_ctrl(decode_sft_ctrl_t *config)
+{
+ int ret;
+ reg_cnfg_glbl_b_t reg_cnfg_glbl_b = {0};
+
+ ret = read_register(CNFG_GLBL_B, (uint8_t *)&(reg_cnfg_glbl_b));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ *config = (decode_sft_ctrl_t)reg_cnfg_glbl_b.bits.sft_ctrl;
+
+ return MAX77655_NO_ERROR;
+}
+
+int MAX77655::set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit)
+{
+ int ret;
+ uint8_t reg_addr;
+ reg_intm_glbl_t reg_intm_glbl;
+
+ ret = read_register(INTM_GLBL, (uint8_t *)&(reg_intm_glbl));
+
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case INTM_GLBL_nEN_FM:
+ reg_intm_glbl.bits.nen_fm = maskBit;
+ break;
+ case INTM_GLBL_nEN_RM:
+ reg_intm_glbl.bits.nen_rm = maskBit;
+ break;
+ case INTM_GLBL_TJAL1_RM:
+ reg_intm_glbl.bits.tjal1_rm = maskBit;
+ break;
+ case INTM_GLBL_TJAL2_RM:
+ reg_intm_glbl.bits.tjal2_rm = maskBit;
+ break;
+ case INTM_GLBL_SBB0_FM:
+ reg_intm_glbl.bits.sbb0_fm = maskBit;
+ break;
+ case INTM_GLBL_SBB1_FM:
+ reg_intm_glbl.bits.sbb1_fm = maskBit;
+ break;
+ case INTM_GLBL_SBB2_FM:
+ reg_intm_glbl.bits.sbb2_fm = maskBit;
+ break;
+ case INTM_GLBL_SBB3_FM:
+ reg_intm_glbl.bits.sbb3_fm = maskBit;
+ break;
+ default:
+ return MAX77655_INVALID_DATA;
+ break;
+ }
+
+ return write_register(INTM_GLBL, (uint8_t *)&(reg_intm_glbl));
+}
+
+int MAX77655::get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit)
+{
+ int ret;
+ uint8_t reg_addr;
+ reg_intm_glbl_t reg_intm_glbl = {0};
+
+ ret = read_register(INTM_GLBL, (uint8_t *)&(reg_intm_glbl));
+
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case INTM_GLBL_nEN_FM:
+ *maskBit = (uint8_t)reg_intm_glbl.bits.nen_fm;
+ break;
+ case INTM_GLBL_nEN_RM:
+ *maskBit = (uint8_t)reg_intm_glbl.bits.nen_rm;
+ break;
+ case INTM_GLBL_TJAL1_RM:
+ *maskBit = (uint8_t)reg_intm_glbl.bits.tjal1_rm;
+ break;
+ case INTM_GLBL_TJAL2_RM:
+ *maskBit = (uint8_t)reg_intm_glbl.bits.tjal2_rm;
+ break;
+ case INTM_GLBL_SBB0_FM:
+ *maskBit = (uint8_t)reg_intm_glbl.bits.sbb0_fm;
+ break;
+ case INTM_GLBL_SBB1_FM:
+ *maskBit = (uint8_t)reg_intm_glbl.bits.sbb1_fm;
+ break;
+ case INTM_GLBL_SBB2_FM:
+ *maskBit = (uint8_t)reg_intm_glbl.bits.sbb2_fm;
+ break;
+ case INTM_GLBL_SBB3_FM:
+ *maskBit = (uint8_t)reg_intm_glbl.bits.sbb3_fm;
+ break;
+ default:
+ return MAX77655_INVALID_DATA;
+ break;
+ }
+
+ return MAX77655_NO_ERROR;
+}
+
+int MAX77655::get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status)
+{
+ int ret;
+ reg_stat_glbl_t reg_stat_glbl = {0};
+
+ ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case STAT_GLBL_STAT_EN:
+ *status = (uint8_t)reg_stat_glbl.bits.stat_en;
+ break;
+ case STAT_GLBL_TJAL1_S:
+ *status = (uint8_t)reg_stat_glbl.bits.tjal1_s;
+ break;
+ case STAT_GLBL_TJAL2_S:
+ *status = (uint8_t)reg_stat_glbl.bits.tjal2_s;
+ break;
+ case STAT_GLBL_SBB0_S:
+ *status = (uint8_t)reg_stat_glbl.bits.sbb0_s;
+ break;
+ case STAT_GLBL_SBB1_S:
+ *status = (uint8_t)reg_stat_glbl.bits.sbb1_s;
+ break;
+ case STAT_GLBL_SBB2_S:
+ *status = (uint8_t)reg_stat_glbl.bits.sbb2_s;
+ break;
+ case STAT_GLBL_SBB3_S:
+ *status = (uint8_t)reg_stat_glbl.bits.sbb3_s;
+ break;
+ default:
+ ret = MAX77655_INVALID_DATA;
+ break;
+ }
+
+ return ret;
+}
+
+int MAX77655::get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag)
+{
+ int ret;
+ reg_ercflag_t reg_ercflag = {0};
+
+ ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ switch (bit_field)
+ {
+ case ERCFLAG_TOVLD:
+ *flag = (uint8_t)reg_ercflag.bits.tovld;
+ break;
+ case ERCFLAG_OVLO:
+ *flag = (uint8_t)reg_ercflag.bits.ovlo;
+ break;
+ case ERCFLAG_UVLO:
+ *flag = (uint8_t)reg_ercflag.bits.uvlo;
+ break;
+ case ERCFLAG_MRST:
+ *flag = (uint8_t)reg_ercflag.bits.mrst;
+ break;
+ case ERCFLAG_SFT_OFF_F:
+ *flag = (uint8_t)reg_ercflag.bits.sft_off_f;
+ break;
+ case ERCFLAG_SFT_CRST_F:
+ *flag = (uint8_t)reg_ercflag.bits.sft_crst_f;
+ break;
+ default:
+ ret = MAX77655_INVALID_DATA;
+ break;
+ }
+
+ return ret;
+}
+
+int MAX77655::get_cid(void) {
+ char rbuf[1] = {0};
+ int ret;
+
+ ret = read_register(CID, (uint8_t *)&(rbuf));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ return *rbuf;
+}
+
+int MAX77655::set_drv_sbb(decode_drv_sbb_t config)
+{
+ reg_config_sbb_top_t reg_config_sbb_top;
+
+ SET_BIT_FIELD(CONFIG_SBB_TOP, reg_config_sbb_top, reg_config_sbb_top.bits.drv_sbb, config);
+
+ return MAX77655_NO_ERROR;
+}
+
+int MAX77655::get_drv_sbb(decode_drv_sbb_t *config)
+{
+ int ret;
+ reg_config_sbb_top_t reg_config_sbb_top = {0};
+
+ ret = read_register(CONFIG_SBB_TOP, (uint8_t *)&(reg_config_sbb_top));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ *config = (decode_drv_sbb_t)reg_config_sbb_top.bits.drv_sbb;
+
+ return MAX77655_NO_ERROR;
+}
+
+int MAX77655::set_tv_sbb(uint8_t channel, float voltV)
+{
+ uint8_t value;
+ reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a;
+ reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a;
+ reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a;
+ reg_cnfg_sbb3_a_t reg_cnfg_sbb3_a;
+ float voltmV = voltV * 1000;
+
+ if (voltmV < 500) voltmV = 500;
+ else if (voltmV > 4000) voltmV = 4000;
+
+ value = (voltmV - 500) / 25;
+
+ if (channel == 0) {
+ SET_BIT_FIELD(CNFG_SBB0_A, reg_cnfg_sbb0_a, reg_cnfg_sbb0_a.bits.tv_sbb0, value);
+ }
+ else if (channel == 1) {
+ SET_BIT_FIELD(CNFG_SBB1_A, reg_cnfg_sbb1_a, reg_cnfg_sbb1_a.bits.tv_sbb1, value);
+ }
+ else if (channel == 2) {
+ SET_BIT_FIELD(CNFG_SBB2_A, reg_cnfg_sbb2_a, reg_cnfg_sbb2_a.bits.tv_sbb2, value);
+ }
+ else if (channel == 3) {
+ SET_BIT_FIELD(CNFG_SBB3_A, reg_cnfg_sbb3_a, reg_cnfg_sbb3_a.bits.tv_sbb3, value);
+ }
+ else {
+ return MAX77655_INVALID_DATA;
+ }
+
+ return MAX77655_NO_ERROR;
+}
+
+int MAX77655::get_tv_sbb(uint8_t channel, float *voltV)
+{
+ int ret;
+ uint8_t bit_value;
+ reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0};
+ reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0};
+ reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0};
+ reg_cnfg_sbb3_a_t reg_cnfg_sbb3_a = {0};
+
+ if (channel == 0) {
+ ret = read_register(CNFG_SBB0_A, (uint8_t *)&(reg_cnfg_sbb0_a));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_sbb0_a.bits.tv_sbb0;
+ }
+ else if (channel == 1) {
+ ret = read_register(CNFG_SBB1_A, (uint8_t *)&(reg_cnfg_sbb1_a));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_sbb1_a.bits.tv_sbb1;
+ }
+ else if (channel == 2) {
+ ret = read_register(CNFG_SBB2_A, (uint8_t *)&(reg_cnfg_sbb2_a));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_sbb2_a.bits.tv_sbb2;
+ }
+ else if (channel == 3) {
+ ret = read_register(CNFG_SBB3_A, (uint8_t *)&(reg_cnfg_sbb3_a));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ bit_value = (uint8_t)reg_cnfg_sbb3_a.bits.tv_sbb3;
+ }
+ else {
+ return MAX77655_INVALID_DATA;
+ }
+
+ if (bit_value > 141) bit_value = 141;
+ *voltV = (bit_value * 0.025f) + 0.5f;
+
+ return MAX77655_NO_ERROR;
+}
+
+int MAX77655::set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb)
+{
+ reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b;
+ reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b;
+ reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b;
+ reg_cnfg_sbb3_b_t reg_cnfg_sbb3_b;
+
+ if (channel == 0) {
+ SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.ade_sbb0, ade_sbb);
+ }
+ else if (channel == 1) {
+ SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.ade_sbb1, ade_sbb);
+ }
+ else if (channel == 2) {
+ SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.ade_sbb2, ade_sbb);
+ }
+ else if (channel == 3) {
+ SET_BIT_FIELD(CNFG_SBB3_B, reg_cnfg_sbb3_b, reg_cnfg_sbb3_b.bits.ade_sbb3, ade_sbb);
+ }
+ else {
+ return MAX77655_INVALID_DATA;
+ }
+
+ return MAX77655_NO_ERROR;
+}
+
+int MAX77655::get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb)
+{
+ int ret;
+ reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+ reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+ reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+ reg_cnfg_sbb3_b_t reg_cnfg_sbb3_b = {0};
+
+ if (channel == 0) {
+ ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb0_b.bits.ade_sbb0;
+ }
+ else if (channel == 1) {
+ ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb1_b.bits.ade_sbb1;
+ }
+ else if (channel == 2) {
+ ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb2_b.bits.ade_sbb2;
+ }
+ else if (channel == 3) {
+ ret = read_register(CNFG_SBB3_B, (uint8_t *)&(reg_cnfg_sbb3_b));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb3_b.bits.ade_sbb3;
+ }
+ else {
+ return MAX77655_INVALID_DATA;
+ }
+
+ return MAX77655_NO_ERROR;
+}
+
+int MAX77655::set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb)
+{
+ reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b;
+ reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b;
+ reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b;
+ reg_cnfg_sbb3_b_t reg_cnfg_sbb3_b;
+
+ if (channel == 0) {
+ SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.en_sbb0, en_sbb);
+ }
+ else if (channel == 1) {
+ SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.en_sbb1, en_sbb);
+ }
+ else if (channel == 2) {
+ SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.en_sbb2, en_sbb);
+ }
+ else if (channel == 3) {
+ SET_BIT_FIELD(CNFG_SBB3_B, reg_cnfg_sbb3_b, reg_cnfg_sbb3_b.bits.en_sbb3, en_sbb);
+ }
+ else {
+ return MAX77655_INVALID_DATA;
+ }
+
+ return MAX77655_NO_ERROR;
+}
+
+int MAX77655::get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb)
+{
+ int ret;
+ reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
+ reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
+ reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
+ reg_cnfg_sbb3_b_t reg_cnfg_sbb3_b = {0};
+
+ if (channel == 0) {
+ ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb0_b.bits.en_sbb0;
+ }
+ else if (channel == 1) {
+ ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb1_b.bits.en_sbb1;
+ }
+ else if (channel == 2) {
+ ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb2_b.bits.en_sbb2;
+ }
+ else if (channel == 3) {
+ ret = read_register(CNFG_SBB3_B, (uint8_t *)&(reg_cnfg_sbb3_b));
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb3_b.bits.en_sbb3;
+ }
+ else return MAX77655_INVALID_DATA;
+
+ return MAX77655_NO_ERROR;
+}
+
+int MAX77655::irq_disable_all()
+{
+ int ret;
+ uint8_t reg = 0;
+ uint8_t status = 0;
+
+ //Disable Masks in INTM_GLBL
+ ret = write_register(INTM_GLBL, ®);
+ if (ret != MAX77655_NO_ERROR) return ret;
+
+ // Clear Interrupt Flags in INT_GLBL
+ return read_register(INT_GLBL, &status);
+}
+
+void MAX77655::set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb)
+{
+ interrupt_handler_list[id].func = func;
+ interrupt_handler_list[id].cb = cb;
+}
+
+void MAX77655::post_interrupt_work()
+{
+ int ret;
+ uint8_t reg = 0, inten = 0, not_inten = 0, mask = 0;
+
+ while (true) {
+
+ ThisThread::flags_wait_any(POST_INTR_WORK_SIGNAL_ID);
+ // Check Interrupt Flags in INT_GLBL0
+ ret = read_register(INT_GLBL, ®);
+ if (ret != MAX77655_NO_ERROR) return;
+
+ ret = read_register(INTM_GLBL, &inten);
+ if (ret != MAX77655_NO_ERROR) return;
+
+ not_inten = ~inten; // 0 means unmasked.
+
+ for (int i = 0; i <= INT_GLBL_SBB3_FM; i++) {
+ mask = (1 << i);
+ /*
+ ***************************************************
+ This is special case. when nEN is pulled high, the
+ on/off controller initiates a power-down sequence and
+ goes to shutdown mode.
+ ***************************************************
+ */
+ if (((reg & mask) && (not_inten & mask))
+ || ((reg & (1 << INT_GLBL_nEN_F)) && (i == INT_GLBL_nEN_F))
+ || ((reg & (1 << INT_GLBL_nEN_R)) && (i == INT_GLBL_nEN_R))) {
+ if (interrupt_handler_list[i].func != NULL) {
+ interrupt_handler_list[i]
+ .func(interrupt_handler_list[i].cb);
+ }
+ }
+ }
+ }
+}
+
+void MAX77655::interrupt_handler()
+{
+ post_intr_work_thread->flags_set(POST_INTR_WORK_SIGNAL_ID);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MAX77655.h Tue Aug 23 18:11:21 2022 +0300
@@ -0,0 +1,503 @@
+/*******************************************************************************
+ * Copyright(C) Analog Devices Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Analog Devices Inc.
+ * shall not be used except as stated in the Analog Devices Inc.
+ * Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Analog Devices Inc.retains all ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MAX77655_H_
+#define _MAX77655_H_
+
+#include "mbed.h"
+#include "MAX77655_regs.h"
+
+#define MAX77655_NO_ERROR 0
+#define MAX77655_VALUE_NULL -1
+#define MAX77655_WRITE_DATA_FAILED -2
+#define MAX77655_READ_DATA_FAILED -3
+#define MAX77655_INVALID_DATA -4
+
+#define MAX77655_I2C_ADDRESS 0x88
+
+/**
+ * @brief MAX77655 Low IQ SIMO PMIC with 4-Outputs Delivering up to
+ * 700mA Total Output Current
+ *
+ * @details The MAX77655 is a highly efficient, complete power supply for low-power, ultra-compact applications.
+ *
+ * @code
+ * @endcode
+ */
+
+class MAX77655
+{
+private:
+ I2C *i2c_handler;
+ InterruptIn *irq_pin; // interrupt pin
+
+ /**
+ * @brief Register Addresses
+ * @details Enumerated MAX77655 register addresses
+ */
+ typedef enum {
+ CNFG_GLBL_A = 0x00, // Configuration Global A
+ CNFG_GLBL_B = 0x01, // Configuration Global B
+ INT_GLBL = 0x02, // Interrupt Global Status
+ INTM_GLBL = 0x03, // Interrupt Mask
+ STAT_GLBL = 0x04, // Global Status
+ ERCFLAG = 0x05, // Flags
+ CID = 0x06, // Chip Identification Code
+ CONFIG_SBB_TOP = 0x07, // SIMO Buck-Boost Configuration
+ CNFG_SBB0_A = 0x08, // SIMO Buck-Boost 0 Configuration A
+ CNFG_SBB0_B = 0x09, // SIMO Buck-Boost 0 Configuration B
+ CNFG_SBB1_A = 0x0A, // SIMO Buck-Boost 1 Configuration A
+ CNFG_SBB1_B = 0x0B, // SIMO Buck-Boost 1 Configuration B
+ CNFG_SBB2_A = 0x0C, // SIMO Buck-Boost 2 Configuration A
+ CNFG_SBB2_B = 0x0D, // SIMO Buck-Boost 2 Configuration B
+ CNFG_SBB3_A = 0x0E, // SIMO Buck-Boost 3 Configuration A
+ CNFG_SBB3_B = 0x0F, // SIMO Buck-Boost 3 Configuration B
+ } reg_t;
+
+ void interrupt_handler();
+
+ void (MAX77655::*funcptr)(void);
+
+ void post_interrupt_work();
+
+ Thread *post_intr_work_thread;
+
+ struct handler {
+ void (*func)(void *);
+ void *cb;
+ };
+
+ handler interrupt_handler_list[8];
+
+public:
+ /**
+ * @brief MAX77655 constructor.
+ */
+ MAX77655(I2C *i2c, PinName IRQPin = NC);
+
+ /**
+ * @brief MAX77655 destructor.
+ */
+ ~MAX77655();
+
+ /**
+ * @brief Function pointer type to interrupt handler function
+ */
+ typedef void (*interrupt_handler_function)(void *);
+
+ /**
+ * @brief Read from a register.
+ *
+ * @param[in] reg Address of a register to be written.
+ * @param[out] value Pointer to save result value.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int read_register(uint8_t reg, uint8_t *value);
+
+ /**
+ * @brief Write to a register.
+ *
+ * @param[in] reg Address of a register to be written.
+ * @param[out] value Pointer of value to be written to register.
+ *
+ * @returns 0 on success, negative error code on failure.
+ */
+ int write_register(uint8_t reg, const uint8_t *value);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_GLBL_A (0x00)
+ * - Bit Fields : [7:0]
+ * - Default : 0x0
+ * - Description : Event Recorder Flags.
+ */
+ typedef enum {
+ CNFG_GLBL_A_DBEN_nEN,
+ CNFG_GLBL_A_nEN_MODE,
+ CNFG_GLBL_A_MRT,
+ CNFG_GLBL_A_BIAS_LPM,
+ CNFG_GLBL_A_PU_DIS,
+ CNFG_GLBL_A_RSVD
+ }reg_bit_cnfg_glbl_a_t;
+
+ /**
+ * @brief Set CNFG_GLBL_A (0x00) register.
+ *
+ * @param[in] bit_field Register bit field to be written.
+ * @param[in] config Configuration bit field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_cnfg_glbl_a(reg_bit_cnfg_glbl_a_t bit_field, uint8_t config);
+
+ /**
+ * @brief Get CNFG_GLBL_A (0x00) register.
+ *
+ * @param[in] bit_field Register bit field to be written.
+ * @param[out] config Pointer of value to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_cnfg_glbl_a(reg_bit_cnfg_glbl_a_t bit_field, uint8_t *config);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_GLBL_B (0x01)
+ * - Bit Fields : [2:0]
+ * - Default : 0x0
+ * - Description : Software Control Functions
+ */
+ typedef enum {
+ SFT_CTRL_NO_ACTION,
+ SFT_CTRL_SOFTWARE_COLD_RESET,
+ SFT_CTRL_SOFTWARE_OFF,
+ SFT_CTRL_SOFTWARE_STANDBY,
+ SFT_CTRL_RESERVED
+ }decode_sft_ctrl_t;
+
+ /**
+ * @brief Set CNFG_GLBL_B (0x01) register.
+ *
+ * @param[in] config Register bit field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_sft_ctrl(decode_sft_ctrl_t config);
+
+ /**
+ * @brief Get CNFG_GLBL_B (0x01) register.
+ *
+ * @param[in] config Register bit field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_sft_ctrl(decode_sft_ctrl_t *config);
+
+ /**
+ * @brief Register Configuration.
+ * All Interrupt Flags combined from INT_GLBL0 (0x02)
+ *
+ * @details
+ * - Register : INT_GLBL (0x02)
+ * - Bit Fields :
+ * - Default : 0x0
+ * - Description : Enumerated interrupts.
+ */
+ typedef enum {
+ INT_GLBL_nEN_F,
+ INT_GLBL_nEN_R,
+ INT_GLBL_TJAL1_R,
+ INT_GLBL_TJAL2_R,
+ INT_GLBL_SBB0_FM,
+ INT_GLBL_SBB1_FM,
+ INT_GLBL_SBB2_FM,
+ INT_GLBL_SBB3_FM
+ } reg_bit_int_glbl_t;
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : INTM_GLBL (0x03)
+ * - Bit Fields : [7:0]
+ * - Default : 0x0
+ * - Description : All interrupt mask bits.
+ */
+ typedef enum {
+ INTM_GLBL_nEN_FM,
+ INTM_GLBL_nEN_RM,
+ INTM_GLBL_TJAL1_RM,
+ INTM_GLBL_TJAL2_RM,
+ INTM_GLBL_SBB0_FM,
+ INTM_GLBL_SBB1_FM,
+ INTM_GLBL_SBB2_FM,
+ INTM_GLBL_SBB3_FM
+ }reg_bit_int_mask_t;
+
+ /**
+ * @brief Set bit field of INTM_GLBL (0x03) register.
+ *
+ * @param[in] bit_field Register bit field to be set.
+ * @param[out] maskBit 0x0: Interrupt is unmasked,
+ * 0x1: Interrupt is masked.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit);
+
+ /**
+ * @brief Get bit field of INTM_GLBL (0x03) register.
+ *
+ * @param[in] bit_field Register bit field to be written.
+ * @param[out] maskBit 0x0: Interrupt is unmasked,
+ * 0x1: Interrupt is masked.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : STAT_GLBL (0x04)
+ * - Bit Fields : [7:0]
+ * - Default : 0x0
+ * - Description : Global Status.
+ */
+ typedef enum {
+ STAT_GLBL_STAT_EN,
+ STAT_GLBL_TJAL1_S,
+ STAT_GLBL_TJAL2_S,
+ STAT_GLBL_RSVD,
+ STAT_GLBL_SBB0_S,
+ STAT_GLBL_SBB1_S,
+ STAT_GLBL_SBB2_S,
+ STAT_GLBL_SBB3_S
+ }reg_bit_stat_glbl_t;
+
+ /**
+ * @brief Get bit field of STAT_GLBL (0x04) register.
+ *
+ * @param[in] bit_field STAT_GLBL register bit field to be written.
+ * @param[out] status Pointer to save result of Status Global bit state.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : ERCFLAG (0x05)
+ * - Bit Fields : [7:0]
+ * - Default : 0x0
+ * - Description : Event Recorder Flags.
+ */
+ typedef enum {
+ ERCFLAG_TOVLD,
+ ERCFLAG_OVLO,
+ ERCFLAG_UVLO,
+ ERCFLAG_MRST,
+ ERCFLAG_SFT_OFF_F,
+ ERCFLAG_SFT_CRST_F,
+ ERCFLAG_RSVD
+ }reg_bit_ercflag_t;
+
+ /**
+ * @brief Get bit field of ERCFLAG (0x05) register.
+ *
+ * @param[in] bit_field ERCFLAG register bit field to be written.
+ * @param[out] flag Pointer to save result of ercglag bit states.
+ * For individual bit
+ * 0x0: ERCFLAG has not occurred,
+ * 0x1: ERCFLAG has occurred.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag);
+
+ /**
+ * @brief Get bit field of CID (0x06) register.
+ *
+ * @return CID on success, error code on failure.
+ */
+ int get_cid(void);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CONFIG_SBB_TOP (0x07)
+ * - Bit Fields : [1:0]
+ * - Default : 0x0
+ * - Description : Configuration for SIMO Buck Boost
+ */
+ typedef enum {
+ DRV_SBB_FASTEST_TRANSITION_TIME,
+ DRV_SBB_A_LITTLE_SLOWER_THAN_0X00,
+ DRV_SBB_A_LITTLE_SLOWER_THAN_0X01,
+ DRV_SBB_A_LITTLE_SLOWER_THAN_0X02
+ }decode_drv_sbb_t;
+
+ /**
+ * @brief Set CONFIG_SBB_TOP (0x07) register.
+ *
+ * @param[in] config Configuration value to be written.
+ * 0x0: Fastest transition time (~0.6ns)
+ * 0x1: A little slower than 0b00 (~1.2ns)
+ * 0x2: A little slower than 0b01 (~1.8ns)
+ * 0x3: A little slower than 0b10 (~8ns)
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_drv_sbb(decode_drv_sbb_t config);
+
+ /**
+ * @brief Get CONFIG_SBB_TOP (0x07) register.
+ *
+ * @param[out] config Configuration value to be read.
+ * 0x0: Fastest transition time (~0.6ns)
+ * 0x1: A little slower than 0b00 (~1.2ns)
+ * 0x2: A little slower than 0b01 (~1.8ns)
+ * 0x3: A little slower than 0b10 (~8ns)
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_drv_sbb(decode_drv_sbb_t *config);
+
+ /**
+ * @brief Set SIMO Buck-Boost Channel x Target Output Voltage.
+ * CNFG_SBB0_A (0x08), CNFG_SBB1_A (0x0A), CNFG_SBB2_A (0x0C) and CNFG_SBB3_A (0x0E)
+ *
+ * @param[in] channel Channel number: 0, 1, 2 or 3.
+ * @param[in] voltV SIMO buck-boost channel x target output voltage field to be written.
+ * SBBx = 500mV + 25mV x TV_SBBx[7:0]
+ * 0x00: 0.500V 0x01: 0.525V 0x02: 0.550V
+ 0x03: 0.575V ...
+ 0x8B: 3.975V 0x8C: 4.000V 0x8D–0xFF: Reserved
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_tv_sbb(uint8_t channel, float voltV);
+
+ /**
+ * @brief Get SIMO Buck-Boost Channel x Target Output Voltage.
+ * CNFG_SBB0_A (0x08), CNFG_SBB1_A (0x0A), CNFG_SBB2_A (0x0C) and CNFG_SBB3_A (0x0E)
+ *
+ * @param[in] channel Channel number: 0, 1, 2 or 3.
+ * @param[out] voltV SIMO buck-boost channel x target output voltage field to be read.
+ * SBBx = 500mV + 25mV x TV_SBBx[7:0]
+ * 0x00: 0.500V 0x01: 0.525V 0x02: 0.550V
+ 0x03: 0.575V ...
+ 0x8B: 3.975V 0x8C: 4.000V 0x8D–0xFF: Reserved
+ * @return 0 on success, error code on failure.
+ */
+ int get_tv_sbb(uint8_t channel, float *voltV);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_SBB0_B (0x09), CNFG_SBB1_B (0x0B), CNFG_SBB2_B (0x0D) and CNFG_SBB3_B (0x0F)
+ * - Bit Fields : [3]
+ * - Default : 0x0
+ * - Description : SIMO Buck-Boost Channel 0, 1, 2 or 3 Active-Discharge Enable.
+ */
+ typedef enum {
+ ADE_SBB_DISABLED,
+ ADE_SBB_ENABLED
+ }decode_ade_sbb_t;
+
+ /**
+ * @brief Set SIMO Buck-Boost Channel x Active-Discharge Enable.
+ *
+ * @param[in] channel Channel number: 0, 1, 2 or 3.
+ * @param[in] ade_sbb SIMO buck-boost channel x active-discharge enable bit to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb);
+
+ /**
+ * @brief Get SIMO Buck-Boost Channel x Active-Discharge Enable.
+ *
+ * @param[in] channel Channel number: 0, 1, 2 or 3.
+ * @param[out] ade_sbb SIMO buck-boost channel x active-discharge enable bit to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb);
+
+ /**
+ * @brief Register Configuration
+ *
+ * @details
+ * - Register : CNFG_SBB0_B (0x09), CNFG_SBB1_B (0x0B), CNFG_SBB2_B (0x0D) and CNFG_SBB3_B (0x0F)
+ * - Bit Fields : [2:0]
+ * - Default : 0x0
+ * - Description : Enable Control for SIMO Buck-Boost Channel 0, 1, 2 or 3.
+ */
+ typedef enum {
+ EN_SBB_FPS_SLOT_0,
+ EN_SBB_FPS_SLOT_1,
+ EN_SBB_FPS_SLOT_2,
+ EN_SBB_FPS_SLOT_3,
+ EN_SBB_OFF,
+ EN_SBB_SAME_AS_0X04,
+ EN_SBB_ON,
+ EN_SBB_SAME_AS_0X06
+ }decode_en_sbb_t;
+
+ /**
+ * @brief Set Enable Control for SIMO Buck-Boost Channel x.
+ *
+ * @param[in] channel Channel number: 0, 1, 2 or 3.
+ * @param[in] en_sbb Enable control for SIMO buck-boost channel x field to be written.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb);
+
+ /**
+ * @brief Get Enable Control for SIMO Buck-Boost Channel x.
+ *
+ * @param[in] channel Channel number: 0, 1, 2 or 3.
+ * @param[out] en_sbb Enable control for SIMO buck-boost channel x field to be read.
+ *
+ * @return 0 on success, error code on failure.
+ */
+ int get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb);
+
+ /**
+ * @brief Disable all interrupts
+ *
+ * @return 0 on success, error code on failure
+ */
+ int irq_disable_all();
+
+ /**
+ * @brief Set Interrupt Handler for a Specific Interrupt ID.
+ *
+ * @param[in] id reg_bit_reg_bit_int_glbl_t id, one of INTR_ID_*.
+ * @param[in] func Interrupt handler function.
+ * @param[in] cb Interrupt handler data.
+ */
+ void set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb);
+};
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MAX77655_regs.h Tue Aug 23 18:11:21 2022 +0300
@@ -0,0 +1,445 @@
+/*******************************************************************************
+ * Copyright(C) Analog Devices Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files(the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Analog Devices Inc.
+ * shall not be used except as stated in the Analog Devices Inc.
+ * Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Analog Devices Inc.retains all ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MAX77655_REGS_H_
+#define MAX77655_REGS_H_
+
+/**
+ * @brief CNFG_GLBL_A Register
+ *
+ * Address : 0x00
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char dben_nen : 1; /**< Debounce Timer Enable for the nEN Pin. Bit 0.
+ 0x0: 100μs Debounce
+ 0x1: 30ms Debounce */
+ unsigned char nen_mode : 2; /**< nEN Input (ON-KEY) Default Configuration Mode. Bit 2:1.
+ 0b00 = Push-button mode
+ 0b01 = Slide-switch mode
+ 0b10 = Logic mode
+ 0b11 = Reserved */
+ unsigned char mrt : 1; /**< Manual Reset Time Configuration. Bit 3.
+ 0x0: Manual Reset Time is 16s.
+ 0x1: Manual Reset Time is 8s. */
+ unsigned char bias_lpm : 1; /**< Main Bias Low-Power Mode Software Request. Bit 4.
+ 0 = Main Bias requested to be in Normal-Power Mode by software.
+ 1 = Main Bias request to be in Low-Power Mode by software. */
+ unsigned char pu_dis : 1; /**< nEN Internal Pullup Resistor. Bit 5.
+ 0 = Strong internal nEN pullup (200kΩ)
+ 1 = Internal pullup disabled */
+ unsigned char rsvd : 2; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 7:6. */
+ } bits;
+} reg_cnfg_glbl_a_t;
+
+/**
+ * @brief CNFG_GLBL_B Register
+ *
+ * Address : 0x01
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char sft_ctrl : 3; /**< Software Control Functions. Bit 2:0.
+ 0x0: No Action
+ 0x1: Software Cold Reset (SFT_CRST). The device powers down, resets, and then powers up again.
+ 0x2: Software Off (SFT_OFF). The device powers down, resets, and then remains off until a wake-up event.
+ 0x3: Software Standby (SFT_STBY). The device powers down and goes to standby mode.
+ 0x4: Software Exit Standby (SFT_EXIT_STBY). The device exits standby mode and powers up again.
+ 0x5 - 0x7: Reserved */
+ unsigned char rsvd : 5; /**< Reserved. Bit 7:3. Unutilized bit. Write to 0. Reads are don't care */
+ } bits;
+} reg_cnfg_glbl_b_t;
+
+/**
+ * @brief INT_GLBL Register
+ *
+ * Address : 0x02
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char nen_f : 1; /**< nEN Falling Interrupt.Bit 0.
+ 0 = No nEN falling edges have occurred since the last time this bit was read.
+ 1 = A nEN falling edge as occurred since the last time this bit was read. */
+ unsigned char nen_r : 1; /**< nEN Rising Interrupt. Bit 1.
+ 0 = No nEN rising edges have occurred since the last time this bit was read.
+ 1 = A nEN rising edge as occurred since the last time this bit was read. */
+ unsigned char tjal1_r : 1; /**< Thermal Alarm 1 Rising Interrupt. Bit 2.
+ 0 = The junction temperature has not risen above TJAL1 since the last time this bit was read.
+ 1 = The junction temperature has risen above TJAL1 since the last time this bit was read. */
+ unsigned char tjal2_r : 1; /**< Thermal Alarm 2 Rising Interrupt. Bit 3.
+ 0 = The junction temperature has not risen above TJAL2 since the last time this bit was read.
+ 1 = The junction temperature has risen above TJAL2 since the last time this bit was read. */
+ unsigned char sbb0_f : 1; /**< SBB0 Channel Fault Interrupt. Bit 4.
+ 0x0: SBB0 was not overloaded since the last time this bit was read.
+ 0x1: SBB0 was overloaded since the last time this bit was read. */
+ unsigned char sbb1_f : 1; /**< SBB1 Channel Fault Interrupt. Bit 5.
+ 0x0: SBB1 was not overloaded since the last time this bit was read.
+ 0x1: SBB1 was overloaded since the last time this bit was read. */
+ unsigned char sbb2_f : 1; /**< SBB2 Channel Fault Interrupt. Bit 6.
+ 0x0: SBB2 was not overloaded since the last time this bit was read.
+ 0x1: SBB2 was overloaded since the last time this bit was read. */
+ unsigned char sbb3_f : 1; /**< SBB3 Channel Fault Interrupt. Bit 7.
+ 0x0: SBB3 was not overloaded since the last time this bit was read.
+ 0x1: SBB3 was overloaded since the last time this bit was read. */
+ } bits;
+} reg_int_glbl0_t;
+
+/**
+ * @brief INTM_GLBL Register
+ *
+ * Address : 0x03
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char nen_fm : 1; /**< nEN Falling Interrupt Mask. Bit 0.
+ 0 = Unmasked. If nEN_F goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to nEN_F. */
+ unsigned char nen_rm : 1; /**< nEN Rising Interrupt Mask. Bit 1.
+ 0 = Unmasked. If nEN_R goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to nEN_R. */
+ unsigned char tjal1_rm : 1; /**< Thermal Alarm 1 Rising Interrupt Mask. Bit 2.
+ 0 = Unmasked. If TJAL1_R goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to TJAL1_R. */
+ unsigned char tjal2_rm : 1; /**< Thermal Alarm 2 Rising Interrupt Mask. Bit 3.
+ 0 = Unmasked. If TJAL2_R goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to TJAL2_R. */
+ unsigned char sbb0_fm : 1; /**< SBB0 Channel Fault Interrupt Mask. Bit 4.
+ 0 = Unmasked. If SBB0_FM goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to SBB0_FM. */
+ unsigned char sbb1_fm : 1; /**< SBB1 Channel Fault Interrupt Mask. Bit 5.
+ 0 = Unmasked. If SBB1_FM goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to SBB1_FM. */
+ unsigned char sbb2_fm : 1; /**< SBB2 Channel Fault Interrupt Mask. Bit 6.
+ 0 = Unmasked. If SBB2_FM goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to SBB2_FM. */
+ unsigned char sbb3_fm : 1; /**< SBB3 Channel Fault Interrupt Mask. Bit 7.
+ 0 = Unmasked. If SBB3_FM goes from 0 to 1, then nIRQ goes low.
+ nIRQ goes high when all interrupt bits are cleared.
+ 1 = Masked. nIRQ does not go low due to SBB3_FM. */
+ } bits;
+} reg_intm_glbl_t;
+
+/**
+ * @brief STAT_GLBL Register
+ *
+ * Address : 0x04
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char stat_en : 1; /**< Debounced Status for the nEN input. Bit 0.
+ 0 = nEN is not active (logic high)
+ 1 = nEN is active (logic low) */
+ unsigned char tjal1_s : 1; /**< Thermal Alarm 1 Status. Bit 1.
+ 0 = The junction temperature is less than TJAL1
+ 1 = The junction temperature is greater than TJAL1 */
+ unsigned char tjal2_s : 1; /**< Thermal Alarm 2 Status. Bit 2.
+ 0 = The junction temperature is less than TJAL2
+ 1 = The junction temperature is greater than TJAL2 */
+ unsigned char rsvd : 1; /**< Reserved. Unutilized bit. Write to 0. Reads are don't care. Bit 3. */
+ unsigned char sbb0_s : 1; /**< SBB0 Channel Regulation Status. Bit 4.
+ 0x0: SBB0 is overloaded or disabled
+ 0x1: SBB0 is not overloaded */
+ unsigned char sbb1_s : 1; /**< SBB1 Channel Regulation Status. Bit 5.
+ 0x0: SBB1 is overloaded or disabled
+ 0x1: SBB1 is not overloaded */
+ unsigned char sbb2_s : 1; /**< SBB2 Channel Regulation Status. Bit 6.
+ 0x0: SBB2 is overloaded or disabled
+ 0x1: SBB2 is not overloaded */
+ unsigned char sbb3_s : 1; /**< SBB3 Channel Regulation Status. Bit 7.
+ 0x0: SBB3 is overloaded or disabled
+ 0x1: SBB3 is not overloaded */
+ } bits;
+} reg_stat_glbl_t;
+
+/**
+ * @brief ERCFLAG Register
+ *
+ * Address : 0x05
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char tovld : 1; /**< Thermal Overload. Bit 0.
+ 0 = Thermal overload has not occurred since the last read of this register.
+ 1 = Thermal overload has occurred since the list read of this register.
+ This indicates that the junction temperature has exceeded 165ºC. */
+ unsigned char ovlo : 1; /**< Overvoltage Lockout. Bit 1.
+ 0 = The overvoltage lockout has not occurred since the last read of this register.
+ 1 = The overvoltage lockout has occurred since the last read of this register */
+ unsigned char uvlo : 1; /**< Undervoltage Lockout. Bit 2.
+ 0 = The undervoltage lockout has not occurred since the last read of this register.
+ 1 = The undervoltage lockout has occurred since the last read of this register */
+ unsigned char mrst : 1; /**< Manual Reset Timer. Bit 3.
+ 0 = A Manual Reset has not occurred since this last read of this register.
+ 1 = A Manual Reset has occurred since this last read of this register. */
+ unsigned char sft_off_f : 1; /**< Software Off Flag. Bit 4.
+ 0 = The SFT_OFF function has not occurred since the last read of this register.
+ 1 = The SFT_OFF function has occurred since the last read of this register. */
+ unsigned char sft_crst_f : 1; /**< Software Cold Reset Flag. Bit 5.
+ 0 = The software cold reset has not occurred since the last read of this register.
+ 1 = The software cold reset has occurred since the last read of this register. */
+ unsigned char rsvd : 2; /**< Reserved. Bit 7:6. Unutilized bit. Write to 0. Reads are don't care. */
+ } bits;
+} reg_ercflag_t;
+
+/**
+ * @brief CID Register
+ *
+ * Address : 0x06
+ */
+typedef union {
+ unsigned char raw;
+ struct {
+ unsigned char cid : 8; /**< Chip Identification Code. Bit 7:0.
+ The Chip Identification Code refers to a set of reset values in the register map, or the "OTP configuration.". */
+ } bits;
+} reg_cid_t;
+
+/**
+ * @brief CONFIG_SBB_TOP
+ *
+ * Address : 0x07
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char drv_sbb : 2; /**< SIMO Buck-Boost (all channels) Drive Strength Trim. Bit 1:0.
+ 0b00 = Fastest transition time (~0.6ns)
+ 0b01 = A little slower than 0b00 (~1.2ns)
+ 0b10 = A little slower than 0b01 (~1.8ns)
+ 0b11 = A little slower than 0b10 (~8ns) */
+ unsigned char rsvd : 6; /**< Bit 7:2.*/
+ } bits;
+} reg_config_sbb_top_t;
+
+/**
+ * @brief CNFG_SBB0_A
+ *
+ * Address : 0x08
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char tv_sbb0 : 8; /**< SIMO Buck-Boost Channel 0 Target Output Voltage. Bit 7:0.
+ 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V
+ 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V
+ 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V
+ ...
+ 0x8B: 3.975V
+ 0x8C: 4.000V
+ 0x8D–0xFF: Reserved */
+ } bits;
+} reg_cnfg_sbb0_a_t;
+
+/**
+ * @brief CNFG_SBB0_B
+ *
+ * Address : 0x09
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char en_sbb0 : 3; /**< Enable Control for SIMO Buck-Boost Channel 0,
+ selecting either an FPS slot the channel powers-up and powers-down in
+ or whether the channel is forced on or off. Bit 2:0.
+ 0b000 = FPS slot 0 0b001 = FPS slot 1
+ 0b010 = FPS slot 2 0b011 = FPS slot 3
+ 0b100 = Off irrespective of FPS
+ 0b101 = same as 0b100 0b110 = On irrespective of FPS
+ 0b111 = same as 0b110 */
+ unsigned char ade_sbb0 : 1; /**< SIMO Buck-Boost Channel 0 Active-Discharge Enable. Bit 3.
+ 0 = The active discharge function is disabled.
+ When SBB0 is disabled, its discharge rate is a function of the output capacitance and the external load.
+ 1 = The active discharge function is enabled.
+ When SBB0 is disabled, an internal resistor (RAD_SBB0) is activated from SBB0 to PGND to help the output voltage discharge. */
+ unsigned char rsvd1 : 2; /**< Reserved. Bit 5:4. Unutilized bit. They are don't care. */
+ unsigned char rsvd2 : 2; /**< Reserved. Bit 7:6. Unutilized bit. They are don't care. */
+ } bits;
+} reg_cnfg_sbb0_b_t;
+
+/**
+ * @brief CNFG_SBB1_A
+ *
+ * Address : 0x0A
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char tv_sbb1 : 8; /**< SIMO Buck-Boost Channel 1 Target Output Voltage. Bit 7:0.
+ 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V
+ 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V
+ 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V
+ ...
+ 0x8B: 3.975V
+ 0x8C: 4.000V
+ 0x8D–0xFF: Reserved */
+ } bits;
+} reg_cnfg_sbb1_a_t;
+
+/**
+ * @brief CNFG_SBB1_B
+ *
+ * Address : 0x0B
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char en_sbb1 : 3; /**< Enable Control for SIMO Buck-Boost Channel 1,
+ selecting either an FPS slot the channel powers-up and powers-down in
+ or whether the channel is forced on or off. Bit 2:0.
+ 0b000 = FPS slot 0 0b001 = FPS slot 1
+ 0b010 = FPS slot 2 0b011 = FPS slot 3
+ 0b100 = Off irrespective of FPS
+ 0b101 = same as 0b100 0b110 = On irrespective of FPS
+ 0b111 = same as 0b110 */
+ unsigned char ade_sbb1 : 1; /**< SIMO Buck-Boost Channel 1 Active-Discharge Enable. Bit 3.
+ 0 = The active discharge function is disabled.
+ When SBB1 is disabled, its discharge rate is a function of the output capacitance and the external load.
+ 1 = The active discharge function is enabled.
+ When SBB1 is disabled, an internal resistor (RAD_SBB1) is activated from SBB0 to PGND to help the output voltage discharge. */
+ unsigned char rsvd1 : 2; /**< Reserved. Bit 5:4. Unutilized bit. They are don't care. */
+ unsigned char rsvd2 : 2; /**< Reserved. Bit 7:6. Unutilized bit. They are don't care. */
+ } bits;
+} reg_cnfg_sbb1_b_t;
+
+/**
+ * @brief CNFG_SBB2_A
+ *
+ * Address : 0x0C
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char tv_sbb2 : 8; /**< SIMO Buck-Boost Channel 2 Target Output Voltage. Bit 7:0.
+ 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V
+ 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V
+ 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V
+ ...
+ 0x8B: 3.975V
+ 0x8C: 4.000V
+ 0x8D–0xFF: Reserved */
+ } bits;
+} reg_cnfg_sbb2_a_t;
+
+/**
+ * @brief CNFG_SBB2_B
+ *
+ * Address : 0x0D
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char en_sbb2 : 3; /**< Enable Control for SIMO Buck-Boost Channel 2,
+ selecting either an FPS slot the channel powers-up and powers-down in
+ or whether the channel is forced on or off. Bit 2:0.
+ 0b000 = FPS slot 0 0b001 = FPS slot 1
+ 0b010 = FPS slot 2 0b011 = FPS slot 3
+ 0b100 = Off irrespective of FPS
+ 0b101 = same as 0b100 0b110 = On irrespective of FPS
+ 0b111 = same as 0b110 */
+ unsigned char ade_sbb2 : 1; /**< SIMO Buck-Boost Channel 2 Active-Discharge Enable Bit 3.
+ 0 = The active discharge function is disabled.
+ When SBB2 is disabled, its discharge rate is a function of the output capacitance and the external load.
+ 1 = The active discharge function is enabled.
+ When SBB2 is disabled, an internal resistor (RAD_SBB2) is activated from SBB0 to PGND to help the output voltage discharge. */
+ unsigned char rsvd1 : 2; /**< Reserved. Bit 5:4. Unutilized bit. They are don't care. */
+ unsigned char rsvd2 : 2; /**< Reserved. Bit 7:6. Unutilized bit. They are don't care. */
+ } bits;
+} reg_cnfg_sbb2_b_t;
+
+/**
+ * @brief CNFG_SBB3_A
+ *
+ * Address : 0x0E
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char tv_sbb3 : 8; /**< SIMO Buck-Boost Channel 3 Target Output Voltage. Bit 7:0.
+ 0x00 = 0.500V 0x01 = 0.525V 0x02 = 0.550V
+ 0x03 = 0.575V 0x04 = 0.600V 0x05 = 0.625V
+ 0x06 = 0.650V 0x07 = 0.675V 0x08 = 0.700V
+ ...
+ 0x8B: 3.975V
+ 0x8C: 4.000V
+ 0x8D–0xFF: Reserved */
+ } bits;
+} reg_cnfg_sbb3_a_t;
+
+/**
+ * @brief CNFG_SBB3_B
+ *
+ * Address : 0x0F
+ */
+typedef union {
+ unsigned char raw;
+ struct
+ {
+ unsigned char en_sbb3 : 3; /**< Enable Control for SIMO Buck-Boost Channel 3,
+ selecting either an FPS slot the channel powers-up and powers-down in
+ or whether the channel is forced on or off. Bit 2:0.
+ 0b000 = FPS slot 0 0b001 = FPS slot 1
+ 0b010 = FPS slot 2 0b011 = FPS slot 3
+ 0b100 = Off irrespective of FPS
+ 0b101 = same as 0b100 0b110 = On irrespective of FPS
+ 0b111 = same as 0b110 */
+ unsigned char ade_sbb3 : 1; /**< SIMO Buck-Boost Channel 3 Active-Discharge Enable Bit 3.
+ 0 = The active discharge function is disabled.
+ When SBB3 is disabled, its discharge rate is a function of the output capacitance and the external load.
+ 1 = The active discharge function is enabled.
+ When SBB3 is disabled, an internal resistor (RAD_SBB3) is activated from SBB0 to PGND to help the output voltage discharge. */
+ unsigned char rsvd1 : 2; /**< Reserved. Bit 5:4. Unutilized bit. They are don't care. */
+ unsigned char rsvd2 : 2; /**< Reserved. Bit 7:6. Unutilized bit. They are don't care. */
+ } bits;
+} reg_cnfg_sbb3_b_t;
+
+#endif /* MAX77655_REGS_H_ */